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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

Browse source 
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Remove unused galileo-boars header files
  [MIPS] Rename SERIAL_PORT_DEFNS for EV64120
  [MIPS] Add UART IRQ number for EV64120
  [MIPS] Remove excite_flash.c
  [MIPS] Update i8259 resources.
  [MIPS] Make unwind_stack() can dig into interrupted context
  [MIPS] Stacktrace build-fix and improvement
  [MIPS] QEMU: Add support for little endian mips
  [MIPS] Remove __flush_icache_page
  [MIPS] lockdep: update defconfigs
  [MIPS] lockdep: Add STACKTRACE_SUPPORT and enable LOCKDEP_SUPPORT
  [MIPS] lockdep: fix TRACE_IRQFLAGS_SUPPORT
This commit is contained in:
Linus Torvalds 2006-10-02 08:18:43 -07:00
commit 12dce6263d
72 changed files with 359 additions and 625 deletions
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2
include/asm-mips/cacheflush.h
View file

@ -46,8 +46,6 @@ static inline void flush_dcache_page(struct page *page)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
extern void (*__flush_icache_page)(struct vm_area_struct *vma,
struct page *page);
static inline void flush_icache_page(struct vm_area_struct *vma,
struct page *page)
{

55
include/asm-mips/galileo-boards/ev96100.h
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@ -1,55 +0,0 @@
/*
*
*/
#ifndef _MIPS_EV96100_H
#define _MIPS_EV96100_H
#include <asm/addrspace.h>
/*
* GT64120 config space base address
*/
#define GT64120_BASE (KSEG1ADDR(0x14000000))
#define MIPS_GT_BASE GT64120_BASE
/*
* PCI Bus allocation
*/
#define GT_PCI_MEM_BASE 0x12000000UL
#define GT_PCI_MEM_SIZE 0x02000000UL
#define GT_PCI_IO_BASE 0x10000000UL
#define GT_PCI_IO_SIZE 0x02000000UL
#define GT_ISA_IO_BASE PCI_IO_BASE
/*
* Duart I/O ports.
*/
#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20)
#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00)
/*
* EV96100 interrupt controller register base.
*/
#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
/*
* EV96100 UART register base.
*/
#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR
#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR
#define EV96100_BASE_BAUD ( 3686400 / 16 )
/*
* Because of an error/peculiarity in the Galileo chip, we need to swap the
* bytes when running bigendian.
*/
#define __GT_READ(ofs) \
(*(volatile u32 *)(GT64120_BASE+(ofs)))
#define __GT_WRITE(ofs, data) \
do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
#endif /* !(_MIPS_EV96100_H) */

12
include/asm-mips/galileo-boards/ev96100int.h
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@ -1,12 +0,0 @@
/*
*
*/
#ifndef _MIPS_EV96100INT_H
#define _MIPS_EV96100INT_H
#define EV96100INT_UART_0 6 /* IP 6 */
#define EV96100INT_TIMER 7 /* IP 7 */
extern void ev96100int_init(void);
#endif /* !(_MIPS_EV96100_H) */

25
include/asm-mips/irqflags.h
View file

@ -213,12 +213,37 @@ static inline int raw_irqs_disabled_flags(unsigned long flags)
* Do the CPU's IRQ-state tracing from assembly code.
*/
#ifdef CONFIG_TRACE_IRQFLAGS
/* Reload some registers clobbered by trace_hardirqs_on */
#ifdef CONFIG_64BIT
# define TRACE_IRQS_RELOAD_REGS \
LONG_L $11, PT_R11(sp); \
LONG_L $10, PT_R10(sp); \
LONG_L $9, PT_R9(sp); \
LONG_L $8, PT_R8(sp); \
LONG_L $7, PT_R7(sp); \
LONG_L $6, PT_R6(sp); \
LONG_L $5, PT_R5(sp); \
LONG_L $4, PT_R4(sp); \
LONG_L $2, PT_R2(sp)
#else
# define TRACE_IRQS_RELOAD_REGS \
LONG_L $7, PT_R7(sp); \
LONG_L $6, PT_R6(sp); \
LONG_L $5, PT_R5(sp); \
LONG_L $4, PT_R4(sp); \
LONG_L $2, PT_R2(sp)
#endif
# define TRACE_IRQS_ON \
CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \
jal trace_hardirqs_on
# define TRACE_IRQS_ON_RELOAD \
TRACE_IRQS_ON; \
TRACE_IRQS_RELOAD_REGS
# define TRACE_IRQS_OFF \
jal trace_hardirqs_off
#else
# define TRACE_IRQS_ON
# define TRACE_IRQS_ON_RELOAD
# define TRACE_IRQS_OFF
#endif

1
include/asm-mips/mach-ev64120/mach-gt64120.h
View file

@ -42,6 +42,7 @@ extern unsigned long gt64120_base;
#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR))
#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR))
#define EV64120_BASE_BAUD ( 3686400 / 16 )
#define EV64120_UART_IRQ 6
/*
* PCI interrupts will come in on either the INTA or INTD interrups lines,

17
include/asm-mips/serial.h
View file

@ -55,19 +55,18 @@
* Galileo EV64120 evaluation board
*/
#ifdef CONFIG_MIPS_EV64120
#include <asm/galileo-boards/ev96100.h>
#include <asm/galileo-boards/ev96100int.h>
#define EV96100_SERIAL_PORT_DEFNS \
{ .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
#include <mach-gt64120.h>
#define EV64120_SERIAL_PORT_DEFNS \
{ .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
.flags = STD_COM_FLAGS, \
.iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
.iomem_base = EV64120_UART0_REGS_BASE, .iomem_reg_shift = 2, \
.io_type = SERIAL_IO_MEM }, \
{ .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
{ .baud_base = EV64120_BASE_BAUD, .irq = EV64120_UART_IRQ, \
.flags = STD_COM_FLAGS, \
.iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
.iomem_base = EV64120_UART1_REGS_BASE, .iomem_reg_shift = 2, \
.io_type = SERIAL_IO_MEM },
#else
#define EV96100_SERIAL_PORT_DEFNS
#define EV64120_SERIAL_PORT_DEFNS
#endif
#ifdef CONFIG_MIPS_ITE8172
@ -239,7 +238,7 @@
#define SERIAL_PORT_DFNS \
DDB5477_SERIAL_PORT_DEFNS \
EV96100_SERIAL_PORT_DEFNS \
EV64120_SERIAL_PORT_DEFNS \
IP32_SERIAL_PORT_DEFNS \
ITE_SERIAL_PORT_DEFNS \
IVR_SERIAL_PORT_DEFNS \

44
include/asm-mips/stacktrace.h Normal file
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@ -0,0 +1,44 @@
#ifndef _ASM_STACKTRACE_H
#define _ASM_STACKTRACE_H
#include <asm/ptrace.h>
#ifdef CONFIG_KALLSYMS
extern int raw_show_trace;
extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
unsigned long pc, unsigned long *ra);
#else
#define raw_show_trace 1
#define unwind_stack(task, sp, pc, ra) 0
#endif
static __always_inline void prepare_frametrace(struct pt_regs *regs)
{
#ifndef CONFIG_KALLSYMS
/*
* Remove any garbage that may be in regs (specially func
* addresses) to avoid show_raw_backtrace() to report them
*/
memset(regs, 0, sizeof(*regs));
#endif
__asm__ __volatile__(
".set push\n\t"
".set noat\n\t"
#ifdef CONFIG_64BIT
"1: dla $1, 1b\n\t"
"sd $1, %0\n\t"
"sd $29, %1\n\t"
"sd $31, %2\n\t"
#else
"1: la $1, 1b\n\t"
"sw $1, %0\n\t"
"sw $29, %1\n\t"
"sw $31, %2\n\t"
#endif
".set pop\n\t"
: "=m" (regs->cp0_epc),
"=m" (regs->regs[29]), "=m" (regs->regs[31])
: : "memory");
}
#endif /* _ASM_STACKTRACE_H */