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bindings: clock: qcom: Add support of clock ids for SERAPH

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Add the clock handles for GCC/CAMCC/GPUCC/VIDEOCC/LSRCC/EVACC/TCSRCC,
so that the clients can request on the clock ids for SERAPH platform.

Change-Id: I87d32ada7cfe017c8f971e1df7fe255c84b5d86e
Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com>
This commit is contained in:
Kalpak Kawadkar 2024-07-24 15:23:15 +05:30
parent d2fad072d1
commit 728db2cc9a
7 changed files with 544 additions and 0 deletions
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153
include/dt-bindings/clock/qcom,camcc-seraph.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SERAPH_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SERAPH_H
/* CAM_CC clocks */
#define CAM_CC_PLL0 0
#define CAM_CC_PLL0_OUT_EVEN 1
#define CAM_CC_PLL0_OUT_ODD 2
#define CAM_CC_PLL1 3
#define CAM_CC_PLL1_OUT_EVEN 4
#define CAM_CC_PLL2 5
#define CAM_CC_PLL3 6
#define CAM_CC_PLL3_OUT_EVEN 7
#define CAM_CC_PLL4 8
#define CAM_CC_PLL4_OUT_EVEN 9
#define CAM_CC_PLL5 10
#define CAM_CC_PLL5_OUT_EVEN 11
#define CAM_CC_PLL6 12
#define CAM_CC_PLL6_OUT_EVEN 13
#define CAM_CC_PLL6_OUT_ODD 14
#define CAM_CC_BPS_AHB_CLK 15
#define CAM_CC_BPS_CLK 16
#define CAM_CC_BPS_CLK_SRC 17
#define CAM_CC_BPS_FAST_AHB_CLK 18
#define CAM_CC_CAMNOC_AHB_CLK 19
#define CAM_CC_CAMNOC_AXI_HF_CLK 20
#define CAM_CC_CAMNOC_AXI_NRT_CLK 21
#define CAM_CC_CAMNOC_AXI_RT_CLK 22
#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 23
#define CAM_CC_CAMNOC_AXI_SF_CLK 24
#define CAM_CC_CAMNOC_DCD_XO_CLK 25
#define CAM_CC_CAMNOC_XO_CLK 26
#define CAM_CC_CCI_0_CLK 27
#define CAM_CC_CCI_0_CLK_SRC 28
#define CAM_CC_CCI_1_CLK 29
#define CAM_CC_CCI_1_CLK_SRC 30
#define CAM_CC_CCI_2_CLK 31
#define CAM_CC_CCI_2_CLK_SRC 32
#define CAM_CC_CCI_3_CLK 33
#define CAM_CC_CCI_3_CLK_SRC 34
#define CAM_CC_CORE_AHB_CLK 35
#define CAM_CC_CPAS_AHB_CLK 36
#define CAM_CC_CPAS_BPS_CLK 37
#define CAM_CC_CPAS_FAST_AHB_CLK 38
#define CAM_CC_CPAS_IFE_0_CLK 39
#define CAM_CC_CPAS_IFE_1_CLK 40
#define CAM_CC_CPAS_IFE_LITE_0_CLK 41
#define CAM_CC_CPAS_IFE_LITE_1_CLK 42
#define CAM_CC_CPAS_IFE_LITE_2_CLK 43
#define CAM_CC_CPAS_IPE_NPS_CLK 44
#define CAM_CC_CPHY_RX_CLK_SRC 45
#define CAM_CC_CSI0PHYTIMER_CLK 46
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 47
#define CAM_CC_CSI1PHYTIMER_CLK 48
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 49
#define CAM_CC_CSI2PHYTIMER_CLK 50
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 51
#define CAM_CC_CSI4PHYTIMER_CLK 52
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 53
#define CAM_CC_CSID_CLK 54
#define CAM_CC_CSID_CLK_SRC 55
#define CAM_CC_CSID_CSIPHY_RX_CLK 56
#define CAM_CC_CSIPHY0_CLK 57
#define CAM_CC_CSIPHY1_CLK 58
#define CAM_CC_CSIPHY2_CLK 59
#define CAM_CC_CSIPHY4_CLK 60
#define CAM_CC_DRV_AHB_CLK 61
#define CAM_CC_DRV_XO_CLK 62
#define CAM_CC_FAST_AHB_CLK_SRC 63
#define CAM_CC_GDSC_CLK 64
#define CAM_CC_ICP_AHB_CLK 65
#define CAM_CC_ICP_ATB_CLK 66
#define CAM_CC_ICP_CLK 67
#define CAM_CC_ICP_CLK_SRC 68
#define CAM_CC_ICP_CTI_CLK 69
#define CAM_CC_ICP_TS_CLK 70
#define CAM_CC_IFE_0_CLK 71
#define CAM_CC_IFE_0_CLK_SRC 72
#define CAM_CC_IFE_0_FAST_AHB_CLK 73
#define CAM_CC_IFE_1_CLK 74
#define CAM_CC_IFE_1_CLK_SRC 75
#define CAM_CC_IFE_1_FAST_AHB_CLK 76
#define CAM_CC_IFE_LITE_0_AHB_CLK 77
#define CAM_CC_IFE_LITE_0_CLK 78
#define CAM_CC_IFE_LITE_0_CLK_SRC 79
#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 80
#define CAM_CC_IFE_LITE_0_CSID_CLK 81
#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 82
#define CAM_CC_IFE_LITE_1_AHB_CLK 83
#define CAM_CC_IFE_LITE_1_CLK 84
#define CAM_CC_IFE_LITE_1_CLK_SRC 85
#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 86
#define CAM_CC_IFE_LITE_1_CSID_CLK 87
#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 88
#define CAM_CC_IFE_LITE_2_AHB_CLK 89
#define CAM_CC_IFE_LITE_2_CLK 90
#define CAM_CC_IFE_LITE_2_CLK_SRC 91
#define CAM_CC_IFE_LITE_2_CPHY_RX_CLK 92
#define CAM_CC_IFE_LITE_2_CSID_CLK 93
#define CAM_CC_IFE_LITE_2_CSID_CLK_SRC 94
#define CAM_CC_IPE_NPS_AHB_CLK 95
#define CAM_CC_IPE_NPS_CLK 96
#define CAM_CC_IPE_NPS_CLK_SRC 97
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 98
#define CAM_CC_IPE_PPS_CLK 99
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 100
#define CAM_CC_JPEG_1_CLK 101
#define CAM_CC_JPEG_CLK 102
#define CAM_CC_JPEG_CLK_SRC 103
#define CAM_CC_MCLK0_CLK 104
#define CAM_CC_MCLK0_CLK_SRC 105
#define CAM_CC_MCLK1_CLK 106
#define CAM_CC_MCLK1_CLK_SRC 107
#define CAM_CC_MCLK2_CLK 108
#define CAM_CC_MCLK2_CLK_SRC 109
#define CAM_CC_MCLK3_CLK 110
#define CAM_CC_MCLK3_CLK_SRC 111
#define CAM_CC_MCLK4_CLK 112
#define CAM_CC_MCLK4_CLK_SRC 113
#define CAM_CC_MCLK5_CLK 114
#define CAM_CC_MCLK5_CLK_SRC 115
#define CAM_CC_MCLK6_CLK 116
#define CAM_CC_MCLK6_CLK_SRC 117
#define CAM_CC_MCLK7_CLK 118
#define CAM_CC_MCLK7_CLK_SRC 119
#define CAM_CC_QDSS_DEBUG_CLK 120
#define CAM_CC_QDSS_DEBUG_CLK_SRC 121
#define CAM_CC_QDSS_DEBUG_XO_CLK 122
#define CAM_CC_SLEEP_CLK 123
#define CAM_CC_SLEEP_CLK_SRC 124
#define CAM_CC_SLOW_AHB_CLK_SRC 125
#define CAM_CC_SOC_AHB_CLK 126
#define CAM_CC_XO_CLK_SRC 127
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_CAMNOC_BCR 1
#define CAM_CC_DRV_BCR 2
#define CAM_CC_ICP_BCR 3
#define CAM_CC_IFE_0_BCR 4
#define CAM_CC_IFE_1_BCR 5
#define CAM_CC_IFE_LITE_0_BCR 6
#define CAM_CC_IFE_LITE_1_BCR 7
#define CAM_CC_IFE_LITE_2_BCR 8
#define CAM_CC_IPE_0_BCR 9
#define CAM_CC_QDSS_DEBUG_BCR 10
#define CAM_CC_TITAN_TOP_BCR 11
#endif

32
include/dt-bindings/clock/qcom,evacc-seraph.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_EVA_CC_SERAPH_H
#define _DT_BINDINGS_CLK_QCOM_EVA_CC_SERAPH_H
/* EVA_CC clocks */
#define EVA_CC_PLL0 0
#define EVA_CC_AHB_CLK 1
#define EVA_CC_AHB_CLK_SRC 2
#define EVA_CC_MVS0_CLK 3
#define EVA_CC_MVS0_CLK_SRC 4
#define EVA_CC_MVS0_DIV_CLK_SRC 5
#define EVA_CC_MVS0_FREERUN_CLK 6
#define EVA_CC_MVS0_SHIFT_CLK 7
#define EVA_CC_MVS0C_CLK 8
#define EVA_CC_MVS0C_DIV2_DIV_CLK_SRC 9
#define EVA_CC_MVS0C_FREERUN_CLK 10
#define EVA_CC_MVS0C_SHIFT_CLK 11
#define EVA_CC_SLEEP_CLK 12
#define EVA_CC_SLEEP_CLK_SRC 13
#define EVA_CC_XO_CLK 14
#define EVA_CC_XO_CLK_SRC 15
/* EVA_CC resets */
#define EVA_CC_INTERFACE_BCR 0
#define EVA_CC_MVS0_BCR 1
#define EVA_CC_MVS0C_BCR 2
#endif

219
include/dt-bindings/clock/qcom,gcc-seraph.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SERAPH_H
#define _DT_BINDINGS_CLK_QCOM_GCC_SERAPH_H
/* GCC clocks */
#define GCC_GPLL0 0
#define GCC_GPLL0_OUT_EVEN 1
#define GCC_GPLL2 2
#define GCC_GPLL4 3
#define GCC_GPLL6 4
#define GCC_GPLL7 5
#define GCC_GPLL8 6
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 7
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
#define GCC_BOOT_ROM_AHB_CLK 9
#define GCC_CAMERA_AHB_CLK 10
#define GCC_CAMERA_CTI_CLK 11
#define GCC_CAMERA_HF_AXI_CLK 12
#define GCC_CAMERA_SF_AXI_CLK 13
#define GCC_CAMERA_TSCTR_CLK 14
#define GCC_CAMERA_XO_CLK 15
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 16
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17
#define GCC_CNOC_PCIE_SF_AXI_CLK 18
#define GCC_DDRSS_PCIE_SF_QTB_CLK 19
#define GCC_DISP_0_AHB_CLK 20
#define GCC_DISP_0_HF_AXI_CLK 21
#define GCC_DISP_0_XO_CLK 22
#define GCC_DISP_SF_AXI_CLK 23
#define GCC_DISP_TSCTR_CLK 24
#define GCC_EVA_AHB_CLK 25
#define GCC_EVA_AXI0_CLK 26
#define GCC_EVA_AXI0C_CLK 27
#define GCC_EVA_XO_CLK 28
#define GCC_GP10_CLK 29
#define GCC_GP10_CLK_SRC 30
#define GCC_GP10_DIV_CLK_SRC 31
#define GCC_GP11_CLK 32
#define GCC_GP11_CLK_SRC 33
#define GCC_GP11_DIV_CLK_SRC 34
#define GCC_GP1_CLK 35
#define GCC_GP1_CLK_SRC 36
#define GCC_GP2_CLK 37
#define GCC_GP2_CLK_SRC 38
#define GCC_GP3_CLK 39
#define GCC_GP3_CLK_SRC 40
#define GCC_GP4_CLK 41
#define GCC_GP4_CLK_SRC 42
#define GCC_GP4_DIV_CLK_SRC 43
#define GCC_GP5_CLK 44
#define GCC_GP5_CLK_SRC 45
#define GCC_GP5_DIV_CLK_SRC 46
#define GCC_GP6_CLK 47
#define GCC_GP6_CLK_SRC 48
#define GCC_GP6_DIV_CLK_SRC 49
#define GCC_GP7_CLK 50
#define GCC_GP7_CLK_SRC 51
#define GCC_GP7_DIV_CLK_SRC 52
#define GCC_GP8_CLK 53
#define GCC_GP8_CLK_SRC 54
#define GCC_GP8_DIV_CLK_SRC 55
#define GCC_GP9_CLK 56
#define GCC_GP9_CLK_SRC 57
#define GCC_GP9_DIV_CLK_SRC 58
#define GCC_GPU_CFG_AHB_CLK 59
#define GCC_GPU_GPLL0_CLK_SRC 60
#define GCC_GPU_GPLL0_DIV_CLK_SRC 61
#define GCC_GPU_MEMNOC_GFX_CLK 62
#define GCC_LSR_AHB_CLK 63
#define GCC_LSR_AXI0_CLK 64
#define GCC_LSR_AXI_CV_CPU_CLK 65
#define GCC_LSR_XO_CLK 66
#define GCC_PCIE_0_AUX_CLK 67
#define GCC_PCIE_0_AUX_CLK_SRC 68
#define GCC_PCIE_0_CFG_AHB_CLK 69
#define GCC_PCIE_0_MSTR_AXI_CLK 70
#define GCC_PCIE_0_PHY_RCHNG_CLK 71
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 72
#define GCC_PCIE_0_PIPE_CLK 73
#define GCC_PCIE_0_PIPE_CLK_SRC 74
#define GCC_PCIE_0_PIPE_DIV2_CLK 75
#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 76
#define GCC_PCIE_0_SLV_AXI_CLK 77
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 78
#define GCC_PCIE_1_AUX_CLK 79
#define GCC_PCIE_1_AUX_CLK_SRC 80
#define GCC_PCIE_1_CFG_AHB_CLK 81
#define GCC_PCIE_1_MSTR_AXI_CLK 82
#define GCC_PCIE_1_PHY_RCHNG_CLK 83
#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 84
#define GCC_PCIE_1_PIPE_CLK 85
#define GCC_PCIE_1_PIPE_CLK_SRC 86
#define GCC_PCIE_1_PIPE_DIV2_CLK 87
#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 88
#define GCC_PCIE_1_SLV_AXI_CLK 89
#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 90
#define GCC_PCIE_RSCC_CFG_AHB_CLK 91
#define GCC_PCIE_RSCC_XO_CLK 92
#define GCC_PDM2_CLK 93
#define GCC_PDM2_CLK_SRC 94
#define GCC_PDM_AHB_CLK 95
#define GCC_PDM_XO4_CLK 96
#define GCC_PWM0_XO512_CLK 97
#define GCC_PWM1_XO512_CLK 98
#define GCC_PWM2_XO512_CLK 99
#define GCC_PWM3_XO512_CLK 100
#define GCC_PWM4_XO512_CLK 101
#define GCC_PWM5_XO512_CLK 102
#define GCC_PWM6_XO512_CLK 103
#define GCC_PWM7_XO512_CLK 104
#define GCC_PWM8_XO512_CLK 105
#define GCC_PWM9_XO512_CLK 106
#define GCC_QMIP_CAMERA_ICP_AHB_CLK 107
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 108
#define GCC_QMIP_CAMERA_RT_AHB_CLK 109
#define GCC_QMIP_DISP_AHB_CLK 110
#define GCC_QMIP_GPU_AHB_CLK 111
#define GCC_QMIP_PCIE_AHB_CLK 112
#define GCC_QMIP_VENUS_LSR0_AHB_CLK 113
#define GCC_QMIP_VENUS_LSR1_AHB_CLK 114
#define GCC_QMIP_VENUS_LSR_CV_CPU_AHB_CLK 115
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 116
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 117
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 118
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 119
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 120
#define GCC_QUPV3_WRAP1_CORE_CLK 121
#define GCC_QUPV3_WRAP1_S0_CLK 122
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 123
#define GCC_QUPV3_WRAP1_S1_CLK 124
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 125
#define GCC_QUPV3_WRAP1_S2_CLK 126
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 127
#define GCC_QUPV3_WRAP1_S3_CLK 128
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 129
#define GCC_QUPV3_WRAP1_S4_CLK 130
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 131
#define GCC_QUPV3_WRAP1_S5_CLK 132
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 133
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 134
#define GCC_QUPV3_WRAP2_CORE_CLK 135
#define GCC_QUPV3_WRAP2_S0_CLK 136
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 137
#define GCC_QUPV3_WRAP2_S1_CLK 138
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 139
#define GCC_QUPV3_WRAP2_S2_CLK 140
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 141
#define GCC_QUPV3_WRAP2_S3_CLK 142
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 143
#define GCC_QUPV3_WRAP2_S4_CLK 144
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 145
#define GCC_QUPV3_WRAP2_S5_CLK 146
#define GCC_QUPV3_WRAP2_S5_CLK_SRC 147
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 148
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 149
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 150
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 151
#define GCC_SDCC1_AHB_CLK 152
#define GCC_SDCC1_APPS_CLK 153
#define GCC_SDCC1_APPS_CLK_SRC 154
#define GCC_SDCC1_ICE_CORE_CLK 155
#define GCC_SDCC1_ICE_CORE_CLK_SRC 156
#define GCC_SDCC2_AHB_CLK 157
#define GCC_SDCC2_APPS_CLK 158
#define GCC_SDCC2_APPS_CLK_SRC 159
#define GCC_USB30_PRIM_ATB_CLK 160
#define GCC_USB30_PRIM_MASTER_CLK 161
#define GCC_USB30_PRIM_MASTER_CLK_SRC 162
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 163
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 164
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 165
#define GCC_USB30_PRIM_SLEEP_CLK 166
#define GCC_USB3_PRIM_PHY_AUX_CLK 167
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 168
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 169
#define GCC_USB3_PRIM_PHY_PIPE_CLK 170
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 171
#define GCC_VIDEO_AHB_CLK 172
#define GCC_VIDEO_AXI0_CLK 173
#define GCC_VIDEO_AXI1_CLK 174
#define GCC_VIDEO_XO_CLK 175
/* GCC resets */
#define GCC_CAMERA_BCR 0
#define GCC_DISPLAY_0_BCR 1
#define GCC_EVA_BCR 2
#define GCC_GPU_BCR 3
#define GCC_LSR_BCR 4
#define GCC_PCIE_0_BCR 5
#define GCC_PCIE_0_LINK_DOWN_BCR 6
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 7
#define GCC_PCIE_0_PHY_BCR 8
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 9
#define GCC_PCIE_1_BCR 10
#define GCC_PCIE_1_LINK_DOWN_BCR 11
#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 12
#define GCC_PCIE_1_PHY_BCR 13
#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 14
#define GCC_PCIE_RSCC_BCR 15
#define GCC_PDM_BCR 16
#define GCC_QUPV3_WRAPPER_1_BCR 17
#define GCC_QUPV3_WRAPPER_2_BCR 18
#define GCC_QUSB2PHY_PRIM_BCR 19
#define GCC_SDCC1_BCR 20
#define GCC_SDCC2_BCR 21
#define GCC_TCSR_PCIE_BCR 22
#define GCC_USB30_PRIM_BCR 23
#define GCC_USB3_DP_PHY_PRIM_BCR 24
#define GCC_USB3_PHY_PRIM_BCR 25
#define GCC_USB3PHY_PHY_PRIM_BCR 26
#define GCC_VIDEO_BCR 27
#define GCC_VIDEO_AXI0_CLK_ARES 28
#define GCC_VIDEO_AXI1_CLK_ARES 29
#endif

49
include/dt-bindings/clock/qcom,gpucc-seraph.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SERAPH_H
#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SERAPH_H
/* GPU_CC clocks */
#define GPU_CC_PLL0 0
#define GPU_CC_PLL0_OUT_EVEN 1
#define GPU_CC_AHB_CLK 2
#define GPU_CC_CB_CLK 3
#define GPU_CC_CX_ACCU_SHIFT_CLK 4
#define GPU_CC_CX_GMU_CLK 5
#define GPU_CC_CXO_AON_CLK 6
#define GPU_CC_CXO_CLK 7
#define GPU_CC_DEMET_CLK 8
#define GPU_CC_DEMET_DIV_CLK_SRC 9
#define GPU_CC_DPM_CLK 10
#define GPU_CC_FREQ_MEASURE_CLK 11
#define GPU_CC_GMU_CLK_SRC 12
#define GPU_CC_GX_ACCU_SHIFT_CLK 13
#define GPU_CC_GX_GMU_CLK 14
#define GPU_CC_HUB_AON_CLK 15
#define GPU_CC_HUB_CLK_SRC 16
#define GPU_CC_HUB_CX_INT_CLK 17
#define GPU_CC_HUB_DIV_CLK_SRC 18
#define GPU_CC_MEMNOC_GFX_CLK 19
#define GPU_CC_RBCPR_AHB_CLK 20
#define GPU_CC_RBCPR_CLK 21
#define GPU_CC_RBCPR_CLK_SRC 22
#define GPU_CC_RSCC_HUB_AON_CLK 23
#define GPU_CC_RSCC_XO_AON_CLK 24
#define GPU_CC_SLEEP_CLK 25
#define GPU_CC_XO_CLK_SRC 26
#define GPU_CC_XO_DIV_CLK_SRC 27
/* GPU_CC resets */
#define GPU_CC_CB_BCR 0
#define GPU_CC_CX_BCR 1
#define GPU_CC_FAST_HUB_BCR 2
#define GPU_CC_FF_BCR 3
#define GPU_CC_GMU_BCR 4
#define GPU_CC_GX_BCR 5
#define GPU_CC_RBCPR_BCR 6
#define GPU_CC_XO_BCR 7
#endif

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include/dt-bindings/clock/qcom,lsrcc-seraph.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_LSR_CC_SERAPH_H
#define _DT_BINDINGS_CLK_QCOM_LSR_CC_SERAPH_H
/* LSR_CC clocks */
#define LSR_CC_PLL0 0
#define LSR_CC_PLL1 1
#define LSR_CC_AHB_CLK 2
#define LSR_CC_AHB_CLK_SRC 3
#define LSR_CC_MVS0_CLK 4
#define LSR_CC_MVS0_CLK_SRC 5
#define LSR_CC_MVS0_FREERUN_CLK 6
#define LSR_CC_MVS0_SHIFT_CLK 7
#define LSR_CC_MVS0C_CLK 8
#define LSR_CC_MVS0C_CLK_SRC 9
#define LSR_CC_MVS0C_FREERUN_CLK 10
#define LSR_CC_MVS0C_SHIFT_CLK 11
#define LSR_CC_SLEEP_CLK 12
#define LSR_CC_SLEEP_CLK_SRC 13
#define LSR_CC_XO_CLK 14
#define LSR_CC_XO_CLK_SRC 15
/* LSR_CC resets */
#define LSR_CC_INTERFACE_BCR 0
#define LSR_CC_LSR_NOC_BCR 1
#define LSR_CC_MVS0_BCR 2
#define LSR_CC_MVS0C_BCR 3
#endif

14
include/dt-bindings/clock/qcom,tcsrcc-seraph.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_SERAPH_H
#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_SERAPH_H
/* TCSR_CC clocks */
#define TCSR_PCIE_0_CLKREF_EN 0
#define TCSR_PCIE_1_CLKREF_EN 1
#define TCSR_USB3_CLKREF_EN 2
#endif

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include/dt-bindings/clock/qcom,videocc-seraph.h Normal file
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SERAPH_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SERAPH_H
/* VIDEO_CC clocks */
#define VIDEO_CC_PLL0 0
#define VIDEO_CC_PLL1 1
#define VIDEO_CC_PLL2 2
#define VIDEO_CC_AHB_CLK 3
#define VIDEO_CC_AHB_CLK_SRC 4
#define VIDEO_CC_MVS0_CLK 5
#define VIDEO_CC_MVS0_CLK_SRC 6
#define VIDEO_CC_MVS0_FREERUN_CLK 7
#define VIDEO_CC_MVS0_SHIFT_CLK 8
#define VIDEO_CC_MVS0_VPP0_CLK 9
#define VIDEO_CC_MVS0_VPP0_FREERUN_CLK 10
#define VIDEO_CC_MVS0_VPP1_CLK 11
#define VIDEO_CC_MVS0_VPP1_FREERUN_CLK 12
#define VIDEO_CC_MVS0B_CLK 13
#define VIDEO_CC_MVS0B_CLK_SRC 14
#define VIDEO_CC_MVS0B_FREERUN_CLK 15
#define VIDEO_CC_MVS0C_CLK 16
#define VIDEO_CC_MVS0C_CLK_SRC 17
#define VIDEO_CC_MVS0C_FREERUN_CLK 18
#define VIDEO_CC_MVS0C_SHIFT_CLK 19
#define VIDEO_CC_SLEEP_CLK 20
#define VIDEO_CC_TS_XO_CLK 21
#define VIDEO_CC_XO_CLK 22
#define VIDEO_CC_XO_CLK_SRC 23
/* VIDEO_CC resets */
#define VIDEO_CC_INTERFACE_BCR 0
#define VIDEO_CC_MVS0_BCR 1
#define VIDEO_CC_MVS0_VPP0_BCR 2
#define VIDEO_CC_MVS0_VPP1_BCR 3
#define VIDEO_CC_MVS0C_BCR 4
#define VIDEO_CC_MVS0C_CLK_ARES 5
#define VIDEO_CC_XO_CLK_ARES 6
#endif