NothingOSS/android_kernel_msm-6.1_nothing_sm7635
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

- Always do default APIC routing setup so that cpumasks are properly

Browse source 
allocated and are present when later accessed ("nosmp" and x2APIC)
 
 - Clarify the bit overlap between an old APIC and a modern, integrated one
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmKL3BMACgkQEsHwGGHe
 VUrkNRAAjqxwBP28EnYvHthvbxhfsuwws+OcSm2lt5SK5WGZK+p1pnDrPvxSawF8
 t7O1oyIJfSaFmEPqs52Z/dj7noKJPBhDNoevmDVTmfQZkGvpDT1xjBATfABjbsnf
 SGUXK6c8rg20afGiOO9GLL7DB/zArDRdf/2fpn6f+1I5tJCAurnjp9A1ssZw3KBl
 m5plwaoQSsyCkqJtpT+Q5Mu9fyfaqTPPMBJrPi0tbRlVjryXJh7GW31TQfmHn3V7
 wDUvtfD2kY9kzs/EHL3ilxmnlLfCya5f1kW76z5Yek3GkxCoMD0vFYJ0VUTd8KFf
 mi7e2w4L1x6fyYiNKaMEeoml1aed03qifcdXF9Gv+t6fRdzmWwo1IgzQq+gu+WQ4
 p8U6GfzbXPN92xQfEsq7n7jmiKNL5S0e+VHFHE0xV1YxmEELwH5nURnk7g/idjZS
 IJWhR3xNBtsFxHr/JmfGbk8qPBMNX6B2W0sVkIC9Zc0gDr9v5Gw06fYh/venSiOC
 ePOO/RsMDftFBsHipc8o5IdkZXmr487hThNyt1vFZCL7V0TE3Vsw+aU9btzpBoz9
 t4QuZw+iO6Z0SZy6Jt/27cp43Ky5Jp/ry+HNQmfFwDaXnh0ZeYQOZOMVgvODBmaw
 N4qblX8UDd8+gtR7W9EDyXu+9UK35Nh3VbUO8MfOCRp2EaZqk/U=
 =fkbm
 -----END PGP SIGNATURE-----

Merge tag 'x86_apic_for_v5.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 APIC updates from Borislav Petkov:

 - Always do default APIC routing setup so that cpumasks are properly
   allocated and are present when later accessed ("nosmp" and x2APIC)

 - Clarify the bit overlap between an old APIC and a modern, integrated
   one

* tag 'x86_apic_for_v5.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/apic: Do apic driver probe for "nosmp" use case
  x86/apic: Clarify i82489DX bit overlap in APIC_LVT0
This commit is contained in:
Linus Torvalds 2022-05-23 19:16:09 -07:00
commit 9166542010
2 changed files with 12 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

6
arch/x86/include/asm/apicdef.h
View file

@ -95,12 +95,6 @@
#define APIC_LVTTHMR 0x330
#define APIC_LVTPC 0x340
#define APIC_LVT0 0x350
#define APIC_LVT_TIMER_BASE_MASK (0x3 << 18)
#define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3)
#define SET_APIC_TIMER_BASE(x) (((x) << 18))
#define APIC_TIMER_BASE_CLKIN 0x0
#define APIC_TIMER_BASE_TMBASE 0x1
#define APIC_TIMER_BASE_DIV 0x2
#define APIC_LVT_TIMER_ONESHOT (0 << 17)
#define APIC_LVT_TIMER_PERIODIC (1 << 17)
#define APIC_LVT_TIMER_TSCDEADLINE (2 << 17)

16
arch/x86/kernel/apic/apic.c
View file

@ -320,6 +320,9 @@ int lapic_get_maxlvt(void)
#define APIC_DIVISOR 16
#define TSC_DIVISOR 8
/* i82489DX specific */
#define I82489DX_BASE_DIVIDER (((0x2) << 18))
/*
* This function sets up the local APIC timer, with a timeout of
* 'clocks' APIC bus clock. During calibration we actually call
@ -340,8 +343,14 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
/*
* The i82489DX APIC uses bit 18 and 19 for the base divider. This
* overlaps with bit 18 on integrated APICs, but is not documented
* in the SDM. No problem though. i82489DX equipped systems do not
* have TSC deadline timer.
*/
if (!lapic_is_integrated())
lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
lvtt_value |= I82489DX_BASE_DIVIDER;
if (!irqen)
lvtt_value |= APIC_LVT_MASKED;
@ -1419,22 +1428,21 @@ void __init apic_intr_mode_init(void)
return;
case APIC_VIRTUAL_WIRE:
pr_info("APIC: Switch to virtual wire mode setup\n");
default_setup_apic_routing();
break;
case APIC_VIRTUAL_WIRE_NO_CONFIG:
pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
upmode = true;
default_setup_apic_routing();
break;
case APIC_SYMMETRIC_IO:
pr_info("APIC: Switch to symmetric I/O mode setup\n");
default_setup_apic_routing();
break;
case APIC_SYMMETRIC_IO_NO_ROUTING:
pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
break;
}
default_setup_apic_routing();
if (x86_platform.apic_post_init)
x86_platform.apic_post_init();