pci: msm: Add support for APSS based L1ss sleep
Few PCIe endpoints like NVMe are always expecting the device to be in D0 state and the link to be active (or in l1ss) all the time (including in S3 state). Some NVMe endpoints are treating link down as power cycle, So turning off the link during S3 can reduce life span of the NVMe. For that reason adding apss-based l1ss-sleep support. With this, all the PCIe resources can be turned off after link has entered into L1ss in the suspend path. This meets NVMe requirements and also at the same time lets the system go to XO shutdown. Change-Id: I0d28567d37c1a4cfbfdc9294a132078b5c53e10d Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
This commit is contained in:
Paras Sharma
parent
1d8860003e
commit
a51213fac9
1 changed files with 211 additions and 0 deletions
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@ -267,6 +267,10 @@
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#define MSM_PCIE_MAX_PIPE_RESET (1)
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#define MSM_PCIE_MAX_LINKDOWN_RESET (2)
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/* QPHY_POWER_DOWN_CONTROL */
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#define MSM_PCIE_PHY_SW_PWRDN BIT(0)
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#define MSM_PCIE_PHY_REFCLK_DRV_DSBL BIT(1)
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/* QPHY_START_CONTROL bits */
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#define ICC_AVG_BW (500)
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#define ICC_PEAK_BW (800)
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@ -276,6 +280,9 @@
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#define L23_READY_POLL_TIMEOUT (100000)
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#define L1SS_POLL_INTERVAL_US (1000)
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#define L1SS_POLL_TIMEOUT_US (200000)
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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#define PCIE_UPPER_ADDR(addr) ((u32)((addr) >> 32))
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#else
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@ -1058,6 +1065,7 @@ struct msm_pcie_dev_t {
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struct clk *ref_clk_src;
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bool cfg_access;
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bool apss_based_l1ss_sleep;
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spinlock_t cfg_lock;
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unsigned long irqsave_flags;
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struct mutex enumerate_lock;
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@ -4100,6 +4108,49 @@ static int msm_pcie_vreg_init(struct msm_pcie_dev_t *dev)
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return rc;
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}
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static void msm_pcie_vreg_init_analog_rails(struct msm_pcie_dev_t *dev)
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{
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int i, rc;
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for (i = 0; i < MSM_PCIE_MAX_VREG; i++) {
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if (dev->vreg[i].hdl) {
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/*
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* Enable all the voltage regulators except the 3p3 regulator,
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* as 3p3 is main power supply for some endpoints like NVMe.
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*/
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if (strcmp(dev->vreg[i].name, "vreg-3p3")) {
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PCIE_DBG(dev, "Vreg %s is being enabled\n",
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dev->vreg[i].name);
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rc = regulator_enable(dev->vreg[i].hdl);
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if (rc) {
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PCIE_ERR(dev,
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"PCIe: RC%d can't enable regulator %s: %d\n",
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dev->rc_idx, dev->vreg[i].name, rc);
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}
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}
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}
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}
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}
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static void msm_pcie_vreg_deinit_analog_rails(struct msm_pcie_dev_t *dev)
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{
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int i;
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for (i = MSM_PCIE_MAX_VREG - 1; i >= 0; i--) {
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if (dev->vreg[i].hdl) {
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/*
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* Disable all the voltage regulators except the 3p3 regulator,
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* as 3p3 is main power supply for some endpoints like NVMe.
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*/
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if (strcmp(dev->vreg[i].name, "vreg-3p3")) {
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PCIE_DBG(dev, "Vreg %s is being disabled\n",
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dev->vreg[i].name);
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regulator_disable(dev->vreg[i].hdl);
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}
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}
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}
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}
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static void msm_pcie_vreg_deinit(struct msm_pcie_dev_t *dev)
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{
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int i, ret;
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@ -7867,6 +7918,8 @@ static void msm_pcie_read_dt(struct msm_pcie_dev_t *pcie_dev, int rc_idx,
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pcie_dev->l1_1_pcipm_supported = pcie_dev->l1ss_supported;
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pcie_dev->l1_2_pcipm_supported = pcie_dev->l1ss_supported;
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pcie_dev->apss_based_l1ss_sleep = of_property_read_bool(of_node,
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"qcom,apss-based-l1ss-sleep");
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of_property_read_u32(of_node, "qcom,l1-2-th-scale",
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&pcie_dev->l1_2_th_scale);
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of_property_read_u32(of_node, "qcom,l1-2-th-value",
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@ -8779,6 +8832,163 @@ out:
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}
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EXPORT_SYMBOL(msm_pcie_set_link_bandwidth);
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static int __maybe_unused msm_pcie_pm_suspend_noirq(struct device *dev)
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{
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u32 val;
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int ret_l1ss, i, rc;
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unsigned long irqsave_flags;
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struct msm_pcie_dev_t *pcie_dev = (struct msm_pcie_dev_t *)
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dev_get_drvdata(dev);
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PCIE_DBG(pcie_dev, "RC%d: entry\n", pcie_dev->rc_idx);
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mutex_lock(&pcie_dev->recovery_lock);
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if (pcie_dev->enumerated && pcie_dev->power_on &&
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pcie_dev->apss_based_l1ss_sleep) {
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ret_l1ss = readl_poll_timeout((pcie_dev->parf
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+ PCIE20_PARF_PM_STTS), val, (val & BIT(8)), L1SS_POLL_INTERVAL_US,
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L1SS_POLL_TIMEOUT_US);
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if (!ret_l1ss) {
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PCIE_DBG(pcie_dev, "RC%d: Link is in L1ss\n",
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pcie_dev->rc_idx);
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} else {
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PCIE_INFO(pcie_dev, "RC%d: Link is not in L1ss\n",
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pcie_dev->rc_idx);
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mutex_unlock(&pcie_dev->recovery_lock);
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PCIE_DBG(pcie_dev, "RC%d: exit\n", pcie_dev->rc_idx);
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return 0;
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}
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pcie_dev->power_on = false;
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pcie_dev->user_suspend = true;
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spin_lock_irqsave(&pcie_dev->irq_lock, irqsave_flags);
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pcie_dev->suspending = true;
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spin_unlock_irqrestore(&pcie_dev->irq_lock, irqsave_flags);
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spin_lock_irqsave(&pcie_dev->cfg_lock,
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pcie_dev->irqsave_flags);
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pcie_dev->cfg_access = false;
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spin_unlock_irqrestore(&pcie_dev->cfg_lock,
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pcie_dev->irqsave_flags);
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if (!pcie_dev->lpi_enable)
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msm_msi_config_access(dev_get_msi_domain(&pcie_dev->dev->dev),
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false);
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if (pcie_dev->phy_power_down_offset)
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msm_pcie_write_reg(pcie_dev->phy, pcie_dev->phy_power_down_offset, 0);
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for (i = 0; i < pcie_dev->num_clk; i++)
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if (pcie_dev->clk[i].hdl)
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clk_disable_unprepare(pcie_dev->clk[i].hdl);
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rc = msm_pcie_icc_vote(pcie_dev, 0, 0, false);
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if (rc)
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goto out;
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msm_pcie_pipe_clk_deinit(pcie_dev);
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msm_pcie_vreg_deinit_analog_rails(pcie_dev);
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}
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mutex_unlock(&pcie_dev->recovery_lock);
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PCIE_DBG(pcie_dev, "RC%d: exit\n", pcie_dev->rc_idx);
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return 0;
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out:
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mutex_unlock(&pcie_dev->recovery_lock);
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return rc;
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}
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static int __maybe_unused msm_pcie_pm_resume_noirq(struct device *dev)
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{
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int i, rc;
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unsigned long irqsave_flags;
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struct msm_pcie_dev_t *pcie_dev = (struct msm_pcie_dev_t *)
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dev_get_drvdata(dev);
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PCIE_DBG(pcie_dev, "RC%d: entry\n", pcie_dev->rc_idx);
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mutex_lock(&pcie_dev->recovery_lock);
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if (pcie_dev->enumerated && !pcie_dev->power_on &&
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pcie_dev->apss_based_l1ss_sleep) {
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msm_pcie_vreg_init_analog_rails(pcie_dev);
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rc = msm_pcie_icc_vote(pcie_dev, ICC_AVG_BW, ICC_PEAK_BW, false);
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if (rc)
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goto out;
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for (i = 0; i < pcie_dev->num_clk; i++) {
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if (pcie_dev->clk[i].hdl) {
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rc = clk_prepare_enable(pcie_dev->clk[i].hdl);
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if (rc)
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PCIE_ERR(pcie_dev, "PCIe: RC%d failed to enable clk %s\n",
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pcie_dev->rc_idx, pcie_dev->clk[i].name);
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else
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PCIE_DBG2(pcie_dev, "enable clk %s for RC%d.\n",
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pcie_dev->clk[i].name, pcie_dev->rc_idx);
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}
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}
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PCIE_DBG2(pcie_dev, "PCIe: RC%d: successfully set ICC path vote\n",
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pcie_dev->rc_idx);
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msm_pcie_pipe_clk_init(pcie_dev);
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if (pcie_dev->phy_power_down_offset)
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msm_pcie_write_reg(pcie_dev->phy, pcie_dev->phy_power_down_offset,
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MSM_PCIE_PHY_SW_PWRDN | MSM_PCIE_PHY_REFCLK_DRV_DSBL);
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pcie_dev->power_on = true;
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pcie_dev->user_suspend = false;
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spin_lock_irqsave(&pcie_dev->irq_lock, irqsave_flags);
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pcie_dev->suspending = false;
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spin_unlock_irqrestore(&pcie_dev->irq_lock, irqsave_flags);
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spin_lock_irqsave(&pcie_dev->cfg_lock,
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pcie_dev->irqsave_flags);
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pcie_dev->cfg_access = true;
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spin_unlock_irqrestore(&pcie_dev->cfg_lock,
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pcie_dev->irqsave_flags);
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if (!pcie_dev->lpi_enable)
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msm_msi_config_access(dev_get_msi_domain(&pcie_dev->dev->dev),
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true);
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}
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mutex_unlock(&pcie_dev->recovery_lock);
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PCIE_DBG(pcie_dev, "RC%d: exit\n", pcie_dev->rc_idx);
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return 0;
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out:
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mutex_unlock(&pcie_dev->recovery_lock);
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return rc;
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}
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static const struct dev_pm_ops qcom_pcie_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(msm_pcie_pm_suspend_noirq, msm_pcie_pm_resume_noirq)
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};
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static int msm_pci_probe(struct pci_dev *pci_dev,
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const struct pci_device_id *device_id)
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{
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@ -8831,6 +9041,7 @@ static struct platform_driver msm_pcie_driver = {
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.remove = msm_pcie_remove,
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.driver = {
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.name = "pci-msm",
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.pm = &qcom_pcie_pm_ops,
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.of_match_table = msm_pcie_match,
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},
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};
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