ASoC: cs42l42: Ensure a reset pulse meets minimum pulse width.
[ Upstream commit 41dac81b56c82c51a6d00fda5f3af7691ffee2d7 ] The CS42L42 can accept very short reset pulses of a few microseconds but there's no reason to force a very short pulse. Allow a wide range for the usleep_range() so it can be relaxed about the choice of timing source. Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Signed-off-by: Stefan Binding <sbinding@opensource.cirrus.com> Link: https://lore.kernel.org/r/20230913150012.604775-2-sbinding@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -2280,6 +2280,10 @@ int cs42l42_common_probe(struct cs42l42_private *cs42l42,
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if (cs42l42->reset_gpio) {
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dev_dbg(cs42l42->dev, "Found reset GPIO\n");
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/* Ensure minimum reset pulse width */
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usleep_range(10, 500);
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gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
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}
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usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
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