From d874b8f3b2cac41b277c208a438000c6f29a9a77 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Thu, 11 Mar 2021 16:37:45 +0530 Subject: [PATCH 1/2] drivers: pinctrl: Add support to access tlmm spare registers Add support to read and write SPARE registers in TLMM block. Change-Id: I6426b86510256983b509c5f48c2ab02f80b48ef8 Signed-off-by: Mayank Grover Signed-off-by: kamasali --- drivers/pinctrl/qcom/pinctrl-msm.c | 40 ++++++++++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-msm.h | 12 +++++++++ include/linux/pinctrl/qcom-pinctrl.h | 4 +++ 3 files changed, 56 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index e4629101458d..42098f035a58 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -38,6 +38,7 @@ #define DEFAULT_REG_SIZE_4K 1 #define PS_HOLD_OFFSET 0x820 #define QUP_MASK GENMASK(5, 0) +#define SPARE_MASK GENMASK(15, 8) /** * struct msm_pinctrl - state for a pinctrl-msm device @@ -1766,6 +1767,45 @@ int msm_qup_read(unsigned int mode) } EXPORT_SYMBOL(msm_qup_read); +int msm_spare_write(int spare_reg, u32 val) +{ + u32 offset; + const struct msm_spare_tlmm *regs = msm_pinctrl_data->soc->spare_regs; + int num_regs = msm_pinctrl_data->soc->nspare_regs; + + if (!regs || spare_reg >= num_regs) + return -ENOENT; + + offset = regs[spare_reg].offset; + if (offset != 0) { + writel_relaxed(val & SPARE_MASK, + msm_pinctrl_data->regs[0] + offset); + return 0; + } + + return -ENOENT; +} +EXPORT_SYMBOL(msm_spare_write); + +int msm_spare_read(int spare_reg) +{ + u32 offset, val; + const struct msm_spare_tlmm *regs = msm_pinctrl_data->soc->spare_regs; + int num_regs = msm_pinctrl_data->soc->nspare_regs; + + if (!regs || spare_reg >= num_regs) + return -ENOENT; + + offset = regs[spare_reg].offset; + if (offset != 0) { + val = readl_relaxed(msm_pinctrl_data->regs[0] + offset); + return val & SPARE_MASK; + } + + return -ENOENT; +} +EXPORT_SYMBOL(msm_spare_read); + int msm_pinctrl_probe(struct platform_device *pdev, const struct msm_pinctrl_soc_data *soc_data) { diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h index 9bdb03d6ceec..55f69689bd2d 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.h +++ b/drivers/pinctrl/qcom/pinctrl-msm.h @@ -128,6 +128,16 @@ struct pinctrl_qup { u32 offset; }; +/* + * struct msm_spare_tlmm - TLMM spare registers config + * @spare_reg: spare register number + * @offset: Offset of spare register + */ +struct msm_spare_tlmm { + int spare_reg; + u32 offset; +}; + /** * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration * @pins: An array describing all pins the pin controller affects. @@ -172,6 +182,8 @@ struct msm_pinctrl_soc_data { unsigned int gpio_func; unsigned int egpio_func; u32 *dir_conn_addr; + const struct msm_spare_tlmm *spare_regs; + unsigned int nspare_regs; }; extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops; diff --git a/include/linux/pinctrl/qcom-pinctrl.h b/include/linux/pinctrl/qcom-pinctrl.h index 20faa65bd587..9bef8162ec06 100644 --- a/include/linux/pinctrl/qcom-pinctrl.h +++ b/include/linux/pinctrl/qcom-pinctrl.h @@ -17,5 +17,9 @@ int msm_gpio_mpm_wake_set(unsigned int gpio, bool enable); /* API to get gpio pin address */ bool msm_gpio_get_pin_address(unsigned int gpio, struct resource *res); +/* APIS to TLMM Spare registers */ +int msm_spare_write(int spare_reg, u32 val); +int msm_spare_read(int spare_reg); + #endif /* __LINUX_PINCTRL_MSM_H__ */ From c6bb74e540d3b160d01d30a8af74d1f864545d59 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Thu, 18 Mar 2021 11:50:21 +0530 Subject: [PATCH 2/2] pinctrl: qcom: Add blair tlmm spare registers Add support to enable access for tlmm spare registers for blair. Change-Id: I250c0fd796ca80e019c6d5732394817c7527cc1c Signed-off-by: Mayank Grover --- drivers/pinctrl/qcom/pinctrl-blair.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-blair.c b/drivers/pinctrl/qcom/pinctrl-blair.c index cd8ad1aa8969..da1f27305126 100644 --- a/drivers/pinctrl/qcom/pinctrl-blair.c +++ b/drivers/pinctrl/qcom/pinctrl-blair.c @@ -119,7 +119,23 @@ .offset = qup_offset, \ } +#define TLMM_NORTH_SPARE_OFFSET 0x1B3000 +#define TLMM_NORTH_SPARE1_OFFSET 0x1B4000 +#define SPARE_REG(sparereg, spare_offset) \ + { \ + .spare_reg = tlmm_##sparereg, \ + .offset = spare_offset, \ + } + +enum blair_tlmm_spare { + tlmm_west_spare, + tlmm_west_spare1, + tlmm_north_spare, + tlmm_north_spare1, + tlmm_south_spare, + tlmm_south_spare1, +}; static const struct pinctrl_pin_desc blair_pins[] = { PINCTRL_PIN(0, "GPIO_0"), @@ -1313,6 +1329,15 @@ static const struct msm_function blair_functions[] = { FUNCTION(USB_PHY), }; +static const struct msm_spare_tlmm blair_spare_regs[] = { + SPARE_REG(west_spare, 0), + SPARE_REG(west_spare1, 0), + SPARE_REG(north_spare, TLMM_NORTH_SPARE_OFFSET), + SPARE_REG(north_spare1, TLMM_NORTH_SPARE1_OFFSET), + SPARE_REG(south_spare, 0), + SPARE_REG(south_spare1, 0), +}; + /* Every pin is maintained as a single group, and missing or non-existing pin * would be maintained as dummy group to synchronize pin group index with * pin descriptor registered with pinctrl core. @@ -1653,6 +1678,8 @@ static const struct msm_pinctrl_soc_data blair_pinctrl = { .ngpios = 157, .wakeirq_map = blair_mpm_map, .nwakeirq_map = ARRAY_SIZE(blair_mpm_map), + .spare_regs = blair_spare_regs, + .nspare_regs = ARRAY_SIZE(blair_spare_regs), }; static int blair_pinctrl_probe(struct platform_device *pdev)