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drm/amd/display: Fix possible underflow for displays with large vblank

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[ Upstream commit 1a4bcdbea4319efeb26cc4b05be859a7867e02dc ]

[Why]
Underflow observed when using a display with a large vblank region
and low refresh rate

[How]
Simplify calculation of vblank_nom

Increase value for VBlankNomDefaultUS to 800us

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stable-dep-of: 2a9482e55968 ("drm/amd/display: Prevent vtotal from being set to 0")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Daniel Miess 2023-04-25 14:29:48 -04:00 • committed by Greg Kroah-Hartman
parent 342ec1696d
commit d5741133e6
1 changed files with 7 additions and 12 deletions
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19
drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c
View file

@ -32,7 +32,7 @@
#include "dml/display_mode_vba.h" #include "dml/display_mode_vba.h"
struct _vcs_dpi_ip_params_st dcn3_14_ip = { struct _vcs_dpi_ip_params_st dcn3_14_ip = {
.VBlankNomDefaultUS = 668, .VBlankNomDefaultUS = 800,
.gpuvm_enable = 1, .gpuvm_enable = 1,
.gpuvm_max_page_table_levels = 1, .gpuvm_max_page_table_levels = 1,
.hostvm_enable = 1, .hostvm_enable = 1,
@ -288,7 +288,7 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c
struct resource_context *res_ctx = &context->res_ctx; struct resource_context *res_ctx = &context->res_ctx;
struct pipe_ctx *pipe; struct pipe_ctx *pipe;
bool upscaled = false; bool upscaled = false;
bool isFreesyncVideo = false; const unsigned int max_allowed_vblank_nom = 1023;
dc_assert_fp_enabled(); dc_assert_fp_enabled();
@ -302,16 +302,11 @@ int dcn314_populate_dml_pipes_from_context_fpu(struct dc *dc, struct dc_state *c
pipe = &res_ctx->pipe_ctx[i]; pipe = &res_ctx->pipe_ctx[i];
timing = &pipe->stream->timing; timing = &pipe->stream->timing;
isFreesyncVideo = pipe->stream->adjust.v_total_max == pipe->stream->adjust.v_total_min; pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min;
isFreesyncVideo = isFreesyncVideo && pipe->stream->adjust.v_total_min > timing->v_total; pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, dcn3_14_ip.VBlankNomDefaultUS);
if (!isFreesyncVideo) { pipes[pipe_cnt].pipe.dest.vblank_nom = max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width);
pipes[pipe_cnt].pipe.dest.vblank_nom = pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblank_nom);
dcn3_14_ip.VBlankNomDefaultUS / (timing->h_total / (timing->pix_clk_100hz / 10000.0));
} else {
pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min;
pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive;
}
if (pipe->plane_state && if (pipe->plane_state &&
(pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height || (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||