Merge "clk: qcom: niobe: Remove gpu ff clocks support"
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d694f9c51e
2 changed files with 35 additions and 122 deletions
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@ -838,22 +838,22 @@ static struct clk_debug_mux gcc_debug_mux = {
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static const char *const gpu_cc_debug_mux_parent_names[] = {
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"gpu_cc_ahb_clk",
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"gpu_cc_cx_accu_shift_clk",
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"gpu_cc_cx_ff_clk",
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"gpu_cc_cx_gmu_clk",
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"gpu_cc_cxo_clk",
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"gpu_cc_freq_measure_clk",
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"gpu_cc_gx_accu_shift_clk",
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"gpu_cc_gx_acd_ahb_ff_clk",
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"gpu_cc_gx_gmu_clk",
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"gpu_cc_gx_rcg_ahb_ff_clk",
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"gpu_cc_hub_aon_clk",
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"gpu_cc_hub_cx_int_clk",
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"gpu_cc_memnoc_gfx_clk",
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"gx_clkctl_debug_mux",
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"measure_only_gpu_cc_cb_clk",
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"measure_only_gpu_cc_cx_ff_clk",
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"measure_only_gpu_cc_cxo_aon_clk",
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"measure_only_gpu_cc_demet_clk",
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"measure_only_gpu_cc_gx_acd_ahb_ff_clk",
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"measure_only_gpu_cc_gx_ahb_ff_clk",
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"measure_only_gpu_cc_gx_rcg_ahb_ff_clk",
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"measure_only_gpu_cc_rscc_hub_aon_clk",
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"measure_only_gpu_cc_rscc_xo_aon_clk",
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"measure_only_gpu_cc_sleep_clk",
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@ -862,22 +862,22 @@ static const char *const gpu_cc_debug_mux_parent_names[] = {
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static int gpu_cc_debug_mux_sels[] = {
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0x17, /* gpu_cc_ahb_clk */
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0x24, /* gpu_cc_cx_accu_shift_clk */
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0x20, /* gpu_cc_cx_ff_clk */
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0x1D, /* gpu_cc_cx_gmu_clk */
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0x1E, /* gpu_cc_cxo_clk */
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0xF, /* gpu_cc_freq_measure_clk */
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0x15, /* gpu_cc_gx_accu_shift_clk */
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0x13, /* gpu_cc_gx_acd_ahb_ff_clk */
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0x11, /* gpu_cc_gx_gmu_clk */
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0x14, /* gpu_cc_gx_rcg_ahb_ff_clk */
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0x2A, /* gpu_cc_hub_aon_clk */
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0x1F, /* gpu_cc_hub_cx_int_clk */
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0x21, /* gpu_cc_memnoc_gfx_clk */
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0xB, /* gx_clkctl_debug_mux */
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0x28, /* measure_only_gpu_cc_cb_clk */
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0x20, /* measure_only_gpu_cc_cx_ff_clk */
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0xE, /* measure_only_gpu_cc_cxo_aon_clk */
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0x10, /* measure_only_gpu_cc_demet_clk */
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0x13, /* measure_only_gpu_cc_gx_acd_ahb_ff_clk */
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0x12, /* measure_only_gpu_cc_gx_ahb_ff_clk */
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0x14, /* measure_only_gpu_cc_gx_rcg_ahb_ff_clk */
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0x29, /* measure_only_gpu_cc_rscc_hub_aon_clk */
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0xD, /* measure_only_gpu_cc_rscc_xo_aon_clk */
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0x1B, /* measure_only_gpu_cc_sleep_clk */
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@ -1199,6 +1199,14 @@ static struct clk_dummy measure_only_gpu_cc_cb_clk = {
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},
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};
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static struct clk_dummy measure_only_gpu_cc_cx_ff_clk = {
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.rrate = 1000,
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.hw.init = &(const struct clk_init_data){
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.name = "measure_only_gpu_cc_cx_ff_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gpu_cc_cxo_aon_clk = {
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.rrate = 1000,
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.hw.init = &(const struct clk_init_data){
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@ -1215,6 +1223,14 @@ static struct clk_dummy measure_only_gpu_cc_demet_clk = {
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},
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};
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static struct clk_dummy measure_only_gpu_cc_gx_acd_ahb_ff_clk = {
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.rrate = 1000,
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.hw.init = &(const struct clk_init_data){
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.name = "measure_only_gpu_cc_gx_acd_ahb_ff_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gpu_cc_gx_ahb_ff_clk = {
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.rrate = 1000,
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.hw.init = &(const struct clk_init_data){
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@ -1223,6 +1239,14 @@ static struct clk_dummy measure_only_gpu_cc_gx_ahb_ff_clk = {
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},
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};
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static struct clk_dummy measure_only_gpu_cc_gx_rcg_ahb_ff_clk = {
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.rrate = 1000,
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.hw.init = &(const struct clk_init_data){
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.name = "measure_only_gpu_cc_gx_rcg_ahb_ff_clk",
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.ops = &clk_dummy_ops,
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},
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};
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static struct clk_dummy measure_only_gpu_cc_rscc_hub_aon_clk = {
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.rrate = 1000,
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.hw.init = &(const struct clk_init_data){
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@ -1479,9 +1503,12 @@ static struct clk_hw *debugcc_niobe_hws[] = {
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&measure_only_gcc_video_ahb_clk.hw,
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&measure_only_gcc_video_xo_clk.hw,
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&measure_only_gpu_cc_cb_clk.hw,
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&measure_only_gpu_cc_cx_ff_clk.hw,
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&measure_only_gpu_cc_cxo_aon_clk.hw,
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&measure_only_gpu_cc_demet_clk.hw,
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&measure_only_gpu_cc_gx_acd_ahb_ff_clk.hw,
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&measure_only_gpu_cc_gx_ahb_ff_clk.hw,
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&measure_only_gpu_cc_gx_rcg_ahb_ff_clk.hw,
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&measure_only_gpu_cc_rscc_hub_aon_clk.hw,
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&measure_only_gpu_cc_rscc_xo_aon_clk.hw,
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&measure_only_gpu_cc_sleep_clk.hw,
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@ -21,24 +21,9 @@
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#include "vdd-level.h"
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_LOW_L1 + 1, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_gfx, VDD_LOWER + 1, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mx, VDD_LOW_L1 + 1, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mxc, VDD_LOWER + 1, 1, vdd_corner);
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static struct clk_vdd_class *gpu_cc_niobe_regulators[] = {
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&vdd_cx,
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&vdd_gfx,
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&vdd_mx,
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&vdd_mxc,
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};
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static struct clk_vdd_class *gpu_cc_niobe_regulators_1[] = {
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&vdd_cx,
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&vdd_gfx,
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&vdd_mxc,
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};
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static struct clk_vdd_class *gpu_cc_niobe_regulators_2[] = {
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&vdd_cx,
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&vdd_mx,
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};
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@ -123,18 +108,6 @@ static struct clk_alpha_pll_postdiv gpu_cc_pll0_out_even = {
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},
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "gpll0_out_main" },
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{ .fw_name = "gpll0_out_main_div" },
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};
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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@ -153,35 +126,6 @@ static const struct clk_parent_data gpu_cc_parent_data_1[] = {
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{ .fw_name = "gpll0_out_main_div" },
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};
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static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = {
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_ff_clk_src = {
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.cmd_rcgr = 0x9474,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_ff_clk_src,
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.enable_safe_config = true,
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.flags = HW_CLK_CTRL_MODE,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "gpu_cc_ff_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_classes = gpu_cc_niobe_regulators_1,
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.num_vdd_classes = ARRAY_SIZE(gpu_cc_niobe_regulators_1),
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 200000000},
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},
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(350000000, P_GPU_CC_PLL0_OUT_EVEN, 1, 0, 0),
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@ -206,8 +150,8 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_classes = gpu_cc_niobe_regulators_2,
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.num_vdd_classes = ARRAY_SIZE(gpu_cc_niobe_regulators_2),
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.vdd_classes = gpu_cc_niobe_regulators,
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.num_vdd_classes = ARRAY_SIZE(gpu_cc_niobe_regulators),
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 350000000,
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@ -294,24 +238,6 @@ static struct clk_branch gpu_cc_cx_accu_shift_clk = {
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},
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};
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static struct clk_branch gpu_cc_cx_ff_clk = {
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.halt_reg = 0x90ec,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x90ec,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_cc_cx_ff_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_ff_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x90d4,
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.halt_check = BRANCH_HALT_VOTED,
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@ -370,24 +296,6 @@ static struct clk_branch gpu_cc_gx_accu_shift_clk = {
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},
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};
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static struct clk_branch gpu_cc_gx_acd_ahb_ff_clk = {
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.halt_reg = 0x9068,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x9068,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_cc_gx_acd_ahb_ff_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_ff_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_gmu_clk = {
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.halt_reg = 0x9060,
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.halt_check = BRANCH_HALT,
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@ -406,24 +314,6 @@ static struct clk_branch gpu_cc_gx_gmu_clk = {
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},
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};
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static struct clk_branch gpu_cc_gx_rcg_ahb_ff_clk = {
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.halt_reg = 0x906c,
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.halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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.enable_reg = 0x906c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "gpu_cc_gx_rcg_ahb_ff_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&gpu_cc_ff_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
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.halt_reg = 0x7000,
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.halt_check = BRANCH_HALT_VOTED,
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@ -489,16 +379,12 @@ static struct clk_branch gpu_cc_memnoc_gfx_clk = {
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static struct clk_regmap *gpu_cc_niobe_clocks[] = {
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[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
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[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr,
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[GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
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[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
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[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
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[GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
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[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
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[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
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[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr,
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[GPU_CC_GX_ACD_AHB_FF_CLK] = &gpu_cc_gx_acd_ahb_ff_clk.clkr,
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[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
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[GPU_CC_GX_RCG_AHB_FF_CLK] = &gpu_cc_gx_rcg_ahb_ff_clk.clkr,
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[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
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[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
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[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
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