diff --git a/include/dt-bindings/clock/qcom,gcc-direwolf.h b/include/dt-bindings/clock/qcom,gcc-direwolf.h new file mode 100644 index 000000000000..8122a0a78c6c --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-direwolf.h @@ -0,0 +1,481 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H +#define _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL2 2 +#define GCC_GPLL4 3 +#define GCC_GPLL7 4 +#define GCC_GPLL8 5 +#define GCC_GPLL9 6 +#define GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK 7 +#define GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK 8 +#define GCC_AGGRE_NOC_PCIE_4_AXI_CLK 9 +#define GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK 10 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 11 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 12 +#define GCC_AGGRE_USB3_MP_AXI_CLK 13 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 14 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 15 +#define GCC_AGGRE_USB4_1_AXI_CLK 16 +#define GCC_AGGRE_USB4_AXI_CLK 17 +#define GCC_AGGRE_USB_NOC_AXI_CLK 18 +#define GCC_AGGRE_USB_NOC_NORTH_AXI_CLK 19 +#define GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK 20 +#define GCC_AHB2PHY0_CLK 21 +#define GCC_AHB2PHY2_CLK 22 +#define GCC_BOOT_ROM_AHB_CLK 23 +#define GCC_CAMERA_AHB_CLK 24 +#define GCC_CAMERA_HF_AXI_CLK 25 +#define GCC_CAMERA_SF_AXI_CLK 26 +#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 27 +#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 28 +#define GCC_CAMERA_THROTTLE_XO_CLK 29 +#define GCC_CAMERA_XO_CLK 30 +#define GCC_CFG_NOC_USB3_MP_AXI_CLK 31 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 32 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 33 +#define GCC_CNOC_PCIE0_TUNNEL_CLK 34 +#define GCC_CNOC_PCIE1_TUNNEL_CLK 35 +#define GCC_CNOC_PCIE4_QX_CLK 36 +#define GCC_DDRSS_GPU_AXI_CLK 37 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 38 +#define GCC_DISP1_AHB_CLK 39 +#define GCC_DISP1_HF_AXI_CLK 40 +#define GCC_DISP1_SF_AXI_CLK 41 +#define GCC_DISP1_THROTTLE_NRT_AXI_CLK 42 +#define GCC_DISP1_THROTTLE_RT_AXI_CLK 43 +#define GCC_DISP1_XO_CLK 44 +#define GCC_DISP_AHB_CLK 45 +#define GCC_DISP_HF_AXI_CLK 46 +#define GCC_DISP_SF_AXI_CLK 47 +#define GCC_DISP_THROTTLE_NRT_AXI_CLK 48 +#define GCC_DISP_THROTTLE_RT_AXI_CLK 49 +#define GCC_DISP_XO_CLK 50 +#define GCC_EMAC0_AXI_CLK 51 +#define GCC_EMAC0_PTP_CLK 52 +#define GCC_EMAC0_PTP_CLK_SRC 53 +#define GCC_EMAC0_RGMII_CLK 54 +#define GCC_EMAC0_RGMII_CLK_SRC 55 +#define GCC_EMAC0_SLV_AHB_CLK 56 +#define GCC_EMAC1_AXI_CLK 57 +#define GCC_EMAC1_PTP_CLK 58 +#define GCC_EMAC1_PTP_CLK_SRC 59 +#define GCC_EMAC1_RGMII_CLK 60 +#define GCC_EMAC1_RGMII_CLK_SRC 61 +#define GCC_EMAC1_SLV_AHB_CLK 62 +#define GCC_GP1_CLK 63 +#define GCC_GP1_CLK_SRC 64 +#define GCC_GP2_CLK 65 +#define GCC_GP2_CLK_SRC 66 +#define GCC_GP3_CLK 67 +#define GCC_GP3_CLK_SRC 68 +#define GCC_GP4_CLK 69 +#define GCC_GP4_CLK_SRC 70 +#define GCC_GP5_CLK 71 +#define GCC_GP5_CLK_SRC 72 +#define GCC_GPU_CFG_AHB_CLK 73 +#define GCC_GPU_GPLL0_CLK_SRC 74 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 75 +#define GCC_GPU_IREF_EN 76 +#define GCC_GPU_MEMNOC_GFX_CLK 77 +#define GCC_GPU_SNOC_DVM_GFX_CLK 78 +#define GCC_GPU_TCU_THROTTLE_AHB_CLK 79 +#define GCC_GPU_TCU_THROTTLE_CLK 80 +#define GCC_PCIE0_PHY_RCHNG_CLK 81 +#define GCC_PCIE1_PHY_RCHNG_CLK 82 +#define GCC_PCIE2A_PHY_RCHNG_CLK 83 +#define GCC_PCIE2B_PHY_RCHNG_CLK 84 +#define GCC_PCIE3A_PHY_RCHNG_CLK 85 +#define GCC_PCIE3B_PHY_RCHNG_CLK 86 +#define GCC_PCIE4_PHY_RCHNG_CLK 87 +#define GCC_PCIE_0_AUX_CLK 88 +#define GCC_PCIE_0_AUX_CLK_SRC 89 +#define GCC_PCIE_0_CFG_AHB_CLK 90 +#define GCC_PCIE_0_MSTR_AXI_CLK 91 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 92 +#define GCC_PCIE_0_PIPE_CLK 93 +#define GCC_PCIE_0_SLV_AXI_CLK 94 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 95 +#define GCC_PCIE_1_AUX_CLK 96 +#define GCC_PCIE_1_AUX_CLK_SRC 97 +#define GCC_PCIE_1_CFG_AHB_CLK 98 +#define GCC_PCIE_1_MSTR_AXI_CLK 99 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 100 +#define GCC_PCIE_1_PIPE_CLK 101 +#define GCC_PCIE_1_SLV_AXI_CLK 102 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 103 +#define GCC_PCIE_2A2B_CLKREF_CLK 104 +#define GCC_PCIE_2A_AUX_CLK 105 +#define GCC_PCIE_2A_AUX_CLK_SRC 106 +#define GCC_PCIE_2A_CFG_AHB_CLK 107 +#define GCC_PCIE_2A_MSTR_AXI_CLK 108 +#define GCC_PCIE_2A_PHY_RCHNG_CLK_SRC 109 +#define GCC_PCIE_2A_PIPE_CLK 110 +#define GCC_PCIE_2A_PIPE_CLK_SRC 111 +#define GCC_PCIE_2A_PIPE_DIV_CLK_SRC 112 +#define GCC_PCIE_2A_PIPEDIV2_CLK 113 +#define GCC_PCIE_2A_SLV_AXI_CLK 114 +#define GCC_PCIE_2A_SLV_Q2A_AXI_CLK 115 +#define GCC_PCIE_2B_AUX_CLK 116 +#define GCC_PCIE_2B_AUX_CLK_SRC 117 +#define GCC_PCIE_2B_CFG_AHB_CLK 118 +#define GCC_PCIE_2B_MSTR_AXI_CLK 119 +#define GCC_PCIE_2B_PHY_RCHNG_CLK_SRC 120 +#define GCC_PCIE_2B_PIPE_CLK 121 +#define GCC_PCIE_2B_PIPE_CLK_SRC 122 +#define GCC_PCIE_2B_PIPE_DIV_CLK_SRC 123 +#define GCC_PCIE_2B_PIPEDIV2_CLK 124 +#define GCC_PCIE_2B_SLV_AXI_CLK 125 +#define GCC_PCIE_2B_SLV_Q2A_AXI_CLK 126 +#define GCC_PCIE_3A3B_CLKREF_CLK 127 +#define GCC_PCIE_3A_AUX_CLK 128 +#define GCC_PCIE_3A_AUX_CLK_SRC 129 +#define GCC_PCIE_3A_CFG_AHB_CLK 130 +#define GCC_PCIE_3A_MSTR_AXI_CLK 131 +#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 132 +#define GCC_PCIE_3A_PIPE_CLK 133 +#define GCC_PCIE_3A_PIPE_CLK_SRC 134 +#define GCC_PCIE_3A_PIPE_DIV_CLK_SRC 135 +#define GCC_PCIE_3A_PIPEDIV2_CLK 136 +#define GCC_PCIE_3A_SLV_AXI_CLK 137 +#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 138 +#define GCC_PCIE_3B_AUX_CLK 139 +#define GCC_PCIE_3B_AUX_CLK_SRC 140 +#define GCC_PCIE_3B_CFG_AHB_CLK 141 +#define GCC_PCIE_3B_MSTR_AXI_CLK 142 +#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 143 +#define GCC_PCIE_3B_PIPE_CLK 144 +#define GCC_PCIE_3B_PIPE_CLK_SRC 145 +#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 146 +#define GCC_PCIE_3B_PIPEDIV2_CLK 147 +#define GCC_PCIE_3B_SLV_AXI_CLK 148 +#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 149 +#define GCC_PCIE_4_AUX_CLK 150 +#define GCC_PCIE_4_AUX_CLK_SRC 151 +#define GCC_PCIE_4_CFG_AHB_CLK 152 +#define GCC_PCIE_4_CLKREF_CLK 153 +#define GCC_PCIE_4_MSTR_AXI_CLK 154 +#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 155 +#define GCC_PCIE_4_PIPE_CLK 156 +#define GCC_PCIE_4_PIPE_CLK_SRC 157 +#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 158 +#define GCC_PCIE_4_PIPEDIV2_CLK 159 +#define GCC_PCIE_4_SLV_AXI_CLK 160 +#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 161 +#define GCC_PCIE_RSCC_AHB_CLK 162 +#define GCC_PCIE_RSCC_XO_CLK 163 +#define GCC_PCIE_RSCC_XO_CLK_SRC 164 +#define GCC_PCIE_THROTTLE_CFG_CLK 165 +#define GCC_PDM2_CLK 166 +#define GCC_PDM2_CLK_SRC 167 +#define GCC_PDM_AHB_CLK 168 +#define GCC_PDM_XO4_CLK 169 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 170 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 171 +#define GCC_QMIP_DISP1_AHB_CLK 172 +#define GCC_QMIP_DISP1_ROT_AHB_CLK 173 +#define GCC_QMIP_DISP_AHB_CLK 174 +#define GCC_QMIP_DISP_ROT_AHB_CLK 175 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 176 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 177 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 178 +#define GCC_QUPV3_WRAP0_CORE_CLK 179 +#define GCC_QUPV3_WRAP0_QSPI0_CLK 180 +#define GCC_QUPV3_WRAP0_S0_CLK 181 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 182 +#define GCC_QUPV3_WRAP0_S1_CLK 183 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 184 +#define GCC_QUPV3_WRAP0_S2_CLK 185 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 186 +#define GCC_QUPV3_WRAP0_S3_CLK 187 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 188 +#define GCC_QUPV3_WRAP0_S4_CLK 189 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 190 +#define GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC 191 +#define GCC_QUPV3_WRAP0_S5_CLK 192 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 193 +#define GCC_QUPV3_WRAP0_S6_CLK 194 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 195 +#define GCC_QUPV3_WRAP0_S7_CLK 196 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 197 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 198 +#define GCC_QUPV3_WRAP1_CORE_CLK 199 +#define GCC_QUPV3_WRAP1_QSPI0_CLK 200 +#define GCC_QUPV3_WRAP1_S0_CLK 201 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 202 +#define GCC_QUPV3_WRAP1_S1_CLK 203 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 204 +#define GCC_QUPV3_WRAP1_S2_CLK 205 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 206 +#define GCC_QUPV3_WRAP1_S3_CLK 207 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 208 +#define GCC_QUPV3_WRAP1_S4_CLK 209 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 210 +#define GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC 211 +#define GCC_QUPV3_WRAP1_S5_CLK 212 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 213 +#define GCC_QUPV3_WRAP1_S6_CLK 214 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 215 +#define GCC_QUPV3_WRAP1_S7_CLK 216 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 217 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 218 +#define GCC_QUPV3_WRAP2_CORE_CLK 219 +#define GCC_QUPV3_WRAP2_QSPI0_CLK 220 +#define GCC_QUPV3_WRAP2_S0_CLK 221 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 222 +#define GCC_QUPV3_WRAP2_S1_CLK 223 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 224 +#define GCC_QUPV3_WRAP2_S2_CLK 225 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 226 +#define GCC_QUPV3_WRAP2_S3_CLK 227 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 228 +#define GCC_QUPV3_WRAP2_S4_CLK 229 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 230 +#define GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC 231 +#define GCC_QUPV3_WRAP2_S5_CLK 232 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 233 +#define GCC_QUPV3_WRAP2_S6_CLK 234 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 235 +#define GCC_QUPV3_WRAP2_S7_CLK 236 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 237 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 238 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 239 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 240 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 241 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 242 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 243 +#define GCC_SDCC2_AHB_CLK 244 +#define GCC_SDCC2_APPS_CLK 245 +#define GCC_SDCC2_APPS_CLK_SRC 246 +#define GCC_SDCC4_AHB_CLK 247 +#define GCC_SDCC4_APPS_CLK 248 +#define GCC_SDCC4_APPS_CLK_SRC 249 +#define GCC_SYS_NOC_USB_AXI_CLK 250 +#define GCC_UFS_1_CARD_CLKREF_CLK 251 +#define GCC_UFS_CARD_AHB_CLK 252 +#define GCC_UFS_CARD_AXI_CLK 253 +#define GCC_UFS_CARD_AXI_CLK_SRC 254 +#define GCC_UFS_CARD_CLKREF_CLK 255 +#define GCC_UFS_CARD_ICE_CORE_CLK 256 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 257 +#define GCC_UFS_CARD_PHY_AUX_CLK 258 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 259 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 260 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 261 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 262 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 263 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 264 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 265 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 266 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 267 +#define GCC_UFS_PHY_AHB_CLK 268 +#define GCC_UFS_PHY_AXI_CLK 269 +#define GCC_UFS_PHY_AXI_CLK_SRC 270 +#define GCC_UFS_PHY_ICE_CORE_CLK 271 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 272 +#define GCC_UFS_PHY_PHY_AUX_CLK 273 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 274 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 275 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 276 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 277 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 278 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 279 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 280 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 281 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 282 +#define GCC_UFS_REF_CLKREF_CLK 283 +#define GCC_USB2_HS0_CLKREF_CLK 284 +#define GCC_USB2_HS1_CLKREF_CLK 285 +#define GCC_USB2_HS2_CLKREF_CLK 286 +#define GCC_USB2_HS3_CLKREF_CLK 287 +#define GCC_USB30_MP_MASTER_CLK 288 +#define GCC_USB30_MP_MASTER_CLK_SRC 289 +#define GCC_USB30_MP_MOCK_UTMI_CLK 290 +#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 291 +#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 292 +#define GCC_USB30_MP_SLEEP_CLK 293 +#define GCC_USB30_PRIM_MASTER_CLK 294 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 295 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 296 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 297 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 298 +#define GCC_USB30_PRIM_SLEEP_CLK 299 +#define GCC_USB30_SEC_MASTER_CLK 300 +#define GCC_USB30_SEC_MASTER_CLK_SRC 301 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 302 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 303 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 304 +#define GCC_USB30_SEC_SLEEP_CLK 305 +#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 306 +#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 307 +#define GCC_USB3_MP0_CLKREF_CLK 308 +#define GCC_USB3_MP1_CLKREF_CLK 309 +#define GCC_USB3_MP_PHY_AUX_CLK 310 +#define GCC_USB3_MP_PHY_AUX_CLK_SRC 311 +#define GCC_USB3_MP_PHY_COM_AUX_CLK 312 +#define GCC_USB3_MP_PHY_PIPE_0_CLK 313 +#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 314 +#define GCC_USB3_MP_PHY_PIPE_1_CLK 315 +#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 316 +#define GCC_USB3_PRIM_PHY_AUX_CLK 317 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 318 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 319 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 320 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 321 +#define GCC_USB3_SEC_PHY_AUX_CLK 322 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 323 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 324 +#define GCC_USB3_SEC_PHY_PIPE_CLK 325 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 326 +#define GCC_USB4_1_CFG_AHB_CLK 327 +#define GCC_USB4_1_DP_CLK 328 +#define GCC_USB4_1_MASTER_CLK 329 +#define GCC_USB4_1_MASTER_CLK_SRC 330 +#define GCC_USB4_1_PHY_DP_CLK_SRC 331 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 332 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 333 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 334 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 335 +#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 336 +#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 337 +#define GCC_USB4_1_PHY_RX0_CLK 338 +#define GCC_USB4_1_PHY_RX0_CLK_SRC 339 +#define GCC_USB4_1_PHY_RX1_CLK 340 +#define GCC_USB4_1_PHY_RX1_CLK_SRC 341 +#define GCC_USB4_1_PHY_SYS_CLK_SRC 342 +#define GCC_USB4_1_PHY_USB_PIPE_CLK 343 +#define GCC_USB4_1_SB_IF_CLK 344 +#define GCC_USB4_1_SB_IF_CLK_SRC 345 +#define GCC_USB4_1_SYS_CLK 346 +#define GCC_USB4_1_TMU_CLK 347 +#define GCC_USB4_1_TMU_CLK_SRC 348 +#define GCC_USB4_CFG_AHB_CLK 349 +#define GCC_USB4_CLKREF_CLK 350 +#define GCC_USB4_DP_CLK 351 +#define GCC_USB4_EUD_CLKREF_CLK 352 +#define GCC_USB4_MASTER_CLK 353 +#define GCC_USB4_MASTER_CLK_SRC 354 +#define GCC_USB4_PHY_DP_CLK_SRC 355 +#define GCC_USB4_PHY_P2RR2P_PIPE_CLK 356 +#define GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC 357 +#define GCC_USB4_PHY_PCIE_PIPE_CLK 358 +#define GCC_USB4_PHY_PCIE_PIPE_CLK_SRC 359 +#define GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC 360 +#define GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC 361 +#define GCC_USB4_PHY_RX0_CLK 362 +#define GCC_USB4_PHY_RX0_CLK_SRC 363 +#define GCC_USB4_PHY_RX1_CLK 364 +#define GCC_USB4_PHY_RX1_CLK_SRC 365 +#define GCC_USB4_PHY_SYS_CLK_SRC 366 +#define GCC_USB4_PHY_USB_PIPE_CLK 367 +#define GCC_USB4_SB_IF_CLK 368 +#define GCC_USB4_SB_IF_CLK_SRC 369 +#define GCC_USB4_SYS_CLK 370 +#define GCC_USB4_TMU_CLK 371 +#define GCC_USB4_TMU_CLK_SRC 372 +#define GCC_VIDEO_AHB_CLK 373 +#define GCC_VIDEO_AXI0_CLK 374 +#define GCC_VIDEO_AXI1_CLK 375 +#define GCC_VIDEO_CVP_THROTTLE_CLK 376 +#define GCC_VIDEO_VCODEC_THROTTLE_CLK 377 +#define GCC_VIDEO_XO_CLK 378 +#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 379 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 380 +#define GCC_UFS_CARD_AXI_HW_CTL_CLK 381 +#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 382 +#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 383 +#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 384 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 385 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 386 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 387 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 388 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_EMAC1_BCR 1 +#define GCC_PCIE_0_LINK_DOWN_BCR 2 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 3 +#define GCC_PCIE_0_PHY_BCR 4 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_TUNNEL_BCR 6 +#define GCC_PCIE_1_LINK_DOWN_BCR 7 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 8 +#define GCC_PCIE_1_PHY_BCR 9 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_TUNNEL_BCR 11 +#define GCC_PCIE_2A_BCR 12 +#define GCC_PCIE_2A_LINK_DOWN_BCR 13 +#define GCC_PCIE_2A_NOCSR_COM_PHY_BCR 14 +#define GCC_PCIE_2A_PHY_BCR 15 +#define GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR 16 +#define GCC_PCIE_2B_BCR 17 +#define GCC_PCIE_2B_LINK_DOWN_BCR 18 +#define GCC_PCIE_2B_NOCSR_COM_PHY_BCR 19 +#define GCC_PCIE_2B_PHY_BCR 20 +#define GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR 21 +#define GCC_PCIE_3A_BCR 22 +#define GCC_PCIE_3A_LINK_DOWN_BCR 23 +#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 24 +#define GCC_PCIE_3A_PHY_BCR 25 +#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 26 +#define GCC_PCIE_3B_BCR 27 +#define GCC_PCIE_3B_LINK_DOWN_BCR 28 +#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 29 +#define GCC_PCIE_3B_PHY_BCR 30 +#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 31 +#define GCC_PCIE_4_BCR 32 +#define GCC_PCIE_4_LINK_DOWN_BCR 33 +#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 34 +#define GCC_PCIE_4_PHY_BCR 35 +#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 36 +#define GCC_PCIE_PHY_CFG_AHB_BCR 37 +#define GCC_PCIE_PHY_COM_BCR 38 +#define GCC_PCIE_RSCC_BCR 39 +#define GCC_QUSB2PHY_HS0_MP_BCR 40 +#define GCC_QUSB2PHY_HS1_MP_BCR 41 +#define GCC_QUSB2PHY_HS2_MP_BCR 42 +#define GCC_QUSB2PHY_HS3_MP_BCR 43 +#define GCC_QUSB2PHY_PRIM_BCR 44 +#define GCC_QUSB2PHY_SEC_BCR 45 +#define GCC_SDCC2_BCR 46 +#define GCC_SDCC4_BCR 47 +#define GCC_UFS_CARD_BCR 48 +#define GCC_UFS_PHY_BCR 49 +#define GCC_USB2_PHY_PRIM_BCR 50 +#define GCC_USB2_PHY_SEC_BCR 51 +#define GCC_USB30_MP_BCR 52 +#define GCC_USB30_PRIM_BCR 53 +#define GCC_USB30_SEC_BCR 54 +#define GCC_USB3_DP_PHY_PRIM_BCR 55 +#define GCC_USB3_DP_PHY_SEC_BCR 56 +#define GCC_USB3_PHY_PRIM_BCR 57 +#define GCC_USB3_PHY_SEC_BCR 58 +#define GCC_USB3_UNIPHY_MP0_BCR 59 +#define GCC_USB3_UNIPHY_MP1_BCR 60 +#define GCC_USB3PHY_PHY_PRIM_BCR 61 +#define GCC_USB3PHY_PHY_SEC_BCR 62 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 63 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 64 +#define GCC_USB4_1_BCR 65 +#define GCC_USB4_1_DP_PHY_PRIM_BCR 66 +#define GCC_USB4_1_DPPHY_AUX_BCR 67 +#define GCC_USB4_1_PHY_PRIM_BCR 68 +#define GCC_USB4_BCR 69 +#define GCC_USB4_DP_PHY_PRIM_BCR 70 +#define GCC_USB4_DPPHY_AUX_BCR 71 +#define GCC_USB4_PHY_PRIM_BCR 72 +#define GCC_USB4PHY_1_PHY_PRIM_BCR 73 +#define GCC_USB4PHY_PHY_PRIM_BCR 74 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 75 +#define GCC_VIDEO_BCR 76 +#define GCC_VIDEO_AXI0_CLK_ARES 77 +#define GCC_VIDEO_AXI1_CLK_ARES 78 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-lemans.h b/include/dt-bindings/clock/qcom,gcc-lemans.h new file mode 100644 index 000000000000..7d20e9839a34 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-lemans.h @@ -0,0 +1,298 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_LEMANS_H +#define _DT_BINDINGS_CLK_QCOM_GCC_LEMANS_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL1 2 +#define GCC_GPLL4 3 +#define GCC_GPLL5 4 +#define GCC_GPLL7 5 +#define GCC_GPLL9 6 +#define GCC_AGGRE_NOC_QUPV3_AXI_CLK 7 +#define GCC_AGGRE_UFS_CARD_AXI_CLK 8 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 9 +#define GCC_AGGRE_USB2_PRIM_AXI_CLK 10 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 11 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 12 +#define GCC_AHB2PHY0_CLK 13 +#define GCC_AHB2PHY2_CLK 14 +#define GCC_AHB2PHY3_CLK 15 +#define GCC_BOOT_ROM_AHB_CLK 16 +#define GCC_CAMERA_AHB_CLK 17 +#define GCC_CAMERA_HF_AXI_CLK 18 +#define GCC_CAMERA_SF_AXI_CLK 19 +#define GCC_CAMERA_THROTTLE_XO_CLK 20 +#define GCC_CAMERA_XO_CLK 21 +#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 22 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24 +#define GCC_DDRSS_GPU_AXI_CLK 25 +#define GCC_DISP1_AHB_CLK 26 +#define GCC_DISP1_HF_AXI_CLK 27 +#define GCC_DISP1_XO_CLK 28 +#define GCC_DISP_AHB_CLK 29 +#define GCC_DISP_HF_AXI_CLK 30 +#define GCC_DISP_XO_CLK 31 +#define GCC_EDP_REF_CLKREF_EN 32 +#define GCC_EMAC0_AXI_CLK 33 +#define GCC_EMAC0_PHY_AUX_CLK 34 +#define GCC_EMAC0_PHY_AUX_CLK_SRC 35 +#define GCC_EMAC0_PTP_CLK 36 +#define GCC_EMAC0_PTP_CLK_SRC 37 +#define GCC_EMAC0_RGMII_CLK 38 +#define GCC_EMAC0_RGMII_CLK_SRC 39 +#define GCC_EMAC0_SLV_AHB_CLK 40 +#define GCC_EMAC1_AXI_CLK 41 +#define GCC_EMAC1_PHY_AUX_CLK 42 +#define GCC_EMAC1_PHY_AUX_CLK_SRC 43 +#define GCC_EMAC1_PTP_CLK 44 +#define GCC_EMAC1_PTP_CLK_SRC 45 +#define GCC_EMAC1_RGMII_CLK 46 +#define GCC_EMAC1_RGMII_CLK_SRC 47 +#define GCC_EMAC1_SLV_AHB_CLK 48 +#define GCC_GP1_CLK 49 +#define GCC_GP1_CLK_SRC 50 +#define GCC_GP2_CLK 51 +#define GCC_GP2_CLK_SRC 52 +#define GCC_GP3_CLK 53 +#define GCC_GP3_CLK_SRC 54 +#define GCC_GP4_CLK 55 +#define GCC_GP4_CLK_SRC 56 +#define GCC_GP5_CLK 57 +#define GCC_GP5_CLK_SRC 58 +#define GCC_GPU_CFG_AHB_CLK 59 +#define GCC_GPU_GPLL0_CLK_SRC 60 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 61 +#define GCC_GPU_MEMNOC_GFX_CLK 62 +#define GCC_GPU_SNOC_DVM_GFX_CLK 63 +#define GCC_GPU_TCU_THROTTLE_AHB_CLK 64 +#define GCC_GPU_TCU_THROTTLE_CLK 65 +#define GCC_PCIE_0_AUX_CLK 66 +#define GCC_PCIE_0_AUX_CLK_SRC 67 +#define GCC_PCIE_0_CFG_AHB_CLK 68 +#define GCC_PCIE_0_MSTR_AXI_CLK 69 +#define GCC_PCIE_0_PHY_AUX_CLK 70 +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 71 +#define GCC_PCIE_0_PHY_RCHNG_CLK 72 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 73 +#define GCC_PCIE_0_PIPE_CLK 74 +#define GCC_PCIE_0_PIPE_CLK_SRC 75 +#define GCC_PCIE_0_PIPE_DIV_CLK_SRC 76 +#define GCC_PCIE_0_PIPEDIV2_CLK 77 +#define GCC_PCIE_0_SLV_AXI_CLK 78 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 79 +#define GCC_PCIE_1_AUX_CLK 80 +#define GCC_PCIE_1_AUX_CLK_SRC 81 +#define GCC_PCIE_1_CFG_AHB_CLK 82 +#define GCC_PCIE_1_MSTR_AXI_CLK 83 +#define GCC_PCIE_1_PHY_AUX_CLK 84 +#define GCC_PCIE_1_PHY_AUX_CLK_SRC 85 +#define GCC_PCIE_1_PHY_RCHNG_CLK 86 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 87 +#define GCC_PCIE_1_PIPE_CLK 88 +#define GCC_PCIE_1_PIPE_CLK_SRC 89 +#define GCC_PCIE_1_PIPE_DIV_CLK_SRC 90 +#define GCC_PCIE_1_PIPEDIV2_CLK 91 +#define GCC_PCIE_1_SLV_AXI_CLK 92 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 93 +#define GCC_PCIE_CLKREF_EN 94 +#define GCC_PCIE_THROTTLE_CFG_CLK 95 +#define GCC_PDM2_CLK 96 +#define GCC_PDM2_CLK_SRC 97 +#define GCC_PDM_AHB_CLK 98 +#define GCC_PDM_XO4_CLK 99 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 100 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 101 +#define GCC_QMIP_DISP1_AHB_CLK 102 +#define GCC_QMIP_DISP1_ROT_AHB_CLK 103 +#define GCC_QMIP_DISP_AHB_CLK 104 +#define GCC_QMIP_DISP_ROT_AHB_CLK 105 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 106 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 107 +#define GCC_QMIP_VIDEO_VCPU_AHB_CLK 108 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 109 +#define GCC_QUPV3_WRAP0_CORE_CLK 110 +#define GCC_QUPV3_WRAP0_S0_CLK 111 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 112 +#define GCC_QUPV3_WRAP0_S1_CLK 113 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 114 +#define GCC_QUPV3_WRAP0_S2_CLK 115 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 116 +#define GCC_QUPV3_WRAP0_S3_CLK 117 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 118 +#define GCC_QUPV3_WRAP0_S4_CLK 119 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 120 +#define GCC_QUPV3_WRAP0_S5_CLK 121 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 122 +#define GCC_QUPV3_WRAP0_S6_CLK 123 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 124 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 125 +#define GCC_QUPV3_WRAP1_CORE_CLK 126 +#define GCC_QUPV3_WRAP1_S0_CLK 127 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 128 +#define GCC_QUPV3_WRAP1_S1_CLK 129 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 130 +#define GCC_QUPV3_WRAP1_S2_CLK 131 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 132 +#define GCC_QUPV3_WRAP1_S3_CLK 133 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 134 +#define GCC_QUPV3_WRAP1_S4_CLK 135 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 136 +#define GCC_QUPV3_WRAP1_S5_CLK 137 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 138 +#define GCC_QUPV3_WRAP1_S6_CLK 139 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 140 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 141 +#define GCC_QUPV3_WRAP2_CORE_CLK 142 +#define GCC_QUPV3_WRAP2_S0_CLK 143 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 144 +#define GCC_QUPV3_WRAP2_S1_CLK 145 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 146 +#define GCC_QUPV3_WRAP2_S2_CLK 147 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 148 +#define GCC_QUPV3_WRAP2_S3_CLK 149 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 150 +#define GCC_QUPV3_WRAP2_S4_CLK 151 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 152 +#define GCC_QUPV3_WRAP2_S5_CLK 153 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 154 +#define GCC_QUPV3_WRAP2_S6_CLK 155 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 156 +#define GCC_QUPV3_WRAP3_CORE_2X_CLK 157 +#define GCC_QUPV3_WRAP3_CORE_CLK 158 +#define GCC_QUPV3_WRAP3_QSPI_CLK 159 +#define GCC_QUPV3_WRAP3_S0_CLK 160 +#define GCC_QUPV3_WRAP3_S0_CLK_SRC 161 +#define GCC_QUPV3_WRAP3_S0_DIV_CLK_SRC 162 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 163 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 164 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 165 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 166 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 167 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 168 +#define GCC_QUPV3_WRAP_3_M_AHB_CLK 169 +#define GCC_QUPV3_WRAP_3_S_AHB_CLK 170 +#define GCC_SDCC1_AHB_CLK 171 +#define GCC_SDCC1_APPS_CLK 172 +#define GCC_SDCC1_APPS_CLK_SRC 173 +#define GCC_SDCC1_ICE_CORE_CLK 174 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 175 +#define GCC_SGMI_CLKREF_EN 176 +#define GCC_TSCSS_AHB_CLK 177 +#define GCC_TSCSS_CNTR_CLK_SRC 178 +#define GCC_TSCSS_ETU_CLK 179 +#define GCC_TSCSS_GLOBAL_CNTR_CLK 180 +#define GCC_UFS_CARD_AHB_CLK 181 +#define GCC_UFS_CARD_AXI_CLK 182 +#define GCC_UFS_CARD_AXI_CLK_SRC 183 +#define GCC_UFS_CARD_ICE_CORE_CLK 184 +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 185 +#define GCC_UFS_CARD_PHY_AUX_CLK 186 +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 187 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 188 +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 189 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 190 +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 191 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 192 +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 193 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 194 +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 195 +#define GCC_UFS_PHY_AHB_CLK 196 +#define GCC_UFS_PHY_AXI_CLK 197 +#define GCC_UFS_PHY_AXI_CLK_SRC 198 +#define GCC_UFS_PHY_ICE_CORE_CLK 199 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 200 +#define GCC_UFS_PHY_PHY_AUX_CLK 201 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 202 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 203 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 204 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 205 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 206 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 207 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 208 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 209 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 210 +#define GCC_USB20_MASTER_CLK 211 +#define GCC_USB20_MASTER_CLK_SRC 212 +#define GCC_USB20_MOCK_UTMI_CLK 213 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 214 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 215 +#define GCC_USB20_SLEEP_CLK 216 +#define GCC_USB30_PRIM_MASTER_CLK 217 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 218 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 219 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 220 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 221 +#define GCC_USB30_PRIM_SLEEP_CLK 222 +#define GCC_USB30_SEC_MASTER_CLK 223 +#define GCC_USB30_SEC_MASTER_CLK_SRC 224 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 225 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 226 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 227 +#define GCC_USB30_SEC_SLEEP_CLK 228 +#define GCC_USB3_PRIM_PHY_AUX_CLK 229 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 230 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 231 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 232 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 233 +#define GCC_USB3_SEC_PHY_AUX_CLK 234 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 235 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 236 +#define GCC_USB3_SEC_PHY_PIPE_CLK 237 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 238 +#define GCC_USB_CLKREF_EN 239 +#define GCC_VIDEO_AHB_CLK 240 +#define GCC_VIDEO_AXI0_CLK 241 +#define GCC_VIDEO_AXI1_CLK 242 +#define GCC_VIDEO_XO_CLK 243 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 244 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 245 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 246 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 247 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 248 + +/* GCC resets */ +#define GCC_EMAC0_BCR 0 +#define GCC_EMAC1_BCR 1 +#define GCC_PCIE_0_BCR 2 +#define GCC_PCIE_0_LINK_DOWN_BCR 3 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 4 +#define GCC_PCIE_0_PHY_BCR 5 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 6 +#define GCC_PCIE_1_BCR 7 +#define GCC_PCIE_1_LINK_DOWN_BCR 8 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 9 +#define GCC_PCIE_1_PHY_BCR 10 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 11 +#define GCC_PCIE_RSCC_BCR 12 +#define GCC_SDCC1_BCR 13 +#define GCC_UFS_CARD_BCR 14 +#define GCC_UFS_PHY_BCR 15 +#define GCC_USB20_PRIM_BCR 16 +#define GCC_USB2_PHY_PRIM_BCR 17 +#define GCC_USB2_PHY_SEC_BCR 18 +#define GCC_USB30_PRIM_BCR 19 +#define GCC_USB30_SEC_BCR 20 +#define GCC_USB3_DP_PHY_PRIM_BCR 21 +#define GCC_USB3_DP_PHY_SEC_BCR 22 +#define GCC_USB3_PHY_PRIM_BCR 23 +#define GCC_USB3_PHY_SEC_BCR 24 +#define GCC_USB3_PHY_TERT_BCR 25 +#define GCC_USB3_UNIPHY_MP0_BCR 26 +#define GCC_USB3_UNIPHY_MP1_BCR 27 +#define GCC_USB3PHY_PHY_PRIM_BCR 28 +#define GCC_USB3PHY_PHY_SEC_BCR 29 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 30 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 31 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 32 +#define GCC_VIDEO_BCR 33 +#define GCC_VIDEO_AXI0_CLK_ARES 34 +#define GCC_VIDEO_AXI1_CLK_ARES 35 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bindings/clock/qcom,gcc-sc8180x.h index e893415ae13d..593489cf05d0 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h @@ -2,6 +2,7 @@ /* * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2021, Linaro Ltd. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8180X_H @@ -246,6 +247,21 @@ #define GCC_PCIE_3_CLKREF_CLK 236 #define GCC_USB3_PRIM_CLKREF_CLK 237 #define GCC_USB3_SEC_CLKREF_CLK 238 +#define GPLL9 239 +#define GCC_AGGRE_UFS_CARD_2_AXI_CLK 240 +#define GCC_CAMERA_AHB_CLK 241 +#define GCC_CAMERA_XO_CLK 242 +#define GCC_CPUSS_DVM_BUS_CLK 243 +#define GCC_CPUSS_GNOC_CLK 244 +#define GCC_DISP_AHB_CLK 245 +#define GCC_DISP_XO_CLK 246 +#define GCC_GPU_CFG_AHB_CLK 247 +#define GCC_GPU_IREF_CLK 248 +#define GCC_NPU_CFG_AHB_CLK 249 +#define GCC_UFS_CARD_CLKREF_CLK 250 +#define GCC_VIDEO_AHB_CLK 251 +#define GCC_VIDEO_XO_CLK 252 +#define GCC_UFS_MEM_CLKREF_CLK 254 #define GCC_EMAC_BCR 0 #define GCC_GPU_BCR 1 @@ -292,6 +308,10 @@ #define GCC_VIDEO_AXI0_CLK_BCR 42 #define GCC_VIDEO_AXI1_CLK_BCR 43 #define GCC_USB3_DP_PHY_SEC_BCR 44 +#define GCC_USB3_UNIPHY_MP0_BCR 45 +#define GCC_USB3_UNIPHY_MP1_BCR 46 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 47 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 48 /* GCC GDSCRs */ #define EMAC_GDSC 0 diff --git a/include/dt-bindings/input/qcom,qpnp-power-on.h b/include/dt-bindings/input/qcom,qpnp-power-on.h new file mode 100644 index 000000000000..2aa5060d7733 --- /dev/null +++ b/include/dt-bindings/input/qcom,qpnp-power-on.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2019,2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_INPUT_QCOM_POWER_ON_H +#define _DT_BINDINGS_INPUT_QCOM_POWER_ON_H + +/* PMIC PON peripheral logical power on types: */ +#define PON_POWER_ON_TYPE_KPDPWR 0 +#define PON_POWER_ON_TYPE_RESIN 1 +#define PON_POWER_ON_TYPE_CBLPWR 2 +#define PON_POWER_ON_TYPE_KPDPWR_RESIN 3 + +/* PMIC PON peripheral physical power off types: */ +#define PON_POWER_OFF_TYPE_WARM_RESET 0x01 +#define PON_POWER_OFF_TYPE_SHUTDOWN 0x04 +#define PON_POWER_OFF_TYPE_DVDD_SHUTDOWN 0x05 +#define PON_POWER_OFF_TYPE_HARD_RESET 0x07 +#define PON_POWER_OFF_TYPE_DVDD_HARD_RESET 0x08 + +#endif diff --git a/include/dt-bindings/phy/qcom,sm8150-qmp-usb3.h b/include/dt-bindings/phy/qcom,sm8150-qmp-usb3.h new file mode 100644 index 000000000000..24d53793022c --- /dev/null +++ b/include/dt-bindings/phy/qcom,sm8150-qmp-usb3.h @@ -0,0 +1,1316 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef _DT_BINDINGS_PHY_QCOM_SM8150_QMP_USB_H +#define _DT_BINDINGS_PHY_QCOM_SM8150_QMP_USB_H + +/* USB3-DP Combo PHY register offsets */ +#define USB3_DP_COM_PHY_MODE_CTRL 0x0000 +#define USB3_DP_COM_SW_RESET 0x0004 +#define USB3_DP_COM_POWER_DOWN_CTRL 0x0008 +#define USB3_DP_COM_SWI_CTRL 0x000C +#define USB3_DP_COM_TYPEC_CTRL 0x0010 +#define USB3_DP_COM_TYPEC_PWRDN_CTRL 0x0014 +#define USB3_DP_COM_DP_BIST_CFG_0 0x0018 +#define USB3_DP_COM_RESET_OVRD_CTRL 0x001C +#define USB3_DP_COM_DBG_CLK_MUX_CTRL 0x0020 +#define USB3_DP_COM_TYPEC_STATUS 0x0024 +#define USB3_DP_COM_PLACEHOLDER_STATUS 0x0028 +#define USB3_DP_COM_REVISION_ID0 0x002C +#define USB3_DP_COM_REVISION_ID1 0x0030 +#define USB3_DP_COM_REVISION_ID2 0x0034 +#define USB3_DP_COM_REVISION_ID3 0x0038 +#define USB3_DP_QSERDES_COM_ATB_SEL1 0x1000 +#define USB3_DP_QSERDES_COM_ATB_SEL2 0x1004 +#define USB3_DP_QSERDES_COM_FREQ_UPDATE 0x1008 +#define USB3_DP_QSERDES_COM_BG_TIMER 0x100C +#define USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x1010 +#define USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x1014 +#define USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x1018 +#define USB3_DP_QSERDES_COM_SSC_PER1 0x101C +#define USB3_DP_QSERDES_COM_SSC_PER2 0x1020 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x1024 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x1028 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x102C +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x1030 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x1034 +#define USB3_DP_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x1038 +#define USB3_DP_QSERDES_COM_POST_DIV 0x103C +#define USB3_DP_QSERDES_COM_POST_DIV_MUX 0x1040 +#define USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x1044 +#define USB3_DP_QSERDES_COM_CLK_ENABLE1 0x1048 +#define USB3_DP_QSERDES_COM_SYS_CLK_CTRL 0x104C +#define USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x1050 +#define USB3_DP_QSERDES_COM_PLL_EN 0x1054 +#define USB3_DP_QSERDES_COM_PLL_IVCO 0x1058 +#define USB3_DP_QSERDES_COM_CMN_IETRIM 0x105C +#define USB3_DP_QSERDES_COM_CMN_IPTRIM 0x1060 +#define USB3_DP_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x1064 +#define USB3_DP_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x1068 +#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE0 0x106C +#define USB3_DP_QSERDES_COM_CLK_EP_DIV_MODE1 0x1070 +#define USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x1074 +#define USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x1078 +#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x107C +#define USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x1080 +#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x1084 +#define USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x1088 +#define USB3_DP_QSERDES_COM_PLL_CNTRL 0x108C +#define USB3_DP_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x1090 +#define USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1094 +#define USB3_DP_QSERDES_COM_CML_SYSCLK_SEL 0x1098 +#define USB3_DP_QSERDES_COM_RESETSM_CNTRL 0x109C +#define USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x10A0 +#define USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x10A4 +#define USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x10A8 +#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x10AC +#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x10B0 +#define USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x10B4 +#define USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x10B8 +#define USB3_DP_QSERDES_COM_DEC_START_MODE0 0x10BC +#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0 0x10C0 +#define USB3_DP_QSERDES_COM_DEC_START_MODE1 0x10C4 +#define USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1 0x10C8 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0x10CC +#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0x10D0 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x10D4 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0x10D8 +#define USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0x10DC +#define USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x10E0 +#define USB3_DP_QSERDES_COM_INTEGLOOP_INITVAL 0x10E4 +#define USB3_DP_QSERDES_COM_INTEGLOOP_EN 0x10E8 +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x10EC +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10F0 +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x10F4 +#define USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x10F8 +#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x10FC +#define USB3_DP_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x1100 +#define USB3_DP_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x1104 +#define USB3_DP_QSERDES_COM_VCO_TUNE_CTRL 0x1108 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x110C +#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x1110 +#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x1114 +#define USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x1118 +#define USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x111C +#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL1 0x1120 +#define USB3_DP_QSERDES_COM_VCO_TUNE_INITVAL2 0x1124 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL1 0x1128 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MINVAL2 0x112C +#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL1 0x1130 +#define USB3_DP_QSERDES_COM_VCO_TUNE_MAXVAL2 0x1134 +#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER1 0x1138 +#define USB3_DP_QSERDES_COM_VCO_TUNE_TIMER2 0x113C +#define USB3_DP_QSERDES_COM_CMN_STATUS 0x1140 +#define USB3_DP_QSERDES_COM_RESET_SM_STATUS 0x1144 +#define USB3_DP_QSERDES_COM_RESTRIM_CODE_STATUS 0x1148 +#define USB3_DP_QSERDES_COM_PLLCAL_CODE1_STATUS 0x114C +#define USB3_DP_QSERDES_COM_PLLCAL_CODE2_STATUS 0x1150 +#define USB3_DP_QSERDES_COM_CLK_SELECT 0x1154 +#define USB3_DP_QSERDES_COM_HSCLK_SEL 0x1158 +#define USB3_DP_QSERDES_COM_HSCLK_HS_SWITCH_SEL 0x115C +#define USB3_DP_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x1160 +#define USB3_DP_QSERDES_COM_PLL_ANALOG 0x1164 +#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE0 0x1168 +#define USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x116C +#define USB3_DP_QSERDES_COM_SW_RESET 0x1170 +#define USB3_DP_QSERDES_COM_CORE_CLK_EN 0x1174 +#define USB3_DP_QSERDES_COM_C_READY_STATUS 0x1178 +#define USB3_DP_QSERDES_COM_CMN_CONFIG 0x117C +#define USB3_DP_QSERDES_COM_CMN_RATE_OVERRIDE 0x1180 +#define USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x1184 +#define USB3_DP_QSERDES_COM_DEBUG_BUS0 0x1188 +#define USB3_DP_QSERDES_COM_DEBUG_BUS1 0x118C +#define USB3_DP_QSERDES_COM_DEBUG_BUS2 0x1190 +#define USB3_DP_QSERDES_COM_DEBUG_BUS3 0x1194 +#define USB3_DP_QSERDES_COM_DEBUG_BUS_SEL 0x1198 +#define USB3_DP_QSERDES_COM_CMN_MISC1 0x119C +#define USB3_DP_QSERDES_COM_CMN_MISC2 0x11A0 +#define USB3_DP_QSERDES_COM_CMN_MODE 0x11A4 +#define USB3_DP_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x11A8 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x11AC +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x11B0 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x11B4 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x11B8 +#define USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11BC +#define USB3_DP_QSERDES_TXA_BIST_MODE_LANENO 0x1200 +#define USB3_DP_QSERDES_TXA_BIST_INVERT 0x1204 +#define USB3_DP_QSERDES_TXA_CLKBUF_ENABLE 0x1208 +#define USB3_DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x120C +#define USB3_DP_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x1210 +#define USB3_DP_QSERDES_TXA_TX_DRV_LVL 0x1214 +#define USB3_DP_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x1218 +#define USB3_DP_QSERDES_TXA_RESET_TSYNC_EN 0x121C +#define USB3_DP_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x1220 +#define USB3_DP_QSERDES_TXA_TX_BAND 0x1224 +#define USB3_DP_QSERDES_TXA_SLEW_CNTL 0x1228 +#define USB3_DP_QSERDES_TXA_INTERFACE_SELECT 0x122C +#define USB3_DP_QSERDES_TXA_LPB_EN 0x1230 +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x1234 +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x1238 +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x123C +#define USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x1240 +#define USB3_DP_QSERDES_TXA_PERL_LENGTH1 0x1244 +#define USB3_DP_QSERDES_TXA_PERL_LENGTH2 0x1248 +#define USB3_DP_QSERDES_TXA_SERDES_BYP_EN_OUT 0x124C +#define USB3_DP_QSERDES_TXA_DEBUG_BUS_SEL 0x1250 +#define USB3_DP_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x1254 +#define USB3_DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x1258 +#define USB3_DP_QSERDES_TXA_TX_POL_INV 0x125C +#define USB3_DP_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x1260 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN1 0x1264 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN2 0x1268 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN3 0x126C +#define USB3_DP_QSERDES_TXA_BIST_PATTERN4 0x1270 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN5 0x1274 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN6 0x1278 +#define USB3_DP_QSERDES_TXA_BIST_PATTERN7 0x127C +#define USB3_DP_QSERDES_TXA_BIST_PATTERN8 0x1280 +#define USB3_DP_QSERDES_TXA_LANE_MODE_1 0x1284 +#define USB3_DP_QSERDES_TXA_LANE_MODE_2 0x1288 +#define USB3_DP_QSERDES_TXA_LANE_MODE_3 0x128C +#define USB3_DP_QSERDES_TXA_ATB_SEL1 0x1290 +#define USB3_DP_QSERDES_TXA_ATB_SEL2 0x1294 +#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL 0x1298 +#define USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x129C +#define USB3_DP_QSERDES_TXA_PRBS_SEED1 0x12A0 +#define USB3_DP_QSERDES_TXA_PRBS_SEED2 0x12A4 +#define USB3_DP_QSERDES_TXA_PRBS_SEED3 0x12A8 +#define USB3_DP_QSERDES_TXA_PRBS_SEED4 0x12AC +#define USB3_DP_QSERDES_TXA_RESET_GEN 0x12B0 +#define USB3_DP_QSERDES_TXA_RESET_GEN_MUXES 0x12B4 +#define USB3_DP_QSERDES_TXA_TRAN_DRVR_EMP_EN 0x12B8 +#define USB3_DP_QSERDES_TXA_TX_INTERFACE_MODE 0x12BC +#define USB3_DP_QSERDES_TXA_PWM_CTRL 0x12C0 +#define USB3_DP_QSERDES_TXA_PWM_ENCODED_OR_DATA 0x12C4 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_1_DIVIDER_BAND2 0x12C8 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_2_DIVIDER_BAND2 0x12CC +#define USB3_DP_QSERDES_TXA_PWM_GEAR_3_DIVIDER_BAND2 0x12D0 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_4_DIVIDER_BAND2 0x12D4 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_1_DIVIDER_BAND0_1 0x12D8 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_2_DIVIDER_BAND0_1 0x12DC +#define USB3_DP_QSERDES_TXA_PWM_GEAR_3_DIVIDER_BAND0_1 0x12E0 +#define USB3_DP_QSERDES_TXA_PWM_GEAR_4_DIVIDER_BAND0_1 0x12E4 +#define USB3_DP_QSERDES_TXA_VMODE_CTRL1 0x12E8 +#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0x12EC +#define USB3_DP_QSERDES_TXA_BIST_STATUS 0x12F0 +#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT1 0x12F4 +#define USB3_DP_QSERDES_TXA_BIST_ERROR_COUNT2 0x12F8 +#define USB3_DP_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0x12FC +#define USB3_DP_QSERDES_TXA_LANE_DIG_CONFIG 0x1300 +#define USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x1304 +#define USB3_DP_QSERDES_TXA_PRE_EMPH 0x1308 +#define USB3_DP_QSERDES_TXA_SW_RESET 0x130C +#define USB3_DP_QSERDES_TXA_DIG_BKUP_CTRL 0x1310 +#define USB3_DP_QSERDES_TXA_DEBUG_BUS0 0x1314 +#define USB3_DP_QSERDES_TXA_DEBUG_BUS1 0x1318 +#define USB3_DP_QSERDES_TXA_DEBUG_BUS2 0x131C +#define USB3_DP_QSERDES_TXA_DEBUG_BUS3 0x1320 +#define USB3_DP_QSERDES_TXA_READ_EQCODE 0x1324 +#define USB3_DP_QSERDES_TXA_READ_OFFSETCODE 0x1328 +#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_LOW 0x132C +#define USB3_DP_QSERDES_TXA_IA_ERROR_COUNTER_HIGH 0x1330 +#define USB3_DP_QSERDES_TXA_VGA_READ_CODE 0x1334 +#define USB3_DP_QSERDES_TXA_VTH_READ_CODE 0x1338 +#define USB3_DP_QSERDES_TXA_DFE_TAP1_READ_CODE 0x133C +#define USB3_DP_QSERDES_TXA_DFE_TAP2_READ_CODE 0x1340 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_I 0x1344 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_IBAR 0x1348 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_Q 0x134C +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_QBAR 0x1350 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_A 0x1354 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_ABAR 0x1358 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SM_ON 0x135C +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_CAL_DONE 0x1360 +#define USB3_DP_QSERDES_TXA_IDAC_STATUS_SIGNERROR 0x1364 +#define USB3_DP_QSERDES_TXA_DCC_CAL_STATUS 0x1368 +#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_HALF 0x1400 +#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN_QUARTER 0x1404 +#define USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x1408 +#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_HALF 0x140C +#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN_QUARTER 0x1410 +#define USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x1414 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_HALF 0x1418 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN_QUARTER 0x141C +#define USB3_DP_QSERDES_RXA_UCDR_SVS_FO_GAIN 0x1420 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_HALF 0x1424 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN_QUARTER 0x1428 +#define USB3_DP_QSERDES_RXA_UCDR_SVS_SO_GAIN 0x142C +#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x1430 +#define USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x1434 +#define USB3_DP_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x1438 +#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x143C +#define USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x1440 +#define USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x1444 +#define USB3_DP_QSERDES_RXA_UCDR_PI_CTRL2 0x1448 +#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x144C +#define USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x1450 +#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x1454 +#define USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x1458 +#define USB3_DP_QSERDES_RXA_AUX_CONTROL 0x145C +#define USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x1460 +#define USB3_DP_QSERDES_RXA_RCLK_AUXDATA_SEL 0x1464 +#define USB3_DP_QSERDES_RXA_AC_JTAG_ENABLE 0x1468 +#define USB3_DP_QSERDES_RXA_AC_JTAG_INITP 0x146C +#define USB3_DP_QSERDES_RXA_AC_JTAG_INITN 0x1470 +#define USB3_DP_QSERDES_RXA_AC_JTAG_LVL 0x1474 +#define USB3_DP_QSERDES_RXA_AC_JTAG_MODE 0x1478 +#define USB3_DP_QSERDES_RXA_AC_JTAG_RESET 0x147C +#define USB3_DP_QSERDES_RXA_RX_TERM_BW 0x1480 +#define USB3_DP_QSERDES_RXA_RX_RCVR_IQ_EN 0x1484 +#define USB3_DP_QSERDES_RXA_RX_IDAC_I_DC_OFFSETS 0x1488 +#define USB3_DP_QSERDES_RXA_RX_IDAC_IBAR_DC_OFFSETS 0x148C +#define USB3_DP_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x1490 +#define USB3_DP_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x1494 +#define USB3_DP_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x1498 +#define USB3_DP_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x149C +#define USB3_DP_QSERDES_RXA_RX_IDAC_EN 0x14A0 +#define USB3_DP_QSERDES_RXA_RX_IDAC_ENABLES 0x14A4 +#define USB3_DP_QSERDES_RXA_RX_IDAC_SIGN 0x14A8 +#define USB3_DP_QSERDES_RXA_RX_HIGHZ_HIGHRATE 0x14AC +#define USB3_DP_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x14B0 +#define USB3_DP_QSERDES_RXA_DFE_1 0x14B4 +#define USB3_DP_QSERDES_RXA_DFE_2 0x14B8 +#define USB3_DP_QSERDES_RXA_DFE_3 0x14BC +#define USB3_DP_QSERDES_RXA_DFE_4 0x14C0 +#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH1 0x14C4 +#define USB3_DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH2 0x14C8 +#define USB3_DP_QSERDES_RXA_TX_ADAPT_POST_THRESH 0x14CC +#define USB3_DP_QSERDES_RXA_TX_ADAPT_MAIN_THRESH 0x14D0 +#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x14D4 +#define USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x14D8 +#define USB3_DP_QSERDES_RXA_GM_CAL 0x14DC +#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_LSB 0x14E0 +#define USB3_DP_QSERDES_RXA_RX_VGA_GAIN2_MSB 0x14E4 +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL1 0x14E8 +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x14EC +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x14F0 +#define USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x14F4 +#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x14F8 +#define USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x14FC +#define USB3_DP_QSERDES_RXA_RX_IDAC_MEASURE_TIME 0x1500 +#define USB3_DP_QSERDES_RXA_RX_IDAC_ACCUMULATOR 0x1504 +#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x1508 +#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x150C +#define USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1510 +#define USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x1514 +#define USB3_DP_QSERDES_RXA_SIGDET_ENABLES 0x1518 +#define USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x151C +#define USB3_DP_QSERDES_RXA_SIGDET_LVL 0x1520 +#define USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x1524 +#define USB3_DP_QSERDES_RXA_RX_BAND 0x1528 +#define USB3_DP_QSERDES_RXA_CDR_FREEZE_UP_DN 0x152C +#define USB3_DP_QSERDES_RXA_CDR_RESET_OVERRIDE 0x1530 +#define USB3_DP_QSERDES_RXA_RX_INTERFACE_MODE 0x1534 +#define USB3_DP_QSERDES_RXA_JITTER_GEN_MODE 0x1538 +#define USB3_DP_QSERDES_RXA_SJ_AMP1 0x153C +#define USB3_DP_QSERDES_RXA_SJ_AMP2 0x1540 +#define USB3_DP_QSERDES_RXA_SJ_PER1 0x1544 +#define USB3_DP_QSERDES_RXA_SJ_PER2 0x1548 +#define USB3_DP_QSERDES_RXA_PPM_OFFSET1 0x154C +#define USB3_DP_QSERDES_RXA_PPM_OFFSET2 0x1550 +#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD1 0x1554 +#define USB3_DP_QSERDES_RXA_SIGN_PPM_PERIOD2 0x1558 +#define USB3_DP_QSERDES_RXA_RX_PWM_ENABLE_AND_DATA 0x155C +#define USB3_DP_QSERDES_RXA_RX_PWM_GEAR1_TIMEOUT_COUNT 0x1560 +#define USB3_DP_QSERDES_RXA_RX_PWM_GEAR2_TIMEOUT_COUNT 0x1564 +#define USB3_DP_QSERDES_RXA_RX_PWM_GEAR3_TIMEOUT_COUNT 0x1568 +#define USB3_DP_QSERDES_RXA_RX_PWM_GEAR4_TIMEOUT_COUNT 0x156C +#define USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x1570 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x1574 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x1578 +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x157C +#define USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x1580 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x1584 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1588 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x158C +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x1590 +#define USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x1594 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_LOW 0x1598 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH 0x159C +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH2 0x15A0 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH3 0x15A4 +#define USB3_DP_QSERDES_RXA_RX_MODE_10_HIGH4 0x15A8 +#define USB3_DP_QSERDES_RXA_PHPRE_CTRL 0x15AC +#define USB3_DP_QSERDES_RXA_PHPRE_INITVAL 0x15B0 +#define USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x15B4 +#define USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x15B8 +#define USB3_DP_QSERDES_RXA_DCC_CTRL1 0x15BC +#define USB3_DP_QSERDES_RXA_DCC_CTRL2 0x15C0 +#define USB3_DP_QSERDES_RXA_VTH_CODE 0x15C4 +#define USB3_DP_QSERDES_RXA_VTH_MIN_THRESH 0x15C8 +#define USB3_DP_QSERDES_RXA_VTH_MAX_THRESH 0x15CC +#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x15D0 +#define USB3_DP_QSERDES_RXA_PI_CTRL1 0x15D4 +#define USB3_DP_QSERDES_RXA_PI_CTRL2 0x15D8 +#define USB3_DP_QSERDES_RXA_PI_QUAD 0x15DC +#define USB3_DP_QSERDES_RXA_IDATA1 0x15E0 +#define USB3_DP_QSERDES_RXA_IDATA2 0x15E4 +#define USB3_DP_QSERDES_RXA_AUX_DATA1 0x15E8 +#define USB3_DP_QSERDES_RXA_AUX_DATA2 0x15EC +#define USB3_DP_QSERDES_RXA_AC_JTAG_OUTP 0x15F0 +#define USB3_DP_QSERDES_RXA_AC_JTAG_OUTN 0x15F4 +#define USB3_DP_QSERDES_RXA_RX_SIGDET 0x15F8 +#define USB3_DP_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x15FC +#define USB3_DP_QSERDES_TXB_BIST_MODE_LANENO 0x1600 +#define USB3_DP_QSERDES_TXB_BIST_INVERT 0x1604 +#define USB3_DP_QSERDES_TXB_CLKBUF_ENABLE 0x1608 +#define USB3_DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x160C +#define USB3_DP_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x1610 +#define USB3_DP_QSERDES_TXB_TX_DRV_LVL 0x1614 +#define USB3_DP_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x1618 +#define USB3_DP_QSERDES_TXB_RESET_TSYNC_EN 0x161C +#define USB3_DP_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x1620 +#define USB3_DP_QSERDES_TXB_TX_BAND 0x1624 +#define USB3_DP_QSERDES_TXB_SLEW_CNTL 0x1628 +#define USB3_DP_QSERDES_TXB_INTERFACE_SELECT 0x162C +#define USB3_DP_QSERDES_TXB_LPB_EN 0x1630 +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x1634 +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x1638 +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x163C +#define USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x1640 +#define USB3_DP_QSERDES_TXB_PERL_LENGTH1 0x1644 +#define USB3_DP_QSERDES_TXB_PERL_LENGTH2 0x1648 +#define USB3_DP_QSERDES_TXB_SERDES_BYP_EN_OUT 0x164C +#define USB3_DP_QSERDES_TXB_DEBUG_BUS_SEL 0x1650 +#define USB3_DP_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x1654 +#define USB3_DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x1658 +#define USB3_DP_QSERDES_TXB_TX_POL_INV 0x165C +#define USB3_DP_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x1660 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN1 0x1664 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN2 0x1668 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN3 0x166C +#define USB3_DP_QSERDES_TXB_BIST_PATTERN4 0x1670 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN5 0x1674 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN6 0x1678 +#define USB3_DP_QSERDES_TXB_BIST_PATTERN7 0x167C +#define USB3_DP_QSERDES_TXB_BIST_PATTERN8 0x1680 +#define USB3_DP_QSERDES_TXB_LANE_MODE_1 0x1684 +#define USB3_DP_QSERDES_TXB_LANE_MODE_2 0x1688 +#define USB3_DP_QSERDES_TXB_LANE_MODE_3 0x168C +#define USB3_DP_QSERDES_TXB_ATB_SEL1 0x1690 +#define USB3_DP_QSERDES_TXB_ATB_SEL2 0x1694 +#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL 0x1698 +#define USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x169C +#define USB3_DP_QSERDES_TXB_PRBS_SEED1 0x16A0 +#define USB3_DP_QSERDES_TXB_PRBS_SEED2 0x16A4 +#define USB3_DP_QSERDES_TXB_PRBS_SEED3 0x16A8 +#define USB3_DP_QSERDES_TXB_PRBS_SEED4 0x16AC +#define USB3_DP_QSERDES_TXB_RESET_GEN 0x16B0 +#define USB3_DP_QSERDES_TXB_RESET_GEN_MUXES 0x16B4 +#define USB3_DP_QSERDES_TXB_TRAN_DRVR_EMP_EN 0x16B8 +#define USB3_DP_QSERDES_TXB_TX_INTERFACE_MODE 0x16BC +#define USB3_DP_QSERDES_TXB_PWM_CTRL 0x16C0 +#define USB3_DP_QSERDES_TXB_PWM_ENCODED_OR_DATA 0x16C4 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_1_DIVIDER_BAND2 0x16C8 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_2_DIVIDER_BAND2 0x16CC +#define USB3_DP_QSERDES_TXB_PWM_GEAR_3_DIVIDER_BAND2 0x16D0 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_4_DIVIDER_BAND2 0x16D4 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_1_DIVIDER_BAND0_1 0x16D8 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_2_DIVIDER_BAND0_1 0x16DC +#define USB3_DP_QSERDES_TXB_PWM_GEAR_3_DIVIDER_BAND0_1 0x16E0 +#define USB3_DP_QSERDES_TXB_PWM_GEAR_4_DIVIDER_BAND0_1 0x16E4 +#define USB3_DP_QSERDES_TXB_VMODE_CTRL1 0x16E8 +#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0x16EC +#define USB3_DP_QSERDES_TXB_BIST_STATUS 0x16F0 +#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT1 0x16F4 +#define USB3_DP_QSERDES_TXB_BIST_ERROR_COUNT2 0x16F8 +#define USB3_DP_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0x16FC +#define USB3_DP_QSERDES_TXB_LANE_DIG_CONFIG 0x1700 +#define USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x1704 +#define USB3_DP_QSERDES_TXB_PRE_EMPH 0x1708 +#define USB3_DP_QSERDES_TXB_SW_RESET 0x170C +#define USB3_DP_QSERDES_TXB_DIG_BKUP_CTRL 0x1710 +#define USB3_DP_QSERDES_TXB_DEBUG_BUS0 0x1714 +#define USB3_DP_QSERDES_TXB_DEBUG_BUS1 0x1718 +#define USB3_DP_QSERDES_TXB_DEBUG_BUS2 0x171C +#define USB3_DP_QSERDES_TXB_DEBUG_BUS3 0x1720 +#define USB3_DP_QSERDES_TXB_READ_EQCODE 0x1724 +#define USB3_DP_QSERDES_TXB_READ_OFFSETCODE 0x1728 +#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_LOW 0x172C +#define USB3_DP_QSERDES_TXB_IA_ERROR_COUNTER_HIGH 0x1730 +#define USB3_DP_QSERDES_TXB_VGA_READ_CODE 0x1734 +#define USB3_DP_QSERDES_TXB_VTH_READ_CODE 0x1738 +#define USB3_DP_QSERDES_TXB_DFE_TAP1_READ_CODE 0x173C +#define USB3_DP_QSERDES_TXB_DFE_TAP2_READ_CODE 0x1740 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_I 0x1744 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_IBAR 0x1748 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_Q 0x174C +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_QBAR 0x1750 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_A 0x1754 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_ABAR 0x1758 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SM_ON 0x175C +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_CAL_DONE 0x1760 +#define USB3_DP_QSERDES_TXB_IDAC_STATUS_SIGNERROR 0x1764 +#define USB3_DP_QSERDES_TXB_DCC_CAL_STATUS 0x1768 +#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_HALF 0x1800 +#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN_QUARTER 0x1804 +#define USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x1808 +#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_HALF 0x180C +#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN_QUARTER 0x1810 +#define USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x1814 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_HALF 0x1818 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN_QUARTER 0x181C +#define USB3_DP_QSERDES_RXB_UCDR_SVS_FO_GAIN 0x1820 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_HALF 0x1824 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN_QUARTER 0x1828 +#define USB3_DP_QSERDES_RXB_UCDR_SVS_SO_GAIN 0x182C +#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x1830 +#define USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x1834 +#define USB3_DP_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x1838 +#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x183C +#define USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x1840 +#define USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x1844 +#define USB3_DP_QSERDES_RXB_UCDR_PI_CTRL2 0x1848 +#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x184C +#define USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x1850 +#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x1854 +#define USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x1858 +#define USB3_DP_QSERDES_RXB_AUX_CONTROL 0x185C +#define USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x1860 +#define USB3_DP_QSERDES_RXB_RCLK_AUXDATA_SEL 0x1864 +#define USB3_DP_QSERDES_RXB_AC_JTAG_ENABLE 0x1868 +#define USB3_DP_QSERDES_RXB_AC_JTAG_INITP 0x186C +#define USB3_DP_QSERDES_RXB_AC_JTAG_INITN 0x1870 +#define USB3_DP_QSERDES_RXB_AC_JTAG_LVL 0x1874 +#define USB3_DP_QSERDES_RXB_AC_JTAG_MODE 0x1878 +#define USB3_DP_QSERDES_RXB_AC_JTAG_RESET 0x187C +#define USB3_DP_QSERDES_RXB_RX_TERM_BW 0x1880 +#define USB3_DP_QSERDES_RXB_RX_RCVR_IQ_EN 0x1884 +#define USB3_DP_QSERDES_RXB_RX_IDAC_I_DC_OFFSETS 0x1888 +#define USB3_DP_QSERDES_RXB_RX_IDAC_IBAR_DC_OFFSETS 0x188C +#define USB3_DP_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x1890 +#define USB3_DP_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x1894 +#define USB3_DP_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x1898 +#define USB3_DP_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x189C +#define USB3_DP_QSERDES_RXB_RX_IDAC_EN 0x18A0 +#define USB3_DP_QSERDES_RXB_RX_IDAC_ENABLES 0x18A4 +#define USB3_DP_QSERDES_RXB_RX_IDAC_SIGN 0x18A8 +#define USB3_DP_QSERDES_RXB_RX_HIGHZ_HIGHRATE 0x18AC +#define USB3_DP_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x18B0 +#define USB3_DP_QSERDES_RXB_DFE_1 0x18B4 +#define USB3_DP_QSERDES_RXB_DFE_2 0x18B8 +#define USB3_DP_QSERDES_RXB_DFE_3 0x18BC +#define USB3_DP_QSERDES_RXB_DFE_4 0x18C0 +#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH1 0x18C4 +#define USB3_DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH2 0x18C8 +#define USB3_DP_QSERDES_RXB_TX_ADAPT_POST_THRESH 0x18CC +#define USB3_DP_QSERDES_RXB_TX_ADAPT_MAIN_THRESH 0x18D0 +#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x18D4 +#define USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x18D8 +#define USB3_DP_QSERDES_RXB_GM_CAL 0x18DC +#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_LSB 0x18E0 +#define USB3_DP_QSERDES_RXB_RX_VGA_GAIN2_MSB 0x18E4 +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL1 0x18E8 +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x18EC +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x18F0 +#define USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18F4 +#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x18F8 +#define USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x18FC +#define USB3_DP_QSERDES_RXB_RX_IDAC_MEASURE_TIME 0x1900 +#define USB3_DP_QSERDES_RXB_RX_IDAC_ACCUMULATOR 0x1904 +#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x1908 +#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x190C +#define USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1910 +#define USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x1914 +#define USB3_DP_QSERDES_RXB_SIGDET_ENABLES 0x1918 +#define USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x191C +#define USB3_DP_QSERDES_RXB_SIGDET_LVL 0x1920 +#define USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x1924 +#define USB3_DP_QSERDES_RXB_RX_BAND 0x1928 +#define USB3_DP_QSERDES_RXB_CDR_FREEZE_UP_DN 0x192C +#define USB3_DP_QSERDES_RXB_CDR_RESET_OVERRIDE 0x1930 +#define USB3_DP_QSERDES_RXB_RX_INTERFACE_MODE 0x1934 +#define USB3_DP_QSERDES_RXB_JITTER_GEN_MODE 0x1938 +#define USB3_DP_QSERDES_RXB_SJ_AMP1 0x193C +#define USB3_DP_QSERDES_RXB_SJ_AMP2 0x1940 +#define USB3_DP_QSERDES_RXB_SJ_PER1 0x1944 +#define USB3_DP_QSERDES_RXB_SJ_PER2 0x1948 +#define USB3_DP_QSERDES_RXB_PPM_OFFSET1 0x194C +#define USB3_DP_QSERDES_RXB_PPM_OFFSET2 0x1950 +#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD1 0x1954 +#define USB3_DP_QSERDES_RXB_SIGN_PPM_PERIOD2 0x1958 +#define USB3_DP_QSERDES_RXB_RX_PWM_ENABLE_AND_DATA 0x195C +#define USB3_DP_QSERDES_RXB_RX_PWM_GEAR1_TIMEOUT_COUNT 0x1960 +#define USB3_DP_QSERDES_RXB_RX_PWM_GEAR2_TIMEOUT_COUNT 0x1964 +#define USB3_DP_QSERDES_RXB_RX_PWM_GEAR3_TIMEOUT_COUNT 0x1968 +#define USB3_DP_QSERDES_RXB_RX_PWM_GEAR4_TIMEOUT_COUNT 0x196C +#define USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x1970 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x1974 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x1978 +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x197C +#define USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x1980 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x1984 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1988 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x198C +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x1990 +#define USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x1994 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_LOW 0x1998 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH 0x199C +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH2 0x19A0 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH3 0x19A4 +#define USB3_DP_QSERDES_RXB_RX_MODE_10_HIGH4 0x19A8 +#define USB3_DP_QSERDES_RXB_PHPRE_CTRL 0x19AC +#define USB3_DP_QSERDES_RXB_PHPRE_INITVAL 0x19B0 +#define USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x19B4 +#define USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x19B8 +#define USB3_DP_QSERDES_RXB_DCC_CTRL1 0x19BC +#define USB3_DP_QSERDES_RXB_DCC_CTRL2 0x19C0 +#define USB3_DP_QSERDES_RXB_VTH_CODE 0x19C4 +#define USB3_DP_QSERDES_RXB_VTH_MIN_THRESH 0x19C8 +#define USB3_DP_QSERDES_RXB_VTH_MAX_THRESH 0x19CC +#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x19D0 +#define USB3_DP_QSERDES_RXB_PI_CTRL1 0x19D4 +#define USB3_DP_QSERDES_RXB_PI_CTRL2 0x19D8 +#define USB3_DP_QSERDES_RXB_PI_QUAD 0x19DC +#define USB3_DP_QSERDES_RXB_IDATA1 0x19E0 +#define USB3_DP_QSERDES_RXB_IDATA2 0x19E4 +#define USB3_DP_QSERDES_RXB_AUX_DATA1 0x19E8 +#define USB3_DP_QSERDES_RXB_AUX_DATA2 0x19EC +#define USB3_DP_QSERDES_RXB_AC_JTAG_OUTP 0x19F0 +#define USB3_DP_QSERDES_RXB_AC_JTAG_OUTN 0x19F4 +#define USB3_DP_QSERDES_RXB_RX_SIGDET 0x19F8 +#define USB3_DP_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x19FC +#define USB3_DP_PCS_MISC_TYPEC_CTRL 0x1A00 +#define USB3_DP_PCS_MISC_TYPEC_PWRDN_CTRL 0x1A04 +#define USB3_DP_PCS_MISC_PCS_MISC_CONFIG1 0x1A08 +#define USB3_DP_PCS_MISC_CLAMP_ENABLE 0x1A0C +#define USB3_DP_PCS_MISC_TYPEC_STATUS 0x1A10 +#define USB3_DP_PCS_MISC_PLACEHOLDER_STATUS 0x1A14 +#define USB3_DP_PCS_LN_PCS_STATUS1 0x1B00 +#define USB3_DP_PCS_LN_PCS_STATUS2 0x1B04 +#define USB3_DP_PCS_LN_PCS_STATUS2_CLEAR 0x1B08 +#define USB3_DP_PCS_LN_PCS_STATUS3 0x1B0C +#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x1B10 +#define USB3_DP_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x1B14 +#define USB3_DP_PCS_LN_BIST_CHK_STATUS 0x1B18 +#define USB3_DP_PCS_LN_INSIG_SW_CTRL1 0x1B1C +#define USB3_DP_PCS_LN_INSIG_MX_CTRL1 0x1B20 +#define USB3_DP_PCS_LN_OUTSIG_SW_CTRL1 0x1B24 +#define USB3_DP_PCS_LN_OUTSIG_MX_CTRL1 0x1B28 +#define USB3_DP_PCS_LN_TEST_CONTROL 0x1B2C +#define USB3_DP_PCS_LN_BIST_CTRL 0x1B30 +#define USB3_DP_PCS_LN_PRBS_SEED0 0x1B34 +#define USB3_DP_PCS_LN_PRBS_SEED1 0x1B38 +#define USB3_DP_PCS_LN_FIXED_PAT_CTRL 0x1B3C +#define USB3_DP_PCS_SW_RESET 0x1C00 +#define USB3_DP_PCS_REVISION_ID0 0x1C04 +#define USB3_DP_PCS_REVISION_ID1 0x1C08 +#define USB3_DP_PCS_REVISION_ID2 0x1C0C +#define USB3_DP_PCS_REVISION_ID3 0x1C10 +#define USB3_DP_PCS_PCS_STATUS1 0x1C14 +#define USB3_DP_PCS_PCS_STATUS2 0x1C18 +#define USB3_DP_PCS_PCS_STATUS3 0x1C1C +#define USB3_DP_PCS_PCS_STATUS4 0x1C20 +#define USB3_DP_PCS_PCS_STATUS5 0x1C24 +#define USB3_DP_PCS_PCS_STATUS6 0x1C28 +#define USB3_DP_PCS_PCS_STATUS7 0x1C2C +#define USB3_DP_PCS_DEBUG_BUS_0_STATUS 0x1C30 +#define USB3_DP_PCS_DEBUG_BUS_1_STATUS 0x1C34 +#define USB3_DP_PCS_DEBUG_BUS_2_STATUS 0x1C38 +#define USB3_DP_PCS_DEBUG_BUS_3_STATUS 0x1C3C +#define USB3_DP_PCS_POWER_DOWN_CONTROL 0x1C40 +#define USB3_DP_PCS_START_CONTROL 0x1C44 +#define USB3_DP_PCS_INSIG_SW_CTRL1 0x1C48 +#define USB3_DP_PCS_INSIG_SW_CTRL2 0x1C4C +#define USB3_DP_PCS_INSIG_SW_CTRL3 0x1C50 +#define USB3_DP_PCS_INSIG_SW_CTRL4 0x1C54 +#define USB3_DP_PCS_INSIG_SW_CTRL5 0x1C58 +#define USB3_DP_PCS_INSIG_SW_CTRL6 0x1C5C +#define USB3_DP_PCS_INSIG_SW_CTRL7 0x1C60 +#define USB3_DP_PCS_INSIG_SW_CTRL8 0x1C64 +#define USB3_DP_PCS_INSIG_MX_CTRL1 0x1C68 +#define USB3_DP_PCS_INSIG_MX_CTRL2 0x1C6C +#define USB3_DP_PCS_INSIG_MX_CTRL3 0x1C70 +#define USB3_DP_PCS_INSIG_MX_CTRL4 0x1C74 +#define USB3_DP_PCS_INSIG_MX_CTRL5 0x1C78 +#define USB3_DP_PCS_INSIG_MX_CTRL7 0x1C7C +#define USB3_DP_PCS_INSIG_MX_CTRL8 0x1C80 +#define USB3_DP_PCS_OUTSIG_SW_CTRL1 0x1C84 +#define USB3_DP_PCS_OUTSIG_MX_CTRL1 0x1C88 +#define USB3_DP_PCS_CLAMP_ENABLE 0x1C8C +#define USB3_DP_PCS_POWER_STATE_CONFIG1 0x1C90 +#define USB3_DP_PCS_POWER_STATE_CONFIG2 0x1C94 +#define USB3_DP_PCS_FLL_CNTRL1 0x1C98 +#define USB3_DP_PCS_FLL_CNTRL2 0x1C9C +#define USB3_DP_PCS_FLL_CNT_VAL_L 0x1CA0 +#define USB3_DP_PCS_FLL_CNT_VAL_H_TOL 0x1CA4 +#define USB3_DP_PCS_FLL_MAN_CODE 0x1CA8 +#define USB3_DP_PCS_TEST_CONTROL1 0x1CAC +#define USB3_DP_PCS_TEST_CONTROL2 0x1CB0 +#define USB3_DP_PCS_TEST_CONTROL3 0x1CB4 +#define USB3_DP_PCS_TEST_CONTROL4 0x1CB8 +#define USB3_DP_PCS_TEST_CONTROL5 0x1CBC +#define USB3_DP_PCS_TEST_CONTROL6 0x1CC0 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG1 0x1CC4 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x1CC8 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x1CCC +#define USB3_DP_PCS_LOCK_DETECT_CONFIG4 0x1CD0 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG5 0x1CD4 +#define USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x1CD8 +#define USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x1CDC +#define USB3_DP_PCS_REFGEN_REQ_CONFIG2 0x1CE0 +#define USB3_DP_PCS_REFGEN_REQ_CONFIG3 0x1CE4 +#define USB3_DP_PCS_BIST_CTRL 0x1CE8 +#define USB3_DP_PCS_PRBS_POLY0 0x1CEC +#define USB3_DP_PCS_PRBS_POLY1 0x1CF0 +#define USB3_DP_PCS_FIXED_PAT0 0x1CF4 +#define USB3_DP_PCS_FIXED_PAT1 0x1CF8 +#define USB3_DP_PCS_FIXED_PAT2 0x1CFC +#define USB3_DP_PCS_FIXED_PAT3 0x1D00 +#define USB3_DP_PCS_FIXED_PAT4 0x1D04 +#define USB3_DP_PCS_FIXED_PAT5 0x1D08 +#define USB3_DP_PCS_FIXED_PAT6 0x1D0C +#define USB3_DP_PCS_FIXED_PAT7 0x1D10 +#define USB3_DP_PCS_FIXED_PAT8 0x1D14 +#define USB3_DP_PCS_FIXED_PAT9 0x1D18 +#define USB3_DP_PCS_FIXED_PAT10 0x1D1C +#define USB3_DP_PCS_FIXED_PAT11 0x1D20 +#define USB3_DP_PCS_FIXED_PAT12 0x1D24 +#define USB3_DP_PCS_FIXED_PAT13 0x1D28 +#define USB3_DP_PCS_FIXED_PAT14 0x1D2C +#define USB3_DP_PCS_FIXED_PAT15 0x1D30 +#define USB3_DP_PCS_TXMGN_CONFIG 0x1D34 +#define USB3_DP_PCS_G12S1_TXMGN_V0 0x1D38 +#define USB3_DP_PCS_G12S1_TXMGN_V1 0x1D3C +#define USB3_DP_PCS_G12S1_TXMGN_V2 0x1D40 +#define USB3_DP_PCS_G12S1_TXMGN_V3 0x1D44 +#define USB3_DP_PCS_G12S1_TXMGN_V4 0x1D48 +#define USB3_DP_PCS_G12S1_TXMGN_V0_RS 0x1D4C +#define USB3_DP_PCS_G12S1_TXMGN_V1_RS 0x1D50 +#define USB3_DP_PCS_G12S1_TXMGN_V2_RS 0x1D54 +#define USB3_DP_PCS_G12S1_TXMGN_V3_RS 0x1D58 +#define USB3_DP_PCS_G12S1_TXMGN_V4_RS 0x1D5C +#define USB3_DP_PCS_G3S2_TXMGN_MAIN 0x1D60 +#define USB3_DP_PCS_G3S2_TXMGN_MAIN_RS 0x1D64 +#define USB3_DP_PCS_G12S1_TXDEEMPH_M6DB 0x1D68 +#define USB3_DP_PCS_G12S1_TXDEEMPH_M3P5DB 0x1D6C +#define USB3_DP_PCS_G3S2_PRE_GAIN 0x1D70 +#define USB3_DP_PCS_G3S2_POST_GAIN 0x1D74 +#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET 0x1D78 +#define USB3_DP_PCS_G3S2_PRE_GAIN_RS 0x1D7C +#define USB3_DP_PCS_G3S2_POST_GAIN_RS 0x1D80 +#define USB3_DP_PCS_G3S2_PRE_POST_OFFSET_RS 0x1D84 +#define USB3_DP_PCS_RX_SIGDET_LVL 0x1D88 +#define USB3_DP_PCS_RX_SIGDET_DTCT_CNTRL 0x1D8C +#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0x1D90 +#define USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x1D94 +#define USB3_DP_PCS_RATE_SLEW_CNTRL1 0x1D98 +#define USB3_DP_PCS_RATE_SLEW_CNTRL2 0x1D9C +#define USB3_DP_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1DA0 +#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1DA4 +#define USB3_DP_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1DA8 +#define USB3_DP_PCS_TSYNC_RSYNC_TIME 0x1DAC +#define USB3_DP_PCS_CDR_RESET_TIME 0x1DB0 +#define USB3_DP_PCS_TSYNC_DLY_TIME 0x1DB4 +#define USB3_DP_PCS_ELECIDLE_DLY_SEL 0x1DB8 +#define USB3_DP_PCS_CMN_ACK_OUT_SEL 0x1DBC +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x1DC0 +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x1DC4 +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG3 0x1DC8 +#define USB3_DP_PCS_ALIGN_DETECT_CONFIG4 0x1DCC +#define USB3_DP_PCS_PCS_TX_RX_CONFIG 0x1DD0 +#define USB3_DP_PCS_RX_IDLE_DTCT_CNTRL 0x1DD4 +#define USB3_DP_PCS_RX_DCC_CAL_CONFIG 0x1DD8 +#define USB3_DP_PCS_EQ_CONFIG1 0x1DDC +#define USB3_DP_PCS_EQ_CONFIG2 0x1DE0 +#define USB3_DP_PCS_EQ_CONFIG3 0x1DE4 +#define USB3_DP_PCS_EQ_CONFIG4 0x1DE8 +#define USB3_DP_PCS_EQ_CONFIG5 0x1DEC +#define USB3_DP_PCS_USB3_POWER_STATE_CONFIG1 0x1F00 +#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x1F04 +#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x1F08 +#define USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x1F0C +#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x1F10 +#define USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x1F14 +#define USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x1F18 +#define USB3_DP_PCS_USB3_LFPS_TX_ECSTART 0x1F1C +#define USB3_DP_PCS_USB3_LFPS_PER_TIMER_VAL 0x1F20 +#define USB3_DP_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x1F24 +#define USB3_DP_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x1F28 +#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x1F2C +#define USB3_DP_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x1F30 +#define USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x1F34 +#define USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x1F38 +#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x1F3C +#define USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x1F40 +#define USB3_DP_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x1F44 +#define USB3_DP_PCS_USB3_ARCVR_DTCT_CM_DLY 0x1F48 +#define USB3_DP_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x1F4C +#define USB3_DP_PCS_USB3_ALFPS_DEGLITCH_VAL 0x1F50 +#define USB3_DP_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x1F54 +#define USB3_DP_PCS_USB3_TEST_CONTROL 0x1F58 +#define USB3_DP_QSERDES_RXA_AUX_DATA_TCOURSE_TFINE 0x1F5C +#define USB3_DP_QSERDES_RXB_AUX_DATA_TCOURSE_TFINE 0x1F60 + +/* USB3 Uni PHY register offsets */ +#define USB3_UNI_QSERDES_COM_ATB_SEL1 0x0000 +#define USB3_UNI_QSERDES_COM_ATB_SEL2 0x0004 +#define USB3_UNI_QSERDES_COM_FREQ_UPDATE 0x0008 +#define USB3_UNI_QSERDES_COM_BG_TIMER 0x000C +#define USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x0010 +#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER1 0x0014 +#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER2 0x0018 +#define USB3_UNI_QSERDES_COM_SSC_PER1 0x001C +#define USB3_UNI_QSERDES_COM_SSC_PER2 0x0020 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0x0024 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x0028 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0 0x002C +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0x0030 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x0034 +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1 0x0038 +#define USB3_UNI_QSERDES_COM_POST_DIV 0x003C +#define USB3_UNI_QSERDES_COM_POST_DIV_MUX 0x0040 +#define USB3_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0044 +#define USB3_UNI_QSERDES_COM_CLK_ENABLE1 0x0048 +#define USB3_UNI_QSERDES_COM_SYS_CLK_CTRL 0x004C +#define USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0050 +#define USB3_UNI_QSERDES_COM_PLL_EN 0x0054 +#define USB3_UNI_QSERDES_COM_PLL_IVCO 0x0058 +#define USB3_UNI_QSERDES_COM_CMN_IETRIM 0x005C +#define USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x0060 +#define USB3_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x0064 +#define USB3_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0068 +#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE0 0x006C +#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE1 0x0070 +#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x0074 +#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x0078 +#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x007C +#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x0080 +#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x0084 +#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x0088 +#define USB3_UNI_QSERDES_COM_PLL_CNTRL 0x008C +#define USB3_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0090 +#define USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x0094 +#define USB3_UNI_QSERDES_COM_CML_SYSCLK_SEL 0x0098 +#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL 0x009C +#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL2 0x00A0 +#define USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x00A4 +#define USB3_UNI_QSERDES_COM_LOCK_CMP_CFG 0x00A8 +#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x00AC +#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x00B0 +#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x00B4 +#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x00B8 +#define USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x00BC +#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE0 0x00C0 +#define USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x00C4 +#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE1 0x00C8 +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0x00CC +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0x00D0 +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x00D4 +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0x00D8 +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0x00DC +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x00E0 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_INITVAL 0x00E4 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_EN 0x00E8 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00EC +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00F0 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00F4 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00F8 +#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 0x00FC +#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 0x0100 +#define USB3_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x0104 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_CTRL 0x0108 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x010C +#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x0110 +#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE0 0x0114 +#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x0118 +#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x011C +#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL1 0x0120 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL2 0x0124 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL1 0x0128 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL2 0x012C +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1 0x0130 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0134 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER1 0x0138 +#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER2 0x013C +#define USB3_UNI_QSERDES_COM_CMN_STATUS 0x0140 +#define USB3_UNI_QSERDES_COM_RESET_SM_STATUS 0x0144 +#define USB3_UNI_QSERDES_COM_RESTRIM_CODE_STATUS 0x0148 +#define USB3_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS 0x014C +#define USB3_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0150 +#define USB3_UNI_QSERDES_COM_CLK_SELECT 0x0154 +#define USB3_UNI_QSERDES_COM_HSCLK_SEL 0x0158 +#define USB3_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL 0x015C +#define USB3_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0160 +#define USB3_UNI_QSERDES_COM_PLL_ANALOG 0x0164 +#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE0 0x0168 +#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x016C +#define USB3_UNI_QSERDES_COM_SW_RESET 0x0170 +#define USB3_UNI_QSERDES_COM_CORE_CLK_EN 0x0174 +#define USB3_UNI_QSERDES_COM_C_READY_STATUS 0x0178 +#define USB3_UNI_QSERDES_COM_CMN_CONFIG 0x017C +#define USB3_UNI_QSERDES_COM_CMN_RATE_OVERRIDE 0x0180 +#define USB3_UNI_QSERDES_COM_SVS_MODE_CLK_SEL 0x0184 +#define USB3_UNI_QSERDES_COM_DEBUG_BUS0 0x0188 +#define USB3_UNI_QSERDES_COM_DEBUG_BUS1 0x018C +#define USB3_UNI_QSERDES_COM_DEBUG_BUS2 0x0190 +#define USB3_UNI_QSERDES_COM_DEBUG_BUS3 0x0194 +#define USB3_UNI_QSERDES_COM_DEBUG_BUS_SEL 0x0198 +#define USB3_UNI_QSERDES_COM_CMN_MISC1 0x019C +#define USB3_UNI_QSERDES_COM_CMN_MISC2 0x01A0 +#define USB3_UNI_QSERDES_COM_CMN_MODE 0x01A4 +#define USB3_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL 0x01A8 +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x01AC +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x01B0 +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x01B4 +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x01B8 +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x01BC +#define USB3_UNI_QSERDES_TX_BIST_MODE_LANENO 0x0200 +#define USB3_UNI_QSERDES_TX_BIST_INVERT 0x0204 +#define USB3_UNI_QSERDES_TX_CLKBUF_ENABLE 0x0208 +#define USB3_UNI_QSERDES_TX_TX_EMP_POST1_LVL 0x020C +#define USB3_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP 0x0210 +#define USB3_UNI_QSERDES_TX_TX_DRV_LVL 0x0214 +#define USB3_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET 0x0218 +#define USB3_UNI_QSERDES_TX_RESET_TSYNC_EN 0x021C +#define USB3_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN 0x0220 +#define USB3_UNI_QSERDES_TX_TX_BAND 0x0224 +#define USB3_UNI_QSERDES_TX_SLEW_CNTL 0x0228 +#define USB3_UNI_QSERDES_TX_INTERFACE_SELECT 0x022C +#define USB3_UNI_QSERDES_TX_LPB_EN 0x0230 +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0x0234 +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0x0238 +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x023C +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0240 +#define USB3_UNI_QSERDES_TX_PERL_LENGTH1 0x0244 +#define USB3_UNI_QSERDES_TX_PERL_LENGTH2 0x0248 +#define USB3_UNI_QSERDES_TX_SERDES_BYP_EN_OUT 0x024C +#define USB3_UNI_QSERDES_TX_DEBUG_BUS_SEL 0x0250 +#define USB3_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN 0x0254 +#define USB3_UNI_QSERDES_TX_HIGHZ_DRVR_EN 0x0258 +#define USB3_UNI_QSERDES_TX_TX_POL_INV 0x025C +#define USB3_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN 0x0260 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN1 0x0264 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN2 0x0268 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN3 0x026C +#define USB3_UNI_QSERDES_TX_BIST_PATTERN4 0x0270 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN5 0x0274 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN6 0x0278 +#define USB3_UNI_QSERDES_TX_BIST_PATTERN7 0x027C +#define USB3_UNI_QSERDES_TX_BIST_PATTERN8 0x0280 +#define USB3_UNI_QSERDES_TX_LANE_MODE_1 0x0284 +#define USB3_UNI_QSERDES_TX_LANE_MODE_2 0x0288 +#define USB3_UNI_QSERDES_TX_LANE_MODE_3 0x028C +#define USB3_UNI_QSERDES_TX_ATB_SEL1 0x0290 +#define USB3_UNI_QSERDES_TX_ATB_SEL2 0x0294 +#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL 0x0298 +#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x029C +#define USB3_UNI_QSERDES_TX_PRBS_SEED1 0x02A0 +#define USB3_UNI_QSERDES_TX_PRBS_SEED2 0x02A4 +#define USB3_UNI_QSERDES_TX_PRBS_SEED3 0x02A8 +#define USB3_UNI_QSERDES_TX_PRBS_SEED4 0x02AC +#define USB3_UNI_QSERDES_TX_RESET_GEN 0x02B0 +#define USB3_UNI_QSERDES_TX_RESET_GEN_MUXES 0x02B4 +#define USB3_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN 0x02B8 +#define USB3_UNI_QSERDES_TX_TX_INTERFACE_MODE 0x02BC +#define USB3_UNI_QSERDES_TX_PWM_CTRL 0x02C0 +#define USB3_UNI_QSERDES_TX_PWM_ENCODED_OR_DATA 0x02C4 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2 0x02C8 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2 0x02CC +#define USB3_UNI_QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2 0x02D0 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2 0x02D4 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x02D8 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x02DC +#define USB3_UNI_QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x02E0 +#define USB3_UNI_QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x02E4 +#define USB3_UNI_QSERDES_TX_VMODE_CTRL1 0x02E8 +#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1 0x02EC +#define USB3_UNI_QSERDES_TX_BIST_STATUS 0x02F0 +#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT1 0x02F4 +#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT2 0x02F8 +#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1 0x02FC +#define USB3_UNI_QSERDES_TX_LANE_DIG_CONFIG 0x0300 +#define USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x0304 +#define USB3_UNI_QSERDES_TX_PRE_EMPH 0x0308 +#define USB3_UNI_QSERDES_TX_SW_RESET 0x030C +#define USB3_UNI_QSERDES_TX_DIG_BKUP_CTRL 0x0310 +#define USB3_UNI_QSERDES_TX_DEBUG_BUS0 0x0314 +#define USB3_UNI_QSERDES_TX_DEBUG_BUS1 0x0318 +#define USB3_UNI_QSERDES_TX_DEBUG_BUS2 0x031C +#define USB3_UNI_QSERDES_TX_DEBUG_BUS3 0x0320 +#define USB3_UNI_QSERDES_TX_READ_EQCODE 0x0324 +#define USB3_UNI_QSERDES_TX_READ_OFFSETCODE 0x0328 +#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW 0x032C +#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH 0x0330 +#define USB3_UNI_QSERDES_TX_VGA_READ_CODE 0x0334 +#define USB3_UNI_QSERDES_TX_VTH_READ_CODE 0x0338 +#define USB3_UNI_QSERDES_TX_DFE_TAP1_READ_CODE 0x033C +#define USB3_UNI_QSERDES_TX_DFE_TAP2_READ_CODE 0x0340 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_I 0x0344 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_IBAR 0x0348 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_Q 0x034C +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_QBAR 0x0350 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_A 0x0354 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_ABAR 0x0358 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SM_ON 0x035C +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE 0x0360 +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR 0x0364 +#define USB3_UNI_QSERDES_TX_DCC_CAL_STATUS 0x0368 +#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF 0x0400 +#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER 0x0404 +#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0408 +#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF 0x040C +#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER 0x0410 +#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x0414 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF 0x0418 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER 0x041C +#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN 0x0420 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x0424 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x0428 +#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN 0x042C +#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x0430 +#define USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x0434 +#define USB3_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY 0x0438 +#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0x043C +#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0440 +#define USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x0444 +#define USB3_UNI_QSERDES_RX_UCDR_PI_CTRL2 0x0448 +#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x044C +#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x0450 +#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x0454 +#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x0458 +#define USB3_UNI_QSERDES_RX_AUX_CONTROL 0x045C +#define USB3_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE 0x0460 +#define USB3_UNI_QSERDES_RX_RCLK_AUXDATA_SEL 0x0464 +#define USB3_UNI_QSERDES_RX_AC_JTAG_ENABLE 0x0468 +#define USB3_UNI_QSERDES_RX_AC_JTAG_INITP 0x046C +#define USB3_UNI_QSERDES_RX_AC_JTAG_INITN 0x0470 +#define USB3_UNI_QSERDES_RX_AC_JTAG_LVL 0x0474 +#define USB3_UNI_QSERDES_RX_AC_JTAG_MODE 0x0478 +#define USB3_UNI_QSERDES_RX_AC_JTAG_RESET 0x047C +#define USB3_UNI_QSERDES_RX_RX_TERM_BW 0x0480 +#define USB3_UNI_QSERDES_RX_RX_RCVR_IQ_EN 0x0484 +#define USB3_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS 0x0488 +#define USB3_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS 0x048C +#define USB3_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS 0x0490 +#define USB3_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS 0x0494 +#define USB3_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS 0x0498 +#define USB3_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS 0x049C +#define USB3_UNI_QSERDES_RX_RX_IDAC_EN 0x04A0 +#define USB3_UNI_QSERDES_RX_RX_IDAC_ENABLES 0x04A4 +#define USB3_UNI_QSERDES_RX_RX_IDAC_SIGN 0x04A8 +#define USB3_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE 0x04AC +#define USB3_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x04B0 +#define USB3_UNI_QSERDES_RX_DFE_1 0x04B4 +#define USB3_UNI_QSERDES_RX_DFE_2 0x04B8 +#define USB3_UNI_QSERDES_RX_DFE_3 0x04BC +#define USB3_UNI_QSERDES_RX_DFE_4 0x04C0 +#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1 0x04C4 +#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2 0x04C8 +#define USB3_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH 0x04CC +#define USB3_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH 0x04D0 +#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x04D4 +#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x04D8 +#define USB3_UNI_QSERDES_RX_GM_CAL 0x04DC +#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB 0x04E0 +#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB 0x04E4 +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 0x04E8 +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x04EC +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x04F0 +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x04F4 +#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0x04F8 +#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x04FC +#define USB3_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME 0x0500 +#define USB3_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR 0x0504 +#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB 0x0508 +#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB 0x050C +#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0510 +#define USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0514 +#define USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x0518 +#define USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x051C +#define USB3_UNI_QSERDES_RX_SIGDET_LVL 0x0520 +#define USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0524 +#define USB3_UNI_QSERDES_RX_RX_BAND 0x0528 +#define USB3_UNI_QSERDES_RX_CDR_FREEZE_UP_DN 0x052C +#define USB3_UNI_QSERDES_RX_CDR_RESET_OVERRIDE 0x0530 +#define USB3_UNI_QSERDES_RX_RX_INTERFACE_MODE 0x0534 +#define USB3_UNI_QSERDES_RX_JITTER_GEN_MODE 0x0538 +#define USB3_UNI_QSERDES_RX_SJ_AMP1 0x053C +#define USB3_UNI_QSERDES_RX_SJ_AMP2 0x0540 +#define USB3_UNI_QSERDES_RX_SJ_PER1 0x0544 +#define USB3_UNI_QSERDES_RX_SJ_PER2 0x0548 +#define USB3_UNI_QSERDES_RX_PPM_OFFSET1 0x054C +#define USB3_UNI_QSERDES_RX_PPM_OFFSET2 0x0550 +#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD1 0x0554 +#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD2 0x0558 +#define USB3_UNI_QSERDES_RX_RX_PWM_ENABLE_AND_DATA 0x055C +#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT 0x0560 +#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT 0x0564 +#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT 0x0568 +#define USB3_UNI_QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT 0x056C +#define USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x0570 +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x0574 +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x0578 +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x057C +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0x0580 +#define USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x0584 +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x0588 +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x058C +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0590 +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0x0594 +#define USB3_UNI_QSERDES_RX_RX_MODE_10_LOW 0x0598 +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH 0x059C +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH2 0x05A0 +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH3 0x05A4 +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH4 0x05A8 +#define USB3_UNI_QSERDES_RX_PHPRE_CTRL 0x05AC +#define USB3_UNI_QSERDES_RX_PHPRE_INITVAL 0x05B0 +#define USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x05B4 +#define USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x05B8 +#define USB3_UNI_QSERDES_RX_DCC_CTRL1 0x05BC +#define USB3_UNI_QSERDES_RX_DCC_CTRL2 0x05C0 +#define USB3_UNI_QSERDES_RX_VTH_CODE 0x05C4 +#define USB3_UNI_QSERDES_RX_VTH_MIN_THRESH 0x05C8 +#define USB3_UNI_QSERDES_RX_VTH_MAX_THRESH 0x05CC +#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1 0x05D0 +#define USB3_UNI_QSERDES_RX_PI_CTRL1 0x05D4 +#define USB3_UNI_QSERDES_RX_PI_CTRL2 0x05D8 +#define USB3_UNI_QSERDES_RX_PI_QUAD 0x05DC +#define USB3_UNI_QSERDES_RX_IDATA1 0x05E0 +#define USB3_UNI_QSERDES_RX_IDATA2 0x05E4 +#define USB3_UNI_QSERDES_RX_AUX_DATA1 0x05E8 +#define USB3_UNI_QSERDES_RX_AUX_DATA2 0x05EC +#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTP 0x05F0 +#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTN 0x05F4 +#define USB3_UNI_QSERDES_RX_RX_SIGDET 0x05F8 +#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1 0x05FC +#define USB3_UNI_PCS_LN_PCS_STATUS1 0x0600 +#define USB3_UNI_PCS_LN_PCS_STATUS2 0x0604 +#define USB3_UNI_PCS_LN_PCS_STATUS2_CLEAR 0x0608 +#define USB3_UNI_PCS_LN_PCS_STATUS3 0x060C +#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x0610 +#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x0614 +#define USB3_UNI_PCS_LN_BIST_CHK_STATUS 0x0618 +#define USB3_UNI_PCS_LN_INSIG_SW_CTRL1 0x061C +#define USB3_UNI_PCS_LN_INSIG_MX_CTRL1 0x0620 +#define USB3_UNI_PCS_LN_OUTSIG_SW_CTRL1 0x0624 +#define USB3_UNI_PCS_LN_OUTSIG_MX_CTRL1 0x0628 +#define USB3_UNI_PCS_LN_TEST_CONTROL 0x062C +#define USB3_UNI_PCS_LN_BIST_CTRL 0x0630 +#define USB3_UNI_PCS_LN_PRBS_SEED0 0x0634 +#define USB3_UNI_PCS_LN_PRBS_SEED1 0x0638 +#define USB3_UNI_PCS_LN_FIXED_PAT_CTRL 0x063C +#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST 0x0700 +#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS 0x0704 +#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN 0x0708 +#define USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_L 0x070C +#define USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_H 0x0710 +#define USB3_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG 0x0714 +#define USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1 0x0718 +#define USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2 0x071C +#define USB3_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS 0x0720 +#define USB3_UNI_PCS_SW_RESET 0x0800 +#define USB3_UNI_PCS_REVISION_ID0 0x0804 +#define USB3_UNI_PCS_REVISION_ID1 0x0808 +#define USB3_UNI_PCS_REVISION_ID2 0x080C +#define USB3_UNI_PCS_REVISION_ID3 0x0810 +#define USB3_UNI_PCS_PCS_STATUS1 0x0814 +#define USB3_UNI_PCS_PCS_STATUS2 0x0818 +#define USB3_UNI_PCS_PCS_STATUS3 0x081C +#define USB3_UNI_PCS_PCS_STATUS4 0x0820 +#define USB3_UNI_PCS_PCS_STATUS5 0x0824 +#define USB3_UNI_PCS_PCS_STATUS6 0x0828 +#define USB3_UNI_PCS_PCS_STATUS7 0x082C +#define USB3_UNI_PCS_DEBUG_BUS_0_STATUS 0x0830 +#define USB3_UNI_PCS_DEBUG_BUS_1_STATUS 0x0834 +#define USB3_UNI_PCS_DEBUG_BUS_2_STATUS 0x0838 +#define USB3_UNI_PCS_DEBUG_BUS_3_STATUS 0x083C +#define USB3_UNI_PCS_POWER_DOWN_CONTROL 0x0840 +#define USB3_UNI_PCS_START_CONTROL 0x0844 +#define USB3_UNI_PCS_INSIG_SW_CTRL1 0x0848 +#define USB3_UNI_PCS_INSIG_SW_CTRL2 0x084C +#define USB3_UNI_PCS_INSIG_SW_CTRL3 0x0850 +#define USB3_UNI_PCS_INSIG_SW_CTRL4 0x0854 +#define USB3_UNI_PCS_INSIG_SW_CTRL5 0x0858 +#define USB3_UNI_PCS_INSIG_SW_CTRL6 0x085C +#define USB3_UNI_PCS_INSIG_SW_CTRL7 0x0860 +#define USB3_UNI_PCS_INSIG_SW_CTRL8 0x0864 +#define USB3_UNI_PCS_INSIG_MX_CTRL1 0x0868 +#define USB3_UNI_PCS_INSIG_MX_CTRL2 0x086C +#define USB3_UNI_PCS_INSIG_MX_CTRL3 0x0870 +#define USB3_UNI_PCS_INSIG_MX_CTRL4 0x0874 +#define USB3_UNI_PCS_INSIG_MX_CTRL5 0x0878 +#define USB3_UNI_PCS_INSIG_MX_CTRL7 0x087C +#define USB3_UNI_PCS_INSIG_MX_CTRL8 0x0880 +#define USB3_UNI_PCS_OUTSIG_SW_CTRL1 0x0884 +#define USB3_UNI_PCS_OUTSIG_MX_CTRL1 0x0888 +#define USB3_UNI_PCS_CLAMP_ENABLE 0x088C +#define USB3_UNI_PCS_POWER_STATE_CONFIG1 0x0890 +#define USB3_UNI_PCS_POWER_STATE_CONFIG2 0x0894 +#define USB3_UNI_PCS_FLL_CNTRL1 0x0898 +#define USB3_UNI_PCS_FLL_CNTRL2 0x089C +#define USB3_UNI_PCS_FLL_CNT_VAL_L 0x08A0 +#define USB3_UNI_PCS_FLL_CNT_VAL_H_TOL 0x08A4 +#define USB3_UNI_PCS_FLL_MAN_CODE 0x08A8 +#define USB3_UNI_PCS_TEST_CONTROL1 0x08AC +#define USB3_UNI_PCS_TEST_CONTROL2 0x08B0 +#define USB3_UNI_PCS_TEST_CONTROL3 0x08B4 +#define USB3_UNI_PCS_TEST_CONTROL4 0x08B8 +#define USB3_UNI_PCS_TEST_CONTROL5 0x08BC +#define USB3_UNI_PCS_TEST_CONTROL6 0x08C0 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0x08C4 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x08C8 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x08CC +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG4 0x08D0 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG5 0x08D4 +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x08D8 +#define USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x08DC +#define USB3_UNI_PCS_REFGEN_REQ_CONFIG2 0x08E0 +#define USB3_UNI_PCS_REFGEN_REQ_CONFIG3 0x08E4 +#define USB3_UNI_PCS_BIST_CTRL 0x08E8 +#define USB3_UNI_PCS_PRBS_POLY0 0x08EC +#define USB3_UNI_PCS_PRBS_POLY1 0x08F0 +#define USB3_UNI_PCS_FIXED_PAT0 0x08F4 +#define USB3_UNI_PCS_FIXED_PAT1 0x08F8 +#define USB3_UNI_PCS_FIXED_PAT2 0x08FC +#define USB3_UNI_PCS_FIXED_PAT3 0x0900 +#define USB3_UNI_PCS_FIXED_PAT4 0x0904 +#define USB3_UNI_PCS_FIXED_PAT5 0x0908 +#define USB3_UNI_PCS_FIXED_PAT6 0x090C +#define USB3_UNI_PCS_FIXED_PAT7 0x0910 +#define USB3_UNI_PCS_FIXED_PAT8 0x0914 +#define USB3_UNI_PCS_FIXED_PAT9 0x0918 +#define USB3_UNI_PCS_FIXED_PAT10 0x091C +#define USB3_UNI_PCS_FIXED_PAT11 0x0920 +#define USB3_UNI_PCS_FIXED_PAT12 0x0924 +#define USB3_UNI_PCS_FIXED_PAT13 0x0928 +#define USB3_UNI_PCS_FIXED_PAT14 0x092C +#define USB3_UNI_PCS_FIXED_PAT15 0x0930 +#define USB3_UNI_PCS_TXMGN_CONFIG 0x0934 +#define USB3_UNI_PCS_G12S1_TXMGN_V0 0x0938 +#define USB3_UNI_PCS_G12S1_TXMGN_V1 0x093C +#define USB3_UNI_PCS_G12S1_TXMGN_V2 0x0940 +#define USB3_UNI_PCS_G12S1_TXMGN_V3 0x0944 +#define USB3_UNI_PCS_G12S1_TXMGN_V4 0x0948 +#define USB3_UNI_PCS_G12S1_TXMGN_V0_RS 0x094C +#define USB3_UNI_PCS_G12S1_TXMGN_V1_RS 0x0950 +#define USB3_UNI_PCS_G12S1_TXMGN_V2_RS 0x0954 +#define USB3_UNI_PCS_G12S1_TXMGN_V3_RS 0x0958 +#define USB3_UNI_PCS_G12S1_TXMGN_V4_RS 0x095C +#define USB3_UNI_PCS_G3S2_TXMGN_MAIN 0x0960 +#define USB3_UNI_PCS_G3S2_TXMGN_MAIN_RS 0x0964 +#define USB3_UNI_PCS_G12S1_TXDEEMPH_M6DB 0x0968 +#define USB3_UNI_PCS_G12S1_TXDEEMPH_M3P5DB 0x096C +#define USB3_UNI_PCS_G3S2_PRE_GAIN 0x0970 +#define USB3_UNI_PCS_G3S2_POST_GAIN 0x0974 +#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET 0x0978 +#define USB3_UNI_PCS_G3S2_PRE_GAIN_RS 0x097C +#define USB3_UNI_PCS_G3S2_POST_GAIN_RS 0x0980 +#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET_RS 0x0984 +#define USB3_UNI_PCS_RX_SIGDET_LVL 0x0988 +#define USB3_UNI_PCS_RX_SIGDET_DTCT_CNTRL 0x098C +#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0x0990 +#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x0994 +#define USB3_UNI_PCS_RATE_SLEW_CNTRL1 0x0998 +#define USB3_UNI_PCS_RATE_SLEW_CNTRL2 0x099C +#define USB3_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x09A0 +#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x09A4 +#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x09A8 +#define USB3_UNI_PCS_TSYNC_RSYNC_TIME 0x09AC +#define USB3_UNI_PCS_CDR_RESET_TIME 0x09B0 +#define USB3_UNI_PCS_TSYNC_DLY_TIME 0x09B4 +#define USB3_UNI_PCS_ELECIDLE_DLY_SEL 0x09B8 +#define USB3_UNI_PCS_CMN_ACK_OUT_SEL 0x09BC +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x09C0 +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x09C4 +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG3 0x09C8 +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG4 0x09CC +#define USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x09D0 +#define USB3_UNI_PCS_RX_IDLE_DTCT_CNTRL 0x09D4 +#define USB3_UNI_PCS_RX_DCC_CAL_CONFIG 0x09D8 +#define USB3_UNI_PCS_EQ_CONFIG1 0x09DC +#define USB3_UNI_PCS_EQ_CONFIG2 0x09E0 +#define USB3_UNI_PCS_EQ_CONFIG3 0x09E4 +#define USB3_UNI_PCS_EQ_CONFIG4 0x09E8 +#define USB3_UNI_PCS_EQ_CONFIG5 0x09EC +#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_STATUS 0x0C00 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_STATUS 0x0C04 +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG1 0x0C08 +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG2 0x0C0C +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG3 0x0C10 +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG4 0x0C14 +#define USB3_UNI_PCS_PCIE_PCS_TX_RX_CONFIG 0x0C18 +#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x0C1C +#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x0C20 +#define USB3_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x0C24 +#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0x0C28 +#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0x0C2C +#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0x0C30 +#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0x0C34 +#define USB3_UNI_PCS_PCIE_SIGDET_CNTRL 0x0C38 +#define USB3_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0x0C3C +#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x0C40 +#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x0C44 +#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x0C48 +#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x0C4C +#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x0C50 +#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2 0x0C54 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG1 0x0C58 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG2 0x0C5C +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG3 0x0C60 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG4 0x0C64 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG5 0x0C68 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG6 0x0C6C +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG7 0x0C70 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0x0C74 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x0C78 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0x0C7C +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x0C80 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x0C84 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0x0C88 +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0x0C8C +#define USB3_UNI_PCS_PCIE_OSC_DTCT_ACTIONS 0x0C90 +#define USB3_UNI_PCS_PCIE_LOCAL_FS 0x0C94 +#define USB3_UNI_PCS_PCIE_LOCAL_LF 0x0C98 +#define USB3_UNI_PCS_PCIE_LOCAL_FS_RS 0x0C9C +#define USB3_UNI_PCS_PCIE_EQ_CONFIG1 0x0CA0 +#define USB3_UNI_PCS_PCIE_EQ_CONFIG2 0x0CA4 +#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_PRE 0x0CA8 +#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_PRE 0x0CAC +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE 0x0CB0 +#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_PRE 0x0CB4 +#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_PRE 0x0CB8 +#define USB3_UNI_PCS_PCIE_PRESET_P10_PRE 0x0CBC +#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS 0x0CC0 +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS 0x0CC4 +#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS 0x0CC8 +#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_POST 0x0CCC +#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_POST 0x0CD0 +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST 0x0CD4 +#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_POST 0x0CD8 +#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_POST 0x0CDC +#define USB3_UNI_PCS_PCIE_PRESET_P10_POST 0x0CE0 +#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS 0x0CE4 +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS 0x0CE8 +#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS 0x0CEC +#define USB3_UNI_PCS_PCIE_RXEQEVAL_TIME 0x0CF0 +#define USB3_UNI_PCS_PCIE_INSIG_SW_CTRL1 0x0CF4 +#define USB3_UNI_PCS_PCIE_INSIG_MX_CTRL1 0x0CF8 +#define USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1 0x0E00 +#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x0E04 +#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x0E08 +#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x0E0C +#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x0E10 +#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x0E14 +#define USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x0E18 +#define USB3_UNI_PCS_USB3_LFPS_TX_ECSTART 0x0E1C +#define USB3_UNI_PCS_USB3_LFPS_PER_TIMER_VAL 0x0E20 +#define USB3_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x0E24 +#define USB3_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x0E28 +#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x0E2C +#define USB3_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x0E30 +#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x0E34 +#define USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x0E38 +#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x0E3C +#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x0E40 +#define USB3_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x0E44 +#define USB3_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY 0x0E48 +#define USB3_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x0E4C +#define USB3_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL 0x0E50 +#define USB3_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x0E54 +#define USB3_UNI_PCS_USB3_TEST_CONTROL 0x0E58 +#define USB3_UNI_PCS_USB3_RXTERMINATION_DLY_SEL 0x0E5C + +#endif /* _DT_BINDINGS_PHY_QCOM_SM8150_QMP_USB_H */ diff --git a/include/dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h b/include/dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h new file mode 100644 index 000000000000..99ca2a070e9a --- /dev/null +++ b/include/dt-bindings/phy/qcom,usb3-5nm-qmp-uni.h @@ -0,0 +1,621 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef _DT_BINDINGS_PHY_QCOM_5NM_QMP_UNI_USB_H +#define _DT_BINDINGS_PHY_QCOM_5NM_QMP_UNI_USB_H + +/* USB3 Uni PHY register offsets */ +/* Module: USB3_UNI_PHY_QSERDES_COM_QSERDES_COM_PCIE_USB3_UNI_QMP_PLL */ +#define USB3_UNI_QSERDES_COM_ATB_SEL1 (0x0000 + 0x0000) +#define USB3_UNI_QSERDES_COM_ATB_SEL2 (0x0000 + 0x0004) +#define USB3_UNI_QSERDES_COM_FREQ_UPDATE (0x0000 + 0x0008) +#define USB3_UNI_QSERDES_COM_BG_TIMER (0x0000 + 0x000c) +#define USB3_UNI_QSERDES_COM_SSC_EN_CENTER (0x0000 + 0x0010) +#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER1 (0x0000 + 0x0014) +#define USB3_UNI_QSERDES_COM_SSC_ADJ_PER2 (0x0000 + 0x0018) +#define USB3_UNI_QSERDES_COM_SSC_PER1 (0x0000 + 0x001c) +#define USB3_UNI_QSERDES_COM_SSC_PER2 (0x0000 + 0x0020) +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 (0x0000 + 0x0024) +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 (0x0000 + 0x0028) +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE0 (0x0000 + 0x002c) +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 (0x0000 + 0x0030) +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 (0x0000 + 0x0034) +#define USB3_UNI_QSERDES_COM_SSC_STEP_SIZE3_MODE1 (0x0000 + 0x0038) +#define USB3_UNI_QSERDES_COM_POST_DIV (0x0000 + 0x003c) +#define USB3_UNI_QSERDES_COM_POST_DIV_MUX (0x0000 + 0x0040) +#define USB3_UNI_QSERDES_COM_BIAS_EN_CLKBUFLR_EN (0x0000 + 0x0044) +#define USB3_UNI_QSERDES_COM_CLK_ENABLE1 (0x0000 + 0x0048) +#define USB3_UNI_QSERDES_COM_SYS_CLK_CTRL (0x0000 + 0x004c) +#define USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE (0x0000 + 0x0050) +#define USB3_UNI_QSERDES_COM_PLL_EN (0x0000 + 0x0054) +#define USB3_UNI_QSERDES_COM_PLL_IVCO (0x0000 + 0x0058) +#define USB3_UNI_QSERDES_COM_CMN_IETRIM (0x0000 + 0x005c) +#define USB3_UNI_QSERDES_COM_CMN_IPTRIM (0x0000 + 0x0060) +#define USB3_UNI_QSERDES_COM_EP_CLOCK_DETECT_CTRL (0x0000 + 0x0064) +#define USB3_UNI_QSERDES_COM_SYSCLK_DET_COMP_STATUS (0x0000 + 0x0068) +#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE0 (0x0000 + 0x006c) +#define USB3_UNI_QSERDES_COM_CLK_EP_DIV_MODE1 (0x0000 + 0x0070) +#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 (0x0000 + 0x0074) +#define USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 (0x0000 + 0x0078) +#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 (0x0000 + 0x007c) +#define USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 (0x0000 + 0x0080) +#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 (0x0000 + 0x0084) +#define USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 (0x0000 + 0x0088) +#define USB3_UNI_QSERDES_COM_PLL_CNTRL (0x0000 + 0x008c) +#define USB3_UNI_QSERDES_COM_BIAS_EN_CTRL_BY_PSM (0x0000 + 0x0090) +#define USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL (0x0000 + 0x0094) +#define USB3_UNI_QSERDES_COM_CML_SYSCLK_SEL (0x0000 + 0x0098) +#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL (0x0000 + 0x009c) +#define USB3_UNI_QSERDES_COM_RESETSM_CNTRL2 (0x0000 + 0x00a0) +#define USB3_UNI_QSERDES_COM_LOCK_CMP_EN (0x0000 + 0x00a4) +#define USB3_UNI_QSERDES_COM_LOCK_CMP_CFG (0x0000 + 0x00a8) +#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 (0x0000 + 0x00ac) +#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 (0x0000 + 0x00b0) +#define USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 (0x0000 + 0x00b4) +#define USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 (0x0000 + 0x00b8) +#define USB3_UNI_QSERDES_COM_DEC_START_MODE0 (0x0000 + 0x00bc) +#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE0 (0x0000 + 0x00c0) +#define USB3_UNI_QSERDES_COM_DEC_START_MODE1 (0x0000 + 0x00c4) +#define USB3_UNI_QSERDES_COM_DEC_START_MSB_MODE1 (0x0000 + 0x00c8) +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 (0x0000 + 0x00cc) +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 (0x0000 + 0x00d0) +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 (0x0000 + 0x00d4) +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 (0x0000 + 0x00d8) +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 (0x0000 + 0x00dc) +#define USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 (0x0000 + 0x00e0) +#define USB3_UNI_QSERDES_COM_INTEGLOOP_INITVAL (0x0000 + 0x00e4) +#define USB3_UNI_QSERDES_COM_INTEGLOOP_EN (0x0000 + 0x00e8) +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 (0x0000 + 0x00ec) +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 (0x0000 + 0x00f0) +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 (0x0000 + 0x00f4) +#define USB3_UNI_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 (0x0000 + 0x00f8) +#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN0 (0x0000 + 0x00fc) +#define USB3_UNI_QSERDES_COM_INTEGLOOP_P_PATH_GAIN1 (0x0000 + 0x0100) +#define USB3_UNI_QSERDES_COM_VCOCAL_DEADMAN_CTRL (0x0000 + 0x0104) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_CTRL (0x0000 + 0x0108) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAP (0x0000 + 0x010c) +#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 (0x0000 + 0x0110) +#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE0 (0x0000 + 0x0114) +#define USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 (0x0000 + 0x0118) +#define USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 (0x0000 + 0x011c) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL1 (0x0000 + 0x0120) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_INITVAL2 (0x0000 + 0x0124) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL1 (0x0000 + 0x0128) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MINVAL2 (0x0000 + 0x012c) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL1 (0x0000 + 0x0130) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_MAXVAL2 (0x0000 + 0x0134) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER1 (0x0000 + 0x0138) +#define USB3_UNI_QSERDES_COM_VCO_TUNE_TIMER2 (0x0000 + 0x013c) +#define USB3_UNI_QSERDES_COM_CMN_STATUS (0x0000 + 0x0140) +#define USB3_UNI_QSERDES_COM_RESET_SM_STATUS (0x0000 + 0x0144) +#define USB3_UNI_QSERDES_COM_RESTRIM_CODE_STATUS (0x0000 + 0x0148) +#define USB3_UNI_QSERDES_COM_PLLCAL_CODE1_STATUS (0x0000 + 0x014c) +#define USB3_UNI_QSERDES_COM_PLLCAL_CODE2_STATUS (0x0000 + 0x0150) +#define USB3_UNI_QSERDES_COM_CLK_SELECT (0x0000 + 0x0154) +#define USB3_UNI_QSERDES_COM_HSCLK_SEL (0x0000 + 0x0158) +#define USB3_UNI_QSERDES_COM_HSCLK_HS_SWITCH_SEL (0x0000 + 0x015c) +#define USB3_UNI_QSERDES_COM_INTEGLOOP_BINCODE_STATUS (0x0000 + 0x0160) +#define USB3_UNI_QSERDES_COM_PLL_ANALOG (0x0000 + 0x0164) +#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE0 (0x0000 + 0x0168) +#define USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 (0x0000 + 0x016c) +#define USB3_UNI_QSERDES_COM_SW_RESET (0x0000 + 0x0170) +#define USB3_UNI_QSERDES_COM_CORE_CLK_EN (0x0000 + 0x0174) +#define USB3_UNI_QSERDES_COM_C_READY_STATUS (0x0000 + 0x0178) +#define USB3_UNI_QSERDES_COM_CMN_CONFIG (0x0000 + 0x017c) +#define USB3_UNI_QSERDES_COM_CMN_RATE_OVERRIDE (0x0000 + 0x0180) +#define USB3_UNI_QSERDES_COM_SVS_MODE_CLK_SEL (0x0000 + 0x0184) +#define USB3_UNI_QSERDES_COM_DEBUG_BUS0 (0x0000 + 0x0188) +#define USB3_UNI_QSERDES_COM_DEBUG_BUS1 (0x0000 + 0x018c) +#define USB3_UNI_QSERDES_COM_DEBUG_BUS2 (0x0000 + 0x0190) +#define USB3_UNI_QSERDES_COM_DEBUG_BUS3 (0x0000 + 0x0194) +#define USB3_UNI_QSERDES_COM_DEBUG_BUS_SEL (0x0000 + 0x0198) +#define USB3_UNI_QSERDES_COM_CMN_MISC1 (0x0000 + 0x019c) +#define USB3_UNI_QSERDES_COM_CMN_MODE (0x0000 + 0x01a0) +#define USB3_UNI_QSERDES_COM_CMN_MODE_CONTD (0x0000 + 0x01a4) +#define USB3_UNI_QSERDES_COM_VCO_DC_LEVEL_CTRL (0x0000 + 0x01a8) +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 (0x0000 + 0x01ac) +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 (0x0000 + 0x01b0) +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 (0x0000 + 0x01b4) +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 (0x0000 + 0x01b8) +#define USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL (0x0000 + 0x01bc) +#define USB3_UNI_QSERDES_COM_RESERVED_1 (0x0000 + 0x01c0) +#define USB3_UNI_QSERDES_COM_MODE_OPERATION_STATUS (0x0000 + 0x01c4) + +/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS_PCIE_USB3_UNI_PCS */ +#define USB3_UNI_PCS_SW_RESET (0x0200 + 0x0000) +#define USB3_UNI_PCS_REVISION_ID0 (0x0200 + 0x0004) +#define USB3_UNI_PCS_REVISION_ID1 (0x0200 + 0x0008) +#define USB3_UNI_PCS_REVISION_ID2 (0x0200 + 0x000c) +#define USB3_UNI_PCS_REVISION_ID3 (0x0200 + 0x0010) +#define USB3_UNI_PCS_PCS_STATUS1 (0x0200 + 0x0014) +#define USB3_UNI_PCS_PCS_STATUS2 (0x0200 + 0x0018) +#define USB3_UNI_PCS_PCS_STATUS3 (0x0200 + 0x001c) +#define USB3_UNI_PCS_PCS_STATUS4 (0x0200 + 0x0020) +#define USB3_UNI_PCS_PCS_STATUS5 (0x0200 + 0x0024) +#define USB3_UNI_PCS_PCS_STATUS6 (0x0200 + 0x0028) +#define USB3_UNI_PCS_PCS_STATUS7 (0x0200 + 0x002c) +#define USB3_UNI_PCS_DEBUG_BUS_0_STATUS (0x0200 + 0x0030) +#define USB3_UNI_PCS_DEBUG_BUS_1_STATUS (0x0200 + 0x0034) +#define USB3_UNI_PCS_DEBUG_BUS_2_STATUS (0x0200 + 0x0038) +#define USB3_UNI_PCS_DEBUG_BUS_3_STATUS (0x0200 + 0x003c) +#define USB3_UNI_PCS_POWER_DOWN_CONTROL (0x0200 + 0x0040) +#define USB3_UNI_PCS_START_CONTROL (0x0200 + 0x0044) +#define USB3_UNI_PCS_INSIG_SW_CTRL1 (0x0200 + 0x0048) +#define USB3_UNI_PCS_INSIG_SW_CTRL2 (0x0200 + 0x004c) +#define USB3_UNI_PCS_INSIG_SW_CTRL3 (0x0200 + 0x0050) +#define USB3_UNI_PCS_INSIG_SW_CTRL4 (0x0200 + 0x0054) +#define USB3_UNI_PCS_INSIG_SW_CTRL5 (0x0200 + 0x0058) +#define USB3_UNI_PCS_INSIG_SW_CTRL6 (0x0200 + 0x005c) +#define USB3_UNI_PCS_INSIG_SW_CTRL7 (0x0200 + 0x0060) +#define USB3_UNI_PCS_INSIG_SW_CTRL8 (0x0200 + 0x0064) +#define USB3_UNI_PCS_INSIG_MX_CTRL1 (0x0200 + 0x0068) +#define USB3_UNI_PCS_INSIG_MX_CTRL2 (0x0200 + 0x006c) +#define USB3_UNI_PCS_INSIG_MX_CTRL3 (0x0200 + 0x0070) +#define USB3_UNI_PCS_INSIG_MX_CTRL4 (0x0200 + 0x0074) +#define USB3_UNI_PCS_INSIG_MX_CTRL5 (0x0200 + 0x0078) +#define USB3_UNI_PCS_INSIG_MX_CTRL7 (0x0200 + 0x007c) +#define USB3_UNI_PCS_INSIG_MX_CTRL8 (0x0200 + 0x0080) +#define USB3_UNI_PCS_OUTSIG_SW_CTRL1 (0x0200 + 0x0084) +#define USB3_UNI_PCS_OUTSIG_MX_CTRL1 (0x0200 + 0x0088) +#define USB3_UNI_PCS_CLAMP_ENABLE (0x0200 + 0x008c) +#define USB3_UNI_PCS_POWER_STATE_CONFIG1 (0x0200 + 0x0090) +#define USB3_UNI_PCS_POWER_STATE_CONFIG2 (0x0200 + 0x0094) +#define USB3_UNI_PCS_FLL_CNTRL1 (0x0200 + 0x0098) +#define USB3_UNI_PCS_FLL_CNTRL2 (0x0200 + 0x009c) +#define USB3_UNI_PCS_FLL_CNT_VAL_L (0x0200 + 0x00a0) +#define USB3_UNI_PCS_FLL_CNT_VAL_H_TOL (0x0200 + 0x00a4) +#define USB3_UNI_PCS_FLL_MAN_CODE (0x0200 + 0x00a8) +#define USB3_UNI_PCS_TEST_CONTROL1 (0x0200 + 0x00ac) +#define USB3_UNI_PCS_TEST_CONTROL2 (0x0200 + 0x00b0) +#define USB3_UNI_PCS_TEST_CONTROL3 (0x0200 + 0x00b4) +#define USB3_UNI_PCS_TEST_CONTROL4 (0x0200 + 0x00b8) +#define USB3_UNI_PCS_TEST_CONTROL5 (0x0200 + 0x00bc) +#define USB3_UNI_PCS_TEST_CONTROL6 (0x0200 + 0x00c0) +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG1 (0x0200 + 0x00c4) +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG2 (0x0200 + 0x00c8) +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG3 (0x0200 + 0x00cc) +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG4 (0x0200 + 0x00d0) +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG5 (0x0200 + 0x00d4) +#define USB3_UNI_PCS_LOCK_DETECT_CONFIG6 (0x0200 + 0x00d8) +#define USB3_UNI_PCS_REFGEN_REQ_CONFIG1 (0x0200 + 0x00dc) +#define USB3_UNI_PCS_REFGEN_REQ_CONFIG2 (0x0200 + 0x00e0) +#define USB3_UNI_PCS_REFGEN_REQ_CONFIG3 (0x0200 + 0x00e4) +#define USB3_UNI_PCS_BIST_CTRL (0x0200 + 0x00e8) +#define USB3_UNI_PCS_PRBS_POLY0 (0x0200 + 0x00ec) +#define USB3_UNI_PCS_PRBS_POLY1 (0x0200 + 0x00f0) +#define USB3_UNI_PCS_FIXED_PAT0 (0x0200 + 0x00f4) +#define USB3_UNI_PCS_FIXED_PAT1 (0x0200 + 0x00f8) +#define USB3_UNI_PCS_FIXED_PAT2 (0x0200 + 0x00fc) +#define USB3_UNI_PCS_FIXED_PAT3 (0x0200 + 0x0100) +#define USB3_UNI_PCS_FIXED_PAT4 (0x0200 + 0x0104) +#define USB3_UNI_PCS_FIXED_PAT5 (0x0200 + 0x0108) +#define USB3_UNI_PCS_FIXED_PAT6 (0x0200 + 0x010c) +#define USB3_UNI_PCS_FIXED_PAT7 (0x0200 + 0x0110) +#define USB3_UNI_PCS_FIXED_PAT8 (0x0200 + 0x0114) +#define USB3_UNI_PCS_FIXED_PAT9 (0x0200 + 0x0118) +#define USB3_UNI_PCS_FIXED_PAT10 (0x0200 + 0x011c) +#define USB3_UNI_PCS_FIXED_PAT11 (0x0200 + 0x0120) +#define USB3_UNI_PCS_FIXED_PAT12 (0x0200 + 0x0124) +#define USB3_UNI_PCS_FIXED_PAT13 (0x0200 + 0x0128) +#define USB3_UNI_PCS_FIXED_PAT14 (0x0200 + 0x012c) +#define USB3_UNI_PCS_FIXED_PAT15 (0x0200 + 0x0130) +#define USB3_UNI_PCS_TXMGN_CONFIG (0x0200 + 0x0134) +#define USB3_UNI_PCS_G12S1_TXMGN_V0 (0x0200 + 0x0138) +#define USB3_UNI_PCS_G12S1_TXMGN_V1 (0x0200 + 0x013c) +#define USB3_UNI_PCS_G12S1_TXMGN_V2 (0x0200 + 0x0140) +#define USB3_UNI_PCS_G12S1_TXMGN_V3 (0x0200 + 0x0144) +#define USB3_UNI_PCS_G12S1_TXMGN_V4 (0x0200 + 0x0148) +#define USB3_UNI_PCS_G12S1_TXMGN_V0_RS (0x0200 + 0x014c) +#define USB3_UNI_PCS_G12S1_TXMGN_V1_RS (0x0200 + 0x0150) +#define USB3_UNI_PCS_G12S1_TXMGN_V2_RS (0x0200 + 0x0154) +#define USB3_UNI_PCS_G12S1_TXMGN_V3_RS (0x0200 + 0x0158) +#define USB3_UNI_PCS_G12S1_TXMGN_V4_RS (0x0200 + 0x015c) +#define USB3_UNI_PCS_G3S2_TXMGN_MAIN (0x0200 + 0x0160) +#define USB3_UNI_PCS_G3S2_TXMGN_MAIN_RS (0x0200 + 0x0164) +#define USB3_UNI_PCS_G12S1_TXDEEMPH_M6DB (0x0200 + 0x0168) +#define USB3_UNI_PCS_G12S1_TXDEEMPH_M3P5DB (0x0200 + 0x016c) +#define USB3_UNI_PCS_G3S2_PRE_GAIN (0x0200 + 0x0170) +#define USB3_UNI_PCS_G3S2_POST_GAIN (0x0200 + 0x0174) +#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET (0x0200 + 0x0178) +#define USB3_UNI_PCS_G3S2_PRE_GAIN_RS (0x0200 + 0x017c) +#define USB3_UNI_PCS_G3S2_POST_GAIN_RS (0x0200 + 0x0180) +#define USB3_UNI_PCS_G3S2_PRE_POST_OFFSET_RS (0x0200 + 0x0184) +#define USB3_UNI_PCS_RX_SIGDET_LVL (0x0200 + 0x0188) +#define USB3_UNI_PCS_RX_SIGDET_DTCT_CNTRL (0x0200 + 0x018c) +#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L (0x0200 + 0x0190) +#define USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H (0x0200 + 0x0194) +#define USB3_UNI_PCS_RATE_SLEW_CNTRL1 (0x0200 + 0x0198) +#define USB3_UNI_PCS_RATE_SLEW_CNTRL2 (0x0200 + 0x019c) +#define USB3_UNI_PCS_PWRUP_RESET_DLY_TIME_AUXCLK (0x0200 + 0x01a0) +#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L (0x0200 + 0x01a4) +#define USB3_UNI_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H (0x0200 + 0x01a8) +#define USB3_UNI_PCS_TSYNC_RSYNC_TIME (0x0200 + 0x01ac) +#define USB3_UNI_PCS_CDR_RESET_TIME (0x0200 + 0x01b0) +#define USB3_UNI_PCS_TSYNC_DLY_TIME (0x0200 + 0x01b4) +#define USB3_UNI_PCS_ELECIDLE_DLY_SEL (0x0200 + 0x01b8) +#define USB3_UNI_PCS_CMN_ACK_OUT_SEL (0x0200 + 0x01bc) +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 (0x0200 + 0x01c0) +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 (0x0200 + 0x01c4) +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG3 (0x0200 + 0x01c8) +#define USB3_UNI_PCS_ALIGN_DETECT_CONFIG4 (0x0200 + 0x01cc) +#define USB3_UNI_PCS_PCS_TX_RX_CONFIG (0x0200 + 0x01d0) +#define USB3_UNI_PCS_RX_IDLE_DTCT_CNTRL (0x0200 + 0x01d4) +#define USB3_UNI_PCS_RX_DCC_CAL_CONFIG (0x0200 + 0x01d8) +#define USB3_UNI_PCS_EQ_CONFIG1 (0x0200 + 0x01dc) +#define USB3_UNI_PCS_EQ_CONFIG2 (0x0200 + 0x01e0) +#define USB3_UNI_PCS_EQ_CONFIG3 (0x0200 + 0x01e4) +#define USB3_UNI_PCS_EQ_CONFIG4 (0x0200 + 0x01e8) +#define USB3_UNI_PCS_EQ_CONFIG5 (0x0200 + 0x01ec) + +/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_PCIE_USB3_UNI_PCS_PCIE_PCIE_USB3_UNI_PCS_PCIE */ +#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_STATUS (0x0600 + 0x0000) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_STATUS (0x0600 + 0x0004) +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG1 (0x0600 + 0x0008) +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG2 (0x0600 + 0x000c) +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG3 (0x0600 + 0x0010) +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG4 (0x0600 + 0x0014) +#define USB3_UNI_PCS_PCIE_POWER_STATE_CONFIG5 (0x0600 + 0x0018) +#define USB3_UNI_PCS_PCIE_PCS_TX_RX_CONFIG (0x0600 + 0x001c) +#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_DRIVE (0x0600 + 0x0020) +#define USB3_UNI_PCS_PCIE_ENDPOINT_REFCLK_CNTRL (0x0600 + 0x0024) +#define USB3_UNI_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK (0x0600 + 0x0028) +#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L (0x0600 + 0x002c) +#define USB3_UNI_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H (0x0600 + 0x0030) +#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 (0x0600 + 0x0034) +#define USB3_UNI_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 (0x0600 + 0x0038) +#define USB3_UNI_PCS_PCIE_SIGDET_CNTRL (0x0600 + 0x003c) +#define USB3_UNI_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME (0x0600 + 0x0040) +#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L (0x0600 + 0x0044) +#define USB3_UNI_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H (0x0600 + 0x0048) +#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L (0x0600 + 0x004c) +#define USB3_UNI_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H (0x0600 + 0x0050) +#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG1 (0x0600 + 0x0054) +#define USB3_UNI_PCS_PCIE_INT_AUX_CLK_CONFIG2 (0x0600 + 0x0058) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG1 (0x0600 + 0x005c) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG2 (0x0600 + 0x0060) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG3 (0x0600 + 0x0064) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG4 (0x0600 + 0x0068) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG5 (0x0600 + 0x006c) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG6 (0x0600 + 0x0070) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_CONFIG7 (0x0600 + 0x0074) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 (0x0600 + 0x0078) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 (0x0600 + 0x007c) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 (0x0600 + 0x0080) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 (0x0600 + 0x0084) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 (0x0600 + 0x0088) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 (0x0600 + 0x008c) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 (0x0600 + 0x0090) +#define USB3_UNI_PCS_PCIE_OSC_DTCT_ACTIONS (0x0600 + 0x0094) +#define USB3_UNI_PCS_PCIE_LOCAL_FS (0x0600 + 0x0098) +#define USB3_UNI_PCS_PCIE_LOCAL_LF (0x0600 + 0x009c) +#define USB3_UNI_PCS_PCIE_LOCAL_FS_RS (0x0600 + 0x00a0) +#define USB3_UNI_PCS_PCIE_EQ_CONFIG1 (0x0600 + 0x00a4) +#define USB3_UNI_PCS_PCIE_EQ_CONFIG2 (0x0600 + 0x00a8) +#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_PRE (0x0600 + 0x00ac) +#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_PRE (0x0600 + 0x00b0) +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE (0x0600 + 0x00b4) +#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_PRE (0x0600 + 0x00b8) +#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_PRE (0x0600 + 0x00bc) +#define USB3_UNI_PCS_PCIE_PRESET_P10_PRE (0x0600 + 0x00c0) +#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_PRE_RS (0x0600 + 0x00c4) +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_PRE_RS (0x0600 + 0x00c8) +#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_PRE_RS (0x0600 + 0x00cc) +#define USB3_UNI_PCS_PCIE_PRESET_P0_P1_POST (0x0600 + 0x00d0) +#define USB3_UNI_PCS_PCIE_PRESET_P2_P3_POST (0x0600 + 0x00d4) +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST (0x0600 + 0x00d8) +#define USB3_UNI_PCS_PCIE_PRESET_P6_P7_POST (0x0600 + 0x00dc) +#define USB3_UNI_PCS_PCIE_PRESET_P8_P9_POST (0x0600 + 0x00e0) +#define USB3_UNI_PCS_PCIE_PRESET_P10_POST (0x0600 + 0x00e4) +#define USB3_UNI_PCS_PCIE_PRESET_P1_P3_POST_RS (0x0600 + 0x00e8) +#define USB3_UNI_PCS_PCIE_PRESET_P4_P5_POST_RS (0x0600 + 0x00ec) +#define USB3_UNI_PCS_PCIE_PRESET_P6_P9_POST_RS (0x0600 + 0x00f0) +#define USB3_UNI_PCS_PCIE_RXEQEVAL_TIME (0x0600 + 0x00f4) + +/* Module: + * USB3_UNI_PHY_PCIE_USB3_UNI_PCS_INTGEN_PCIE_USB3_UNI_PCS_INTGEN_PCIE_USB3_UNI_PCS_DEBUG_INTGEN + */ +#define USB3_UNI_PCS_INTGEN_INTGEN_STATUS1 (0x0800 + 0x0000) +#define USB3_UNI_PCS_INTGEN_INTGEN_STATUS2 (0x0800 + 0x0004) +#define USB3_UNI_PCS_INTGEN_CONFIG1 (0x0800 + 0x0008) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG1 (0x0800 + 0x000c) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG2 (0x0800 + 0x0010) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG3 (0x0800 + 0x0014) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG4 (0x0800 + 0x0018) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK1_CONFIG5 (0x0800 + 0x001c) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG1 (0x0800 + 0x0020) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG2 (0x0800 + 0x0024) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG3 (0x0800 + 0x0028) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG4 (0x0800 + 0x002c) +#define USB3_UNI_PCS_INTGEN_SIGNALBLK2_CONFIG5 (0x0800 + 0x0030) +#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG1 (0x0800 + 0x0034) +#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG2 (0x0800 + 0x0038) +#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG3 (0x0800 + 0x003c) +#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG4 (0x0800 + 0x0040) +#define USB3_UNI_PCS_INTGEN_STRINGBLK1_CONFIG5 (0x0800 + 0x0044) +#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG1 (0x0800 + 0x0048) +#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG2 (0x0800 + 0x004c) +#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG3 (0x0800 + 0x0050) +#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG4 (0x0800 + 0x0054) +#define USB3_UNI_PCS_INTGEN_STRINGBLK2_CONFIG5 (0x0800 + 0x0058) + +/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LN_PCIE_USB3_UNI_PCS_LANE */ +#define USB3_UNI_PCS_LN_PCS_STATUS1 (0x0a00 + 0x0000) +#define USB3_UNI_PCS_LN_PCS_STATUS2 (0x0a00 + 0x0004) +#define USB3_UNI_PCS_LN_PCS_STATUS2_CLEAR (0x0a00 + 0x0008) +#define USB3_UNI_PCS_LN_PCS_STATUS3 (0x0a00 + 0x000c) +#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS (0x0a00 + 0x0010) +#define USB3_UNI_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS (0x0a00 + 0x0014) +#define USB3_UNI_PCS_LN_BIST_CHK_STATUS (0x0a00 + 0x0018) +#define USB3_UNI_PCS_LN_INSIG_SW_CTRL1 (0x0a00 + 0x001c) +#define USB3_UNI_PCS_LN_INSIG_MX_CTRL1 (0x0a00 + 0x0020) +#define USB3_UNI_PCS_LN_OUTSIG_SW_CTRL1 (0x0a00 + 0x0024) +#define USB3_UNI_PCS_LN_OUTSIG_MX_CTRL1 (0x0a00 + 0x0028) +#define USB3_UNI_PCS_LN_TEST_CONTROL1 (0x0a00 + 0x002c) +#define USB3_UNI_PCS_LN_BIST_CTRL (0x0a00 + 0x0030) +#define USB3_UNI_PCS_LN_PRBS_SEED0 (0x0a00 + 0x0034) +#define USB3_UNI_PCS_LN_PRBS_SEED1 (0x0a00 + 0x0038) +#define USB3_UNI_PCS_LN_FIXED_PAT_CTRL (0x0a00 + 0x003c) +#define USB3_UNI_PCS_LN_EQ_CONFIG (0x0a00 + 0x0040) +#define USB3_UNI_PCS_LN_TEST_CONTROL2 (0x0a00 + 0x0044) +#define USB3_UNI_PCS_LN_TEST_CONTROL3 (0x0a00 + 0x0048) + +/* Module: + * USB3_UNI_PHY_PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LN_PCIE_USB3_UNI_PCS_PCIE_LANE + */ +#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST (0x0c00 + 0x0000) +#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_PRE_POST_RS (0x0c00 + 0x0004) +#define USB3_UNI_PCS_PCIE_LN_PRESET_OVERRIDE_EN (0x0c00 + 0x0008) +#define USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_L (0x0c00 + 0x000c) +#define USB3_UNI_PCS_PCIE_LN_PRESET_DSBL_H (0x0c00 + 0x0010) +#define USB3_UNI_PCS_PCIE_LN_LANE_OFF_CONFIG (0x0c00 + 0x0014) +#define USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG1 (0x0c00 + 0x0018) +#define USB3_UNI_PCS_PCIE_LN_RXEQ_DONE_CONFIG2 (0x0c00 + 0x001c) +#define USB3_UNI_PCS_PCIE_LN_PCIE_PCS_STATUS (0x0c00 + 0x0020) +#define USB3_UNI_PCS_PCIE_LN_INSIG_SW_CTRL2 (0x0c00 + 0x0024) +#define USB3_UNI_PCS_PCIE_LN_INSIG_MX_CTRL2 (0x0c00 + 0x0028) + +/* Module: USB3_UNI_PHY_QSERDES_TX_QSERDES_TX_PCIE_USB3_UNI_QMP_TX */ +#define USB3_UNI_QSERDES_TX_BIST_MODE_LANENO (0x0e00 + 0x0000) +#define USB3_UNI_QSERDES_TX_BIST_INVERT (0x0e00 + 0x0004) +#define USB3_UNI_QSERDES_TX_CLKBUF_ENABLE (0x0e00 + 0x0008) +#define USB3_UNI_QSERDES_TX_TX_EMP_POST1_LVL (0x0e00 + 0x000c) +#define USB3_UNI_QSERDES_TX_TX_IDLE_LVL_LARGE_AMP (0x0e00 + 0x0010) +#define USB3_UNI_QSERDES_TX_TX_DRV_LVL (0x0e00 + 0x0014) +#define USB3_UNI_QSERDES_TX_TX_DRV_LVL_OFFSET (0x0e00 + 0x0018) +#define USB3_UNI_QSERDES_TX_RESET_TSYNC_EN (0x0e00 + 0x001c) +#define USB3_UNI_QSERDES_TX_PRE_STALL_LDO_BOOST_EN (0x0e00 + 0x0020) +#define USB3_UNI_QSERDES_TX_TX_BAND (0x0e00 + 0x0024) +#define USB3_UNI_QSERDES_TX_SLEW_CNTL (0x0e00 + 0x0028) +#define USB3_UNI_QSERDES_TX_INTERFACE_SELECT (0x0e00 + 0x002c) +#define USB3_UNI_QSERDES_TX_LPB_EN (0x0e00 + 0x0030) +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX (0x0e00 + 0x0034) +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX (0x0e00 + 0x0038) +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX (0x0e00 + 0x003c) +#define USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX (0x0e00 + 0x0040) +#define USB3_UNI_QSERDES_TX_PERL_LENGTH1 (0x0e00 + 0x0044) +#define USB3_UNI_QSERDES_TX_PERL_LENGTH2 (0x0e00 + 0x0048) +#define USB3_UNI_QSERDES_TX_SERDES_BYP_EN_OUT (0x0e00 + 0x004c) +#define USB3_UNI_QSERDES_TX_DEBUG_BUS_SEL (0x0e00 + 0x0050) +#define USB3_UNI_QSERDES_TX_TRANSCEIVER_BIAS_EN (0x0e00 + 0x0054) +#define USB3_UNI_QSERDES_TX_HIGHZ_DRVR_EN (0x0e00 + 0x0058) +#define USB3_UNI_QSERDES_TX_TX_POL_INV (0x0e00 + 0x005c) +#define USB3_UNI_QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN (0x0e00 + 0x0060) +#define USB3_UNI_QSERDES_TX_BIST_PATTERN1 (0x0e00 + 0x0064) +#define USB3_UNI_QSERDES_TX_BIST_PATTERN2 (0x0e00 + 0x0068) +#define USB3_UNI_QSERDES_TX_BIST_PATTERN3 (0x0e00 + 0x006c) +#define USB3_UNI_QSERDES_TX_BIST_PATTERN4 (0x0e00 + 0x0070) +#define USB3_UNI_QSERDES_TX_BIST_PATTERN5 (0x0e00 + 0x0074) +#define USB3_UNI_QSERDES_TX_BIST_PATTERN6 (0x0e00 + 0x0078) +#define USB3_UNI_QSERDES_TX_BIST_PATTERN7 (0x0e00 + 0x007c) +#define USB3_UNI_QSERDES_TX_BIST_PATTERN8 (0x0e00 + 0x0080) +#define USB3_UNI_QSERDES_TX_LANE_MODE_1 (0x0e00 + 0x0084) +#define USB3_UNI_QSERDES_TX_LANE_MODE_2 (0x0e00 + 0x0088) +#define USB3_UNI_QSERDES_TX_LANE_MODE_3 (0x0e00 + 0x008c) +#define USB3_UNI_QSERDES_TX_LANE_MODE_4 (0x0e00 + 0x0090) +#define USB3_UNI_QSERDES_TX_LANE_MODE_5 (0x0e00 + 0x0094) +#define USB3_UNI_QSERDES_TX_ATB_SEL1 (0x0e00 + 0x0098) +#define USB3_UNI_QSERDES_TX_ATB_SEL2 (0x0e00 + 0x009c) +#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL (0x0e00 + 0x00a0) +#define USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 (0x0e00 + 0x00a4) +#define USB3_UNI_QSERDES_TX_PRBS_SEED1 (0x0e00 + 0x00a8) +#define USB3_UNI_QSERDES_TX_PRBS_SEED2 (0x0e00 + 0x00ac) +#define USB3_UNI_QSERDES_TX_PRBS_SEED3 (0x0e00 + 0x00b0) +#define USB3_UNI_QSERDES_TX_PRBS_SEED4 (0x0e00 + 0x00b4) +#define USB3_UNI_QSERDES_TX_RESET_GEN (0x0e00 + 0x00b8) +#define USB3_UNI_QSERDES_TX_RESET_GEN_MUXES (0x0e00 + 0x00bc) +#define USB3_UNI_QSERDES_TX_TRAN_DRVR_EMP_EN (0x0e00 + 0x00c0) +#define USB3_UNI_QSERDES_TX_TX_INTERFACE_MODE (0x0e00 + 0x00c4) +#define USB3_UNI_QSERDES_TX_VMODE_CTRL1 (0x0e00 + 0x00c8) +#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_CTRL_1 (0x0e00 + 0x00cc) +#define USB3_UNI_QSERDES_TX_BIST_STATUS (0x0e00 + 0x00d0) +#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT1 (0x0e00 + 0x00d4) +#define USB3_UNI_QSERDES_TX_BIST_ERROR_COUNT2 (0x0e00 + 0x00d8) +#define USB3_UNI_QSERDES_TX_ALOG_OBSV_BUS_STATUS_1 (0x0e00 + 0x00dc) +#define USB3_UNI_QSERDES_TX_LANE_DIG_CONFIG (0x0e00 + 0x00e0) +#define USB3_UNI_QSERDES_TX_PI_QEC_CTRL (0x0e00 + 0x00e4) +#define USB3_UNI_QSERDES_TX_PRE_EMPH (0x0e00 + 0x00e8) +#define USB3_UNI_QSERDES_TX_SW_RESET (0x0e00 + 0x00ec) +#define USB3_UNI_QSERDES_TX_DCC_OFFSET (0x0e00 + 0x00f0) +#define USB3_UNI_QSERDES_TX_DCC_CMUX_POSTCAL_OFFSET (0x0e00 + 0x00f4) +#define USB3_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL1 (0x0e00 + 0x00f8) +#define USB3_UNI_QSERDES_TX_DCC_CMUX_CAL_CTRL2 (0x0e00 + 0x00fc) +#define USB3_UNI_QSERDES_TX_DIG_BKUP_CTRL (0x0e00 + 0x0100) +#define USB3_UNI_QSERDES_TX_DEBUG_BUS0 (0x0e00 + 0x0104) +#define USB3_UNI_QSERDES_TX_DEBUG_BUS1 (0x0e00 + 0x0108) +#define USB3_UNI_QSERDES_TX_DEBUG_BUS2 (0x0e00 + 0x010c) +#define USB3_UNI_QSERDES_TX_DEBUG_BUS3 (0x0e00 + 0x0110) +#define USB3_UNI_QSERDES_TX_READ_EQCODE (0x0e00 + 0x0114) +#define USB3_UNI_QSERDES_TX_READ_OFFSETCODE (0x0e00 + 0x0118) +#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_LOW (0x0e00 + 0x011c) +#define USB3_UNI_QSERDES_TX_IA_ERROR_COUNTER_HIGH (0x0e00 + 0x0120) +#define USB3_UNI_QSERDES_TX_VGA_READ_CODE (0x0e00 + 0x0124) +#define USB3_UNI_QSERDES_TX_VTH_READ_CODE (0x0e00 + 0x0128) +#define USB3_UNI_QSERDES_TX_DFE_TAP1_READ_CODE (0x0e00 + 0x012c) +#define USB3_UNI_QSERDES_TX_DFE_TAP2_READ_CODE (0x0e00 + 0x0130) +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_I (0x0e00 + 0x0134) +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_IBAR (0x0e00 + 0x0138) +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_Q (0x0e00 + 0x013c) +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_QBAR (0x0e00 + 0x0140) +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_A (0x0e00 + 0x0144) +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_ABAR (0x0e00 + 0x0148) +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SM_ON (0x0e00 + 0x014c) +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_CAL_DONE (0x0e00 + 0x0150) +#define USB3_UNI_QSERDES_TX_IDAC_STATUS_SIGNERROR (0x0e00 + 0x0154) +#define USB3_UNI_QSERDES_TX_DCC_CAL_STATUS (0x0e00 + 0x0158) +#define USB3_UNI_QSERDES_TX_DCC_READ_CODE_STATUS (0x0e00 + 0x015c) + +/* Module: USB3_UNI_PHY_QSERDES_RX_QSERDES_RX_PCIE_USB3_UNI_QMP_RX */ +#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_HALF (0x1000 + 0x0000) +#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN_QUARTER (0x1000 + 0x0004) +#define USB3_UNI_QSERDES_RX_UCDR_FO_GAIN (0x1000 + 0x0008) +#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_HALF (0x1000 + 0x000c) +#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN_QUARTER (0x1000 + 0x0010) +#define USB3_UNI_QSERDES_RX_UCDR_SO_GAIN (0x1000 + 0x0014) +#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_HALF (0x1000 + 0x0018) +#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER (0x1000 + 0x001c) +#define USB3_UNI_QSERDES_RX_UCDR_SVS_FO_GAIN (0x1000 + 0x0020) +#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_HALF (0x1000 + 0x0024) +#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER (0x1000 + 0x0028) +#define USB3_UNI_QSERDES_RX_UCDR_SVS_SO_GAIN (0x1000 + 0x002c) +#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN (0x1000 + 0x0030) +#define USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE (0x1000 + 0x0034) +#define USB3_UNI_QSERDES_RX_UCDR_FO_TO_SO_DELAY (0x1000 + 0x0038) +#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW (0x1000 + 0x003c) +#define USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH (0x1000 + 0x0040) +#define USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS (0x1000 + 0x0044) +#define USB3_UNI_QSERDES_RX_UCDR_PI_CTRL2 (0x1000 + 0x0048) +#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 (0x1000 + 0x004c) +#define USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 (0x1000 + 0x0050) +#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 (0x1000 + 0x0054) +#define USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 (0x1000 + 0x0058) +#define USB3_UNI_QSERDES_RX_AUX_CONTROL (0x1000 + 0x005c) +#define USB3_UNI_QSERDES_RX_AUX_DATA_TCOARSE_TFINE (0x1000 + 0x0060) +#define USB3_UNI_QSERDES_RX_RCLK_AUXDATA_SEL (0x1000 + 0x0064) +#define USB3_UNI_QSERDES_RX_AC_JTAG_ENABLE (0x1000 + 0x0068) +#define USB3_UNI_QSERDES_RX_AC_JTAG_INITP (0x1000 + 0x006c) +#define USB3_UNI_QSERDES_RX_AC_JTAG_INITN (0x1000 + 0x0070) +#define USB3_UNI_QSERDES_RX_AC_JTAG_LVL (0x1000 + 0x0074) +#define USB3_UNI_QSERDES_RX_AC_JTAG_MODE (0x1000 + 0x0078) +#define USB3_UNI_QSERDES_RX_AC_JTAG_RESET (0x1000 + 0x007c) +#define USB3_UNI_QSERDES_RX_RX_TERM_BW (0x1000 + 0x0080) +#define USB3_UNI_QSERDES_RX_RX_RCVR_IQ_EN (0x1000 + 0x0084) +#define USB3_UNI_QSERDES_RX_RX_IDAC_I_DC_OFFSETS (0x1000 + 0x0088) +#define USB3_UNI_QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS (0x1000 + 0x008c) +#define USB3_UNI_QSERDES_RX_RX_IDAC_Q_DC_OFFSETS (0x1000 + 0x0090) +#define USB3_UNI_QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS (0x1000 + 0x0094) +#define USB3_UNI_QSERDES_RX_RX_IDAC_A_DC_OFFSETS (0x1000 + 0x0098) +#define USB3_UNI_QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS (0x1000 + 0x009c) +#define USB3_UNI_QSERDES_RX_RX_IDAC_EN (0x1000 + 0x00a0) +#define USB3_UNI_QSERDES_RX_RX_IDAC_ENABLES (0x1000 + 0x00a4) +#define USB3_UNI_QSERDES_RX_RX_IDAC_SIGN (0x1000 + 0x00a8) +#define USB3_UNI_QSERDES_RX_RX_HIGHZ_HIGHRATE (0x1000 + 0x00ac) +#define USB3_UNI_QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET (0x1000 + 0x00b0) +#define USB3_UNI_QSERDES_RX_DFE_1 (0x1000 + 0x00b4) +#define USB3_UNI_QSERDES_RX_DFE_2 (0x1000 + 0x00b8) +#define USB3_UNI_QSERDES_RX_DFE_3 (0x1000 + 0x00bc) +#define USB3_UNI_QSERDES_RX_DFE_4 (0x1000 + 0x00c0) +#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH1 (0x1000 + 0x00c4) +#define USB3_UNI_QSERDES_RX_TX_ADAPT_PRE_THRESH2 (0x1000 + 0x00c8) +#define USB3_UNI_QSERDES_RX_TX_ADAPT_POST_THRESH (0x1000 + 0x00cc) +#define USB3_UNI_QSERDES_RX_TX_ADAPT_MAIN_THRESH (0x1000 + 0x00d0) +#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 (0x1000 + 0x00d4) +#define USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 (0x1000 + 0x00d8) +#define USB3_UNI_QSERDES_RX_GM_CAL (0x1000 + 0x00dc) +#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_LSB (0x1000 + 0x00e0) +#define USB3_UNI_QSERDES_RX_RX_VGA_GAIN2_MSB (0x1000 + 0x00e4) +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 (0x1000 + 0x00e8) +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 (0x1000 + 0x00ec) +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 (0x1000 + 0x00f0) +#define USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 (0x1000 + 0x00f4) +#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW (0x1000 + 0x00f8) +#define USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH (0x1000 + 0x00fc) +#define USB3_UNI_QSERDES_RX_RX_IDAC_MEASURE_TIME (0x1000 + 0x0100) +#define USB3_UNI_QSERDES_RX_RX_IDAC_ACCUMULATOR (0x1000 + 0x0104) +#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_LSB (0x1000 + 0x0108) +#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_MSB (0x1000 + 0x010c) +#define USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x1000 + 0x0110) +#define USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 (0x1000 + 0x0114) +#define USB3_UNI_QSERDES_RX_SIGDET_ENABLES (0x1000 + 0x0118) +#define USB3_UNI_QSERDES_RX_SIGDET_CNTRL (0x1000 + 0x011c) +#define USB3_UNI_QSERDES_RX_SIGDET_LVL (0x1000 + 0x0120) +#define USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL (0x1000 + 0x0124) +#define USB3_UNI_QSERDES_RX_RX_BAND (0x1000 + 0x0128) +#define USB3_UNI_QSERDES_RX_CDR_FREEZE_UP_DN (0x1000 + 0x012c) +#define USB3_UNI_QSERDES_RX_CDR_RESET_OVERRIDE (0x1000 + 0x0130) +#define USB3_UNI_QSERDES_RX_RX_INTERFACE_MODE (0x1000 + 0x0134) +#define USB3_UNI_QSERDES_RX_JITTER_GEN_MODE (0x1000 + 0x0138) +#define USB3_UNI_QSERDES_RX_SJ_AMP1 (0x1000 + 0x013c) +#define USB3_UNI_QSERDES_RX_SJ_AMP2 (0x1000 + 0x0140) +#define USB3_UNI_QSERDES_RX_SJ_PER1 (0x1000 + 0x0144) +#define USB3_UNI_QSERDES_RX_SJ_PER2 (0x1000 + 0x0148) +#define USB3_UNI_QSERDES_RX_PPM_OFFSET1 (0x1000 + 0x014c) +#define USB3_UNI_QSERDES_RX_PPM_OFFSET2 (0x1000 + 0x0150) +#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD1 (0x1000 + 0x0154) +#define USB3_UNI_QSERDES_RX_SIGN_PPM_PERIOD2 (0x1000 + 0x0158) +#define USB3_UNI_QSERDES_RX_RX_MODE_00_LOW (0x1000 + 0x015c) +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH (0x1000 + 0x0160) +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 (0x1000 + 0x0164) +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 (0x1000 + 0x0168) +#define USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 (0x1000 + 0x016c) +#define USB3_UNI_QSERDES_RX_RX_MODE_01_LOW (0x1000 + 0x0170) +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH (0x1000 + 0x0174) +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 (0x1000 + 0x0178) +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 (0x1000 + 0x017c) +#define USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 (0x1000 + 0x0180) +#define USB3_UNI_QSERDES_RX_RX_MODE_10_LOW (0x1000 + 0x0184) +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH (0x1000 + 0x0188) +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH2 (0x1000 + 0x018c) +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH3 (0x1000 + 0x0190) +#define USB3_UNI_QSERDES_RX_RX_MODE_10_HIGH4 (0x1000 + 0x0194) +#define USB3_UNI_QSERDES_RX_PHPRE_CTRL (0x1000 + 0x0198) +#define USB3_UNI_QSERDES_RX_PHPRE_INITVAL (0x1000 + 0x019c) +#define USB3_UNI_QSERDES_RX_DFE_EN_TIMER (0x1000 + 0x01a0) +#define USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET (0x1000 + 0x01a4) +#define USB3_UNI_QSERDES_RX_DCC_CTRL1 (0x1000 + 0x01a8) +#define USB3_UNI_QSERDES_RX_DCC_CTRL2 (0x1000 + 0x01ac) +#define USB3_UNI_QSERDES_RX_VTH_CODE (0x1000 + 0x01b0) +#define USB3_UNI_QSERDES_RX_VTH_MIN_THRESH (0x1000 + 0x01b4) +#define USB3_UNI_QSERDES_RX_VTH_MAX_THRESH (0x1000 + 0x01b8) +#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_CTRL_1 (0x1000 + 0x01bc) +#define USB3_UNI_QSERDES_RX_PI_CTRL1 (0x1000 + 0x01c0) +#define USB3_UNI_QSERDES_RX_PI_CTRL2 (0x1000 + 0x01c4) +#define USB3_UNI_QSERDES_RX_PI_QUAD (0x1000 + 0x01c8) +#define USB3_UNI_QSERDES_RX_IDATA1 (0x1000 + 0x01cc) +#define USB3_UNI_QSERDES_RX_IDATA2 (0x1000 + 0x01d0) +#define USB3_UNI_QSERDES_RX_AUX_DATA1 (0x1000 + 0x01d4) +#define USB3_UNI_QSERDES_RX_AUX_DATA2 (0x1000 + 0x01d8) +#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTP (0x1000 + 0x01dc) +#define USB3_UNI_QSERDES_RX_AC_JTAG_OUTN (0x1000 + 0x01e0) +#define USB3_UNI_QSERDES_RX_RX_SIGDET (0x1000 + 0x01e4) +#define USB3_UNI_QSERDES_RX_ALOG_OBSV_BUS_STATUS_1 (0x1000 + 0x01e8) + +/* Module: USB3_UNI_PHY_PCIE_USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3_PCIE_USB3_UNI_PCS_USB3 */ +#define USB3_UNI_PCS_USB3_POWER_STATE_CONFIG1 (0x1200 + 0x0000) +#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_STATUS (0x1200 + 0x0004) +#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL (0x1200 + 0x0008) +#define USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL2 (0x1200 + 0x000c) +#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS (0x1200 + 0x0010) +#define USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR (0x1200 + 0x0014) +#define USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL (0x1200 + 0x0018) +#define USB3_UNI_PCS_USB3_LFPS_TX_ECSTART (0x1200 + 0x001c) +#define USB3_UNI_PCS_USB3_LFPS_PER_TIMER_VAL (0x1200 + 0x0020) +#define USB3_UNI_PCS_USB3_LFPS_TX_END_CNT_U3_START (0x1200 + 0x0024) +#define USB3_UNI_PCS_USB3_LFPS_CONFIG1 (0x1200 + 0x0028) +#define USB3_UNI_PCS_USB3_RXEQTRAINING_LOCK_TIME (0x1200 + 0x002c) +#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME (0x1200 + 0x0030) +#define USB3_UNI_PCS_USB3_RXEQTRAINING_CTLE_TIME (0x1200 + 0x0034) +#define USB3_UNI_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 (0x1200 + 0x0038) +#define USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 (0x1200 + 0x003c) +#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_L (0x1200 + 0x0040) +#define USB3_UNI_PCS_USB3_RCVR_DTCT_DLY_U3_H (0x1200 + 0x0044) +#define USB3_UNI_PCS_USB3_ARCVR_DTCT_EN_PERIOD (0x1200 + 0x0048) +#define USB3_UNI_PCS_USB3_ARCVR_DTCT_CM_DLY (0x1200 + 0x004c) +#define USB3_UNI_PCS_USB3_TXONESZEROS_RUN_LENGTH (0x1200 + 0x0050) +#define USB3_UNI_PCS_USB3_ALFPS_DEGLITCH_VAL (0x1200 + 0x0054) +#define USB3_UNI_PCS_USB3_SIGDET_STARTUP_TIMER_VAL (0x1200 + 0x0058) +#define USB3_UNI_PCS_USB3_TEST_CONTROL (0x1200 + 0x005c) +#define USB3_UNI_PCS_USB3_RXTERMINATION_DLY_SEL (0x1200 + 0x0060) + +#endif /* _DT_BINDINGS_PHY_QCOM_5NM_QMP_UNI_USB_H */ diff --git a/include/dt-bindings/phy/qcom,usb4-5nm-qmp-combo.h b/include/dt-bindings/phy/qcom,usb4-5nm-qmp-combo.h new file mode 100644 index 000000000000..012805b98782 --- /dev/null +++ b/include/dt-bindings/phy/qcom,usb4-5nm-qmp-combo.h @@ -0,0 +1,1546 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_PHY_QCOM_5NM_QMP_COMBO_USB4_H +#define _DT_BINDINGS_PHY_QCOM_5NM_QMP_COMBO_USB4_H + +/* USB4-USB3-DP Combo PHY register offsets */ +/* Module: USB43DP_COM_USB43DP_COM_USB4_USB3_DP_COM */ +#define USB43DP_COM_PHY_MODE_CTRL 0x0000 +#define USB43DP_COM_SW_RESET 0x0004 +#define USB43DP_COM_POWER_DOWN_CTRL 0x0008 +#define USB43DP_COM_SWI_CTRL 0x000C +#define USB43DP_COM_TYPEC_CTRL 0x0010 +#define USB43DP_COM_TYPEC_PWRDN_CTRL 0x0014 +#define USB43DP_COM_DP_BIST_CFG_0 0x0018 +#define USB43DP_COM_RESET_OVRD_CTRL1 0x001C +#define USB43DP_COM_RESET_OVRD_CTRL2 0x0020 +#define USB43DP_COM_DBG_CLK_MUX_CTRL 0x0024 +#define USB43DP_COM_TYPEC_STATUS 0x0028 +#define USB43DP_COM_PLACEHOLDER_STATUS 0x002C +#define USB43DP_COM_REVISION_ID0 0x0030 +#define USB43DP_COM_REVISION_ID1 0x0034 +#define USB43DP_COM_REVISION_ID2 0x0038 +#define USB43DP_COM_REVISION_ID3 0x003C + +/* Module: USB43DP_DBGINT_USB43DP_DBGINT_USB3_PCS_DEBUG_INT */ +#define USB43DP_DBGINT_INTGEN_STATUS1 0x0200 +#define USB43DP_DBGINT_INTGEN_STATUS2 0x0204 +#define USB43DP_DBGINT_CONFIG1 0x0208 +#define USB43DP_DBGINT_SIGNALBLK1_CONFIG1 0x020C +#define USB43DP_DBGINT_SIGNALBLK1_CONFIG2 0x0210 +#define USB43DP_DBGINT_SIGNALBLK1_CONFIG3 0x0214 +#define USB43DP_DBGINT_SIGNALBLK1_CONFIG4 0x0218 +#define USB43DP_DBGINT_SIGNALBLK1_CONFIG5 0x021C +#define USB43DP_DBGINT_SIGNALBLK2_CONFIG1 0x0220 +#define USB43DP_DBGINT_SIGNALBLK2_CONFIG2 0x0224 +#define USB43DP_DBGINT_SIGNALBLK2_CONFIG3 0x0228 +#define USB43DP_DBGINT_SIGNALBLK2_CONFIG4 0x022C +#define USB43DP_DBGINT_SIGNALBLK2_CONFIG5 0x0230 +#define USB43DP_DBGINT_STRINGBLK1_CONFIG1 0x0234 +#define USB43DP_DBGINT_STRINGBLK1_CONFIG2 0x0238 +#define USB43DP_DBGINT_STRINGBLK1_CONFIG3 0x023C +#define USB43DP_DBGINT_STRINGBLK1_CONFIG4 0x0240 +#define USB43DP_DBGINT_STRINGBLK1_CONFIG5 0x0244 +#define USB43DP_DBGINT_STRINGBLK2_CONFIG1 0x0248 +#define USB43DP_DBGINT_STRINGBLK2_CONFIG2 0x024C +#define USB43DP_DBGINT_STRINGBLK2_CONFIG3 0x0250 +#define USB43DP_DBGINT_STRINGBLK2_CONFIG4 0x0254 +#define USB43DP_DBGINT_STRINGBLK2_CONFIG5 0x0258 + +/* Module: USB43DP_QSERDES_TXA_USB43DP_QSERDES_TXA_USB4_USB3_DP_QMP_TX */ +#define USB43DP_QSERDES_TXA_BIST_MODE_LANENO 0x0400 +#define USB43DP_QSERDES_TXA_BIST_INVERT 0x0404 +#define USB43DP_QSERDES_TXA_CLKBUF_ENABLE 0x0408 +#define USB43DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x040C +#define USB43DP_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x0410 +#define USB43DP_QSERDES_TXA_TX_DRV_LVL 0x0414 +#define USB43DP_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x0418 +#define USB43DP_QSERDES_TXA_RESET_TSYNC_EN 0x041C +#define USB43DP_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x0420 +#define USB43DP_QSERDES_TXA_LPB_EN 0x0424 +#define USB43DP_QSERDES_TXA_RES_CODE_LANE_TX 0x0428 +#define USB43DP_QSERDES_TXA_RES_CODE_LANE_RX 0x042C +#define USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x0430 +#define USB43DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0434 +#define USB43DP_QSERDES_TXA_PERL_LENGTH1 0x0438 +#define USB43DP_QSERDES_TXA_PERL_LENGTH2 0x043C +#define USB43DP_QSERDES_TXA_SERDES_BYP_EN_OUT 0x0440 +#define USB43DP_QSERDES_TXA_DEBUG_BUS_SEL 0x0444 +#define USB43DP_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x0448 +#define USB43DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x044C +#define USB43DP_QSERDES_TXA_TX_POL_INV 0x0450 +#define USB43DP_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x0454 +#define USB43DP_QSERDES_TXA_BIST_PATTERN1 0x0458 +#define USB43DP_QSERDES_TXA_BIST_PATTERN2 0x045C +#define USB43DP_QSERDES_TXA_BIST_PATTERN3 0x0460 +#define USB43DP_QSERDES_TXA_BIST_PATTERN4 0x0464 +#define USB43DP_QSERDES_TXA_BIST_PATTERN5 0x0468 +#define USB43DP_QSERDES_TXA_BIST_PATTERN6 0x046C +#define USB43DP_QSERDES_TXA_BIST_PATTERN7 0x0470 +#define USB43DP_QSERDES_TXA_BIST_PATTERN8 0x0474 +#define USB43DP_QSERDES_TXA_LANE_MODE_1 0x0478 +#define USB43DP_QSERDES_TXA_LANE_MODE_2 0x047C +#define USB43DP_QSERDES_TXA_LANE_MODE_3 0x0480 +#define USB43DP_QSERDES_TXA_ATB_SEL1 0x0484 +#define USB43DP_QSERDES_TXA_ATB_SEL2 0x0488 +#define USB43DP_QSERDES_TXA_RCV_DETECT_LVL 0x048C +#define USB43DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x0490 +#define USB43DP_QSERDES_TXA_PRBS_SEED1 0x0494 +#define USB43DP_QSERDES_TXA_PRBS_SEED2 0x0498 +#define USB43DP_QSERDES_TXA_PRBS_SEED3 0x049C +#define USB43DP_QSERDES_TXA_PRBS_SEED4 0x04A0 +#define USB43DP_QSERDES_TXA_RESET_GEN 0x04A4 +#define USB43DP_QSERDES_TXA_RESET_GEN_MUXES 0x04A8 +#define USB43DP_QSERDES_TXA_TRAN_DRVR_EMP_EN 0x04AC +#define USB43DP_QSERDES_TXA_VMODE_CTRL1 0x04B0 +#define USB43DP_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0x04B4 +#define USB43DP_QSERDES_TXA_BIST_STATUS 0x04B8 +#define USB43DP_QSERDES_TXA_BIST_ERROR_COUNT1 0x04BC +#define USB43DP_QSERDES_TXA_BIST_ERROR_COUNT2 0x04C0 +#define USB43DP_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0x04C4 +#define USB43DP_QSERDES_TXA_LANE_DIG_CONFIG 0x04C8 +#define USB43DP_QSERDES_TXA_PI_QEC_CTRL 0x04CC +#define USB43DP_QSERDES_TXA_PRE_EMPH 0x04D0 +#define USB43DP_QSERDES_TXA_SW_RESET 0x04D4 +#define USB43DP_QSERDES_TXA_TX_BAND 0x04D8 +#define USB43DP_QSERDES_TXA_SLEW_CNTL0 0x04DC +#define USB43DP_QSERDES_TXA_SLEW_CNTL1 0x04E0 +#define USB43DP_QSERDES_TXA_INTERFACE_SELECT 0x04E4 +#define USB43DP_QSERDES_TXA_DIG_BKUP_CTRL 0x04E8 +#define USB43DP_QSERDES_TXA_DEBUG_BUS0 0x04EC +#define USB43DP_QSERDES_TXA_DEBUG_BUS1 0x04F0 +#define USB43DP_QSERDES_TXA_DEBUG_BUS2 0x04F4 +#define USB43DP_QSERDES_TXA_DEBUG_BUS3 0x04F8 +#define USB43DP_QSERDES_TXA_TX_BKUP_RO_BUS 0x04FC + +/* Module: USB43DP_QSERDES_RXA_USB43DP_QSERDES_RXA_USB4_USB3_DP_QMP_RX */ +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE0 0x0600 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE1 0x0604 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE2 0x0608 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN_RATE3 0x060C +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE0 0x0610 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE1 0x0614 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE2 0x0618 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_SO_GAIN_RATE3 0x061C +#define USB43DP_QSERDES_RXA_UCDR_SO_SATURATION 0x0620 +#define USB43DP_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x0624 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x0628 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x062C +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x0630 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x0634 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x0638 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x063C +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x0640 +#define USB43DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x0644 +#define USB43DP_QSERDES_RXA_UCDR_PI_CTRL1 0x0648 +#define USB43DP_QSERDES_RXA_UCDR_PI_CTRL2 0x064C +#define USB43DP_QSERDES_RXA_UCDR_SB2_THRESH1_RATE0 0x0650 +#define USB43DP_QSERDES_RXA_UCDR_SB2_THRESH1_RATE1 0x0654 +#define USB43DP_QSERDES_RXA_UCDR_SB2_THRESH1_RATE2 0x0658 +#define USB43DP_QSERDES_RXA_UCDR_SB2_THRESH1_RATE3 0x065C +#define USB43DP_QSERDES_RXA_UCDR_SB2_THRESH2_RATE0 0x0660 +#define USB43DP_QSERDES_RXA_UCDR_SB2_THRESH2_RATE1 0x0664 +#define USB43DP_QSERDES_RXA_UCDR_SB2_THRESH2_RATE2 0x0668 +#define USB43DP_QSERDES_RXA_UCDR_SB2_THRESH2_RATE3 0x066C +#define USB43DP_QSERDES_RXA_UCDR_SB2_GAIN1_RATE0 0x0670 +#define USB43DP_QSERDES_RXA_UCDR_SB2_GAIN1_RATE1 0x0674 +#define USB43DP_QSERDES_RXA_UCDR_SB2_GAIN1_RATE2 0x0678 +#define USB43DP_QSERDES_RXA_UCDR_SB2_GAIN1_RATE3 0x067C +#define USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE0 0x0680 +#define USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE1 0x0684 +#define USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE2 0x0688 +#define USB43DP_QSERDES_RXA_UCDR_SB2_GAIN2_RATE3 0x068C +#define USB43DP_QSERDES_RXA_RXCLK_DIV2_CTRL 0x0690 +#define USB43DP_QSERDES_RXA_RX_BAND 0x0694 +#define USB43DP_QSERDES_RXA_RX_TERM_BW 0x0698 +#define USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE0 0x069C +#define USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE1 0x06A0 +#define USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE2 0x06A4 +#define USB43DP_QSERDES_RXA_UCDR_FO_GAIN_RATE3 0x06A8 +#define USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE0 0x06AC +#define USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE1 0x06B0 +#define USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE2 0x06B4 +#define USB43DP_QSERDES_RXA_UCDR_SO_GAIN_RATE3 0x06B8 +#define USB43DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x06BC +#define USB43DP_QSERDES_RXA_UCDR_PD_DATA_FILTER_ENABLES 0x06C0 +#define USB43DP_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x06C4 +#define USB43DP_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x06C8 +#define USB43DP_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x06CC +#define USB43DP_QSERDES_RXA_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x06D0 +#define USB43DP_QSERDES_RXA_AUX_CONTROL 0x06D4 +#define USB43DP_QSERDES_RXA_AUXDATA_TB 0x06D8 +#define USB43DP_QSERDES_RXA_RCLK_AUXDATA_SEL 0x06DC +#define USB43DP_QSERDES_RXA_EOM_CTRL 0x06E0 +#define USB43DP_QSERDES_RXA_AC_JTAG_ENABLE 0x06E4 +#define USB43DP_QSERDES_RXA_AC_JTAG_INITP 0x06E8 +#define USB43DP_QSERDES_RXA_AC_JTAG_INITN 0x06EC +#define USB43DP_QSERDES_RXA_AC_JTAG_LVL 0x06F0 +#define USB43DP_QSERDES_RXA_AC_JTAG_MODE 0x06F4 +#define USB43DP_QSERDES_RXA_AC_JTAG_RESET 0x06F8 +#define USB43DP_QSERDES_RXA_RX_RCVR_IQ_EN 0x06FC +#define USB43DP_QSERDES_RXA_RX_Q_EN_RATES 0x0700 +#define USB43DP_QSERDES_RXA_RX_IDAC_I0_DC_OFFSETS 0x0704 +#define USB43DP_QSERDES_RXA_RX_IDAC_I0BAR_DC_OFFSETS 0x0708 +#define USB43DP_QSERDES_RXA_RX_IDAC_I1_DC_OFFSETS 0x070C +#define USB43DP_QSERDES_RXA_RX_IDAC_I1BAR_DC_OFFSETS 0x0710 +#define USB43DP_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x0714 +#define USB43DP_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x0718 +#define USB43DP_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x071C +#define USB43DP_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x0720 +#define USB43DP_QSERDES_RXA_RX_IDAC_EN 0x0724 +#define USB43DP_QSERDES_RXA_RX_IDAC_ENABLES 0x0728 +#define USB43DP_QSERDES_RXA_RX_IDAC_SIGN 0x072C +#define USB43DP_QSERDES_RXA_RX_IVCM_CAL_CODE_OVERRIDE 0x0730 +#define USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL1 0x0734 +#define USB43DP_QSERDES_RXA_RX_IVCM_CAL_CTRL2 0x0738 +#define USB43DP_QSERDES_RXA_RX_IVCM_POSTCAL_OFFSET 0x073C +#define USB43DP_QSERDES_RXA_RX_SUMMER_CAL_SPD_MODE 0x0740 +#define USB43DP_QSERDES_RXA_RX_HIGHZ_PARRATE 0x0744 +#define USB43DP_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0748 +#define USB43DP_QSERDES_RXA_DFE_1 0x074C +#define USB43DP_QSERDES_RXA_DFE_2 0x0750 +#define USB43DP_QSERDES_RXA_DFE_3 0x0754 +#define USB43DP_QSERDES_RXA_DFE_4 0x0758 +#define USB43DP_QSERDES_RXA_DFE_TAP3_CTRL 0x075C +#define USB43DP_QSERDES_RXA_DFE_TAP3_MANVAL_KTAP 0x0760 +#define USB43DP_QSERDES_RXA_DFE_TAP4_CTRL 0x0764 +#define USB43DP_QSERDES_RXA_DFE_TAP4_MANVAL_KTAP 0x0768 +#define USB43DP_QSERDES_RXA_DFE_TAP5_CTRL 0x076C +#define USB43DP_QSERDES_RXA_DFE_TAP5_MANVAL_KTAP 0x0770 +#define USB43DP_QSERDES_RXA_TX_ADPT_CTRL 0x0774 +#define USB43DP_QSERDES_RXA_DFE_DAC_ENABLE1 0x0778 +#define USB43DP_QSERDES_RXA_DFE_DAC_ENABLE2 0x077C +#define USB43DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH1 0x0780 +#define USB43DP_QSERDES_RXA_TX_ADAPT_PRE_THRESH2 0x0784 +#define USB43DP_QSERDES_RXA_TX_ADAPT_POST_THRESH1 0x0788 +#define USB43DP_QSERDES_RXA_TX_ADAPT_POST_THRESH2 0x078C +#define USB43DP_QSERDES_RXA_TX_ADAPT_MAIN_THRESH1 0x0790 +#define USB43DP_QSERDES_RXA_TX_ADAPT_MAIN_THRESH2 0x0794 +#define USB43DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x0798 +#define USB43DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x079C +#define USB43DP_QSERDES_RXA_VGA_CAL_MAN_VAL 0x07A0 +#define USB43DP_QSERDES_RXA_VTHRESH_CAL_CNTRL1 0x07A4 +#define USB43DP_QSERDES_RXA_VTHRESH_CAL_CNTRL2 0x07A8 +#define USB43DP_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE0 0x07AC +#define USB43DP_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE1 0x07B0 +#define USB43DP_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE2 0x07B4 +#define USB43DP_QSERDES_RXA_VTHRESH_CAL_MAN_VAL_RATE3 0x07B8 +#define USB43DP_QSERDES_RXA_GM_CAL 0x07BC +#define USB43DP_QSERDES_RXA_RX_VGA_GAIN2_BLK1 0x07C0 +#define USB43DP_QSERDES_RXA_RX_VGA_GAIN2_BLK2 0x07C4 +#define USB43DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x07C8 +#define USB43DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x07CC +#define USB43DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x07D0 +#define USB43DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x07D4 +#define USB43DP_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x07D8 +#define USB43DP_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x07DC +#define USB43DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x07E0 +#define USB43DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x07E4 +#define USB43DP_QSERDES_RXA_SIGDET_ENABLES 0x07E8 +#define USB43DP_QSERDES_RXA_SIGDET_CNTRL 0x07EC +#define USB43DP_QSERDES_RXA_SIGDET_LVL 0x07F0 +#define USB43DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x07F4 +#define USB43DP_QSERDES_RXA_CDR_FREEZE_UP_DN 0x07F8 +#define USB43DP_QSERDES_RXA_CDR_RESET_OVERRIDE 0x07FC +#define USB43DP_QSERDES_RXA_RX_INTERFACE_MODE 0x0800 +#define USB43DP_QSERDES_RXA_JITTER_GEN_MODE 0x0804 +#define USB43DP_QSERDES_RXA_SJ_AMP1 0x0808 +#define USB43DP_QSERDES_RXA_SJ_AMP2 0x080C +#define USB43DP_QSERDES_RXA_SJ_PER1 0x0810 +#define USB43DP_QSERDES_RXA_SJ_PER2 0x0814 +#define USB43DP_QSERDES_RXA_PPM_OFFSET1 0x0818 +#define USB43DP_QSERDES_RXA_PPM_OFFSET2 0x081C +#define USB43DP_QSERDES_RXA_SIGN_PPM_PERIOD1 0x0820 +#define USB43DP_QSERDES_RXA_SIGN_PPM_PERIOD2 0x0824 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B0 0x0828 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B1 0x082C +#define USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B2 0x0830 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B3 0x0834 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B4 0x0838 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B5 0x083C +#define USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B6 0x0840 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE_0_1_B7 0x0844 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE2_B0 0x0848 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE2_B1 0x084C +#define USB43DP_QSERDES_RXA_RX_MODE_RATE2_B2 0x0850 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE2_B3 0x0854 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE2_B4 0x0858 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE2_B5 0x085C +#define USB43DP_QSERDES_RXA_RX_MODE_RATE2_B6 0x0860 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE2_B7 0x0864 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE3_B0 0x0868 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE3_B1 0x086C +#define USB43DP_QSERDES_RXA_RX_MODE_RATE3_B2 0x0870 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE3_B3 0x0874 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE3_B4 0x0878 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE3_B5 0x087C +#define USB43DP_QSERDES_RXA_RX_MODE_RATE3_B6 0x0880 +#define USB43DP_QSERDES_RXA_RX_MODE_RATE3_B7 0x0884 +#define USB43DP_QSERDES_RXA_PHPRE_CTRL 0x0888 +#define USB43DP_QSERDES_RXA_PHPRE_INITVAL 0x088C +#define USB43DP_QSERDES_RXA_DFE_EN_TIMER 0x0890 +#define USB43DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x0894 +#define USB43DP_QSERDES_RXA_DCC_CTRL1 0x0898 +#define USB43DP_QSERDES_RXA_DCC_CTRL2 0x089C +#define USB43DP_QSERDES_RXA_DCC_OFFSET 0x08A0 +#define USB43DP_QSERDES_RXA_DCC_CMUX_POSTCAL_OFFSET 0x08A4 +#define USB43DP_QSERDES_RXA_DCC_CMUX_CAL_CTRL1 0x08A8 +#define USB43DP_QSERDES_RXA_DCC_CMUX_CAL_CTRL2 0x08AC +#define USB43DP_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x08B0 +#define USB43DP_QSERDES_RXA_RX_MARG_CTRL1 0x08B4 +#define USB43DP_QSERDES_RXA_RX_MARG_CTRL2 0x08B8 +#define USB43DP_QSERDES_RXA_RX_MARG_CTRL3 0x08BC +#define USB43DP_QSERDES_RXA_RX_MARG_CTRL_4 0x08C0 +#define USB43DP_QSERDES_RXA_RX_MARG_CFG_RATE_0_1 0x08C4 +#define USB43DP_QSERDES_RXA_RX_MARG_CFG_RATE_2_3 0x08C8 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_CTRL1 0x08CC +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_CTRL2 0x08D0 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH1_RATE210 0x08D4 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH1_RATE3 0x08D8 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH2_RATE210 0x08DC +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH2_RATE3 0x08E0 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH3_RATE210 0x08E4 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH3_RATE3 0x08E8 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH4_RATE210 0x08EC +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH4_RATE3 0x08F0 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH5_RATE210 0x08F4 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH5_RATE3 0x08F8 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH6_RATE210 0x08FC +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH6_RATE3 0x0900 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH7_RATE210 0x0904 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_THRESH7_RATE3 0x0908 +#define USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE10 0x090C +#define USB43DP_QSERDES_RXA_Q_PI_INTRINSIC_BIAS_RATE32 0x0910 +#define USB43DP_QSERDES_RXA_RX_MARG_VERTICAL_CTRL 0x0914 +#define USB43DP_QSERDES_RXA_RX_MARG_VERTICAL_CODE 0x0918 +#define USB43DP_QSERDES_RXA_RES_CODE_THRESH_HIGH_AND_BYP 0x091C +#define USB43DP_QSERDES_RXA_RES_CODE_THRESH_LOW 0x0920 +#define USB43DP_QSERDES_RXA_RX_BKUP_CTRL1 0x0924 +#define USB43DP_QSERDES_RXA_RX_BKUP_CTRL2 0x0928 +#define USB43DP_QSERDES_RXA_RX_BKUP_CTRL3 0x092C +#define USB43DP_QSERDES_RXA_PI_CTRL1 0x0930 +#define USB43DP_QSERDES_RXA_PI_CTRL2 0x0934 +#define USB43DP_QSERDES_RXA_PI_QUAD 0x0938 +#define USB43DP_QSERDES_RXA_QPI_CTRL1 0x093C +#define USB43DP_QSERDES_RXA_QPI_CTRL2 0x0940 +#define USB43DP_QSERDES_RXA_QPI_QUAD 0x0944 +#define USB43DP_QSERDES_RXA_IDATA1 0x0948 +#define USB43DP_QSERDES_RXA_IDATA2 0x094C +#define USB43DP_QSERDES_RXA_IDATA3 0x0950 +#define USB43DP_QSERDES_RXA_AC_JTAG_OUTP 0x0954 +#define USB43DP_QSERDES_RXA_AC_JTAG_OUTN 0x0958 +#define USB43DP_QSERDES_RXA_RX_SIGDET 0x095C +#define USB43DP_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x0960 +#define USB43DP_QSERDES_RXA_READ_EQCODE 0x0964 +#define USB43DP_QSERDES_RXA_READ_OFFSETCODE 0x0968 +#define USB43DP_QSERDES_RXA_IA_ERROR_COUNTER_LOW 0x096C +#define USB43DP_QSERDES_RXA_IA_ERROR_COUNTER_HIGH 0x0970 +#define USB43DP_QSERDES_RXA_VGA_READ_CODE 0x0974 +#define USB43DP_QSERDES_RXA_VTHRESH_READ_CODE 0x0978 +#define USB43DP_QSERDES_RXA_DFE_TAP1_READ_CODE 0x097C +#define USB43DP_QSERDES_RXA_DFE_TAP2_READ_CODE 0x0980 +#define USB43DP_QSERDES_RXA_DFE_TAP3_READ_CODE 0x0984 +#define USB43DP_QSERDES_RXA_DFE_TAP4_READ_CODE 0x0988 +#define USB43DP_QSERDES_RXA_DFE_TAP5_READ_CODE 0x098C +#define USB43DP_QSERDES_RXA_IDAC_STATUS_I0 0x0990 +#define USB43DP_QSERDES_RXA_IDAC_STATUS_I0BAR 0x0994 +#define USB43DP_QSERDES_RXA_IDAC_STATUS_I1 0x0998 +#define USB43DP_QSERDES_RXA_IDAC_STATUS_I1BAR 0x099C +#define USB43DP_QSERDES_RXA_IDAC_STATUS_Q 0x09A0 +#define USB43DP_QSERDES_RXA_IDAC_STATUS_QBAR 0x09A4 +#define USB43DP_QSERDES_RXA_IDAC_STATUS_A 0x09A8 +#define USB43DP_QSERDES_RXA_IDAC_STATUS_ABAR 0x09AC +#define USB43DP_QSERDES_RXA_IDAC_STATUS_SM_ON 0x09B0 +#define USB43DP_QSERDES_RXA_IDAC_STATUS_SIGNERROR 0x09B4 +#define USB43DP_QSERDES_RXA_IVCM_CAL_STATUS 0x09B8 +#define USB43DP_QSERDES_RXA_IVCM_CAL_DEBUG_STATUS 0x09BC +#define USB43DP_QSERDES_RXA_DCC_CAL_STATUS 0x09C0 +#define USB43DP_QSERDES_RXA_DCC_READ_CODE_STATUS 0x09C4 +#define USB43DP_QSERDES_RXA_RX_MARG_DEBUG1_STATUS 0x09C8 +#define USB43DP_QSERDES_RXA_RX_MARG_DEBUG2_STATUS 0x09CC +#define USB43DP_QSERDES_RXA_RX_MARG_READ_CODE_STATUS 0x09D0 +#define USB43DP_QSERDES_RXA_EOM_ERR_CNT_LSB_STATUS 0x09D4 +#define USB43DP_QSERDES_RXA_EOM_ERR_CNT_MSB_STATUS 0x09D8 +#define USB43DP_QSERDES_RXA_RX_MARG_COARSE_TUNE_STATUS 0x09DC +#define USB43DP_QSERDES_RXA_RX_BKUP_READ_BUS1_STATUS 0x09E0 +#define USB43DP_QSERDES_RXA_RX_BKUP_READ_BUS2_STATUS 0x09E4 +#define USB43DP_QSERDES_RXA_RX_BKUP_READ_BUS3_STATUS 0x09E8 + +/* Module: USB43DP_QSERDES_TXB_USB43DP_QSERDES_TXB_USB4_USB3_DP_QMP_TX */ +#define USB43DP_QSERDES_TXB_BIST_MODE_LANENO 0x0A00 +#define USB43DP_QSERDES_TXB_BIST_INVERT 0x0A04 +#define USB43DP_QSERDES_TXB_CLKBUF_ENABLE 0x0A08 +#define USB43DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x0A0C +#define USB43DP_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x0A10 +#define USB43DP_QSERDES_TXB_TX_DRV_LVL 0x0A14 +#define USB43DP_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x0A18 +#define USB43DP_QSERDES_TXB_RESET_TSYNC_EN 0x0A1C +#define USB43DP_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x0A20 +#define USB43DP_QSERDES_TXB_LPB_EN 0x0A24 +#define USB43DP_QSERDES_TXB_RES_CODE_LANE_TX 0x0A28 +#define USB43DP_QSERDES_TXB_RES_CODE_LANE_RX 0x0A2C +#define USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x0A30 +#define USB43DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0A34 +#define USB43DP_QSERDES_TXB_PERL_LENGTH1 0x0A38 +#define USB43DP_QSERDES_TXB_PERL_LENGTH2 0x0A3C +#define USB43DP_QSERDES_TXB_SERDES_BYP_EN_OUT 0x0A40 +#define USB43DP_QSERDES_TXB_DEBUG_BUS_SEL 0x0A44 +#define USB43DP_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x0A48 +#define USB43DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x0A4C +#define USB43DP_QSERDES_TXB_TX_POL_INV 0x0A50 +#define USB43DP_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x0A54 +#define USB43DP_QSERDES_TXB_BIST_PATTERN1 0x0A58 +#define USB43DP_QSERDES_TXB_BIST_PATTERN2 0x0A5C +#define USB43DP_QSERDES_TXB_BIST_PATTERN3 0x0A60 +#define USB43DP_QSERDES_TXB_BIST_PATTERN4 0x0A64 +#define USB43DP_QSERDES_TXB_BIST_PATTERN5 0x0A68 +#define USB43DP_QSERDES_TXB_BIST_PATTERN6 0x0A6C +#define USB43DP_QSERDES_TXB_BIST_PATTERN7 0x0A70 +#define USB43DP_QSERDES_TXB_BIST_PATTERN8 0x0A74 +#define USB43DP_QSERDES_TXB_LANE_MODE_1 0x0A78 +#define USB43DP_QSERDES_TXB_LANE_MODE_2 0x0A7C +#define USB43DP_QSERDES_TXB_LANE_MODE_3 0x0A80 +#define USB43DP_QSERDES_TXB_ATB_SEL1 0x0A84 +#define USB43DP_QSERDES_TXB_ATB_SEL2 0x0A88 +#define USB43DP_QSERDES_TXB_RCV_DETECT_LVL 0x0A8C +#define USB43DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x0A90 +#define USB43DP_QSERDES_TXB_PRBS_SEED1 0x0A94 +#define USB43DP_QSERDES_TXB_PRBS_SEED2 0x0A98 +#define USB43DP_QSERDES_TXB_PRBS_SEED3 0x0A9C +#define USB43DP_QSERDES_TXB_PRBS_SEED4 0x0AA0 +#define USB43DP_QSERDES_TXB_RESET_GEN 0x0AA4 +#define USB43DP_QSERDES_TXB_RESET_GEN_MUXES 0x0AA8 +#define USB43DP_QSERDES_TXB_TRAN_DRVR_EMP_EN 0x0AAC +#define USB43DP_QSERDES_TXB_VMODE_CTRL1 0x0AB0 +#define USB43DP_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0x0AB4 +#define USB43DP_QSERDES_TXB_BIST_STATUS 0x0AB8 +#define USB43DP_QSERDES_TXB_BIST_ERROR_COUNT1 0x0ABC +#define USB43DP_QSERDES_TXB_BIST_ERROR_COUNT2 0x0AC0 +#define USB43DP_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0x0AC4 +#define USB43DP_QSERDES_TXB_LANE_DIG_CONFIG 0x0AC8 +#define USB43DP_QSERDES_TXB_PI_QEC_CTRL 0x0ACC +#define USB43DP_QSERDES_TXB_PRE_EMPH 0x0AD0 +#define USB43DP_QSERDES_TXB_SW_RESET 0x0AD4 +#define USB43DP_QSERDES_TXB_TX_BAND 0x0AD8 +#define USB43DP_QSERDES_TXB_SLEW_CNTL0 0x0ADC +#define USB43DP_QSERDES_TXB_SLEW_CNTL1 0x0AE0 +#define USB43DP_QSERDES_TXB_INTERFACE_SELECT 0x0AE4 +#define USB43DP_QSERDES_TXB_DIG_BKUP_CTRL 0x0AE8 +#define USB43DP_QSERDES_TXB_DEBUG_BUS0 0x0AEC +#define USB43DP_QSERDES_TXB_DEBUG_BUS1 0x0AF0 +#define USB43DP_QSERDES_TXB_DEBUG_BUS2 0x0AF4 +#define USB43DP_QSERDES_TXB_DEBUG_BUS3 0x0AF8 +#define USB43DP_QSERDES_TXB_TX_BKUP_RO_BUS 0x0AFC + +/* Module: USB43DP_QSERDES_RXB_USB43DP_QSERDES_RXB_USB4_USB3_DP_QMP_RX */ +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE0 0x0C00 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE1 0x0C04 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE2 0x0C08 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN_RATE3 0x0C0C +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE0 0x0C10 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE1 0x0C14 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE2 0x0C18 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_SO_GAIN_RATE3 0x0C1C +#define USB43DP_QSERDES_RXB_UCDR_SO_SATURATION 0x0C20 +#define USB43DP_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x0C24 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE0 0x0C28 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE0 0x0C2C +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE1 0x0C30 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE1 0x0C34 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE2 0x0C38 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE2 0x0C3C +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW_RATE3 0x0C40 +#define USB43DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH_RATE3 0x0C44 +#define USB43DP_QSERDES_RXB_UCDR_PI_CTRL1 0x0C48 +#define USB43DP_QSERDES_RXB_UCDR_PI_CTRL2 0x0C4C +#define USB43DP_QSERDES_RXB_UCDR_SB2_THRESH1_RATE0 0x0C50 +#define USB43DP_QSERDES_RXB_UCDR_SB2_THRESH1_RATE1 0x0C54 +#define USB43DP_QSERDES_RXB_UCDR_SB2_THRESH1_RATE2 0x0C58 +#define USB43DP_QSERDES_RXB_UCDR_SB2_THRESH1_RATE3 0x0C5C +#define USB43DP_QSERDES_RXB_UCDR_SB2_THRESH2_RATE0 0x0C60 +#define USB43DP_QSERDES_RXB_UCDR_SB2_THRESH2_RATE1 0x0C64 +#define USB43DP_QSERDES_RXB_UCDR_SB2_THRESH2_RATE2 0x0C68 +#define USB43DP_QSERDES_RXB_UCDR_SB2_THRESH2_RATE3 0x0C6C +#define USB43DP_QSERDES_RXB_UCDR_SB2_GAIN1_RATE0 0x0C70 +#define USB43DP_QSERDES_RXB_UCDR_SB2_GAIN1_RATE1 0x0C74 +#define USB43DP_QSERDES_RXB_UCDR_SB2_GAIN1_RATE2 0x0C78 +#define USB43DP_QSERDES_RXB_UCDR_SB2_GAIN1_RATE3 0x0C7C +#define USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE0 0x0C80 +#define USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE1 0x0C84 +#define USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE2 0x0C88 +#define USB43DP_QSERDES_RXB_UCDR_SB2_GAIN2_RATE3 0x0C8C +#define USB43DP_QSERDES_RXB_RXCLK_DIV2_CTRL 0x0C90 +#define USB43DP_QSERDES_RXB_RX_BAND 0x0C94 +#define USB43DP_QSERDES_RXB_RX_TERM_BW 0x0C98 +#define USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE0 0x0C9C +#define USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE1 0x0CA0 +#define USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE2 0x0CA4 +#define USB43DP_QSERDES_RXB_UCDR_FO_GAIN_RATE3 0x0CA8 +#define USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE0 0x0CAC +#define USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE1 0x0CB0 +#define USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE2 0x0CB4 +#define USB43DP_QSERDES_RXB_UCDR_SO_GAIN_RATE3 0x0CB8 +#define USB43DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x0CBC +#define USB43DP_QSERDES_RXB_UCDR_PD_DATA_FILTER_ENABLES 0x0CC0 +#define USB43DP_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE0 0x0CC4 +#define USB43DP_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE1 0x0CC8 +#define USB43DP_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE2 0x0CCC +#define USB43DP_QSERDES_RXB_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x0CD0 +#define USB43DP_QSERDES_RXB_AUX_CONTROL 0x0CD4 +#define USB43DP_QSERDES_RXB_AUXDATA_TB 0x0CD8 +#define USB43DP_QSERDES_RXB_RCLK_AUXDATA_SEL 0x0CDC +#define USB43DP_QSERDES_RXB_EOM_CTRL 0x0CE0 +#define USB43DP_QSERDES_RXB_AC_JTAG_ENABLE 0x0CE4 +#define USB43DP_QSERDES_RXB_AC_JTAG_INITP 0x0CE8 +#define USB43DP_QSERDES_RXB_AC_JTAG_INITN 0x0CEC +#define USB43DP_QSERDES_RXB_AC_JTAG_LVL 0x0CF0 +#define USB43DP_QSERDES_RXB_AC_JTAG_MODE 0x0CF4 +#define USB43DP_QSERDES_RXB_AC_JTAG_RESET 0x0CF8 +#define USB43DP_QSERDES_RXB_RX_RCVR_IQ_EN 0x0CFC +#define USB43DP_QSERDES_RXB_RX_Q_EN_RATES 0x0D00 +#define USB43DP_QSERDES_RXB_RX_IDAC_I0_DC_OFFSETS 0x0D04 +#define USB43DP_QSERDES_RXB_RX_IDAC_I0BAR_DC_OFFSETS 0x0D08 +#define USB43DP_QSERDES_RXB_RX_IDAC_I1_DC_OFFSETS 0x0D0C +#define USB43DP_QSERDES_RXB_RX_IDAC_I1BAR_DC_OFFSETS 0x0D10 +#define USB43DP_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x0D14 +#define USB43DP_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x0D18 +#define USB43DP_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x0D1C +#define USB43DP_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x0D20 +#define USB43DP_QSERDES_RXB_RX_IDAC_EN 0x0D24 +#define USB43DP_QSERDES_RXB_RX_IDAC_ENABLES 0x0D28 +#define USB43DP_QSERDES_RXB_RX_IDAC_SIGN 0x0D2C +#define USB43DP_QSERDES_RXB_RX_IVCM_CAL_CODE_OVERRIDE 0x0D30 +#define USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL1 0x0D34 +#define USB43DP_QSERDES_RXB_RX_IVCM_CAL_CTRL2 0x0D38 +#define USB43DP_QSERDES_RXB_RX_IVCM_POSTCAL_OFFSET 0x0D3C +#define USB43DP_QSERDES_RXB_RX_SUMMER_CAL_SPD_MODE 0x0D40 +#define USB43DP_QSERDES_RXB_RX_HIGHZ_PARRATE 0x0D44 +#define USB43DP_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0D48 +#define USB43DP_QSERDES_RXB_DFE_1 0x0D4C +#define USB43DP_QSERDES_RXB_DFE_2 0x0D50 +#define USB43DP_QSERDES_RXB_DFE_3 0x0D54 +#define USB43DP_QSERDES_RXB_DFE_4 0x0D58 +#define USB43DP_QSERDES_RXB_DFE_TAP3_CTRL 0x0D5C +#define USB43DP_QSERDES_RXB_DFE_TAP3_MANVAL_KTAP 0x0D60 +#define USB43DP_QSERDES_RXB_DFE_TAP4_CTRL 0x0D64 +#define USB43DP_QSERDES_RXB_DFE_TAP4_MANVAL_KTAP 0x0D68 +#define USB43DP_QSERDES_RXB_DFE_TAP5_CTRL 0x0D6C +#define USB43DP_QSERDES_RXB_DFE_TAP5_MANVAL_KTAP 0x0D70 +#define USB43DP_QSERDES_RXB_TX_ADPT_CTRL 0x0D74 +#define USB43DP_QSERDES_RXB_DFE_DAC_ENABLE1 0x0D78 +#define USB43DP_QSERDES_RXB_DFE_DAC_ENABLE2 0x0D7C +#define USB43DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH1 0x0D80 +#define USB43DP_QSERDES_RXB_TX_ADAPT_PRE_THRESH2 0x0D84 +#define USB43DP_QSERDES_RXB_TX_ADAPT_POST_THRESH1 0x0D88 +#define USB43DP_QSERDES_RXB_TX_ADAPT_POST_THRESH2 0x0D8C +#define USB43DP_QSERDES_RXB_TX_ADAPT_MAIN_THRESH1 0x0D90 +#define USB43DP_QSERDES_RXB_TX_ADAPT_MAIN_THRESH2 0x0D94 +#define USB43DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x0D98 +#define USB43DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0D9C +#define USB43DP_QSERDES_RXB_VGA_CAL_MAN_VAL 0x0DA0 +#define USB43DP_QSERDES_RXB_VTHRESH_CAL_CNTRL1 0x0DA4 +#define USB43DP_QSERDES_RXB_VTHRESH_CAL_CNTRL2 0x0DA8 +#define USB43DP_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE0 0x0DAC +#define USB43DP_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE1 0x0DB0 +#define USB43DP_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE2 0x0DB4 +#define USB43DP_QSERDES_RXB_VTHRESH_CAL_MAN_VAL_RATE3 0x0DB8 +#define USB43DP_QSERDES_RXB_GM_CAL 0x0DBC +#define USB43DP_QSERDES_RXB_RX_VGA_GAIN2_BLK1 0x0DC0 +#define USB43DP_QSERDES_RXB_RX_VGA_GAIN2_BLK2 0x0DC4 +#define USB43DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0DC8 +#define USB43DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x0DCC +#define USB43DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0DD0 +#define USB43DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x0DD4 +#define USB43DP_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x0DD8 +#define USB43DP_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x0DDC +#define USB43DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0DE0 +#define USB43DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x0DE4 +#define USB43DP_QSERDES_RXB_SIGDET_ENABLES 0x0DE8 +#define USB43DP_QSERDES_RXB_SIGDET_CNTRL 0x0DEC +#define USB43DP_QSERDES_RXB_SIGDET_LVL 0x0DF0 +#define USB43DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0DF4 +#define USB43DP_QSERDES_RXB_CDR_FREEZE_UP_DN 0x0DF8 +#define USB43DP_QSERDES_RXB_CDR_RESET_OVERRIDE 0x0DFC +#define USB43DP_QSERDES_RXB_RX_INTERFACE_MODE 0x0E00 +#define USB43DP_QSERDES_RXB_JITTER_GEN_MODE 0x0E04 +#define USB43DP_QSERDES_RXB_SJ_AMP1 0x0E08 +#define USB43DP_QSERDES_RXB_SJ_AMP2 0x0E0C +#define USB43DP_QSERDES_RXB_SJ_PER1 0x0E10 +#define USB43DP_QSERDES_RXB_SJ_PER2 0x0E14 +#define USB43DP_QSERDES_RXB_PPM_OFFSET1 0x0E18 +#define USB43DP_QSERDES_RXB_PPM_OFFSET2 0x0E1C +#define USB43DP_QSERDES_RXB_SIGN_PPM_PERIOD1 0x0E20 +#define USB43DP_QSERDES_RXB_SIGN_PPM_PERIOD2 0x0E24 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B0 0x0E28 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B1 0x0E2C +#define USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B2 0x0E30 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B3 0x0E34 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B4 0x0E38 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B5 0x0E3C +#define USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B6 0x0E40 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE_0_1_B7 0x0E44 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE2_B0 0x0E48 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE2_B1 0x0E4C +#define USB43DP_QSERDES_RXB_RX_MODE_RATE2_B2 0x0E50 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE2_B3 0x0E54 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE2_B4 0x0E58 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE2_B5 0x0E5C +#define USB43DP_QSERDES_RXB_RX_MODE_RATE2_B6 0x0E60 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE2_B7 0x0E64 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE3_B0 0x0E68 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE3_B1 0x0E6C +#define USB43DP_QSERDES_RXB_RX_MODE_RATE3_B2 0x0E70 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE3_B3 0x0E74 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE3_B4 0x0E78 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE3_B5 0x0E7C +#define USB43DP_QSERDES_RXB_RX_MODE_RATE3_B6 0x0E80 +#define USB43DP_QSERDES_RXB_RX_MODE_RATE3_B7 0x0E84 +#define USB43DP_QSERDES_RXB_PHPRE_CTRL 0x0E88 +#define USB43DP_QSERDES_RXB_PHPRE_INITVAL 0x0E8C +#define USB43DP_QSERDES_RXB_DFE_EN_TIMER 0x0E90 +#define USB43DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x0E94 +#define USB43DP_QSERDES_RXB_DCC_CTRL1 0x0E98 +#define USB43DP_QSERDES_RXB_DCC_CTRL2 0x0E9C +#define USB43DP_QSERDES_RXB_DCC_OFFSET 0x0EA0 +#define USB43DP_QSERDES_RXB_DCC_CMUX_POSTCAL_OFFSET 0x0EA4 +#define USB43DP_QSERDES_RXB_DCC_CMUX_CAL_CTRL1 0x0EA8 +#define USB43DP_QSERDES_RXB_DCC_CMUX_CAL_CTRL2 0x0EAC +#define USB43DP_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x0EB0 +#define USB43DP_QSERDES_RXB_RX_MARG_CTRL1 0x0EB4 +#define USB43DP_QSERDES_RXB_RX_MARG_CTRL2 0x0EB8 +#define USB43DP_QSERDES_RXB_RX_MARG_CTRL3 0x0EBC +#define USB43DP_QSERDES_RXB_RX_MARG_CTRL_4 0x0EC0 +#define USB43DP_QSERDES_RXB_RX_MARG_CFG_RATE_0_1 0x0EC4 +#define USB43DP_QSERDES_RXB_RX_MARG_CFG_RATE_2_3 0x0EC8 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_CTRL1 0x0ECC +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_CTRL2 0x0ED0 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH1_RATE210 0x0ED4 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH1_RATE3 0x0ED8 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH2_RATE210 0x0EDC +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH2_RATE3 0x0EE0 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH3_RATE210 0x0EE4 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH3_RATE3 0x0EE8 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH4_RATE210 0x0EEC +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH4_RATE3 0x0EF0 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH5_RATE210 0x0EF4 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH5_RATE3 0x0EF8 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH6_RATE210 0x0EFC +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH6_RATE3 0x0F00 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH7_RATE210 0x0F04 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_THRESH7_RATE3 0x0F08 +#define USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE10 0x0F0C +#define USB43DP_QSERDES_RXB_Q_PI_INTRINSIC_BIAS_RATE32 0x0F10 +#define USB43DP_QSERDES_RXB_RX_MARG_VERTICAL_CTRL 0x0F14 +#define USB43DP_QSERDES_RXB_RX_MARG_VERTICAL_CODE 0x0F18 +#define USB43DP_QSERDES_RXB_RES_CODE_THRESH_HIGH_AND_BYP 0x0F1C +#define USB43DP_QSERDES_RXB_RES_CODE_THRESH_LOW 0x0F20 +#define USB43DP_QSERDES_RXB_RX_BKUP_CTRL1 0x0F24 +#define USB43DP_QSERDES_RXB_RX_BKUP_CTRL2 0x0F28 +#define USB43DP_QSERDES_RXB_RX_BKUP_CTRL3 0x0F2C +#define USB43DP_QSERDES_RXB_PI_CTRL1 0x0F30 +#define USB43DP_QSERDES_RXB_PI_CTRL2 0x0F34 +#define USB43DP_QSERDES_RXB_PI_QUAD 0x0F38 +#define USB43DP_QSERDES_RXB_QPI_CTRL1 0x0F3C +#define USB43DP_QSERDES_RXB_QPI_CTRL2 0x0F40 +#define USB43DP_QSERDES_RXB_QPI_QUAD 0x0F44 +#define USB43DP_QSERDES_RXB_IDATA1 0x0F48 +#define USB43DP_QSERDES_RXB_IDATA2 0x0F4C +#define USB43DP_QSERDES_RXB_IDATA3 0x0F50 +#define USB43DP_QSERDES_RXB_AC_JTAG_OUTP 0x0F54 +#define USB43DP_QSERDES_RXB_AC_JTAG_OUTN 0x0F58 +#define USB43DP_QSERDES_RXB_RX_SIGDET 0x0F5C +#define USB43DP_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x0F60 +#define USB43DP_QSERDES_RXB_READ_EQCODE 0x0F64 +#define USB43DP_QSERDES_RXB_READ_OFFSETCODE 0x0F68 +#define USB43DP_QSERDES_RXB_IA_ERROR_COUNTER_LOW 0x0F6C +#define USB43DP_QSERDES_RXB_IA_ERROR_COUNTER_HIGH 0x0F70 +#define USB43DP_QSERDES_RXB_VGA_READ_CODE 0x0F74 +#define USB43DP_QSERDES_RXB_VTHRESH_READ_CODE 0x0F78 +#define USB43DP_QSERDES_RXB_DFE_TAP1_READ_CODE 0x0F7C +#define USB43DP_QSERDES_RXB_DFE_TAP2_READ_CODE 0x0F80 +#define USB43DP_QSERDES_RXB_DFE_TAP3_READ_CODE 0x0F84 +#define USB43DP_QSERDES_RXB_DFE_TAP4_READ_CODE 0x0F88 +#define USB43DP_QSERDES_RXB_DFE_TAP5_READ_CODE 0x0F8C +#define USB43DP_QSERDES_RXB_IDAC_STATUS_I0 0x0F90 +#define USB43DP_QSERDES_RXB_IDAC_STATUS_I0BAR 0x0F94 +#define USB43DP_QSERDES_RXB_IDAC_STATUS_I1 0x0F98 +#define USB43DP_QSERDES_RXB_IDAC_STATUS_I1BAR 0x0F9C +#define USB43DP_QSERDES_RXB_IDAC_STATUS_Q 0x0FA0 +#define USB43DP_QSERDES_RXB_IDAC_STATUS_QBAR 0x0FA4 +#define USB43DP_QSERDES_RXB_IDAC_STATUS_A 0x0FA8 +#define USB43DP_QSERDES_RXB_IDAC_STATUS_ABAR 0x0FAC +#define USB43DP_QSERDES_RXB_IDAC_STATUS_SM_ON 0x0FB0 +#define USB43DP_QSERDES_RXB_IDAC_STATUS_SIGNERROR 0x0FB4 +#define USB43DP_QSERDES_RXB_IVCM_CAL_STATUS 0x0FB8 +#define USB43DP_QSERDES_RXB_IVCM_CAL_DEBUG_STATUS 0x0FBC +#define USB43DP_QSERDES_RXB_DCC_CAL_STATUS 0x0FC0 +#define USB43DP_QSERDES_RXB_DCC_READ_CODE_STATUS 0x0FC4 +#define USB43DP_QSERDES_RXB_RX_MARG_DEBUG1_STATUS 0x0FC8 +#define USB43DP_QSERDES_RXB_RX_MARG_DEBUG2_STATUS 0x0FCC +#define USB43DP_QSERDES_RXB_RX_MARG_READ_CODE_STATUS 0x0FD0 +#define USB43DP_QSERDES_RXB_EOM_ERR_CNT_LSB_STATUS 0x0FD4 +#define USB43DP_QSERDES_RXB_EOM_ERR_CNT_MSB_STATUS 0x0FD8 +#define USB43DP_QSERDES_RXB_RX_MARG_COARSE_TUNE_STATUS 0x0FDC +#define USB43DP_QSERDES_RXB_RX_BKUP_READ_BUS1_STATUS 0x0FE0 +#define USB43DP_QSERDES_RXB_RX_BKUP_READ_BUS2_STATUS 0x0FE4 +#define USB43DP_QSERDES_RXB_RX_BKUP_READ_BUS3_STATUS 0x0FE8 + +/* Module: USB3_QSERDES_PLL_USB3_QSERDES_PLL_USB4_USB3_DP_QMP_PLL_20G */ +#define USB3_QSERDES_PLL_ATB_SEL1 0x1000 +#define USB3_QSERDES_PLL_ATB_SEL2 0x1004 +#define USB3_QSERDES_PLL_FREQ_UPDATE 0x1008 +#define USB3_QSERDES_PLL_BG_TIMER 0x100C +#define USB3_QSERDES_PLL_SSC_EN_CENTER 0x1010 +#define USB3_QSERDES_PLL_SSC_ADJ_PER1 0x1014 +#define USB3_QSERDES_PLL_SSC_ADJ_PER2 0x1018 +#define USB3_QSERDES_PLL_SSC_PER1 0x101C +#define USB3_QSERDES_PLL_SSC_PER2 0x1020 +#define USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x1024 +#define USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x1028 +#define USB3_QSERDES_PLL_SSC_STEP_SIZE3_MODE0 0x102C +#define USB3_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x1030 +#define USB3_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x1034 +#define USB3_QSERDES_PLL_SSC_STEP_SIZE3_MODE1 0x1038 +#define USB3_QSERDES_PLL_POST_DIV 0x103C +#define USB3_QSERDES_PLL_POST_DIV_MUX 0x1040 +#define USB3_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x1044 +#define USB3_QSERDES_PLL_CLK_ENABLE1 0x1048 +#define USB3_QSERDES_PLL_SYS_CLK_CTRL 0x104C +#define USB3_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x1050 +#define USB3_QSERDES_PLL_PLL_EN 0x1054 +#define USB3_QSERDES_PLL_PLL_IVCO 0x1058 +#define USB3_QSERDES_PLL_CMN_IETRIM 0x105C +#define USB3_QSERDES_PLL_CMN_IPTRIM 0x1060 +#define USB3_QSERDES_PLL_EP_CLOCK_DETECT_CTRL 0x1064 +#define USB3_QSERDES_PLL_SYSCLK_DET_COMP_STATUS 0x1068 +#define USB3_QSERDES_PLL_CLK_EP_DIV_MODE0 0x106C +#define USB3_QSERDES_PLL_CLK_EP_DIV_MODE1 0x1070 +#define USB3_QSERDES_PLL_CP_CTRL_MODE0 0x1074 +#define USB3_QSERDES_PLL_CP_CTRL_MODE1 0x1078 +#define USB3_QSERDES_PLL_PLL_RCTRL_MODE0 0x107C +#define USB3_QSERDES_PLL_PLL_RCTRL_MODE1 0x1080 +#define USB3_QSERDES_PLL_PLL_CCTRL_MODE0 0x1084 +#define USB3_QSERDES_PLL_PLL_CCTRL_MODE1 0x1088 +#define USB3_QSERDES_PLL_PLL_CNTRL 0x108C +#define USB3_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x1090 +#define USB3_QSERDES_PLL_SYSCLK_EN_SEL 0x1094 +#define USB3_QSERDES_PLL_CML_SYSCLK_SEL 0x1098 +#define USB3_QSERDES_PLL_RESETSM_CNTRL 0x109C +#define USB3_QSERDES_PLL_RESETSM_CNTRL2 0x10A0 +#define USB3_QSERDES_PLL_LOCK_CMP_EN 0x10A4 +#define USB3_QSERDES_PLL_LOCK_CMP_CFG 0x10A8 +#define USB3_QSERDES_PLL_LOCK_CMP1_MODE0 0x10AC +#define USB3_QSERDES_PLL_LOCK_CMP2_MODE0 0x10B0 +#define USB3_QSERDES_PLL_LOCK_CMP1_MODE1 0x10B4 +#define USB3_QSERDES_PLL_LOCK_CMP2_MODE1 0x10B8 +#define USB3_QSERDES_PLL_DEC_START_MODE0 0x10BC +#define USB3_QSERDES_PLL_DEC_START_MSB_MODE0 0x10C0 +#define USB3_QSERDES_PLL_DEC_START_MODE1 0x10C4 +#define USB3_QSERDES_PLL_DEC_START_MSB_MODE1 0x10C8 +#define USB3_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x10CC +#define USB3_QSERDES_PLL_DIV_FRAC_START2_MODE0 0x10D0 +#define USB3_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x10D4 +#define USB3_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x10D8 +#define USB3_QSERDES_PLL_DIV_FRAC_START2_MODE1 0x10DC +#define USB3_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x10E0 +#define USB3_QSERDES_PLL_INTEGLOOP_INITVAL 0x10E4 +#define USB3_QSERDES_PLL_INTEGLOOP_EN 0x10E8 +#define USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x10EC +#define USB3_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x10F0 +#define USB3_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x10F4 +#define USB3_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10F8 +#define USB3_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0 0x10FC +#define USB3_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1 0x1100 +#define USB3_QSERDES_PLL_VCOCAL_DEADMAN_CTRL 0x1104 +#define USB3_QSERDES_PLL_VCO_TUNE_CTRL 0x1108 +#define USB3_QSERDES_PLL_VCO_TUNE_MAP 0x110C +#define USB3_QSERDES_PLL_VCO_TUNE1_MODE0 0x1110 +#define USB3_QSERDES_PLL_VCO_TUNE2_MODE0 0x1114 +#define USB3_QSERDES_PLL_VCO_TUNE1_MODE1 0x1118 +#define USB3_QSERDES_PLL_VCO_TUNE2_MODE1 0x111C +#define USB3_QSERDES_PLL_VCO_TUNE_INITVAL1 0x1120 +#define USB3_QSERDES_PLL_VCO_TUNE_INITVAL2 0x1124 +#define USB3_QSERDES_PLL_VCO_TUNE_MINVAL1 0x1128 +#define USB3_QSERDES_PLL_VCO_TUNE_MINVAL2 0x112C +#define USB3_QSERDES_PLL_VCO_TUNE_MAXVAL1 0x1130 +#define USB3_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x1134 +#define USB3_QSERDES_PLL_VCO_TUNE_TIMER1 0x1138 +#define USB3_QSERDES_PLL_VCO_TUNE_TIMER2 0x113C +#define USB3_QSERDES_PLL_CMN_STATUS 0x1140 +#define USB3_QSERDES_PLL_RESET_SM_STATUS 0x1144 +#define USB3_QSERDES_PLL_RESTRIM_CODE_STATUS 0x1148 +#define USB3_QSERDES_PLL_PLLCAL_CODE1_STATUS 0x114C +#define USB3_QSERDES_PLL_PLLCAL_CODE2_STATUS 0x1150 +#define USB3_QSERDES_PLL_CLK_SELECT 0x1154 +#define USB3_QSERDES_PLL_HSCLK_SEL 0x1158 +#define USB3_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x115C +#define USB3_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS 0x1160 +#define USB3_QSERDES_PLL_PLL_ANALOG 0x1164 +#define USB3_QSERDES_PLL_CORECLK_DIV_MODE0 0x1168 +#define USB3_QSERDES_PLL_CORECLK_DIV_MODE1 0x116C +#define USB3_QSERDES_PLL_SW_RESET 0x1170 +#define USB3_QSERDES_PLL_CORE_CLK_EN 0x1174 +#define USB3_QSERDES_PLL_C_READY_STATUS 0x1178 +#define USB3_QSERDES_PLL_CMN_CONFIG 0x117C +#define USB3_QSERDES_PLL_CMN_RATE_OVERRIDE 0x1180 +#define USB3_QSERDES_PLL_SVS_MODE_CLK_SEL 0x1184 +#define USB3_QSERDES_PLL_DEBUG_BUS0 0x1188 +#define USB3_QSERDES_PLL_DEBUG_BUS1 0x118C +#define USB3_QSERDES_PLL_DEBUG_BUS2 0x1190 +#define USB3_QSERDES_PLL_DEBUG_BUS3 0x1194 +#define USB3_QSERDES_PLL_DEBUG_BUS_SEL 0x1198 +#define USB3_QSERDES_PLL_CMN_MISC1 0x119C +#define USB3_QSERDES_PLL_CMN_MODE 0x11A0 +#define USB3_QSERDES_PLL_CMN_MODE_CONTD 0x11A4 +#define USB3_QSERDES_PLL_VCO_DC_LEVEL_CTRL 0x11A8 +#define USB3_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x11AC +#define USB3_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x11B0 +#define USB3_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x11B4 +#define USB3_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x11B8 +#define USB3_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL 0x11BC +#define USB3_QSERDES_PLL_ADDITIONAL_CTRL_1 0x11C0 +#define USB3_QSERDES_PLL_MODE_OPERATION_STATUS 0x11C4 +#define USB3_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_1 0x11C8 +#define USB3_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_2 0x11CC +#define USB3_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_3 0x11D0 +#define USB3_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_4 0x11D4 +#define USB3_QSERDES_PLL_ADDITIONAL_MISC 0x11D8 +#define USB3_QSERDES_PLL_ADDITIONAL_MISC_2 0x11DC +#define USB3_QSERDES_PLL_ADDITIONAL_MISC_3 0x11E0 + +/* Module: USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */ +#define USB3_PCS_MISC_TYPEC_CTRL 0x1200 +#define USB3_PCS_MISC_TYPEC_PWRDN_CTRL 0x1204 +#define USB3_PCS_MISC_PCS_MISC_CONFIG1 0x1208 +#define USB3_PCS_MISC_CLAMP_ENABLE 0x120C +#define USB3_PCS_MISC_TYPEC_STATUS 0x1210 +#define USB3_PCS_MISC_PLACEHOLDER_STATUS 0x1214 + +/* Module: USB3_PCS_LN_USB3_PCS_LN_USB3_PCS_LANE */ +#define USB3_PCS_LN_PCS_STATUS1 0x1300 +#define USB3_PCS_LN_PCS_STATUS2 0x1304 +#define USB3_PCS_LN_PCS_STATUS2_CLEAR 0x1308 +#define USB3_PCS_LN_PCS_STATUS3 0x130C +#define USB3_PCS_LN_BIST_CHK_ERR_CNT_L_STATUS 0x1310 +#define USB3_PCS_LN_BIST_CHK_ERR_CNT_H_STATUS 0x1314 +#define USB3_PCS_LN_BIST_CHK_STATUS 0x1318 +#define USB3_PCS_LN_INSIG_SW_CTRL1 0x131C +#define USB3_PCS_LN_INSIG_MX_CTRL1 0x1320 +#define USB3_PCS_LN_OUTSIG_SW_CTRL1 0x1324 +#define USB3_PCS_LN_OUTSIG_MX_CTRL1 0x1328 +#define USB3_PCS_LN_TEST_CONTROL1 0x132C +#define USB3_PCS_LN_BIST_CTRL 0x1330 +#define USB3_PCS_LN_PRBS_SEED0 0x1334 +#define USB3_PCS_LN_PRBS_SEED1 0x1338 +#define USB3_PCS_LN_FIXED_PAT_CTRL 0x133C +#define USB3_PCS_LN_EQ_CONFIG 0x1340 +#define USB3_PCS_LN_TEST_CONTROL2 0x1344 +#define USB3_PCS_LN_TEST_CONTROL3 0x1348 + +/* Module: USB3_PCS_USB3_PCS_USB3_PCS */ +#define USB3_PCS_SW_RESET 0x1400 +#define USB3_PCS_REVISION_ID0 0x1404 +#define USB3_PCS_REVISION_ID1 0x1408 +#define USB3_PCS_REVISION_ID2 0x140C +#define USB3_PCS_REVISION_ID3 0x1410 +#define USB3_PCS_PCS_STATUS1 0x1414 +#define USB3_PCS_PCS_STATUS2 0x1418 +#define USB3_PCS_PCS_STATUS3 0x141C +#define USB3_PCS_PCS_STATUS4 0x1420 +#define USB3_PCS_PCS_STATUS5 0x1424 +#define USB3_PCS_PCS_STATUS6 0x1428 +#define USB3_PCS_PCS_STATUS7 0x142C +#define USB3_PCS_DEBUG_BUS_0_STATUS 0x1430 +#define USB3_PCS_DEBUG_BUS_1_STATUS 0x1434 +#define USB3_PCS_DEBUG_BUS_2_STATUS 0x1438 +#define USB3_PCS_DEBUG_BUS_3_STATUS 0x143C +#define USB3_PCS_POWER_DOWN_CONTROL 0x1440 +#define USB3_PCS_START_CONTROL 0x1444 +#define USB3_PCS_INSIG_SW_CTRL1 0x1448 +#define USB3_PCS_INSIG_SW_CTRL2 0x144C +#define USB3_PCS_INSIG_SW_CTRL3 0x1450 +#define USB3_PCS_INSIG_SW_CTRL4 0x1454 +#define USB3_PCS_INSIG_SW_CTRL5 0x1458 +#define USB3_PCS_INSIG_SW_CTRL6 0x145C +#define USB3_PCS_INSIG_SW_CTRL7 0x1460 +#define USB3_PCS_INSIG_SW_CTRL8 0x1464 +#define USB3_PCS_INSIG_MX_CTRL1 0x1468 +#define USB3_PCS_INSIG_MX_CTRL2 0x146C +#define USB3_PCS_INSIG_MX_CTRL3 0x1470 +#define USB3_PCS_INSIG_MX_CTRL4 0x1474 +#define USB3_PCS_INSIG_MX_CTRL5 0x1478 +#define USB3_PCS_INSIG_MX_CTRL7 0x147C +#define USB3_PCS_INSIG_MX_CTRL8 0x1480 +#define USB3_PCS_OUTSIG_SW_CTRL1 0x1484 +#define USB3_PCS_OUTSIG_MX_CTRL1 0x1488 +#define USB3_PCS_CLAMP_ENABLE 0x148C +#define USB3_PCS_POWER_STATE_CONFIG1 0x1490 +#define USB3_PCS_POWER_STATE_CONFIG2 0x1494 +#define USB3_PCS_FLL_CNTRL1 0x1498 +#define USB3_PCS_FLL_CNTRL2 0x149C +#define USB3_PCS_FLL_CNT_VAL_L 0x14A0 +#define USB3_PCS_FLL_CNT_VAL_H_TOL 0x14A4 +#define USB3_PCS_FLL_MAN_CODE 0x14A8 +#define USB3_PCS_TEST_CONTROL1 0x14AC +#define USB3_PCS_TEST_CONTROL2 0x14B0 +#define USB3_PCS_TEST_CONTROL3 0x14B4 +#define USB3_PCS_TEST_CONTROL4 0x14B8 +#define USB3_PCS_TEST_CONTROL5 0x14BC +#define USB3_PCS_TEST_CONTROL6 0x14C0 +#define USB3_PCS_LOCK_DETECT_CONFIG1 0x14C4 +#define USB3_PCS_LOCK_DETECT_CONFIG2 0x14C8 +#define USB3_PCS_LOCK_DETECT_CONFIG3 0x14CC +#define USB3_PCS_LOCK_DETECT_CONFIG4 0x14D0 +#define USB3_PCS_LOCK_DETECT_CONFIG5 0x14D4 +#define USB3_PCS_LOCK_DETECT_CONFIG6 0x14D8 +#define USB3_PCS_REFGEN_REQ_CONFIG1 0x14DC +#define USB3_PCS_REFGEN_REQ_CONFIG2 0x14E0 +#define USB3_PCS_REFGEN_REQ_CONFIG3 0x14E4 +#define USB3_PCS_BIST_CTRL 0x14E8 +#define USB3_PCS_PRBS_POLY0 0x14EC +#define USB3_PCS_PRBS_POLY1 0x14F0 +#define USB3_PCS_FIXED_PAT0 0x14F4 +#define USB3_PCS_FIXED_PAT1 0x14F8 +#define USB3_PCS_FIXED_PAT2 0x14FC +#define USB3_PCS_FIXED_PAT3 0x1500 +#define USB3_PCS_FIXED_PAT4 0x1504 +#define USB3_PCS_FIXED_PAT5 0x1508 +#define USB3_PCS_FIXED_PAT6 0x150C +#define USB3_PCS_FIXED_PAT7 0x1510 +#define USB3_PCS_FIXED_PAT8 0x1514 +#define USB3_PCS_FIXED_PAT9 0x1518 +#define USB3_PCS_FIXED_PAT10 0x151C +#define USB3_PCS_FIXED_PAT11 0x1520 +#define USB3_PCS_FIXED_PAT12 0x1524 +#define USB3_PCS_FIXED_PAT13 0x1528 +#define USB3_PCS_FIXED_PAT14 0x152C +#define USB3_PCS_FIXED_PAT15 0x1530 +#define USB3_PCS_TXMGN_CONFIG 0x1534 +#define USB3_PCS_G12S1_TXMGN_V0 0x1538 +#define USB3_PCS_G12S1_TXMGN_V1 0x153C +#define USB3_PCS_G12S1_TXMGN_V2 0x1540 +#define USB3_PCS_G12S1_TXMGN_V3 0x1544 +#define USB3_PCS_G12S1_TXMGN_V4 0x1548 +#define USB3_PCS_G12S1_TXMGN_V0_RS 0x154C +#define USB3_PCS_G12S1_TXMGN_V1_RS 0x1550 +#define USB3_PCS_G12S1_TXMGN_V2_RS 0x1554 +#define USB3_PCS_G12S1_TXMGN_V3_RS 0x1558 +#define USB3_PCS_G12S1_TXMGN_V4_RS 0x155C +#define USB3_PCS_G3S2_TXMGN_MAIN 0x1560 +#define USB3_PCS_G3S2_TXMGN_MAIN_RS 0x1564 +#define USB3_PCS_G12S1_TXDEEMPH_M6DB 0x1568 +#define USB3_PCS_G12S1_TXDEEMPH_M3P5DB 0x156C +#define USB3_PCS_G3S2_PRE_GAIN 0x1570 +#define USB3_PCS_G3S2_POST_GAIN 0x1574 +#define USB3_PCS_G3S2_PRE_POST_OFFSET 0x1578 +#define USB3_PCS_G3S2_PRE_GAIN_RS 0x157C +#define USB3_PCS_G3S2_POST_GAIN_RS 0x1580 +#define USB3_PCS_G3S2_PRE_POST_OFFSET_RS 0x1584 +#define USB3_PCS_RX_SIGDET_LVL 0x1588 +#define USB3_PCS_RX_SIGDET_DTCT_CNTRL 0x158C +#define USB3_PCS_RCVR_DTCT_DLY_P1U2_L 0x1590 +#define USB3_PCS_RCVR_DTCT_DLY_P1U2_H 0x1594 +#define USB3_PCS_RATE_SLEW_CNTRL1 0x1598 +#define USB3_PCS_RATE_SLEW_CNTRL2 0x159C +#define USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x15A0 +#define USB3_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x15A4 +#define USB3_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x15A8 +#define USB3_PCS_TSYNC_RSYNC_TIME 0x15AC +#define USB3_PCS_RX_CONFIG 0x15B0 +#define USB3_PCS_TSYNC_DLY_TIME 0x15B4 +#define USB3_PCS_ELECIDLE_DLY_SEL 0x15B8 +#define USB3_PCS_CMN_ACK_OUT_SEL 0x15BC +#define USB3_PCS_ALIGN_DETECT_CONFIG1 0x15C0 +#define USB3_PCS_ALIGN_DETECT_CONFIG2 0x15C4 +#define USB3_PCS_ALIGN_DETECT_CONFIG3 0x15C8 +#define USB3_PCS_ALIGN_DETECT_CONFIG4 0x15CC +#define USB3_PCS_PCS_TX_RX_CONFIG 0x15D0 +#define USB3_PCS_RX_IDLE_DTCT_CNTRL 0x15D4 +#define USB3_PCS_RX_DCC_CAL_CONFIG 0x15D8 +#define USB3_PCS_EQ_CONFIG1 0x15DC +#define USB3_PCS_EQ_CONFIG2 0x15E0 +#define USB3_PCS_EQ_CONFIG3 0x15E4 +#define USB3_PCS_EQ_CONFIG4 0x15E8 +#define USB3_PCS_EQ_CONFIG5 0x15EC + +/* Module: USB3_PCS_USB3_USB3_PCS_USB3_USB3_PCS_USB3 */ +#define USB3_PCS_USB3_POWER_STATE_CONFIG1 0x1700 +#define USB3_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x1704 +#define USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x1708 +#define USB3_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x170C +#define USB3_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x1710 +#define USB3_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x1714 +#define USB3_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x1718 +#define USB3_PCS_USB3_LFPS_TX_ECSTART 0x171C +#define USB3_PCS_USB3_LFPS_PER_TIMER_VAL 0x1720 +#define USB3_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x1724 +#define USB3_PCS_USB3_LFPS_CONFIG1 0x1728 +#define USB3_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x172C +#define USB3_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x1730 +#define USB3_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x1734 +#define USB3_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x1738 +#define USB3_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x173C +#define USB3_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x1740 +#define USB3_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x1744 +#define USB3_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x1748 +#define USB3_PCS_USB3_ARCVR_DTCT_CM_DLY 0x174C +#define USB3_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x1750 +#define USB3_PCS_USB3_ALFPS_DEGLITCH_VAL 0x1754 +#define USB3_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x1758 +#define USB3_PCS_USB3_TEST_CONTROL 0x175C +#define USB3_PCS_USB3_RXTERMINATION_DLY_SEL 0x1760 + +/* Module: DP_QSERDES_PLL_DP_QSERDES_PLL_USB4_USB3_DP_QMP_PLL */ +#define DP_QSERDES_PLL_ATB_SEL1 0x2000 +#define DP_QSERDES_PLL_ATB_SEL2 0x2004 +#define DP_QSERDES_PLL_FREQ_UPDATE 0x2008 +#define DP_QSERDES_PLL_BG_TIMER 0x200C +#define DP_QSERDES_PLL_SSC_EN_CENTER 0x2010 +#define DP_QSERDES_PLL_SSC_ADJ_PER1 0x2014 +#define DP_QSERDES_PLL_SSC_ADJ_PER2 0x2018 +#define DP_QSERDES_PLL_SSC_PER1 0x201C +#define DP_QSERDES_PLL_SSC_PER2 0x2020 +#define DP_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x2024 +#define DP_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x2028 +#define DP_QSERDES_PLL_SSC_STEP_SIZE3_MODE0 0x202C +#define DP_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x2030 +#define DP_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x2034 +#define DP_QSERDES_PLL_SSC_STEP_SIZE3_MODE1 0x2038 +#define DP_QSERDES_PLL_POST_DIV 0x203C +#define DP_QSERDES_PLL_POST_DIV_MUX 0x2040 +#define DP_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x2044 +#define DP_QSERDES_PLL_CLK_ENABLE1 0x2048 +#define DP_QSERDES_PLL_SYS_CLK_CTRL 0x204C +#define DP_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x2050 +#define DP_QSERDES_PLL_PLL_EN 0x2054 +#define DP_QSERDES_PLL_PLL_IVCO 0x2058 +#define DP_QSERDES_PLL_CMN_IETRIM 0x205C +#define DP_QSERDES_PLL_CMN_IPTRIM 0x2060 +#define DP_QSERDES_PLL_EP_CLOCK_DETECT_CTRL 0x2064 +#define DP_QSERDES_PLL_SYSCLK_DET_COMP_STATUS 0x2068 +#define DP_QSERDES_PLL_CLK_EP_DIV_MODE0 0x206C +#define DP_QSERDES_PLL_CLK_EP_DIV_MODE1 0x2070 +#define DP_QSERDES_PLL_CP_CTRL_MODE0 0x2074 +#define DP_QSERDES_PLL_CP_CTRL_MODE1 0x2078 +#define DP_QSERDES_PLL_PLL_RCTRL_MODE0 0x207C +#define DP_QSERDES_PLL_PLL_RCTRL_MODE1 0x2080 +#define DP_QSERDES_PLL_PLL_CCTRL_MODE0 0x2084 +#define DP_QSERDES_PLL_PLL_CCTRL_MODE1 0x2088 +#define DP_QSERDES_PLL_PLL_CNTRL 0x208C +#define DP_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x2090 +#define DP_QSERDES_PLL_SYSCLK_EN_SEL 0x2094 +#define DP_QSERDES_PLL_CML_SYSCLK_SEL 0x2098 +#define DP_QSERDES_PLL_RESETSM_CNTRL 0x209C +#define DP_QSERDES_PLL_RESETSM_CNTRL2 0x20A0 +#define DP_QSERDES_PLL_LOCK_CMP_EN 0x20A4 +#define DP_QSERDES_PLL_LOCK_CMP_CFG 0x20A8 +#define DP_QSERDES_PLL_LOCK_CMP1_MODE0 0x20AC +#define DP_QSERDES_PLL_LOCK_CMP2_MODE0 0x20B0 +#define DP_QSERDES_PLL_LOCK_CMP1_MODE1 0x20B4 +#define DP_QSERDES_PLL_LOCK_CMP2_MODE1 0x20B8 +#define DP_QSERDES_PLL_DEC_START_MODE0 0x20BC +#define DP_QSERDES_PLL_DEC_START_MSB_MODE0 0x20C0 +#define DP_QSERDES_PLL_DEC_START_MODE1 0x20C4 +#define DP_QSERDES_PLL_DEC_START_MSB_MODE1 0x20C8 +#define DP_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x20CC +#define DP_QSERDES_PLL_DIV_FRAC_START2_MODE0 0x20D0 +#define DP_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x20D4 +#define DP_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x20D8 +#define DP_QSERDES_PLL_DIV_FRAC_START2_MODE1 0x20DC +#define DP_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x20E0 +#define DP_QSERDES_PLL_INTEGLOOP_INITVAL 0x20E4 +#define DP_QSERDES_PLL_INTEGLOOP_EN 0x20E8 +#define DP_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x20EC +#define DP_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x20F0 +#define DP_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x20F4 +#define DP_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x20F8 +#define DP_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0 0x20FC +#define DP_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1 0x2100 +#define DP_QSERDES_PLL_VCOCAL_DEADMAN_CTRL 0x2104 +#define DP_QSERDES_PLL_VCO_TUNE_CTRL 0x2108 +#define DP_QSERDES_PLL_VCO_TUNE_MAP 0x210C +#define DP_QSERDES_PLL_VCO_TUNE1_MODE0 0x2110 +#define DP_QSERDES_PLL_VCO_TUNE2_MODE0 0x2114 +#define DP_QSERDES_PLL_VCO_TUNE1_MODE1 0x2118 +#define DP_QSERDES_PLL_VCO_TUNE2_MODE1 0x211C +#define DP_QSERDES_PLL_VCO_TUNE_INITVAL1 0x2120 +#define DP_QSERDES_PLL_VCO_TUNE_INITVAL2 0x2124 +#define DP_QSERDES_PLL_VCO_TUNE_MINVAL1 0x2128 +#define DP_QSERDES_PLL_VCO_TUNE_MINVAL2 0x212C +#define DP_QSERDES_PLL_VCO_TUNE_MAXVAL1 0x2130 +#define DP_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x2134 +#define DP_QSERDES_PLL_VCO_TUNE_TIMER1 0x2138 +#define DP_QSERDES_PLL_VCO_TUNE_TIMER2 0x213C +#define DP_QSERDES_PLL_CMN_STATUS 0x2140 +#define DP_QSERDES_PLL_RESET_SM_STATUS 0x2144 +#define DP_QSERDES_PLL_RESTRIM_CODE_STATUS 0x2148 +#define DP_QSERDES_PLL_PLLCAL_CODE1_STATUS 0x214C +#define DP_QSERDES_PLL_PLLCAL_CODE2_STATUS 0x2150 +#define DP_QSERDES_PLL_CLK_SELECT 0x2154 +#define DP_QSERDES_PLL_HSCLK_SEL 0x2158 +#define DP_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x215C +#define DP_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS 0x2160 +#define DP_QSERDES_PLL_PLL_ANALOG 0x2164 +#define DP_QSERDES_PLL_CORECLK_DIV_MODE0 0x2168 +#define DP_QSERDES_PLL_CORECLK_DIV_MODE1 0x216C +#define DP_QSERDES_PLL_SW_RESET 0x2170 +#define DP_QSERDES_PLL_CORE_CLK_EN 0x2174 +#define DP_QSERDES_PLL_C_READY_STATUS 0x2178 +#define DP_QSERDES_PLL_CMN_CONFIG 0x217C +#define DP_QSERDES_PLL_CMN_RATE_OVERRIDE 0x2180 +#define DP_QSERDES_PLL_SVS_MODE_CLK_SEL 0x2184 +#define DP_QSERDES_PLL_DEBUG_BUS0 0x2188 +#define DP_QSERDES_PLL_DEBUG_BUS1 0x218C +#define DP_QSERDES_PLL_DEBUG_BUS2 0x2190 +#define DP_QSERDES_PLL_DEBUG_BUS3 0x2194 +#define DP_QSERDES_PLL_DEBUG_BUS_SEL 0x2198 +#define DP_QSERDES_PLL_CMN_MISC1 0x219C +#define DP_QSERDES_PLL_CMN_MODE 0x21A0 +#define DP_QSERDES_PLL_CMN_MODE_CONTD 0x21A4 +#define DP_QSERDES_PLL_VCO_DC_LEVEL_CTRL 0x21A8 +#define DP_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x21AC +#define DP_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x21B0 +#define DP_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x21B4 +#define DP_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x21B8 +#define DP_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL 0x21BC +#define DP_QSERDES_PLL_RESERVED_1 0x21C0 +#define DP_QSERDES_PLL_MODE_OPERATION_STATUS 0x21C4 + +/* Module: DP_DP_DP_PHY */ +#define DP_DP_PHY_REVISION_ID0 0x2200 +#define DP_DP_PHY_REVISION_ID1 0x2204 +#define DP_DP_PHY_REVISION_ID2 0x2208 +#define DP_DP_PHY_REVISION_ID3 0x220C +#define DP_DP_PHY_CFG 0x2210 +#define DP_DP_PHY_CFG_1 0x2214 +#define DP_DP_PHY_PD_CTL 0x2218 +#define DP_DP_PHY_MODE 0x221C +#define DP_DP_PHY_AUX_CFG0 0x2220 +#define DP_DP_PHY_AUX_CFG1 0x2224 +#define DP_DP_PHY_AUX_CFG2 0x2228 +#define DP_DP_PHY_AUX_CFG3 0x222C +#define DP_DP_PHY_AUX_CFG4 0x2230 +#define DP_DP_PHY_AUX_CFG5 0x2234 +#define DP_DP_PHY_AUX_CFG6 0x2238 +#define DP_DP_PHY_AUX_CFG7 0x223C +#define DP_DP_PHY_AUX_CFG8 0x2240 +#define DP_DP_PHY_AUX_CFG9 0x2244 +#define DP_DP_PHY_AUX_CFG10 0x2248 +#define DP_DP_PHY_AUX_CFG11 0x224C +#define DP_DP_PHY_AUX_CFG12 0x2250 +#define DP_DP_PHY_AUX_INTERRUPT_MASK 0x2254 +#define DP_DP_PHY_AUX_INTERRUPT_CLEAR 0x2258 +#define DP_DP_PHY_AUX_BIST_CFG 0x225C +#define DP_DP_PHY_AUX_BIST_PRBS_SEED 0x2260 +#define DP_DP_PHY_AUX_BIST_PRBS_POLY 0x2264 +#define DP_DP_PHY_AUX_TX_PROG_PAT_16B_LSB 0x2268 +#define DP_DP_PHY_AUX_TX_PROG_PAT_16B_MSB 0x226C +#define DP_DP_PHY_VCO_DIV 0x2270 +#define DP_DP_PHY_TSYNC_OVRD 0x2274 +#define DP_DP_PHY_TX0_TX1_LANE_CTL 0x2278 +#define DP_DP_PHY_TX0_TX1_BIST_CFG0 0x227C +#define DP_DP_PHY_TX0_TX1_BIST_CFG1 0x2280 +#define DP_DP_PHY_TX0_TX1_BIST_CFG2 0x2284 +#define DP_DP_PHY_TX0_TX1_BIST_CFG3 0x2288 +#define DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x228C +#define DP_DP_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x2290 +#define DP_DP_PHY_TX0_TX1_BIST_PATTERN0 0x2294 +#define DP_DP_PHY_TX0_TX1_BIST_PATTERN1 0x2298 +#define DP_DP_PHY_TX2_TX3_LANE_CTL 0x229C +#define DP_DP_PHY_TX2_TX3_BIST_CFG0 0x22A0 +#define DP_DP_PHY_TX2_TX3_BIST_CFG1 0x22A4 +#define DP_DP_PHY_TX2_TX3_BIST_CFG2 0x22A8 +#define DP_DP_PHY_TX2_TX3_BIST_CFG3 0x22AC +#define DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x22B0 +#define DP_DP_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x22B4 +#define DP_DP_PHY_TX2_TX3_BIST_PATTERN0 0x22B8 +#define DP_DP_PHY_TX2_TX3_BIST_PATTERN1 0x22BC +#define DP_DP_PHY_MISR_CTRL 0x22C0 +#define DP_DP_PHY_DEBUG_BUS_SEL 0x22C4 +#define DP_DP_PHY_SPARE0 0x22C8 +#define DP_DP_PHY_SPARE1 0x22CC +#define DP_DP_PHY_SPARE2 0x22D0 +#define DP_DP_PHY_SPARE3 0x22D4 +#define DP_DP_PHY_AUX_INTERRUPT_STATUS 0x22D8 +#define DP_DP_PHY_STATUS 0x22DC +#define DP_DP_PHY_AUX_BIST_STATUS0 0x22E0 +#define DP_DP_PHY_AUX_BIST_STATUS1 0x22E4 +#define DP_DP_PHY_AUX_BIST_STATUS2 0x22E8 +#define DP_DP_PHY_TX0_TX1_BIST_STATUS0 0x22EC +#define DP_DP_PHY_TX0_TX1_BIST_STATUS1 0x22F0 +#define DP_DP_PHY_TX0_TX1_BIST_STATUS2 0x22F4 +#define DP_DP_PHY_TX2_TX3_BIST_STATUS0 0x22F8 +#define DP_DP_PHY_TX2_TX3_BIST_STATUS1 0x22FC +#define DP_DP_PHY_TX2_TX3_BIST_STATUS2 0x2300 +#define DP_DP_PHY_MISR_STATUS 0x2304 +#define DP_DP_PHY_TX0_MISR_STATUS000 0x2308 +#define DP_DP_PHY_TX0_MISR_STATUS001 0x230C +#define DP_DP_PHY_TX0_MISR_STATUS010 0x2310 +#define DP_DP_PHY_TX0_MISR_STATUS011 0x2314 +#define DP_DP_PHY_TX0_MISR_STATUS100 0x2318 +#define DP_DP_PHY_TX0_MISR_STATUS101 0x231C +#define DP_DP_PHY_TX0_MISR_STATUS110 0x2320 +#define DP_DP_PHY_TX0_MISR_STATUS111 0x2324 +#define DP_DP_PHY_TX1_MISR_STATUS000 0x2328 +#define DP_DP_PHY_TX1_MISR_STATUS001 0x232C +#define DP_DP_PHY_TX1_MISR_STATUS010 0x2330 +#define DP_DP_PHY_TX1_MISR_STATUS011 0x2334 +#define DP_DP_PHY_TX1_MISR_STATUS100 0x2338 +#define DP_DP_PHY_TX1_MISR_STATUS101 0x233C +#define DP_DP_PHY_TX1_MISR_STATUS110 0x2340 +#define DP_DP_PHY_TX1_MISR_STATUS111 0x2344 +#define DP_DP_PHY_TX2_MISR_STATUS000 0x2348 +#define DP_DP_PHY_TX2_MISR_STATUS001 0x234C +#define DP_DP_PHY_TX2_MISR_STATUS010 0x2350 +#define DP_DP_PHY_TX2_MISR_STATUS011 0x2354 +#define DP_DP_PHY_TX2_MISR_STATUS100 0x2358 +#define DP_DP_PHY_TX2_MISR_STATUS101 0x235C +#define DP_DP_PHY_TX2_MISR_STATUS110 0x2360 +#define DP_DP_PHY_TX2_MISR_STATUS111 0x2364 +#define DP_DP_PHY_TX3_MISR_STATUS000 0x2368 +#define DP_DP_PHY_TX3_MISR_STATUS001 0x236C +#define DP_DP_PHY_TX3_MISR_STATUS010 0x2370 +#define DP_DP_PHY_TX3_MISR_STATUS011 0x2374 +#define DP_DP_PHY_TX3_MISR_STATUS100 0x2378 +#define DP_DP_PHY_TX3_MISR_STATUS101 0x237C +#define DP_DP_PHY_TX3_MISR_STATUS110 0x2380 +#define DP_DP_PHY_TX3_MISR_STATUS111 0x2384 +#define DP_DP_PHY_DEBUG_BUS0 0x2388 +#define DP_DP_PHY_DEBUG_BUS1 0x238C +#define DP_DP_PHY_DEBUG_BUS2 0x2390 +#define DP_DP_PHY_DEBUG_BUS3 0x2394 + +/* Module: USB4_QSERDES_PLL_USB4_QSERDES_PLL_USB4_USB3_DP_QMP_PLL_20G */ +#define USB4_QSERDES_PLL_ATB_SEL1 0x3000 +#define USB4_QSERDES_PLL_ATB_SEL2 0x3004 +#define USB4_QSERDES_PLL_FREQ_UPDATE 0x3008 +#define USB4_QSERDES_PLL_BG_TIMER 0x300C +#define USB4_QSERDES_PLL_SSC_EN_CENTER 0x3010 +#define USB4_QSERDES_PLL_SSC_ADJ_PER1 0x3014 +#define USB4_QSERDES_PLL_SSC_ADJ_PER2 0x3018 +#define USB4_QSERDES_PLL_SSC_PER1 0x301C +#define USB4_QSERDES_PLL_SSC_PER2 0x3020 +#define USB4_QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x3024 +#define USB4_QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x3028 +#define USB4_QSERDES_PLL_SSC_STEP_SIZE3_MODE0 0x302C +#define USB4_QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x3030 +#define USB4_QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x3034 +#define USB4_QSERDES_PLL_SSC_STEP_SIZE3_MODE1 0x3038 +#define USB4_QSERDES_PLL_POST_DIV 0x303C +#define USB4_QSERDES_PLL_POST_DIV_MUX 0x3040 +#define USB4_QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x3044 +#define USB4_QSERDES_PLL_CLK_ENABLE1 0x3048 +#define USB4_QSERDES_PLL_SYS_CLK_CTRL 0x304C +#define USB4_QSERDES_PLL_SYSCLK_BUF_ENABLE 0x3050 +#define USB4_QSERDES_PLL_PLL_EN 0x3054 +#define USB4_QSERDES_PLL_PLL_IVCO 0x3058 +#define USB4_QSERDES_PLL_CMN_IETRIM 0x305C +#define USB4_QSERDES_PLL_CMN_IPTRIM 0x3060 +#define USB4_QSERDES_PLL_EP_CLOCK_DETECT_CTRL 0x3064 +#define USB4_QSERDES_PLL_SYSCLK_DET_COMP_STATUS 0x3068 +#define USB4_QSERDES_PLL_CLK_EP_DIV_MODE0 0x306C +#define USB4_QSERDES_PLL_CLK_EP_DIV_MODE1 0x3070 +#define USB4_QSERDES_PLL_CP_CTRL_MODE0 0x3074 +#define USB4_QSERDES_PLL_CP_CTRL_MODE1 0x3078 +#define USB4_QSERDES_PLL_PLL_RCTRL_MODE0 0x307C +#define USB4_QSERDES_PLL_PLL_RCTRL_MODE1 0x3080 +#define USB4_QSERDES_PLL_PLL_CCTRL_MODE0 0x3084 +#define USB4_QSERDES_PLL_PLL_CCTRL_MODE1 0x3088 +#define USB4_QSERDES_PLL_PLL_CNTRL 0x308C +#define USB4_QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x3090 +#define USB4_QSERDES_PLL_SYSCLK_EN_SEL 0x3094 +#define USB4_QSERDES_PLL_CML_SYSCLK_SEL 0x3098 +#define USB4_QSERDES_PLL_RESETSM_CNTRL 0x309C +#define USB4_QSERDES_PLL_RESETSM_CNTRL2 0x30A0 +#define USB4_QSERDES_PLL_LOCK_CMP_EN 0x30A4 +#define USB4_QSERDES_PLL_LOCK_CMP_CFG 0x30A8 +#define USB4_QSERDES_PLL_LOCK_CMP1_MODE0 0x30AC +#define USB4_QSERDES_PLL_LOCK_CMP2_MODE0 0x30B0 +#define USB4_QSERDES_PLL_LOCK_CMP1_MODE1 0x30B4 +#define USB4_QSERDES_PLL_LOCK_CMP2_MODE1 0x30B8 +#define USB4_QSERDES_PLL_DEC_START_MODE0 0x30BC +#define USB4_QSERDES_PLL_DEC_START_MSB_MODE0 0x30C0 +#define USB4_QSERDES_PLL_DEC_START_MODE1 0x30C4 +#define USB4_QSERDES_PLL_DEC_START_MSB_MODE1 0x30C8 +#define USB4_QSERDES_PLL_DIV_FRAC_START1_MODE0 0x30CC +#define USB4_QSERDES_PLL_DIV_FRAC_START2_MODE0 0x30D0 +#define USB4_QSERDES_PLL_DIV_FRAC_START3_MODE0 0x30D4 +#define USB4_QSERDES_PLL_DIV_FRAC_START1_MODE1 0x30D8 +#define USB4_QSERDES_PLL_DIV_FRAC_START2_MODE1 0x30DC +#define USB4_QSERDES_PLL_DIV_FRAC_START3_MODE1 0x30E0 +#define USB4_QSERDES_PLL_INTEGLOOP_INITVAL 0x30E4 +#define USB4_QSERDES_PLL_INTEGLOOP_EN 0x30E8 +#define USB4_QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x30EC +#define USB4_QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x30F0 +#define USB4_QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x30F4 +#define USB4_QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x30F8 +#define USB4_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN0 0x30FC +#define USB4_QSERDES_PLL_INTEGLOOP_P_PATH_GAIN1 0x3100 +#define USB4_QSERDES_PLL_VCOCAL_DEADMAN_CTRL 0x3104 +#define USB4_QSERDES_PLL_VCO_TUNE_CTRL 0x3108 +#define USB4_QSERDES_PLL_VCO_TUNE_MAP 0x310C +#define USB4_QSERDES_PLL_VCO_TUNE1_MODE0 0x3110 +#define USB4_QSERDES_PLL_VCO_TUNE2_MODE0 0x3114 +#define USB4_QSERDES_PLL_VCO_TUNE1_MODE1 0x3118 +#define USB4_QSERDES_PLL_VCO_TUNE2_MODE1 0x311C +#define USB4_QSERDES_PLL_VCO_TUNE_INITVAL1 0x3120 +#define USB4_QSERDES_PLL_VCO_TUNE_INITVAL2 0x3124 +#define USB4_QSERDES_PLL_VCO_TUNE_MINVAL1 0x3128 +#define USB4_QSERDES_PLL_VCO_TUNE_MINVAL2 0x312C +#define USB4_QSERDES_PLL_VCO_TUNE_MAXVAL1 0x3130 +#define USB4_QSERDES_PLL_VCO_TUNE_MAXVAL2 0x3134 +#define USB4_QSERDES_PLL_VCO_TUNE_TIMER1 0x3138 +#define USB4_QSERDES_PLL_VCO_TUNE_TIMER2 0x313C +#define USB4_QSERDES_PLL_CMN_STATUS 0x3140 +#define USB4_QSERDES_PLL_RESET_SM_STATUS 0x3144 +#define USB4_QSERDES_PLL_RESTRIM_CODE_STATUS 0x3148 +#define USB4_QSERDES_PLL_PLLCAL_CODE1_STATUS 0x314C +#define USB4_QSERDES_PLL_PLLCAL_CODE2_STATUS 0x3150 +#define USB4_QSERDES_PLL_CLK_SELECT 0x3154 +#define USB4_QSERDES_PLL_HSCLK_SEL 0x3158 +#define USB4_QSERDES_PLL_HSCLK_HS_SWITCH_SEL 0x315C +#define USB4_QSERDES_PLL_INTEGLOOP_BINCODE_STATUS 0x3160 +#define USB4_QSERDES_PLL_PLL_ANALOG 0x3164 +#define USB4_QSERDES_PLL_CORECLK_DIV_MODE0 0x3168 +#define USB4_QSERDES_PLL_CORECLK_DIV_MODE1 0x316C +#define USB4_QSERDES_PLL_SW_RESET 0x3170 +#define USB4_QSERDES_PLL_CORE_CLK_EN 0x3174 +#define USB4_QSERDES_PLL_C_READY_STATUS 0x3178 +#define USB4_QSERDES_PLL_CMN_CONFIG 0x317C +#define USB4_QSERDES_PLL_CMN_RATE_OVERRIDE 0x3180 +#define USB4_QSERDES_PLL_SVS_MODE_CLK_SEL 0x3184 +#define USB4_QSERDES_PLL_DEBUG_BUS0 0x3188 +#define USB4_QSERDES_PLL_DEBUG_BUS1 0x318C +#define USB4_QSERDES_PLL_DEBUG_BUS2 0x3190 +#define USB4_QSERDES_PLL_DEBUG_BUS3 0x3194 +#define USB4_QSERDES_PLL_DEBUG_BUS_SEL 0x3198 +#define USB4_QSERDES_PLL_CMN_MISC1 0x319C +#define USB4_QSERDES_PLL_CMN_MODE 0x31A0 +#define USB4_QSERDES_PLL_CMN_MODE_CONTD 0x31A4 +#define USB4_QSERDES_PLL_VCO_DC_LEVEL_CTRL 0x31A8 +#define USB4_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE0 0x31AC +#define USB4_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE0 0x31B0 +#define USB4_QSERDES_PLL_BIN_VCOCAL_CMP_CODE1_MODE1 0x31B4 +#define USB4_QSERDES_PLL_BIN_VCOCAL_CMP_CODE2_MODE1 0x31B8 +#define USB4_QSERDES_PLL_BIN_VCOCAL_HSCLK_SEL 0x31BC +#define USB4_QSERDES_PLL_ADDITIONAL_CTRL_1 0x31C0 +#define USB4_QSERDES_PLL_MODE_OPERATION_STATUS 0x31C4 +#define USB4_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_1 0x31C8 +#define USB4_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_2 0x31CC +#define USB4_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_3 0x31D0 +#define USB4_QSERDES_PLL_AUTO_GAIN_ADJ_CTRL_4 0x31D4 +#define USB4_QSERDES_PLL_ADDITIONAL_MISC 0x31D8 +#define USB4_QSERDES_PLL_ADDITIONAL_MISC_2 0x31DC +#define USB4_QSERDES_PLL_ADDITIONAL_MISC_3 0x31E0 + +/* Module: USB4_PCS_L0_USB4_PCS_L0_USB4_PCS_LANE */ +#define USB4_PCS_L0_PCS_STATUS1 0x3200 +#define USB4_PCS_L0_PCS_STATUS2 0x3204 +#define USB4_PCS_L0_PCS_STATUS3 0x3208 +#define USB4_PCS_L0_BIST_CHK_ERR_CNT_L_STATUS 0x320C +#define USB4_PCS_L0_BIST_CHK_ERR_CNT_H_STATUS 0x3210 +#define USB4_PCS_L0_BIST_CHK_STATUS 0x3214 +#define USB4_PCS_L0_INSIG_SW_CTRL1 0x3218 +#define USB4_PCS_L0_INSIG_SW_CTRL2 0x321C +#define USB4_PCS_L0_INSIG_MX_CTRL1 0x3220 +#define USB4_PCS_L0_INSIG_MX_CTRL2 0x3224 +#define USB4_PCS_L0_OUTSIG_SW_CTRL1 0x3228 +#define USB4_PCS_L0_OUTSIG_SW_CTRL2 0x322C +#define USB4_PCS_L0_OUTSIG_MX_CTRL1 0x3230 +#define USB4_PCS_L0_OUTSIG_MX_CTRL2 0x3234 +#define USB4_PCS_L0_PRESET_OVERRIDE_CONFIG 0x3238 +#define USB4_PCS_L0_TEST_CONTROL1 0x323C +#define USB4_PCS_L0_TEST_CONTROL2 0x3240 +#define USB4_PCS_L0_TEST_CONTROL3 0x3244 +#define USB4_PCS_L0_BIST_CTRL 0x3248 +#define USB4_PCS_L0_PRBS_SEED0 0x324C +#define USB4_PCS_L0_PRBS_SEED1 0x3250 +#define USB4_PCS_L0_LANE_OFF_CONFIG 0x3254 +#define USB4_PCS_L0_RXEQ_STATUS1 0x3258 +#define USB4_PCS_L0_RXEQ_STATUS2 0x325C +#define USB4_PCS_L0_RX_MARGINING_CTRL1 0x3260 +#define USB4_PCS_L0_RX_MARGINING_STATUS1 0x3264 +#define USB4_PCS_L0_RX_MARGINING_STATUS2 0x3268 + +/* Module: USB4_PCS_L1_USB4_PCS_L1_USB4_PCS_LANE */ +#define USB4_PCS_L1_PCS_STATUS1 0x3300 +#define USB4_PCS_L1_PCS_STATUS2 0x3304 +#define USB4_PCS_L1_PCS_STATUS3 0x3308 +#define USB4_PCS_L1_BIST_CHK_ERR_CNT_L_STATUS 0x330C +#define USB4_PCS_L1_BIST_CHK_ERR_CNT_H_STATUS 0x3310 +#define USB4_PCS_L1_BIST_CHK_STATUS 0x3314 +#define USB4_PCS_L1_INSIG_SW_CTRL1 0x3318 +#define USB4_PCS_L1_INSIG_SW_CTRL2 0x331C +#define USB4_PCS_L1_INSIG_MX_CTRL1 0x3320 +#define USB4_PCS_L1_INSIG_MX_CTRL2 0x3324 +#define USB4_PCS_L1_OUTSIG_SW_CTRL1 0x3328 +#define USB4_PCS_L1_OUTSIG_SW_CTRL2 0x332C +#define USB4_PCS_L1_OUTSIG_MX_CTRL1 0x3330 +#define USB4_PCS_L1_OUTSIG_MX_CTRL2 0x3334 +#define USB4_PCS_L1_PRESET_OVERRIDE_CONFIG 0x3338 +#define USB4_PCS_L1_TEST_CONTROL1 0x333C +#define USB4_PCS_L1_TEST_CONTROL2 0x3340 +#define USB4_PCS_L1_TEST_CONTROL3 0x3344 +#define USB4_PCS_L1_BIST_CTRL 0x3348 +#define USB4_PCS_L1_PRBS_SEED0 0x334C +#define USB4_PCS_L1_PRBS_SEED1 0x3350 +#define USB4_PCS_L1_LANE_OFF_CONFIG 0x3354 +#define USB4_PCS_L1_RXEQ_STATUS1 0x3358 +#define USB4_PCS_L1_RXEQ_STATUS2 0x335C +#define USB4_PCS_L1_RX_MARGINING_CTRL1 0x3360 +#define USB4_PCS_L1_RX_MARGINING_STATUS1 0x3364 +#define USB4_PCS_L1_RX_MARGINING_STATUS2 0x3368 + +/* Module: USB4_PCS_USB4_PCS_USB4_PCS */ +#define USB4_PCS_SW_RESET 0x3400 +#define USB4_PCS_REVISION_ID0 0x3404 +#define USB4_PCS_REVISION_ID1 0x3408 +#define USB4_PCS_REVISION_ID2 0x340C +#define USB4_PCS_REVISION_ID3 0x3410 +#define USB4_PCS_PCS_STATUS1 0x3414 +#define USB4_PCS_PCS_STATUS2 0x3418 +#define USB4_PCS_PCS_STATUS3 0x341C +#define USB4_PCS_PCS_STATUS4 0x3420 +#define USB4_PCS_PCS_STATUS5 0x3424 +#define USB4_PCS_PCS_STATUS6 0x3428 +#define USB4_PCS_PCS_STATUS7 0x342C +#define USB4_PCS_DEBUG_BUS_0_STATUS 0x3430 +#define USB4_PCS_DEBUG_BUS_1_STATUS 0x3434 +#define USB4_PCS_DEBUG_BUS_2_STATUS 0x3438 +#define USB4_PCS_DEBUG_BUS_3_STATUS 0x343C +#define USB4_PCS_POWER_DOWN_CONTROL 0x3440 +#define USB4_PCS_START_CONTROL 0x3444 +#define USB4_PCS_INSIG_SW_CTRL1 0x3448 +#define USB4_PCS_INSIG_SW_CTRL2 0x344C +#define USB4_PCS_INSIG_SW_CTRL3 0x3450 +#define USB4_PCS_INSIG_SW_CTRL4 0x3454 +#define USB4_PCS_INSIG_SW_CTRL5 0x3458 +#define USB4_PCS_INSIG_SW_CTRL6 0x345C +#define USB4_PCS_INSIG_SW_CTRL7 0x3460 +#define USB4_PCS_INSIG_SW_CTRL8 0x3464 +#define USB4_PCS_INSIG_MX_CTRL1 0x3468 +#define USB4_PCS_INSIG_MX_CTRL2 0x346C +#define USB4_PCS_INSIG_MX_CTRL3 0x3470 +#define USB4_PCS_INSIG_MX_CTRL4 0x3474 +#define USB4_PCS_INSIG_MX_CTRL5 0x3478 +#define USB4_PCS_INSIG_MX_CTRL8 0x347C +#define USB4_PCS_OUTSIG_SW_CTRL1 0x3480 +#define USB4_PCS_OUTSIG_MX_CTRL1 0x3484 +#define USB4_PCS_OUTSIG_SW_CTRL2 0x3488 +#define USB4_PCS_OUTSIG_MX_CTRL2 0x348C +#define USB4_PCS_POWER_STATE_CONFIG1 0x3490 +#define USB4_PCS_POWER_STATE_CONFIG2 0x3494 +#define USB4_PCS_POWER_STATE_CONFIG3 0x3498 +#define USB4_PCS_POWER_STATE_CONFIG4 0x349C +#define USB4_PCS_FLL_CNTRL1 0x34A0 +#define USB4_PCS_FLL_CNTRL2 0x34A4 +#define USB4_PCS_FLL_CNT_VAL_L 0x34A8 +#define USB4_PCS_FLL_CNT_VAL_H_TOL 0x34AC +#define USB4_PCS_FLL_MAN_CODE 0x34B0 +#define USB4_PCS_TEST_CONTROL1 0x34B4 +#define USB4_PCS_TEST_CONTROL2 0x34B8 +#define USB4_PCS_TEST_CONTROL3 0x34BC +#define USB4_PCS_TEST_CONTROL4 0x34C0 +#define USB4_PCS_TEST_CONTROL5 0x34C4 +#define USB4_PCS_TEST_CONTROL6 0x34C8 +#define USB4_PCS_TEST_CONTROL7 0x34CC +#define USB4_PCS_LOCK_DETECT_CONFIG1 0x34D0 +#define USB4_PCS_LOCK_DETECT_CONFIG2 0x34D4 +#define USB4_PCS_REFGEN_REQ_CONFIG1 0x34D8 +#define USB4_PCS_REFGEN_REQ_CONFIG2 0x34DC +#define USB4_PCS_REFGEN_REQ_CONFIG3 0x34E0 +#define USB4_PCS_BIST_CTRL 0x34E4 +#define USB4_PCS_BIST_CONFIG1 0x34E8 +#define USB4_PCS_BIST_CONFIG2 0x34EC +#define USB4_PCS_BIST_CONFIG3 0x34F0 +#define USB4_PCS_TXMGN_CONFIG 0x34F4 +#define USB4_PCS_G3_TXMGN_MAIN 0x34F8 +#define USB4_PCS_G3_TXMGN_MAIN_RS 0x34FC +#define USB4_PCS_G3_PRE_GAIN 0x3500 +#define USB4_PCS_G3_POST_GAIN 0x3504 +#define USB4_PCS_G3_PRE_POST_OFFSET 0x3508 +#define USB4_PCS_G3_PRE_GAIN_RS 0x350C +#define USB4_PCS_G3_POST_GAIN_RS 0x3510 +#define USB4_PCS_G3_PRE_POST_OFFSET_RS 0x3514 +#define USB4_PCS_G2_TXMGN_MAIN 0x3518 +#define USB4_PCS_G2_TXMGN_MAIN_RS 0x351C +#define USB4_PCS_G2_PRE_GAIN 0x3520 +#define USB4_PCS_G2_POST_GAIN 0x3524 +#define USB4_PCS_G2_PRE_POST_OFFSET 0x3528 +#define USB4_PCS_G2_PRE_GAIN_RS 0x352C +#define USB4_PCS_G2_POST_GAIN_RS 0x3530 +#define USB4_PCS_G2_PRE_POST_OFFSET_RS 0x3534 +#define USB4_PCS_TXCOEFF_CONFIG 0x3538 +#define USB4_PCS_PRESET_P0_P1_PRE 0x353C +#define USB4_PCS_PRESET_P2_P3_PRE 0x3540 +#define USB4_PCS_PRESET_P4_P5_PRE 0x3544 +#define USB4_PCS_PRESET_P6_P7_PRE 0x3548 +#define USB4_PCS_PRESET_P8_P9_PRE 0x354C +#define USB4_PCS_PRESET_P10_P11_PRE 0x3550 +#define USB4_PCS_PRESET_P12_P13_PRE 0x3554 +#define USB4_PCS_PRESET_P14_P15_PRE 0x3558 +#define USB4_PCS_PRESET_P0_P1_POST 0x355C +#define USB4_PCS_PRESET_P2_P3_POST 0x3560 +#define USB4_PCS_PRESET_P4_P5_POST 0x3564 +#define USB4_PCS_PRESET_P6_P7_POST 0x3568 +#define USB4_PCS_PRESET_P8_P9_POST 0x356C +#define USB4_PCS_PRESET_P10_P11_POST 0x3570 +#define USB4_PCS_PRESET_P12_P13_POST 0x3574 +#define USB4_PCS_PRESET_P14_P15_POST 0x3578 +#define USB4_PCS_RX_SIGDET_LVL 0x357C +#define USB4_PCS_RX_SIGDET_DTCT_CNTRL 0x3580 +#define USB4_PCS_RATE_SLEW_CNTRL 0x3584 +#define USB4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x3588 +#define USB4_PCS_C3_WAKEUP_DLY_TIME_AUXCLK_L 0x358C +#define USB4_PCS_C3_WAKEUP_DLY_TIME_AUXCLK_H 0x3590 +#define USB4_PCS_TSYNC_RSYNC_TIME 0x3594 +#define USB4_PCS_CDR_RESET_TIME 0x3598 +#define USB4_PCS_TSYNC_DLY_TIME 0x359C +#define USB4_PCS_ELECIDLE_DLY_SEL 0x35A0 +#define USB4_PCS_CMN_ACK_OUT_SEL 0x35A4 +#define USB4_PCS_PCS_TX_RX_CONFIG1 0x35A8 +#define USB4_PCS_PCS_TX_RX_CONFIG2 0x35AC +#define USB4_PCS_PCS_TX_RX_CONFIG3 0x35B0 +#define USB4_PCS_RX_DCC_CAL_CONFIG 0x35B4 +#define USB4_PCS_EQ_CONFIG1 0x35B8 +#define USB4_PCS_EQ_CONFIG2 0x35BC +#define USB4_PCS_G2_EQ_CONFIG1 0x35C0 +#define USB4_PCS_G2_EQ_CONFIG2 0x35C4 +#define USB4_PCS_G2_EQ_CONFIG3 0x35C8 +#define USB4_PCS_G2_EQ_CONFIG4 0x35CC +#define USB4_PCS_G2_EQ_CONFIG5 0x35D0 +#define USB4_PCS_G2_EQ_CONFIG6 0x35D4 +#define USB4_PCS_G3_EQ_CONFIG1 0x35D8 +#define USB4_PCS_G3_EQ_CONFIG2 0x35DC +#define USB4_PCS_G3_EQ_CONFIG3 0x35E0 +#define USB4_PCS_G3_EQ_CONFIG4 0x35E4 +#define USB4_PCS_G3_EQ_CONFIG5 0x35E8 +#define USB4_PCS_G3_EQ_CONFIG6 0x35EC +#define USB4_PCS_FOM_EQ_CONFIG1 0x35F0 +#define USB4_PCS_FOM_EQ_CONFIG2 0x35F4 +#define USB4_PCS_FOM_EQ_CONFIG3 0x35F8 +#define USB4_PCS_FOM_EQ_CONFIG4 0x35FC +#define USB4_PCS_LFPS_DET_HIGH_COUNT_VAL 0x3600 +#define USB4_PCS_LFPS_TX_ECSTART 0x3604 +#define USB4_PCS_LFPS_TX_END_CNT_C3_START 0x3608 +#define USB4_PCS_MBUS_CONFIG1 0x360C +#define USB4_PCS_MBUS_CTRL1 0x3610 +#define USB4_PCS_MBUS_CTRL2 0x3614 +#define USB4_PCS_MBUS_CTRL3 0x3618 +#define USB4_PCS_MBUS_CTRL4 0x361C +#define USB4_PCS_MBUS_STATUS1 0x3620 +#define USB4_PCS_RX_MARGINING_CONFIG1 0x3624 +#define USB4_PCS_RX_MARGINING_CONFIG2 0x3628 +#define USB4_PCS_RX_MARGINING_CONFIG3 0x362C +#define USB4_PCS_WAKEUP_CLK_CONFIG1 0x3630 +#define USB4_PCS_WAKEUP_CLK_CONFIG2 0x3634 +#define USB4_PCS_WAKEUP_CLK_STATUS 0x3638 +#define USB4_PCS_TX_LATENCY_MEAS_CONFIG1 0x363C +#define USB4_PCS_TX_LATENCY_MEAS_CONFIG2 0x3640 +#define USB4_PCS_TX_LATENCY_STATUS 0x3644 +#define USB4_PCS_SIGDET_CNTRL 0x3648 + +#endif /* _DT_BINDINGS_PHY_QCOM_5NM_QMP_COMBO_USB4_H */