diff --git a/Documentation/ABI/testing/configfs-usb-gadget-uac1 b/Documentation/ABI/testing/configfs-usb-gadget-uac1 index d4b8cf40a9e4..c4ba92f004c3 100644 --- a/Documentation/ABI/testing/configfs-usb-gadget-uac1 +++ b/Documentation/ABI/testing/configfs-usb-gadget-uac1 @@ -6,7 +6,7 @@ Description: ===================== ======================================= c_chmask capture channel mask - c_srate capture sampling rate + c_srate list of capture sampling rates (comma-separated) c_ssize capture sample size (bytes) c_mute_present capture mute control enable c_volume_present capture volume control enable @@ -17,7 +17,7 @@ Description: c_volume_res capture volume control resolution (in 1/256 dB) p_chmask playback channel mask - p_srate playback sampling rate + p_srate list of playback sampling rates (comma-separated) p_ssize playback sample size (bytes) p_mute_present playback mute control enable p_volume_present playback volume control enable @@ -29,4 +29,5 @@ Description: (in 1/256 dB) req_number the number of pre-allocated requests for both capture and playback + function_name name of the interface ===================== ======================================= diff --git a/Documentation/ABI/testing/configfs-usb-gadget-uac2 b/Documentation/ABI/testing/configfs-usb-gadget-uac2 index 7fb3dbe26857..3371c39f651d 100644 --- a/Documentation/ABI/testing/configfs-usb-gadget-uac2 +++ b/Documentation/ABI/testing/configfs-usb-gadget-uac2 @@ -6,8 +6,9 @@ Description: ===================== ======================================= c_chmask capture channel mask - c_srate capture sampling rate + c_srate list of capture sampling rates (comma-separated) c_ssize capture sample size (bytes) + c_hs_bint capture bInterval for HS/SS (1-4: fixed, 0: auto) c_sync capture synchronization type (async/adaptive) c_mute_present capture mute control enable @@ -20,8 +21,9 @@ Description: (in 1/256 dB) fb_max maximum extra bandwidth in async mode p_chmask playback channel mask - p_srate playback sampling rate + p_srate list of playback sampling rates (comma-separated) p_ssize playback sample size (bytes) + p_hs_bint playback bInterval for HS/SS (1-4: fixed, 0: auto) p_mute_present playback mute control enable p_volume_present playback volume control enable p_volume_min playback volume control min value @@ -32,4 +34,5 @@ Description: (in 1/256 dB) req_number the number of pre-allocated requests for both capture and playback + function_name name of the interface ===================== ======================================= diff --git a/Documentation/ABI/testing/sysfs-driver-eud b/Documentation/ABI/testing/sysfs-driver-eud new file mode 100644 index 000000000000..83f3872182a4 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-eud @@ -0,0 +1,9 @@ +What: /sys/bus/platform/drivers/eud/.../enable +Date: February 2022 +Contact: Souradeep Chowdhury +Description: + The Enable/Disable sysfs interface for Embedded + USB Debugger(EUD). This enables and disables the + EUD based on a 1 or a 0 value. By enabling EUD, + the user is able to activate the mini-usb hub of + EUD for debug and trace capabilities. diff --git a/Documentation/core-api/dma-attributes.rst b/Documentation/core-api/dma-attributes.rst index 17706dc91ec9..1887d92e8e92 100644 --- a/Documentation/core-api/dma-attributes.rst +++ b/Documentation/core-api/dma-attributes.rst @@ -130,11 +130,3 @@ accesses to DMA buffers in both privileged "supervisor" and unprivileged subsystem that the buffer is fully accessible at the elevated privilege level (and ideally inaccessible or at least read-only at the lesser-privileged levels). - -DMA_ATTR_OVERWRITE ------------------- - -This is a hint to the DMA-mapping subsystem that the device is expected to -overwrite the entire mapped size, thus the caller does not require any of the -previous buffer contents to be preserved. This allows bounce-buffering -implementations to optimise DMA_FROM_DEVICE transfers. diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml index 697102707703..328952d7acbb 100644 --- a/Documentation/devicetree/bindings/leds/common.yaml +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -185,9 +185,11 @@ examples: }; }; - led-controller@0 { + - | + #include + + led-controller { compatible = "maxim,max77693-led"; - reg = <0 0x100>; led { function = LED_FUNCTION_FLASH; @@ -199,6 +201,9 @@ examples: }; }; + - | + #include + i2c { #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml index a337bcd80c4a..7a86e7926dd2 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml @@ -28,7 +28,12 @@ properties: - const: fsl,imx7ulp-mu - const: fsl,imx8ulp-mu - const: fsl,imx8-mu-scu + - const: fsl,imx8-mu-seco + - const: fsl,imx93-mu-s4 - const: fsl,imx8ulp-mu-s4 + - items: + - const: fsl,imx93-mu + - const: fsl,imx8ulp-mu - items: - enum: - fsl,imx7s-mu @@ -51,7 +56,14 @@ properties: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: tx + - const: rx "#mbox-cells": description: | @@ -86,6 +98,27 @@ required: - interrupts - "#mbox-cells" +allOf: + - if: + properties: + compatible: + enum: + - fsl,imx93-mu-s4 + then: + properties: + interrupt-names: + minItems: 2 + interrupts: + minItems: 2 + + else: + properties: + interrupts: + maxItems: 1 + not: + required: + - interrupt-names + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml new file mode 100644 index 000000000000..fe454a1fba17 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek ADSP mailbox + +maintainers: + - Allen-KH Cheng + +description: | + The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC + to ommunicate with ADSP by passing messages through two mailbox channels. + The MTK ADSP mailbox IPC also provides the ability for one processor to + signal the other processor using interrupts. + +properties: + compatible: + items: + - const: mediatek,mt8195-adsp-mbox + + "#mbox-cells": + const: 0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - "#mbox-cells" + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + adsp_mailbox0:mailbox@10816000 { + compatible = "mediatek,mt8195-adsp-mbox"; + #mbox-cells = <0>; + reg = <0x10816000 0x1000>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 98fe37e8b17b..c2aeba63bd47 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -10,7 +10,8 @@ mailbox.txt for generic information about mailbox device-tree bindings. Required properties: - compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce", - "mediatek,mt8192-gce", "mediatek,mt8195-gce" or "mediatek,mt6779-gce". + "mediatek,mt8186-gce", "mediatek,mt8192-gce", "mediatek,mt8195-gce" or + "mediatek,mt6779-gce". - reg: Address range of the GCE unit - interrupts: The interrupt signal from the GCE block - clock: Clocks according to the common clock binding @@ -40,8 +41,9 @@ Optional properties for a client mutex node: defined in 'dt-bindings/gce/-gce.h'. Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h', -'dt-bindings/gce/mt8183-gce.h', 'dt-bindings/gce/mt8192-gce.h', -'dt-bindings/gce/mt8195-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. +'dt-bindings/gce/mt8183-gce.h', 'dt-bindings/gce/mt8186-gce.h' +'dt-bindings/gce/mt8192-gce.h', 'dt-bindings/gce/mt8195-gce.h' or +'dt-bindings/gce/mt6779-gce.h'. Such as sub-system ids, thread priority, event ids. Example: diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 01e9d9155c83..3b5ba7ecc19d 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -21,6 +21,7 @@ properties: - qcom,msm8916-apcs-kpss-global - qcom,msm8939-apcs-kpss-global - qcom,msm8953-apcs-kpss-global + - qcom,msm8976-apcs-kpss-global - qcom,msm8994-apcs-kpss-global - qcom,msm8996-apcs-hmss-global - qcom,msm8998-apcs-hmss-global diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index acd60c85b4cc..7c25c8d51116 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -75,6 +75,7 @@ additionalProperties: false examples: - | + #include apb { compatible = "simple-bus"; #address-cells = <1>; @@ -84,6 +85,8 @@ examples: syscon: scu@1e6e2000 { compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; pinctrl: pinctrl { compatible = "aspeed,ast2500-pinctrl"; @@ -104,6 +107,12 @@ examples: gfx: display@1e6e6000 { compatible = "aspeed,ast2500-gfx", "syscon"; reg = <0x1e6e6000 0x1000>; + reg-io-width = <4>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + interrupts = <0x19>; + syscon = <&syscon>; + memory-region = <&gfx_memory>; }; }; @@ -130,3 +139,10 @@ examples: }; }; }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt index 4eaae32821ae..e047a198db38 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.txt @@ -85,7 +85,7 @@ Optional Properties (for I2C pins): - function: String. Specifies the pin mux selection. Values must be one of: "alt1", "alt2", "alt3", "alt4" - bias-pull-up: Integer. Pull up strength in Ohm. There are 3 - pull-up resisitors (1.2k, 1.8k, 2.7k) available + pull-up resistors (1.2k, 1.8k, 2.7k) available in parallel for I2C pins, so the valid values are: 568, 720, 831, 1080, 1200, 1800, 2700 Ohm. - bias-disable: No arguments. Disable pin bias. diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml new file mode 100644 index 000000000000..175a992f15e1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM4908 pin controller + +maintainers: + - Rafał Miłecki + +description: + Binding for pin controller present on BCM4908 family SoCs. + +properties: + compatible: + const: brcm,bcm4908-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + function: + enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8, + led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16, + led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24, + led_25, led_26, led_27, led_28, led_29, led_30, led_31, + hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr, + usb1_pwr ] + + groups: + minItems: 1 + maxItems: 2 + items: + enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a, + led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a, + led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b, + led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b, + led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a, + led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a, + led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a, + led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a, + led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a, + led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp, + nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp, + usb1_pwr_grp ] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@ff800560 { + compatible = "brcm,bcm4908-pinctrl"; + reg = <0xff800560 0x10>; + + led_0-a-pins { + function = "led_0"; + groups = "led_0_grp_a"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml new file mode 100644 index 000000000000..66baa6082a4f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx93-pinctrl.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx93-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX93 IOMUX Controller + +maintainers: + - Peng Fan + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +allOf: + - $ref: "pinctrl.yaml#" + +properties: + compatible: + const: fsl,imx93-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can + be found in . The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart3: uart3grp { + fsl,pins = + <0x48 0x1f8 0x41c 0x1 0x0 0x49>, + <0x4c 0x1fc 0x418 0x1 0x0 0x49>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt index 0aff1f28495c..8146193bd8ac 100644 --- a/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt @@ -16,6 +16,7 @@ Required properties for the root node: "amlogic,meson-g12a-periphs-pinctrl" "amlogic,meson-g12a-aobus-pinctrl" "amlogic,meson-a1-periphs-pinctrl" + "amlogic,meson-s4-periphs-pinctrl" - reg: address and size of registers controlling irq functionality === GPIO sub-nodes === diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml index cb554084bdf1..0df4e114fdd6 100644 --- a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -145,7 +145,7 @@ examples: clocks = <&sys_clk>; pinctrl-0 = <&sgpio2_pins>; pinctrl-names = "default"; - reg = <0x1101059c 0x100>; + reg = <0x1101059c 0x118>; microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; bus-frequency = <25000000>; sgpio_in2: gpio@0 { diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 3bb76487669f..5d84fd299ccf 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -4,8 +4,8 @@ Microsemi Ocelot pin controller Device Tree Bindings Required properties: - compatible : Should be "mscc,ocelot-pinctrl", "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl", "mscc,serval-pinctrl" or - "microchip,lan966x-pinctrl" + "mscc,luton-pinctrl", "mscc,serval-pinctrl", + "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml new file mode 100644 index 000000000000..47a56b83a610 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 pin control and GPIO + +maintainers: + - Jonathan Neuschäfer + +properties: + compatible: + const: nuvoton,wpcm450-pinctrl + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + # There are three kinds of subnodes: + # 1. a GPIO controller node for each GPIO bank + # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2) + # 3. a pinconf node configures properties of a single pin + + "^gpio@[0-7]$": + type: object + + description: + Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18 + GPIOs. Some GPIOs support interrupts. + + properties: + reg: + minimum: 0 + maximum: 7 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 3 + description: + The interrupts associated with this GPIO bank + + required: + - reg + - gpio-controller + - '#gpio-cells' + + "^mux-": + $ref: pinmux-node.yaml# + + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo, + clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0, + fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11, + fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ] + function: + description: + The function that a group of pins is muxed to + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0, + dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc, + gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4, + fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1, + hg2, hg3, hg4, hg5, hg6, hg7, gpio ] + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + + "^cfg-": + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + items: + pattern: "^gpio1?[0-9]{1,2}$" + + input-debounce: true + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + mux-rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + pinmux_uid: mux-uid { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + pinctrl_uid: cfg-uid { + pins = "gpio14"; + input-debounce = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>; + + uid { + label = "UID"; + linux,code = <102>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml new file mode 100644 index 000000000000..8a2bb8608291 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8186.yaml @@ -0,0 +1,297 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8186 Pin Controller + +maintainers: + - Sean Wang + +description: | + The Mediatek's Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8186-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: | + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + reg: + description: | + Physical address base for gpio base registers. There are 8 different GPIO + physical address base in mt8186. + maxItems: 8 + + reg-names: + description: | + Gpio base register names. + items: + - const: iocfg0 + - const: iocfg_bm + - const: iocfg_bl + - const: iocfg_br + - const: iocfg_lm + - const: iocfg_rb + - const: iocfg_tl + - const: eint + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + mediatek,rsel-resistance-in-si-unit: + type: boolean + description: | + Identifying i2c pins pull up/down type which is RSEL. It can support + RSEL define or si unit value(ohm) to set different resistance. + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + '^pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = ; + } + }; + /* GPIO128 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = ; + } + }; + }; + $ref: "pinmux-node.yaml" + + properties: + pinmux: + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/-pinfunc.h + directly. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8186 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203] + description: mt8186 pull down RSEL type define value. + - enum: [75000, 5000] + description: mt8186 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8186. + For pull down type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" + define in mt8186. It can also support resistance value(ohm) + "75000" & "5000" in mt8186. + An example of using RSEL define: + pincontroller { + i2c0_pin { + pins { + pinmux = ; + bias-pull-down = ; + } + }; + }; + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel-resistance-in-si-unit; + } + pincontroller { + i2c0_pin { + pins { + pinmux = ; + bias-pull-down = <75000>; + } + }; + }; + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8186 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203] + description: mt8186 pull up RSEL type define value. + - enum: [1000, 5000, 10000, 75000] + description: mt8186 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8186. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" + define in mt8186. It can also support resistance value(ohm) + "1000" & "5000" & "10000" & "75000" in mt8186. + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel-resistance-in-si-unit; + } + pincontroller { + i2c0-pins { + pins { + pinmux = ; + bias-pull-up = <1000>; + } + }; + }; + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8186-pinctrl"; + reg = <0x10005000 0x1000>, + <0x10002000 0x0200>, + <0x10002200 0x0200>, + <0x10002400 0x0200>, + <0x10002600 0x0200>, + <0x10002A00 0x0200>, + <0x10002c00 0x0200>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 185>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + pio-pins { + pins { + pinmux = ; + output-low; + }; + }; + + spi0-pins { + pins-spi { + pinmux = , + , + ; + bias-disable; + }; + pins-spi-mi { + pinmux = ; + bias-pull-down; + }; + }; + + i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <7>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml index 328ea59c5466..c5b755514c46 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8195.yaml @@ -98,7 +98,41 @@ patternProperties: drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8195 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8195 pull down RSEL type define value. + - enum: [75000, 5000] + description: mt8195 pull down RSEL type si unit value(ohm). description: | For pull down type is normal, it don't need add RSEL & R1R0 define and resistance value. @@ -115,13 +149,6 @@ patternProperties: & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in mt8195. It can also support resistance value(ohm) "75000" & "5000" in mt8195. - oneOf: - - enum: [100, 101, 102, 103] - - description: mt8195 pull down PUPD/R0/R1 type define value. - - enum: [200, 201, 202, 203, 204, 205, 206, 207] - - description: mt8195 pull down RSEL type define value. - - enum: [75000, 5000] - - description: mt8195 pull down RSEL type si unit value(ohm). An example of using RSEL define: pincontroller { @@ -146,6 +173,14 @@ patternProperties: }; bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8195 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8195 pull up RSEL type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] + description: mt8195 pull up RSEL type si unit value(ohm). description: | For pull up type is normal, it don't need add RSEL & R1R0 define and resistance value. @@ -163,13 +198,6 @@ patternProperties: define in mt8195. It can also support resistance value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8195. - oneOf: - - enum: [100, 101, 102, 103] - - description: mt8195 pull up PUPD/R0/R1 type define value. - - enum: [200, 201, 202, 203, 204, 205, 206, 207] - - description: mt8195 pull up RSEL type define value. - - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] - - description: mt8195 pull up RSEL type si unit value(ohm). An example of using RSEL define: pincontroller { i2c0-pins { @@ -268,4 +296,13 @@ examples: bias-pull-down; }; }; + + i2c0-pins { + pins { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <7>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml index 64c0a41ca0c3..d4da558cde54 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -34,6 +34,8 @@ properties: gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': description: Specifying the pin number and flags, as defined in include/dt-bindings/gpio/gpio.h diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 9400b665a46f..fe2bcf0694d9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -36,6 +36,7 @@ properties: - qcom,pm8350-gpio - qcom,pm8350b-gpio - qcom,pm8350c-gpio + - qcom,pm8450-gpio - qcom,pm8916-gpio - qcom,pm8917-gpio - qcom,pm8921-gpio diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml index 35c846f59979..df79274d0ec3 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -21,6 +21,7 @@ properties: - qcom,pm8019-mpp - qcom,pm8038-mpp - qcom,pm8058-mpp + - qcom,pm8226-mpp - qcom,pm8821-mpp - qcom,pm8841-mpp - qcom,pm8916-mpp diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml new file mode 100644 index 000000000000..87a381c9a19d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC8280XP TLMM block + +maintainers: + - Bjorn Andersson + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SC8280XP platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sc8280xp-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sc8280xp-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sc8280xp-tlmm-state" + +'$defs': + qcom-sc8280xp-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, + cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, + ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd, + edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1, + emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0, + emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3, + emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, + gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c, + jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1, + mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5, + mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0, + mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, + mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, + mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0, + mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1, + mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq, + pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq, + phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk, + qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, + qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1, + sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig, + tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp, + usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac, + vsense_trigger ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@f100000 { + compatible = "qcom,sc8280xp-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 230>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio4"; + function = "qup14"; + bias-pull-up; + }; + + tx { + pins = "gpio5"; + function = "qup14"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index be8cb0ead62f..780f15bb5e40 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -73,7 +73,6 @@ $defs: properties: drive-strength: enum: [2, 4, 6, 8, 10, 12, 14, 16] - default: 2 description: Selects the drive strength for the specified pins, in mA. diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml index f0c52feb24d7..9de8b0c075e2 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml @@ -10,7 +10,7 @@ maintainers: - Sergio Paracuellos description: - The rt2880 pinmux can only set the muxing of pin groups. muxing indiviual pins + The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins is not supported. There is no pinconf support. properties: @@ -29,12 +29,13 @@ patternProperties: properties: groups: description: Name of the pin group to use for the functions. - enum: [i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, mdio, - pcie, sdhci] + enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, + uart1, uart2, uart3, wdt] function: description: The mux function to select - enum: [gpio, i2c, spi, uart1, uart2, uart3, rgmii1, rgmii2, - mdio, nand1, nand2, sdhci] + enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk, + pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, + spi, uart1, uart2, uart3, wdt refclk, wdt rst] required: - groups diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml index 8548e3639b75..2a57df75d832 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -44,6 +44,7 @@ properties: - renesas,pfc-r8a77990 # R-Car E3 - renesas,pfc-r8a77995 # R-Car D3 - renesas,pfc-r8a779a0 # R-Car V3U + - renesas,pfc-r8a779f0 # R-Car S4-8 - renesas,pfc-sh73a0 # SH-Mobile AG5 reg: diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index b749c82edebd..9ccf54870aa4 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -4,14 +4,14 @@ $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G2L combined Pin and GPIO controller +title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller maintainers: - Geert Uytterhoeven - Lad Prabhakar description: - The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO + The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function @@ -20,8 +20,15 @@ description: properties: compatible: - enum: - - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + oneOf: + - items: + - enum: + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + + - items: + - enum: + - renesas,r9a07g054-pinctrl # RZ/V2L + - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L reg: maxItems: 1 @@ -76,6 +83,7 @@ additionalProperties: output-impedance-ohms: enum: [ 33, 50, 66, 100 ] power-source: + description: I/O voltage in millivolt. enum: [ 1800, 2500, 3300 ] slew-rate: true gpio-hog: true diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 28f0851d07bb..989e48c051cf 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -56,6 +56,7 @@ properties: - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynosautov9-pinctrl + - tesla,fsd-pinctrl interrupts: description: diff --git a/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml new file mode 100644 index 000000000000..d8e75b3e64f1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml @@ -0,0 +1,374 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Pin Controller Device Tree Bindings + +maintainers: + - Dvorkin Dmitry + - Wells Lu + +description: | + The Sunplus SP7021 pin controller is used to control SoC pins. Please + refer to pinctrl-bindings.txt in this directory for details of the common + pinctrl bindings used by client devices. + + SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All + are multiplexed with some special function pins. SP7021 has 3 types of + special function pins: + + (1) function-group pins: + Ex 1 (SPI-NOR flash): + If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87 + will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79 + and 81 will be pins of SPI-NOR flash. + + Ex 2 (UART_0): + If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and + RX pins of UART_0 (UART channel 0). + + Ex 3 (eMMC): + If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77, + 78, 79, 80, 81 will be pins of an eMMC device. + + Properties "function" and "groups" are used to select function-group + pins. + + (2) fully pin-mux (like phone exchange mux) pins: + GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of + SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.) + can be routed to any pins of fully pin-mux pins. + + Ex 1 (UART channel 1): + If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be + routed to GPIO 10 (3 - 1 + 8 = 10). + If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be + routed to GPIO 11 (4 - 1 + 8 = 11). + If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will + be routed to GPIO 12 (5 - 1 + 8 = 12). + If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will + be routed to GPIO 13 (6 - 1 + 8 = 13). + + Ex 2 (I2C channel 0): + If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will + be routed to GPIO 27 (20 - 1 + 8 = 27). + If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0 + will be routed to GPIO 28 (21 - 1 + 9 = 28). + + Totally, SP7021 has 120 peripheral pins. The peripheral pins can be + routed to any of 64 'fully pin-mux' pins. + + (3) I/O processor pins + SP7021 has a built-in I/O processor. + Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor. + + Vendor property "sunplus,pins" is used to select "fully pin-mux" pins, + "I/O processor pins" and "digital GPIO" pins. + + The device node of pin controller of Sunplus SP7021 has following + properties. + +properties: + compatible: + const: sunplus,sp7021-pctl + + gpio-controller: true + + '#gpio-cells': + const: 2 + + reg: + items: + - description: the MOON2 registers + - description: the GPIOXT registers + - description: the FIRST registers + - description: the MOON1 registers + + reg-names: + items: + - const: moon2 + - const: gpioxt + - const: first + - const: moon1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pins or function-pins group available on the machine. Each subnode + will list the pins it needs, and how they should be configured. + + Pinctrl node's client devices use subnodes for desired pin + configuration. Client device subnodes use below standard properties. + $ref: pinmux-node.yaml# + + properties: + sunplus,pins: + description: | + Define 'sunplus,pins' which are used by pinctrl node's client + device. + + It consists of one or more integers which represents the config + setting for corresponding pin. Each integer defines a individual + pin in which: + + Bit 32~24: defines GPIO number. Its range is 0 ~ 98. + Bit 23~16: defines types: (1) fully pin-mux pins + (2) IO processor pins + (3) digital GPIO pins + Bit 15~8: defines pins of peripherals (which are defined in + 'include/dt-binging/pinctrl/sppctl.h'). + Bit 7~0: defines types or initial-state of digital GPIO pins. + + Please use macro SPPCTL_IOPAD to define the integers for pins. + + $ref: /schemas/types.yaml#/definitions/uint32-array + + function: + description: | + Define pin-function which is used by pinctrl node's client device. + The name should be one of string in the following enumeration. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD, + UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ] + + groups: + description: | + Define pin-group in a specified pin-function. + The name should be one of string in the following enumeration. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2, + SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1, + HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ] + + sunplus,zerofunc: + description: | + This is a vendor specific property. It is used to disable pins + which are not used by pinctrl node's client device. + Some pins may be enabled by boot-loader. We can use this + property to disable them. + $ref: /schemas/types.yaml#/definitions/uint32-array + + additionalProperties: false + + allOf: + - if: + properties: + function: + enum: + - SPI_FLASH + then: + properties: + groups: + enum: + - SPI_FLASH1 + - SPI_FLASH2 + - if: + properties: + function: + enum: + - SPI_FLASH_4BIT + then: + properties: + groups: + enum: + - SPI_FLASH_4BIT1 + - SPI_FLASH_4BIT2 + - if: + properties: + function: + enum: + - SPI_NAND + then: + properties: + groups: + enum: + - SPI_NAND + - if: + properties: + function: + enum: + - CARD0_EMMC + then: + properties: + groups: + enum: + - CARD0_EMMC + - if: + properties: + function: + enum: + - SD_CARD + then: + properties: + groups: + enum: + - SD_CARD + - if: + properties: + function: + enum: + - UA0 + then: + properties: + groups: + enum: + - UA0 + - if: + properties: + function: + enum: + - FPGA_IFX + then: + properties: + groups: + enum: + - FPGA_IFX + - if: + properties: + function: + enum: + - HDMI_TX + then: + properties: + groups: + enum: + - HDMI_TX1 + - HDMI_TX2 + - HDMI_TX3 + - if: + properties: + function: + enum: + - LCDIF + then: + properties: + groups: + enum: + - LCDIF + - if: + properties: + function: + enum: + - USB0_OTG + then: + properties: + groups: + enum: + - USB0_OTG + - if: + properties: + function: + enum: + - USB1_OTG + then: + properties: + groups: + enum: + - USB1_OTG + +required: + - compatible + - reg + - reg-names + - "#gpio-cells" + - gpio-controller + - clocks + - resets + +additionalProperties: false + +examples: + - | + #include + + pinctl@9c000100 { + compatible = "sunplus,sp7021-pctl"; + reg = <0x9c000100 0x100>, <0x9c000300 0x100>, + <0x9c0032e4 0x1c>, <0x9c000080 0x20>; + reg-names = "moon2", "gpioxt", "first", "moon1"; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clkc 0x83>; + resets = <&rstc 0x73>; + + uart0-pins { + function = "UA0"; + groups = "UA0"; + }; + + spinand0-pins { + function = "SPI_NAND"; + groups = "SPI_NAND"; + }; + + uart1-pins { + sunplus,pins = < + SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) + SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) + >; + }; + + uart2-pins { + sunplus,pins = < + SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) + SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) + SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0) + SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0) + >; + }; + + emmc-pins { + function = "CARD0_EMMC"; + groups = "CARD0_EMMC"; + }; + + sdcard-pins { + function = "SD_CARD"; + groups = "SD_CARD"; + sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; + }; + + hdmi_A_tx1-pins { + function = "HDMI_TX"; + groups = "HDMI_TX1"; + }; + hdmi_A_tx2-pins { + function = "HDMI_TX"; + groups = "HDMI_TX2"; + }; + hdmi_A_tx3-pins { + function = "HDMI_TX"; + groups = "HDMI_TX3"; + }; + + ethernet-pins { + sunplus,pins = < + SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) + SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) + SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) + SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) + SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) + SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) + SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) + SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) + SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) + >; + sunplus,zerofunc = < + MUXF_L2SW_LED_FLASH0 + MUXF_L2SW_LED_ON0 + MUXF_L2SW_P0_MAC_RMII_RXER + >; + }; + }; +... diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml new file mode 100644 index 000000000000..c98aab209bc5 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,eud.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Embedded USB Debugger + +maintainers: + - Souradeep Chowdhury + +description: + This binding is used to describe the Qualcomm Embedded USB Debugger, which is + mini USB-hub implemented on chip to support USB-based debug capabilities. + +properties: + compatible: + items: + - enum: + - qcom,sc7280-eud + - const: qcom,eud + + reg: + items: + - description: EUD Base Register Region + - description: EUD Mode Manager Register + + interrupts: + description: EUD interrupt + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: + These ports is to be attached to the endpoint of the DWC3 controller node + and type C connector node. The controller has the "usb-role-switch" + property. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: This port is to be attached to the DWC3 controller. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: This port is to be attached to the type C connector. + +required: + - compatible + - reg + - ports + +additionalProperties: false + +examples: + - | + eud@88e0000 { + compatible = "qcom,sc7280-eud","qcom,eud"; + reg = <0x88e0000 0x2000>, + <0x88e2000 0x1000>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; + }; + port@1 { + reg = <1>; + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt deleted file mode 100644 index f7ae79825d7d..000000000000 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ /dev/null @@ -1,115 +0,0 @@ -Samsung Exynos SoC USB controller - -The USB devices interface with USB controllers on Exynos SOCs. -The device node has following properties. - -EHCI -Required properties: - - compatible: should be "samsung,exynos4210-ehci" for USB 2.0 - EHCI controller in host mode. - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - clocks: from common clock binding: handle to usb clock. - - clock-names: from common clock binding: Shall be "usbhost". - - phys: from the *Generic PHY* bindings; array specifying phy(s) used - by the root port. - - phy-names: from the *Generic PHY* bindings; array of the names for - each phy for the root ports, must be a subset of the following: - "host", "hsic0", "hsic1". - -Optional properties: - - samsung,vbus-gpio: if present, specifies the GPIO that - needs to be pulled up for the bus to be powered. - -Example: - - usb@12110000 { - compatible = "samsung,exynos4210-ehci"; - reg = <0x12110000 0x100>; - interrupts = <0 71 0>; - samsung,vbus-gpio = <&gpx2 6 1 3 3>; - - clocks = <&clock 285>; - clock-names = "usbhost"; - - phys = <&usb2phy 1>; - phy-names = "host"; - }; - -OHCI -Required properties: - - compatible: should be "samsung,exynos4210-ohci" for USB 2.0 - OHCI companion controller in host mode. - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: interrupt number to the cpu. - - clocks: from common clock binding: handle to usb clock. - - clock-names: from common clock binding: Shall be "usbhost". - - phys: from the *Generic PHY* bindings; array specifying phy(s) used - by the root port. - - phy-names: from the *Generic PHY* bindings; array of the names for - each phy for the root ports, must be a subset of the following: - "host", "hsic0", "hsic1". - -Example: - usb@12120000 { - compatible = "samsung,exynos4210-ohci"; - reg = <0x12120000 0x100>; - interrupts = <0 71 0>; - - clocks = <&clock 285>; - clock-names = "usbhost"; - - phys = <&usb2phy 1>; - phy-names = "host"; - }; - -DWC3 -Required properties: - - compatible: should be one of the following - - "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on - Exynos5250/5420. - "samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on - Exynos5433. - "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7. - - #address-cells, #size-cells : should be '1' if the device has sub-nodes - with 'reg' property. - - ranges: allows valid 1:1 translation between child's address space and - parent's address space - - clocks: Clock IDs array as required by the controller. - - clock-names: Names of clocks corresponding to IDs in the clock property. - Following clock names shall be provided for different - compatibles: - - samsung,exynos5250-dwusb3: "usbdrd30", - - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk", - "phyclk", - - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk", - "usbdrd30_axius_clk" - - vdd10-supply: 1.0V powr supply - - vdd33-supply: 3.0V/3.3V power supply - -Sub-nodes: -The dwc3 core should be added as subnode to Exynos dwc3 glue. -- dwc3 : - The binding details of dwc3 can be found in: - Documentation/devicetree/bindings/usb/snps,dwc3.yaml - -Example: - usb@12000000 { - compatible = "samsung,exynos5250-dwusb3"; - clocks = <&clock 286>; - clock-names = "usbdrd30"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - vdd10-supply = <&ldo11_reg>; - vdd33-supply = <&ldo9_reg>; - - dwc3 { - compatible = "synopsys,dwc3"; - reg = <0x12000000 0x10000>; - interrupts = <0 72 0>; - usb-phy = <&usb2_phy &usb3_phy>; - }; - }; diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml index 974032b1fda0..01ab0f922ae8 100644 --- a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml @@ -15,9 +15,9 @@ properties: const: fsl,imx8mp-dwc3 reg: - maxItems: 1 - description: Address and length of the register set for the wrapper of - dwc3 core on the SOC. + items: + - description: Address and length of the register set for HSIO Block Control + - description: Address and length of the register set for the wrapper of dwc3 core on the SOC. "#address-cells": enum: [ 1, 2 ] @@ -49,6 +49,28 @@ properties: - const: hsio - const: suspend + fsl,permanently-attached: + type: boolean + description: + Indicates if the device atached to a downstream port is + permanently attached. + + fsl,disable-port-power-control: + type: boolean + description: + Indicates whether the host controller implementation includes port + power control. Defines Bit 3 in capability register (HCCPARAMS). + + fsl,over-current-active-low: + type: boolean + description: + Over current signal polarity is active low. + + fsl,power-active-low: + type: boolean + description: + Power pad (PWR) polarity is active low. + # Required child node: patternProperties: @@ -74,7 +96,8 @@ examples: #include usb3_0: usb@32f10100 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10100 0x8>; + reg = <0x32f10100 0x8>, + <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index 11f7bacd4e2b..084d7135b2d9 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt7629-xhci - mediatek,mt8173-xhci - mediatek,mt8183-xhci + - mediatek,mt8186-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci - const: mediatek,mtk-xhci @@ -146,7 +147,11 @@ properties: 2 - used by mt2712 etc, revision 2 following IPM rule; 101 - used by mt8183, specific 1.01; 102 - used by mt8192, specific 1.02; - enum: [1, 2, 101, 102] + 103 - used by mt8195, IP0, specific 1.03; + 104 - used by mt8195, IP1, specific 1.04; + 105 - used by mt8195, IP2, specific 1.05; + 106 - used by mt8195, IP3, specific 1.06; + enum: [1, 2, 101, 102, 103, 104, 105, 106] mediatek,u3p-dis-msk: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml new file mode 100644 index 000000000000..48c458c65848 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS USB Controller Device Tree Bindings + +allOf: + - $ref: usb-drd.yaml# + +maintainers: + - Conor Dooley + +properties: + compatible: + enum: + - microchip,mpfs-musb + + dr_mode: true + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 2 + + interrupt-names: + items: + - const: dma + - const: mc + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + usb@20201000 { + compatible = "microchip,mpfs-musb"; + reg = <0x20201000 0x1000>; + clocks = <&clkcfg CLK_USB>; + interrupt-parent = <&plic>; + interrupts = <86>, <87>; + interrupt-names = "dma", "mc"; + dr_mode = "host"; + }; + +... diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 2d23a4ff702f..ce252db2aab3 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -16,6 +16,7 @@ properties: - qcom,ipq4019-dwc3 - qcom,ipq6018-dwc3 - qcom,ipq8064-dwc3 + - qcom,msm8953-dwc3 - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 - qcom,sc7180-dwc3 diff --git a/Documentation/devicetree/bindings/usb/richtek,rt1719.yaml b/Documentation/devicetree/bindings/usb/richtek,rt1719.yaml new file mode 100644 index 000000000000..65a93f7738d5 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/richtek,rt1719.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/richtek,rt1719.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Richtek RT1719 sink-only Type-C PD controller bindings + +maintainers: + - ChiYuan Huang + +description: | + The RT1719 is a sink-only USB Type-C contoller that complies with the latest + USB Type-C and PD standards. It does the USB Type-C detection including attach + and orientation. It integrates the physical layer of the USB BMC power + delivery protocol to allow up to 100W of power. The BMC PD block enables full + support for alternative interfaces of the Type-C specification. + +properties: + compatible: + enum: + - richtek,rt1719 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + wakeup-source: + description: enable IRQ remote wakeup, see power/wakeup-source.txt + type: boolean + + connector: + type: object + $ref: ../connector/usb-connector.yaml# + description: + Properties for usb c connector. + +additionalProperties: false + +required: + - compatible + - reg + - connector + - interrupts + +examples: + - | + #include + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + rt1719@43 { + compatible = "richtek,rt1719"; + reg = <0x43>; + interrupts-extended = <&gpio26 2 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&usb_hs>; + }; + }; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&usb_ss>; + }; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml index 04077f2d7faf..b3798d94d2fd 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -30,6 +30,7 @@ select: enum: - rockchip,rk3328-dwc3 - rockchip,rk3399-dwc3 + - rockchip,rk3568-dwc3 required: - compatible @@ -39,6 +40,7 @@ properties: - enum: - rockchip,rk3328-dwc3 - rockchip,rk3399-dwc3 + - rockchip,rk3568-dwc3 - const: snps,dwc3 reg: diff --git a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml new file mode 100644 index 000000000000..22b91a27d776 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/samsung,exynos-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC USB 3.0 DWC3 Controller + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - samsung,exynos5250-dwusb3 + - samsung,exynos5433-dwusb3 + - samsung,exynos7-dwusb3 + + '#address-cells': + const: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + + ranges: true + + '#size-cells': + const: 1 + + vdd10-supply: + description: 1.0V power supply + + vdd33-supply: + description: 3.0V/3.3V power supply + +patternProperties: + "^usb@[0-9a-f]+$": + $ref: snps,dwc3.yaml# + description: Required child node + +required: + - compatible + - '#address-cells' + - clocks + - clock-names + - ranges + - '#size-cells' + - vdd10-supply + - vdd33-supply + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos5250-dwusb3 + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: usbdrd30 + + - if: + properties: + compatible: + contains: + const: samsung,exynos54333-dwusb3 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: aclk + - const: susp_clk + - const: pipe_pclk + - const: phyclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7-dwusb3 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: usbdrd30 + - const: usbdrd30_susp_clk + - const: usbdrd30_axius_clk + +additionalProperties: false + +examples: + - | + #include + #include + + usb { + compatible = "samsung,exynos5250-dwusb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&clock CLK_USBD300>; + clock-names = "usbdrd30"; + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; + + usb@12000000 { + compatible = "snps,dwc3"; + reg = <0x12000000 0x10000>; + interrupts = ; + phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; + phy-names = "usb2-phy", "usb3-phy"; + snps,dis_u3_susphy_quirk; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml b/Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml new file mode 100644 index 000000000000..fbf07d6e707a --- /dev/null +++ b/Documentation/devicetree/bindings/usb/samsung,exynos-usb2.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/samsung,exynos-usb2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC USB 2.0 EHCI/OHCI Controller + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + enum: + - samsung,exynos4210-ehci + - samsung,exynos4210-ohci + + '#address-cells': + const: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: usbhost + + interrupts: + maxItems: 1 + + phys: + minItems: 1 + maxItems: 3 + + phy-names: + items: + enum: [host, hsic0, hsic1] + minItems: 1 + maxItems: 3 + + reg: + maxItems: 1 + + samsung,vbus-gpio: + description: + Only for controller in EHCI mode, if present, specifies the GPIO that + needs to be pulled up for the bus to be powered. + + '#size-cells': + const: 0 + +patternProperties: + "^.*@[0-9a-f]{1,2}$": + description: The hard wired USB devices + type: object + $ref: /usb/usb-device.yaml + +required: + - compatible + - clocks + - clock-names + - interrupts + - phys + - phy-names + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos4210-ohci + then: + properties: + samsung,vbus-gpio: false + +additionalProperties: false + +examples: + - | + #include + #include + + usb@12110000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12110000 0x100>; + interrupts = ; + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; + phys = <&usb2_phy 0>; + phy-names = "host"; + + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "usb0424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usbether@1 { + compatible = "usb0424,ec00"; + reg = <1>; + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + + usb@12120000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12120000 0x100>; + interrupts = ; + clocks = <&clock CLK_USBH20>; + clock-names = "usbhost"; + phys = <&usb2_phy 0>; + phy-names = "host"; + }; diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index d29ffcd27472..f4471f8bdbef 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -263,8 +263,11 @@ properties: Value for REFCLKPER field of GUCTL register for reference clock period in nanoseconds, when the hardware set default does not match the actual clock. - minimum: 1 - maximum: 0x3ff + + This binding is deprecated. Instead, provide an appropriate reference clock. + minimum: 8 + maximum: 62 + deprecated: true snps,rx-thr-num-pkt-prd: description: @@ -332,6 +335,12 @@ properties: items: enum: [1, 4, 8, 16, 32, 64, 128, 256] + port: + $ref: /schemas/graph.yaml#/properties/port + description: + This port is used with the 'usb-role-switch' property to connect the + dwc3 to type C connector. + unevaluatedProperties: false required: diff --git a/Documentation/devicetree/bindings/usb/usb-hcd.yaml b/Documentation/devicetree/bindings/usb/usb-hcd.yaml index 56853c17af66..1dc3d5d7b44f 100644 --- a/Documentation/devicetree/bindings/usb/usb-hcd.yaml +++ b/Documentation/devicetree/bindings/usb/usb-hcd.yaml @@ -33,7 +33,7 @@ patternProperties: "^.*@[0-9a-f]{1,2}$": description: The hard wired USB devices type: object - $ref: /usb/usb-device.yaml + $ref: /schemas/usb/usb-device.yaml additionalProperties: true diff --git a/Documentation/devicetree/bindings/usb/willsemi,wusb3801.yaml b/Documentation/devicetree/bindings/usb/willsemi,wusb3801.yaml new file mode 100644 index 000000000000..c2b2243c7892 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/willsemi,wusb3801.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/willsemi,wusb3801.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: WUSB3801 Type-C port controller DT bindings + +description: + The Will Semiconductor WUSB3801 is a USB Type-C port controller which + supports role and plug orientation detection using the CC pins. It is + compatible with the USB Type-C Cable and Connector Specification v1.2. + +maintainers: + - Samuel Holland + +properties: + compatible: + enum: + - willsemi,wusb3801 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + connector: + type: object + $ref: ../connector/usb-connector.yaml# + description: + The managed USB Type-C connector. Since WUSB3801 does not support + Power Delivery, the node should have the "pd-disable" property. + + properties: + compatible: + const: usb-c-connector + + required: + - pd-disable + +required: + - compatible + - reg + - interrupts + - connector + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tcpc@60 { + compatible = "willsemi,wusb3801"; + reg = <0x60>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + vbus-supply = <&otg_switch>; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + typec-power-opmode = "default"; + pd-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index bb372e15bba4..1eebff4842e0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -876,6 +876,8 @@ patternProperties: description: NXP Semiconductors "^oceanic,.*": description: Oceanic Systems (UK) Ltd. + "^ocs,.*": + description: Orient Chip Technology Co., Ltd. "^oct,.*": description: Octavo Systems LLC "^okaya,.*": @@ -1371,6 +1373,8 @@ patternProperties: description: Wi2Wi, Inc. "^wiligear,.*": description: Wiligear, Ltd. + "^willsemi,.*": + description: Will Semiconductor Ltd. "^winbond,.*": description: Winbond Electronics corp. "^wingtech,.*": diff --git a/Documentation/usb/gadget-testing.rst b/Documentation/usb/gadget-testing.rst index cbbd948c626f..c6d034abce3a 100644 --- a/Documentation/usb/gadget-testing.rst +++ b/Documentation/usb/gadget-testing.rst @@ -726,7 +726,7 @@ The uac2 function provides these attributes in its function directory: ================ ==================================================== c_chmask capture channel mask - c_srate capture sampling rate + c_srate list of capture sampling rates (comma-separated) c_ssize capture sample size (bytes) c_sync capture synchronization type (async/adaptive) c_mute_present capture mute control enable @@ -734,17 +734,20 @@ The uac2 function provides these attributes in its function directory: c_volume_min capture volume control min value (in 1/256 dB) c_volume_max capture volume control max value (in 1/256 dB) c_volume_res capture volume control resolution (in 1/256 dB) + c_hs_bint capture bInterval for HS/SS (1-4: fixed, 0: auto) fb_max maximum extra bandwidth in async mode p_chmask playback channel mask - p_srate playback sampling rate + p_srate list of playback sampling rates (comma-separated) p_ssize playback sample size (bytes) p_mute_present playback mute control enable p_volume_present playback volume control enable p_volume_min playback volume control min value (in 1/256 dB) p_volume_max playback volume control max value (in 1/256 dB) p_volume_res playback volume control resolution (in 1/256 dB) + p_hs_bint playback bInterval for HS/SS (1-4: fixed, 0: auto) req_number the number of pre-allocated request for both capture and playback + function_name name of the interface ================ ==================================================== The attributes have sane default values. @@ -916,7 +919,7 @@ The uac1 function provides these attributes in its function directory: ================ ==================================================== c_chmask capture channel mask - c_srate capture sampling rate + c_srate list of capture sampling rates (comma-separated) c_ssize capture sample size (bytes) c_mute_present capture mute control enable c_volume_present capture volume control enable @@ -924,7 +927,7 @@ The uac1 function provides these attributes in its function directory: c_volume_max capture volume control max value (in 1/256 dB) c_volume_res capture volume control resolution (in 1/256 dB) p_chmask playback channel mask - p_srate playback sampling rate + p_srate list of playback sampling rates (comma-separated) p_ssize playback sample size (bytes) p_mute_present playback mute control enable p_volume_present playback volume control enable @@ -933,6 +936,7 @@ The uac1 function provides these attributes in its function directory: p_volume_res playback volume control resolution (in 1/256 dB) req_number the number of pre-allocated requests for both capture and playback + function_name name of the interface ================ ==================================================== The attributes have sane default values. diff --git a/MAINTAINERS b/MAINTAINERS index d5b0a6ef7a33..95449cdcd259 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2383,6 +2383,7 @@ W: https://github.com/neuschaefer/wpcm450/wiki F: Documentation/devicetree/bindings/*/*wpcm* F: arch/arm/boot/dts/nuvoton-wpcm450* F: arch/arm/mach-npcm/wpcm450.c +F: drivers/*/*/*wpcm* F: drivers/*/*wpcm* ARM/NXP S32G ARCHITECTURE @@ -3716,6 +3717,14 @@ F: Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml F: drivers/net/ethernet/broadcom/bcm4908_enet.* F: drivers/net/ethernet/broadcom/unimac.h +BROADCOM BCM4908 PINMUX DRIVER +M: Rafał Miłecki +M: bcm-kernel-feedback-list@broadcom.com +L: linux-gpio@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml +F: drivers/pinctrl/bcm/pinctrl-bcm4908.c + BROADCOM BCM5301X ARM ARCHITECTURE M: Florian Fainelli M: Hauke Mehrtens @@ -12557,6 +12566,7 @@ S: Maintained F: Documentation/core-api/boot-time-mm.rst F: include/linux/memblock.h F: mm/memblock.c +F: tools/testing/memblock/ MEMORY CONTROLLER DRIVERS M: Krzysztof Kozlowski @@ -15484,6 +15494,16 @@ M: Lakshmi Sowjanya D S: Supported F: drivers/pinctrl/pinctrl-thunderbay.c +PIN CONTROLLER - SUNPLUS / TIBBO +M: Dvorkin Dmitry +M: Wells Lu +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +W: https://sunplus.atlassian.net/wiki/spaces/doc/overview +F: Documentation/devicetree/bindings/pinctrl/sunplus,* +F: drivers/pinctrl/sunplus/ +F: include/dt-bindings/pinctrl/sppctl*.h + PKTCDVD DRIVER M: linux-block@vger.kernel.org S: Orphan @@ -15924,6 +15944,14 @@ F: sound/soc/codecs/wcd-clsh-v2.* F: sound/soc/codecs/wsa881x.c F: sound/soc/qcom/ +QCOM EMBEDDED USB DEBUGGER (EUD) +M: Souradeep Chowdhury +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/ABI/testing/sysfs-driver-eud +F: Documentation/devicetree/bindings/soc/qcom/qcom,eud.yaml +F: drivers/usb/misc/qcom_eud.c + QCOM IPA DRIVER M: Alex Elder L: netdev@vger.kernel.org diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3f8703f3ba5b..794d75173cf5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -921,7 +921,8 @@ usb3_0: usb@32f10100 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10100 0x8>; + reg = <0x32f10100 0x8>, + <0x381f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; @@ -963,7 +964,8 @@ usb3_1: usb@32f10108 { compatible = "fsl,imx8mp-dwc3"; - reg = <0x32f10108 0x8>; + reg = <0x32f10108 0x8>, + <0x382f0000 0x20>; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 4e7efa97724b..aac56575e30d 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -752,12 +752,13 @@ interrupts = ; phys = <&qusb_phy_0>, <&usb0_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + clocks = <&xo>; + clock-names = "ref"; tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; - snps,ref-clock-period-ns = <0x29>; dr_mode = "host"; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 1e0b1bca7c94..8493dd7d5f1f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -223,11 +223,11 @@ clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>; }; -&usb0 { +&dwc3_0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; -&usb1 { +&dwc3_1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 056761c974fd..c715a18368c2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -809,7 +809,6 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; - clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, @@ -823,6 +822,7 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg"; interrupts = <0 65 4>, <0 69 4>; + clock-names = "bus_early", "ref"; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; /* dma-coherent; */ @@ -835,7 +835,6 @@ status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; - clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, @@ -849,6 +848,7 @@ interrupt-parent = <&gic>; interrupt-names = "dwc_usb3", "otg"; interrupts = <0 70 4>, <0 74 4>; + clock-names = "bus_early", "ref"; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; /* dma-coherent; */ diff --git a/arch/openrisc/lib/memcpy.c b/arch/openrisc/lib/memcpy.c index fe2177628fd9..e2af9b510804 100644 --- a/arch/openrisc/lib/memcpy.c +++ b/arch/openrisc/lib/memcpy.c @@ -101,7 +101,7 @@ void *memcpy(void *dest, __const void *src, __kernel_size_t n) */ void *memcpy(void *dest, __const void *src, __kernel_size_t n) { - unsigned char *d = (unsigned char *)dest, *s = (unsigned char *)src; + unsigned char *d, *s; uint32_t *dest_w = (uint32_t *)dest, *src_w = (uint32_t *)src; /* If both source and dest are word aligned copy words */ diff --git a/arch/powerpc/include/asm/livepatch.h b/arch/powerpc/include/asm/livepatch.h index 6f10de6af6e3..1c60094ea0cd 100644 --- a/arch/powerpc/include/asm/livepatch.h +++ b/arch/powerpc/include/asm/livepatch.h @@ -16,16 +16,6 @@ static inline void klp_arch_set_pc(struct ftrace_regs *fregs, unsigned long ip) { ftrace_instruction_pointer_set(fregs, ip); } - -#define klp_get_ftrace_location klp_get_ftrace_location -static inline unsigned long klp_get_ftrace_location(unsigned long faddr) -{ - /* - * Live patch works on PPC32 and only with -mprofile-kernel on PPC64. In - * both cases, the ftrace location is always within the first 16 bytes. - */ - return ftrace_location_range(faddr, faddr + 16); -} #endif /* CONFIG_LIVEPATCH */ #ifdef CONFIG_LIVEPATCH_64 diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c index 9a492fdec1df..7dae0b01abfb 100644 --- a/arch/powerpc/kernel/kprobes.c +++ b/arch/powerpc/kernel/kprobes.c @@ -105,6 +105,27 @@ kprobe_opcode_t *kprobe_lookup_name(const char *name, unsigned int offset) return addr; } +static bool arch_kprobe_on_func_entry(unsigned long offset) +{ +#ifdef PPC64_ELF_ABI_v2 +#ifdef CONFIG_KPROBES_ON_FTRACE + return offset <= 16; +#else + return offset <= 8; +#endif +#else + return !offset; +#endif +} + +/* XXX try and fold the magic of kprobe_lookup_name() in this */ +kprobe_opcode_t *arch_adjust_kprobe_addr(unsigned long addr, unsigned long offset, + bool *on_func_entry) +{ + *on_func_entry = arch_kprobe_on_func_entry(offset); + return (kprobe_opcode_t *)(addr + offset); +} + void *alloc_insn_page(void) { void *page; @@ -218,19 +239,6 @@ static nokprobe_inline void set_current_kprobe(struct kprobe *p, struct pt_regs kcb->kprobe_saved_msr = regs->msr; } -bool arch_kprobe_on_func_entry(unsigned long offset) -{ -#ifdef PPC64_ELF_ABI_v2 -#ifdef CONFIG_KPROBES_ON_FTRACE - return offset <= 16; -#else - return offset <= 8; -#endif -#else - return !offset; -#endif -} - void arch_prepare_kretprobe(struct kretprobe_instance *ri, struct pt_regs *regs) { ri->ret_addr = (kprobe_opcode_t *)regs->link; diff --git a/arch/um/kernel/um_arch.c b/arch/um/kernel/um_arch.c index abceeabe29b9..0760e24f2eba 100644 --- a/arch/um/kernel/um_arch.c +++ b/arch/um/kernel/um_arch.c @@ -424,6 +424,10 @@ void __init check_bugs(void) os_check_bugs(); } +void apply_ibt_endbr(s32 *start, s32 *end) +{ +} + void apply_retpolines(s32 *start, s32 *end) { } diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 10e4c332e15d..7340d9f01b62 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1842,6 +1842,36 @@ config X86_UMIP specific cases in protected and virtual-8086 modes. Emulated results are dummy. +config CC_HAS_IBT + # GCC >= 9 and binutils >= 2.29 + # Retpoline check to work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=93654 + # Clang/LLVM >= 14 + # https://github.com/llvm/llvm-project/commit/e0b89df2e0f0130881bf6c39bf31d7f6aac00e0f + # https://github.com/llvm/llvm-project/commit/dfcf69770bc522b9e411c66454934a37c1f35332 + def_bool ((CC_IS_GCC && $(cc-option, -fcf-protection=branch -mindirect-branch-register)) || \ + (CC_IS_CLANG && CLANG_VERSION >= 140000)) && \ + $(as-instr,endbr64) + +config X86_KERNEL_IBT + prompt "Indirect Branch Tracking" + bool + depends on X86_64 && CC_HAS_IBT && STACK_VALIDATION + # https://github.com/llvm/llvm-project/commit/9d7001eba9c4cb311e03cd8cdc231f9e579f2d0f + depends on !LD_IS_LLD || LLD_VERSION >= 140000 + help + Build the kernel with support for Indirect Branch Tracking, a + hardware support course-grain forward-edge Control Flow Integrity + protection. It enforces that all indirect calls must land on + an ENDBR instruction, as such, the compiler will instrument the + code with them to make this happen. + + In addition to building the kernel with IBT, seal all functions that + are not indirect call targets, avoiding them ever becomming one. + + This requires LTO like objtool runs and will slow down the build. It + does significantly reduce the number of ENDBR instructions in the + kernel image. + config X86_INTEL_MEMORY_PROTECTION_KEYS prompt "Memory Protection Keys" def_bool y @@ -2815,19 +2845,20 @@ config IA32_AOUT help Support old a.out binaries in the 32bit emulation. -config X86_X32 +config X86_X32_ABI bool "x32 ABI for 64-bit mode" depends on X86_64 + # llvm-objcopy does not convert x86_64 .note.gnu.property or + # compressed debug sections to x86_x32 properly: + # https://github.com/ClangBuiltLinux/linux/issues/514 + # https://github.com/ClangBuiltLinux/linux/issues/1141 + depends on $(success,$(OBJCOPY) --version | head -n1 | grep -qv llvm) help Include code to run binaries for the x32 native 32-bit ABI for 64-bit processors. An x32 process gets access to the full 64-bit register file and wide data path while leaving pointers at 32 bits for smaller memory footprint. - You will need a recent binutils (2.22 or later) with - elf32_x86_64 support enabled to compile a kernel with this - option set. - config COMPAT_32 def_bool y depends on IA32_EMULATION || X86_32 @@ -2836,7 +2867,7 @@ config COMPAT_32 config COMPAT def_bool y - depends on IA32_EMULATION || X86_X32 + depends on IA32_EMULATION || X86_X32_ABI if COMPAT config COMPAT_FOR_U64_ALIGNMENT diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 7b526812e356..acb00b8efe2a 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -36,7 +36,7 @@ endif # How to compile the 16-bit code. Note we always compile for -march=i386; # that way we can complain to the user if the CPU is insufficient. -REALMODE_CFLAGS := -m16 -g -Os -DDISABLE_BRANCH_PROFILING \ +REALMODE_CFLAGS := -m16 -g -Os -DDISABLE_BRANCH_PROFILING -D__DISABLE_EXPORTS \ -Wall -Wstrict-prototypes -march=i386 -mregparm=3 \ -fno-strict-aliasing -fomit-frame-pointer -fno-pic \ -mno-mmx -mno-sse $(call cc-option,-fcf-protection=none) @@ -62,8 +62,20 @@ export BITS # KBUILD_CFLAGS += -mno-sse -mno-mmx -mno-sse2 -mno-3dnow -mno-avx -# Intel CET isn't enabled in the kernel +ifeq ($(CONFIG_X86_KERNEL_IBT),y) +# +# Kernel IBT has S_CET.NOTRACK_EN=0, as such the compilers must not generate +# NOTRACK prefixes. Current generation compilers unconditionally employ NOTRACK +# for jump-tables, as such, disable jump-tables for now. +# +# (jump-tables are implicitly disabled by RETPOLINE) +# +# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104816 +# +KBUILD_CFLAGS += $(call cc-option,-fcf-protection=branch -fno-jump-tables) +else KBUILD_CFLAGS += $(call cc-option,-fcf-protection=none) +endif ifeq ($(CONFIG_X86_32),y) BITS := 32 @@ -140,22 +152,6 @@ else KBUILD_CFLAGS += -mcmodel=kernel endif -ifdef CONFIG_X86_X32 - x32_ld_ok := $(call try-run,\ - /bin/echo -e '1: .quad 1b' | \ - $(CC) $(KBUILD_AFLAGS) -c -x assembler -o "$$TMP" - && \ - $(OBJCOPY) -O elf32-x86-64 "$$TMP" "$$TMP.o" && \ - $(LD) -m elf32_x86_64 "$$TMP.o" -o "$$TMP",y,n) - ifeq ($(x32_ld_ok),y) - CONFIG_X86_X32_ABI := y - KBUILD_AFLAGS += -DCONFIG_X86_X32_ABI - KBUILD_CFLAGS += -DCONFIG_X86_X32_ABI - else - $(warning CONFIG_X86_X32 enabled but no binutils support) - endif -endif -export CONFIG_X86_X32_ABI - # # If the function graph tracer is used with mcount instead of fentry, # '-maccumulate-outgoing-args' is needed to prevent a GCC bug diff --git a/arch/x86/crypto/crc32c-pcl-intel-asm_64.S b/arch/x86/crypto/crc32c-pcl-intel-asm_64.S index 80c0d22fc42c..ec35915f0901 100644 --- a/arch/x86/crypto/crc32c-pcl-intel-asm_64.S +++ b/arch/x86/crypto/crc32c-pcl-intel-asm_64.S @@ -195,6 +195,7 @@ crc_array: .altmacro LABEL crc_ %i .noaltmacro + ENDBR crc32q -i*8(block_0), crc_init crc32q -i*8(block_1), crc1 crc32q -i*8(block_2), crc2 @@ -204,6 +205,7 @@ LABEL crc_ %i .altmacro LABEL crc_ %i .noaltmacro + ENDBR crc32q -i*8(block_0), crc_init crc32q -i*8(block_1), crc1 # SKIP crc32 -i*8(block_2), crc2 ; Don't do this one yet @@ -237,6 +239,7 @@ LABEL crc_ %i ################################################################ LABEL crc_ 0 + ENDBR mov tmp, len cmp $128*24, tmp jae full_block diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 466df3e50276..4faac48ebec5 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -86,6 +86,7 @@ SYM_CODE_START(entry_SYSCALL_64) UNWIND_HINT_EMPTY + ENDBR swapgs /* tss.sp2 is scratch space. */ @@ -94,6 +95,7 @@ SYM_CODE_START(entry_SYSCALL_64) movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp SYM_INNER_LABEL(entry_SYSCALL_64_safe_stack, SYM_L_GLOBAL) + ANNOTATE_NOENDBR /* Construct struct pt_regs on stack */ pushq $__USER_DS /* pt_regs->ss */ @@ -276,6 +278,7 @@ SYM_FUNC_END(__switch_to_asm) .pushsection .text, "ax" SYM_CODE_START(ret_from_fork) UNWIND_HINT_EMPTY + ANNOTATE_NOENDBR // copy_thread movq %rax, %rdi call schedule_tail /* rdi: 'prev' task parameter */ @@ -350,6 +353,7 @@ SYM_CODE_END(ret_from_fork) .macro idtentry vector asmsym cfunc has_error_code:req SYM_CODE_START(\asmsym) UNWIND_HINT_IRET_REGS offset=\has_error_code*8 + ENDBR ASM_CLAC .if \has_error_code == 0 @@ -417,6 +421,7 @@ SYM_CODE_END(\asmsym) .macro idtentry_mce_db vector asmsym cfunc SYM_CODE_START(\asmsym) UNWIND_HINT_IRET_REGS + ENDBR ASM_CLAC pushq $-1 /* ORIG_RAX: no syscall to restart */ @@ -472,6 +477,7 @@ SYM_CODE_END(\asmsym) .macro idtentry_vc vector asmsym cfunc SYM_CODE_START(\asmsym) UNWIND_HINT_IRET_REGS + ENDBR ASM_CLAC /* @@ -533,6 +539,7 @@ SYM_CODE_END(\asmsym) .macro idtentry_df vector asmsym cfunc SYM_CODE_START(\asmsym) UNWIND_HINT_IRET_REGS offset=8 + ENDBR ASM_CLAC /* paranoid_entry returns GS information for paranoid_exit in EBX. */ @@ -544,6 +551,9 @@ SYM_CODE_START(\asmsym) movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ call \cfunc + /* For some configurations \cfunc ends up being a noreturn. */ + REACHABLE + jmp paranoid_exit _ASM_NOKPROBE(\asmsym) @@ -564,6 +574,7 @@ __irqentry_text_start: .align 16 .globl __irqentry_text_end __irqentry_text_end: + ANNOTATE_NOENDBR SYM_CODE_START_LOCAL(common_interrupt_return) SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL) @@ -608,8 +619,8 @@ SYM_INNER_LABEL(swapgs_restore_regs_and_return_to_usermode, SYM_L_GLOBAL) /* Restore RDI. */ popq %rdi - SWAPGS - INTERRUPT_RETURN + swapgs + jmp .Lnative_iret SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL) @@ -626,9 +637,14 @@ SYM_INNER_LABEL(restore_regs_and_return_to_kernel, SYM_L_GLOBAL) * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization * when returning from IPI handler. */ - INTERRUPT_RETURN +#ifdef CONFIG_XEN_PV +SYM_INNER_LABEL(early_xen_iret_patch, SYM_L_GLOBAL) + ANNOTATE_NOENDBR + .byte 0xe9 + .long .Lnative_iret - (. + 4) +#endif -SYM_INNER_LABEL_ALIGN(native_iret, SYM_L_GLOBAL) +.Lnative_iret: UNWIND_HINT_IRET_REGS /* * Are we returning to a stack segment from the LDT? Note: in @@ -640,6 +656,7 @@ SYM_INNER_LABEL_ALIGN(native_iret, SYM_L_GLOBAL) #endif SYM_INNER_LABEL(native_irq_return_iret, SYM_L_GLOBAL) + ANNOTATE_NOENDBR // exc_double_fault /* * This may fault. Non-paranoid faults on return to userspace are * handled by fixup_bad_iret. These include #SS, #GP, and #NP. @@ -734,6 +751,7 @@ SYM_FUNC_START(asm_load_gs_index) FRAME_BEGIN swapgs .Lgs_change: + ANNOTATE_NOENDBR // error_entry movl %edi, %gs 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE swapgs @@ -804,6 +822,7 @@ SYM_CODE_END(exc_xen_hypervisor_callback) */ SYM_CODE_START(xen_failsafe_callback) UNWIND_HINT_EMPTY + ENDBR movl %ds, %ecx cmpw %cx, 0x10(%rsp) jne 1f @@ -1063,6 +1082,7 @@ SYM_CODE_END(error_return) */ SYM_CODE_START(asm_exc_nmi) UNWIND_HINT_IRET_REGS + ENDBR /* * We allow breakpoints in NMIs. If a breakpoint occurs, then @@ -1310,6 +1330,7 @@ first_nmi: #endif repeat_nmi: + ANNOTATE_NOENDBR // this code /* * If there was a nested NMI, the first NMI's iret will return * here. But NMIs are still enabled and we can take another @@ -1338,6 +1359,7 @@ repeat_nmi: .endr subq $(5*8), %rsp end_repeat_nmi: + ANNOTATE_NOENDBR // this code /* * Everything below this point can be preempted by a nested NMI. @@ -1421,6 +1443,7 @@ SYM_CODE_END(asm_exc_nmi) */ SYM_CODE_START(ignore_sysret) UNWIND_HINT_EMPTY + ENDBR mov $-ENOSYS, %eax sysretl SYM_CODE_END(ignore_sysret) diff --git a/arch/x86/entry/entry_64_compat.S b/arch/x86/entry/entry_64_compat.S index 0051cf5c792d..4fdb007cddbd 100644 --- a/arch/x86/entry/entry_64_compat.S +++ b/arch/x86/entry/entry_64_compat.S @@ -48,6 +48,7 @@ */ SYM_CODE_START(entry_SYSENTER_compat) UNWIND_HINT_EMPTY + ENDBR /* Interrupts are off on entry. */ SWAPGS @@ -147,6 +148,7 @@ SYM_INNER_LABEL(entry_SYSENTER_compat_after_hwframe, SYM_L_GLOBAL) popfq jmp .Lsysenter_flags_fixed SYM_INNER_LABEL(__end_entry_SYSENTER_compat, SYM_L_GLOBAL) + ANNOTATE_NOENDBR // is_sysenter_singlestep SYM_CODE_END(entry_SYSENTER_compat) /* @@ -198,6 +200,7 @@ SYM_CODE_END(entry_SYSENTER_compat) */ SYM_CODE_START(entry_SYSCALL_compat) UNWIND_HINT_EMPTY + ENDBR /* Interrupts are off on entry. */ swapgs @@ -211,6 +214,7 @@ SYM_CODE_START(entry_SYSCALL_compat) movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp SYM_INNER_LABEL(entry_SYSCALL_compat_safe_stack, SYM_L_GLOBAL) + ANNOTATE_NOENDBR /* Construct struct pt_regs on stack */ pushq $__USER32_DS /* pt_regs->ss */ @@ -340,6 +344,7 @@ SYM_CODE_END(entry_SYSCALL_compat) */ SYM_CODE_START(entry_INT80_compat) UNWIND_HINT_EMPTY + ENDBR /* * Interrupts are off on entry. */ diff --git a/arch/x86/entry/syscalls/Makefile b/arch/x86/entry/syscalls/Makefile index 5b3efed0e4e8..7f3886eeb2ff 100644 --- a/arch/x86/entry/syscalls/Makefile +++ b/arch/x86/entry/syscalls/Makefile @@ -67,7 +67,7 @@ uapisyshdr-y += unistd_32.h unistd_64.h unistd_x32.h syshdr-y += syscalls_32.h syshdr-$(CONFIG_X86_64) += unistd_32_ia32.h unistd_64_x32.h syshdr-$(CONFIG_X86_64) += syscalls_64.h -syshdr-$(CONFIG_X86_X32) += syscalls_x32.h +syshdr-$(CONFIG_X86_X32_ABI) += syscalls_x32.h syshdr-$(CONFIG_XEN) += xen-hypercalls.h uapisyshdr-y := $(addprefix $(uapi)/, $(uapisyshdr-y)) diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h index 58eee6402832..9b10c8c76087 100644 --- a/arch/x86/include/asm/alternative.h +++ b/arch/x86/include/asm/alternative.h @@ -76,6 +76,7 @@ extern int alternatives_patched; extern void alternative_instructions(void); extern void apply_alternatives(struct alt_instr *start, struct alt_instr *end); extern void apply_retpolines(s32 *start, s32 *end); +extern void apply_ibt_endbr(s32 *start, s32 *end); struct module; diff --git a/arch/x86/include/asm/bug.h b/arch/x86/include/asm/bug.h index bab883c0b6fe..4d20a293c6fd 100644 --- a/arch/x86/include/asm/bug.h +++ b/arch/x86/include/asm/bug.h @@ -4,6 +4,7 @@ #include #include +#include /* * Despite that some emulators terminate on UD2, we use it for WARN(). diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 33d41e350c79..86e5e4e26fcb 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -7,6 +7,7 @@ #include #include #include +#include #ifdef CONFIG_SMP @@ -72,4 +73,7 @@ void init_ia32_feat_ctl(struct cpuinfo_x86 *c); #else static inline void init_ia32_feat_ctl(struct cpuinfo_x86 *c) {} #endif + +extern __noendbr void cet_disable(void); + #endif /* _ASM_X86_CPU_H */ diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 3edf05e98e58..73e643ae94b6 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -388,6 +388,7 @@ #define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ +#define X86_FEATURE_IBT (18*32+20) /* Indirect Branch Tracking */ #define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */ #define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */ #define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */ diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index 03cb12775043..98938a68251c 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -120,8 +121,12 @@ extern asmlinkage u64 __efi_call(void *fp, ...); efi_enter_mm(); \ }) -#define arch_efi_call_virt(p, f, args...) \ - efi_call((void *)p->f, args) \ +#define arch_efi_call_virt(p, f, args...) ({ \ + u64 ret, ibt = ibt_save(); \ + ret = efi_call((void *)p->f, args); \ + ibt_restore(ibt); \ + ret; \ +}) #define arch_efi_call_virt_teardown() \ ({ \ diff --git a/arch/x86/include/asm/ibt.h b/arch/x86/include/asm/ibt.h new file mode 100644 index 000000000000..689880eca9ba --- /dev/null +++ b/arch/x86/include/asm/ibt.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_IBT_H +#define _ASM_X86_IBT_H + +#include + +/* + * The rules for enabling IBT are: + * + * - CC_HAS_IBT: the toolchain supports it + * - X86_KERNEL_IBT: it is selected in Kconfig + * - !__DISABLE_EXPORTS: this is regular kernel code + * + * Esp. that latter one is a bit non-obvious, but some code like compressed, + * purgatory, realmode etc.. is built with custom CFLAGS that do not include + * -fcf-protection=branch and things will go *bang*. + * + * When all the above are satisfied, HAS_KERNEL_IBT will be 1, otherwise 0. + */ +#if defined(CONFIG_X86_KERNEL_IBT) && !defined(__DISABLE_EXPORTS) + +#define HAS_KERNEL_IBT 1 + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_X86_64 +#define ASM_ENDBR "endbr64\n\t" +#else +#define ASM_ENDBR "endbr32\n\t" +#endif + +#define __noendbr __attribute__((nocf_check)) + +static inline __attribute_const__ u32 gen_endbr(void) +{ + u32 endbr; + + /* + * Generate ENDBR64 in a way that is sure to not result in + * an ENDBR64 instruction as immediate. + */ + asm ( "mov $~0xfa1e0ff3, %[endbr]\n\t" + "not %[endbr]\n\t" + : [endbr] "=&r" (endbr) ); + + return endbr; +} + +static inline __attribute_const__ u32 gen_endbr_poison(void) +{ + /* + * 4 byte NOP that isn't NOP4 (in fact it is OSP NOP3), such that it + * will be unique to (former) ENDBR sites. + */ + return 0x001f0f66; /* osp nopl (%rax) */ +} + +static inline bool is_endbr(u32 val) +{ + if (val == gen_endbr_poison()) + return true; + + val &= ~0x01000000U; /* ENDBR32 -> ENDBR64 */ + return val == gen_endbr(); +} + +extern __noendbr u64 ibt_save(void); +extern __noendbr void ibt_restore(u64 save); + +#else /* __ASSEMBLY__ */ + +#ifdef CONFIG_X86_64 +#define ENDBR endbr64 +#else +#define ENDBR endbr32 +#endif + +#endif /* __ASSEMBLY__ */ + +#else /* !IBT */ + +#define HAS_KERNEL_IBT 0 + +#ifndef __ASSEMBLY__ + +#define ASM_ENDBR + +#define __noendbr + +static inline bool is_endbr(u32 val) { return false; } + +static inline u64 ibt_save(void) { return 0; } +static inline void ibt_restore(u64 save) { } + +#else /* __ASSEMBLY__ */ + +#define ENDBR + +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_X86_KERNEL_IBT */ + +#define ENDBR_INSN_SIZE (4*HAS_KERNEL_IBT) + +#endif /* _ASM_X86_IBT_H */ diff --git a/arch/x86/include/asm/idtentry.h b/arch/x86/include/asm/idtentry.h index 1345088e9902..7924f27f5c8b 100644 --- a/arch/x86/include/asm/idtentry.h +++ b/arch/x86/include/asm/idtentry.h @@ -5,6 +5,8 @@ /* Interrupts/Exceptions */ #include +#define IDT_ALIGN (8 * (1 + HAS_KERNEL_IBT)) + #ifndef __ASSEMBLY__ #include #include @@ -480,7 +482,7 @@ __visible noinstr void func(struct pt_regs *regs, \ /* * ASM code to emit the common vector entry stubs where each stub is - * packed into 8 bytes. + * packed into IDT_ALIGN bytes. * * Note, that the 'pushq imm8' is emitted via '.byte 0x6a, vector' because * GCC treats the local vector variable as unsigned int and would expand @@ -492,33 +494,33 @@ __visible noinstr void func(struct pt_regs *regs, \ * point is to mask off the bits above bit 7 because the push is sign * extending. */ - .align 8 + .align IDT_ALIGN SYM_CODE_START(irq_entries_start) vector=FIRST_EXTERNAL_VECTOR .rept NR_EXTERNAL_VECTORS UNWIND_HINT_IRET_REGS 0 : + ENDBR .byte 0x6a, vector jmp asm_common_interrupt - nop - /* Ensure that the above is 8 bytes max */ - . = 0b + 8 + /* Ensure that the above is IDT_ALIGN bytes max */ + .fill 0b + IDT_ALIGN - ., 1, 0xcc vector = vector+1 .endr SYM_CODE_END(irq_entries_start) #ifdef CONFIG_X86_LOCAL_APIC - .align 8 + .align IDT_ALIGN SYM_CODE_START(spurious_entries_start) vector=FIRST_SYSTEM_VECTOR .rept NR_SYSTEM_VECTORS UNWIND_HINT_IRET_REGS 0 : + ENDBR .byte 0x6a, vector jmp asm_spurious_interrupt - nop - /* Ensure that the above is 8 bytes max */ - . = 0b + 8 + /* Ensure that the above is IDT_ALIGN bytes max */ + .fill 0b + IDT_ALIGN - ., 1, 0xcc vector = vector+1 .endr SYM_CODE_END(spurious_entries_start) @@ -615,6 +617,11 @@ DECLARE_IDTENTRY_DF(X86_TRAP_DF, exc_double_fault); DECLARE_IDTENTRY_RAW_ERRORCODE(X86_TRAP_DF, xenpv_exc_double_fault); #endif +/* #CP */ +#ifdef CONFIG_X86_KERNEL_IBT +DECLARE_IDTENTRY_ERRORCODE(X86_TRAP_CP, exc_control_protection); +#endif + /* #VC */ #ifdef CONFIG_AMD_MEM_ENCRYPT DECLARE_IDTENTRY_VC(X86_TRAP_VC, exc_vmm_communication); diff --git a/arch/x86/include/asm/irq_stack.h b/arch/x86/include/asm/irq_stack.h index ae9d40f6c706..63f818aedf77 100644 --- a/arch/x86/include/asm/irq_stack.h +++ b/arch/x86/include/asm/irq_stack.h @@ -3,6 +3,7 @@ #define _ASM_X86_IRQ_STACK_H #include +#include #include @@ -99,7 +100,8 @@ } #define ASM_CALL_ARG0 \ - "call %P[__func] \n" + "call %P[__func] \n" \ + ASM_REACHABLE #define ASM_CALL_ARG1 \ "movq %[arg1], %%rdi \n" \ diff --git a/arch/x86/include/asm/irqflags.h b/arch/x86/include/asm/irqflags.h index 87761396e8cc..111104d1c2cd 100644 --- a/arch/x86/include/asm/irqflags.h +++ b/arch/x86/include/asm/irqflags.h @@ -141,13 +141,8 @@ static __always_inline void arch_local_irq_restore(unsigned long flags) #ifdef CONFIG_X86_64 #ifdef CONFIG_XEN_PV #define SWAPGS ALTERNATIVE "swapgs", "", X86_FEATURE_XENPV -#define INTERRUPT_RETURN \ - ANNOTATE_RETPOLINE_SAFE; \ - ALTERNATIVE_TERNARY("jmp *paravirt_iret(%rip);", \ - X86_FEATURE_XENPV, "jmp xen_iret;", "jmp native_iret;") #else #define SWAPGS swapgs -#define INTERRUPT_RETURN jmp native_iret #endif #endif #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h index 030907922bd0..85865f1645bd 100644 --- a/arch/x86/include/asm/linkage.h +++ b/arch/x86/include/asm/linkage.h @@ -3,6 +3,7 @@ #define _ASM_X86_LINKAGE_H #include +#include #undef notrace #define notrace __attribute__((no_instrument_function)) @@ -34,5 +35,35 @@ #endif /* __ASSEMBLY__ */ +/* SYM_FUNC_START -- use for global functions */ +#define SYM_FUNC_START(name) \ + SYM_START(name, SYM_L_GLOBAL, SYM_A_ALIGN) \ + ENDBR + +/* SYM_FUNC_START_NOALIGN -- use for global functions, w/o alignment */ +#define SYM_FUNC_START_NOALIGN(name) \ + SYM_START(name, SYM_L_GLOBAL, SYM_A_NONE) \ + ENDBR + +/* SYM_FUNC_START_LOCAL -- use for local functions */ +#define SYM_FUNC_START_LOCAL(name) \ + SYM_START(name, SYM_L_LOCAL, SYM_A_ALIGN) \ + ENDBR + +/* SYM_FUNC_START_LOCAL_NOALIGN -- use for local functions, w/o alignment */ +#define SYM_FUNC_START_LOCAL_NOALIGN(name) \ + SYM_START(name, SYM_L_LOCAL, SYM_A_NONE) \ + ENDBR + +/* SYM_FUNC_START_WEAK -- use for weak functions */ +#define SYM_FUNC_START_WEAK(name) \ + SYM_START(name, SYM_L_WEAK, SYM_A_ALIGN) \ + ENDBR + +/* SYM_FUNC_START_WEAK_NOALIGN -- use for weak functions, w/o alignment */ +#define SYM_FUNC_START_WEAK_NOALIGN(name) \ + SYM_START(name, SYM_L_WEAK, SYM_A_NONE) \ + ENDBR + #endif /* _ASM_X86_LINKAGE_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 9f1741ac4769..0eb90d21049e 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -362,11 +362,29 @@ #define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c #define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d - #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 +/* Control-flow Enforcement Technology MSRs */ +#define MSR_IA32_U_CET 0x000006a0 /* user mode cet */ +#define MSR_IA32_S_CET 0x000006a2 /* kernel mode cet */ +#define CET_SHSTK_EN BIT_ULL(0) +#define CET_WRSS_EN BIT_ULL(1) +#define CET_ENDBR_EN BIT_ULL(2) +#define CET_LEG_IW_EN BIT_ULL(3) +#define CET_NO_TRACK_EN BIT_ULL(4) +#define CET_SUPPRESS_DISABLE BIT_ULL(5) +#define CET_RESERVED (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9)) +#define CET_SUPPRESS BIT_ULL(10) +#define CET_WAIT_ENDBR BIT_ULL(11) + +#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow stack pointer */ +#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow stack pointer */ +#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow stack pointer */ +#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow stack pointer */ +#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shadow stack table */ + /* Hardware P state interface */ #define MSR_PPERF 0x0000064e #define MSR_PERF_LIMIT_REASONS 0x0000064f diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index 0d76502cc6f5..964442b99245 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -666,6 +666,7 @@ bool __raw_callee_save___native_vcpu_is_preempted(long cpu); ".globl " PV_THUNK_NAME(func) ";" \ ".type " PV_THUNK_NAME(func) ", @function;" \ PV_THUNK_NAME(func) ":" \ + ASM_ENDBR \ FRAME_BEGIN \ PV_SAVE_ALL_CALLER_REGS \ "call " #func ";" \ diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index e1591467668e..89df6c6617f5 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -272,7 +272,6 @@ struct paravirt_patch_template { extern struct pv_info pv_info; extern struct paravirt_patch_template pv_ops; -extern void (*paravirt_iret)(void); #define PARAVIRT_PATCH(x) \ (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index a87e7c33d5ac..91d0f93a00c7 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -837,7 +837,7 @@ bool xen_set_default_idle(void); #define xen_set_default_idle 0 #endif -void stop_this_cpu(void *dummy); +void __noreturn stop_this_cpu(void *dummy); void microcode_check(void); enum l1tf_mitigations { diff --git a/arch/x86/include/asm/qspinlock_paravirt.h b/arch/x86/include/asm/qspinlock_paravirt.h index 1474cf96251d..892fd8c3a6f7 100644 --- a/arch/x86/include/asm/qspinlock_paravirt.h +++ b/arch/x86/include/asm/qspinlock_paravirt.h @@ -2,6 +2,8 @@ #ifndef __ASM_QSPINLOCK_PARAVIRT_H #define __ASM_QSPINLOCK_PARAVIRT_H +#include + /* * For x86-64, PV_CALLEE_SAVE_REGS_THUNK() saves and restores 8 64-bit * registers. For i386, however, only 1 32-bit register needs to be saved @@ -39,6 +41,7 @@ asm (".pushsection .text;" ".type " PV_UNLOCK ", @function;" ".align 4,0x90;" PV_UNLOCK ": " + ASM_ENDBR FRAME_BEGIN "push %rdx;" "mov $0x1,%eax;" diff --git a/arch/x86/include/asm/segment.h b/arch/x86/include/asm/segment.h index b228c9d44ee7..656ed6531d03 100644 --- a/arch/x86/include/asm/segment.h +++ b/arch/x86/include/asm/segment.h @@ -4,6 +4,7 @@ #include #include +#include /* * Constructor for a conventional segment GDT (or LDT) entry. @@ -275,7 +276,7 @@ static inline void vdso_read_cpunode(unsigned *cpu, unsigned *node) * vector has no error code (two bytes), a 'push $vector_number' (two * bytes), and a jump to the common entry code (up to five bytes). */ -#define EARLY_IDT_HANDLER_SIZE 9 +#define EARLY_IDT_HANDLER_SIZE (9 + ENDBR_INSN_SIZE) /* * xen_early_idt_handler_array is for Xen pv guests: for each entry in @@ -283,7 +284,7 @@ static inline void vdso_read_cpunode(unsigned *cpu, unsigned *node) * pop %rcx; pop %r11; jmp early_idt_handler_array[i]; summing up to * max 8 bytes. */ -#define XEN_EARLY_IDT_HANDLER_SIZE 8 +#define XEN_EARLY_IDT_HANDLER_SIZE (8 + ENDBR_INSN_SIZE) #ifndef __ASSEMBLY__ diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index a12458a7a8d4..896e48d45828 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -8,6 +8,7 @@ #include #include +#include #ifdef __i386__ @@ -119,7 +120,7 @@ void *extend_brk(size_t size, size_t align); * executable.) */ #define RESERVE_BRK(name,sz) \ - static void __section(".discard.text") __used notrace \ + static void __section(".discard.text") __noendbr __used notrace \ __brk_reservation_fn_##name##__(void) { \ asm volatile ( \ ".pushsection .brk_reservation,\"aw\",@nobits;" \ diff --git a/arch/x86/include/asm/syscall_wrapper.h b/arch/x86/include/asm/syscall_wrapper.h index 6a2827d0681f..59358d1bf880 100644 --- a/arch/x86/include/asm/syscall_wrapper.h +++ b/arch/x86/include/asm/syscall_wrapper.h @@ -159,7 +159,7 @@ extern long __ia32_sys_ni_syscall(const struct pt_regs *regs); #endif /* CONFIG_IA32_EMULATION */ -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI /* * For the x32 ABI, we need to create a stub for compat_sys_*() which is aware * of the x86-64-style parameter ordering of x32 syscalls. The syscalls common @@ -177,12 +177,12 @@ extern long __ia32_sys_ni_syscall(const struct pt_regs *regs); #define __X32_COMPAT_SYS_NI(name) \ __SYS_NI(x64, compat_sys_##name) -#else /* CONFIG_X86_X32 */ +#else /* CONFIG_X86_X32_ABI */ #define __X32_COMPAT_SYS_STUB0(name) #define __X32_COMPAT_SYS_STUBx(x, name, ...) #define __X32_COMPAT_COND_SYSCALL(name) #define __X32_COMPAT_SYS_NI(name) -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ #ifdef CONFIG_COMPAT diff --git a/arch/x86/include/asm/text-patching.h b/arch/x86/include/asm/text-patching.h index 4cc18ba1b75e..d20ab0921480 100644 --- a/arch/x86/include/asm/text-patching.h +++ b/arch/x86/include/asm/text-patching.h @@ -96,25 +96,41 @@ union text_poke_insn { } __attribute__((packed)); }; +static __always_inline +void __text_gen_insn(void *buf, u8 opcode, const void *addr, const void *dest, int size) +{ + union text_poke_insn *insn = buf; + + BUG_ON(size < text_opcode_size(opcode)); + + /* + * Hide the addresses to avoid the compiler folding in constants when + * referencing code, these can mess up annotations like + * ANNOTATE_NOENDBR. + */ + OPTIMIZER_HIDE_VAR(insn); + OPTIMIZER_HIDE_VAR(addr); + OPTIMIZER_HIDE_VAR(dest); + + insn->opcode = opcode; + + if (size > 1) { + insn->disp = (long)dest - (long)(addr + size); + if (size == 2) { + /* + * Ensure that for JMP8 the displacement + * actually fits the signed byte. + */ + BUG_ON((insn->disp >> 31) != (insn->disp >> 7)); + } + } +} + static __always_inline void *text_gen_insn(u8 opcode, const void *addr, const void *dest) { static union text_poke_insn insn; /* per instance */ - int size = text_opcode_size(opcode); - - insn.opcode = opcode; - - if (size > 1) { - insn.disp = (long)dest - (long)(addr + size); - if (size == 2) { - /* - * Ensure that for JMP9 the displacement - * actually fits the signed byte. - */ - BUG_ON((insn.disp >> 31) != (insn.disp >> 7)); - } - } - + __text_gen_insn(&insn, opcode, addr, dest, text_opcode_size(opcode)); return &insn.text; } diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h index 6221be7cafc3..35317c5c551d 100644 --- a/arch/x86/include/asm/traps.h +++ b/arch/x86/include/asm/traps.h @@ -18,6 +18,8 @@ void __init trap_init(void); asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *eregs); #endif +extern bool ibt_selftest(void); + #ifdef CONFIG_X86_F00F_BUG /* For handling the FOOF bug */ void handle_invalid_op(struct pt_regs *regs); diff --git a/arch/x86/include/asm/vdso.h b/arch/x86/include/asm/vdso.h index 98aa103eb4ab..2963a2f5dbc4 100644 --- a/arch/x86/include/asm/vdso.h +++ b/arch/x86/include/asm/vdso.h @@ -37,7 +37,7 @@ struct vdso_image { extern const struct vdso_image vdso_image_64; #endif -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI extern const struct vdso_image vdso_image_x32; #endif diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index bcba3c643e63..c47cc7f2feeb 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -130,6 +130,8 @@ #define X86_CR4_SMAP _BITUL(X86_CR4_SMAP_BIT) #define X86_CR4_PKE_BIT 22 /* enable Protection Keys support */ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) +#define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology */ +#define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) /* * x86-64 Task Priority Register, CR8 diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index b4e576600969..d374cb3cf024 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -115,6 +115,7 @@ static void __init_or_module add_nops(void *insns, unsigned int len) } extern s32 __retpoline_sites[], __retpoline_sites_end[]; +extern s32 __ibt_endbr_seal[], __ibt_endbr_seal_end[]; extern struct alt_instr __alt_instructions[], __alt_instructions_end[]; extern s32 __smp_locks[], __smp_locks_end[]; void text_poke_early(void *addr, const void *opcode, size_t len); @@ -512,6 +513,42 @@ void __init_or_module noinline apply_retpolines(s32 *start, s32 *end) { } #endif /* CONFIG_RETPOLINE && CONFIG_STACK_VALIDATION */ +#ifdef CONFIG_X86_KERNEL_IBT + +/* + * Generated by: objtool --ibt + */ +void __init_or_module noinline apply_ibt_endbr(s32 *start, s32 *end) +{ + s32 *s; + + for (s = start; s < end; s++) { + u32 endbr, poison = gen_endbr_poison(); + void *addr = (void *)s + *s; + + if (WARN_ON_ONCE(get_kernel_nofault(endbr, addr))) + continue; + + if (WARN_ON_ONCE(!is_endbr(endbr))) + continue; + + DPRINTK("ENDBR at: %pS (%px)", addr, addr); + + /* + * When we have IBT, the lack of ENDBR will trigger #CP + */ + DUMP_BYTES(((u8*)addr), 4, "%px: orig: ", addr); + DUMP_BYTES(((u8*)&poison), 4, "%px: repl: ", addr); + text_poke_early(addr, &poison, 4); + } +} + +#else + +void __init_or_module noinline apply_ibt_endbr(s32 *start, s32 *end) { } + +#endif /* CONFIG_X86_KERNEL_IBT */ + #ifdef CONFIG_SMP static void alternatives_smp_lock(const s32 *start, const s32 *end, u8 *text, u8 *text_end) @@ -713,34 +750,39 @@ asm ( " .pushsection .init.text, \"ax\", @progbits\n" " .type int3_magic, @function\n" "int3_magic:\n" + ANNOTATE_NOENDBR " movl $1, (%" _ASM_ARG1 ")\n" ASM_RET " .size int3_magic, .-int3_magic\n" " .popsection\n" ); -extern __initdata unsigned long int3_selftest_ip; /* defined in asm below */ +extern void int3_selftest_ip(void); /* defined in asm below */ static int __init int3_exception_notify(struct notifier_block *self, unsigned long val, void *data) { + unsigned long selftest = (unsigned long)&int3_selftest_ip; struct die_args *args = data; struct pt_regs *regs = args->regs; + OPTIMIZER_HIDE_VAR(selftest); + if (!regs || user_mode(regs)) return NOTIFY_DONE; if (val != DIE_INT3) return NOTIFY_DONE; - if (regs->ip - INT3_INSN_SIZE != int3_selftest_ip) + if (regs->ip - INT3_INSN_SIZE != selftest) return NOTIFY_DONE; int3_emulate_call(regs, (unsigned long)&int3_magic); return NOTIFY_STOP; } -static void __init int3_selftest(void) +/* Must be noinline to ensure uniqueness of int3_selftest_ip. */ +static noinline void __init int3_selftest(void) { static __initdata struct notifier_block int3_exception_nb = { .notifier_call = int3_exception_notify, @@ -753,18 +795,12 @@ static void __init int3_selftest(void) /* * Basically: int3_magic(&val); but really complicated :-) * - * Stick the address of the INT3 instruction into int3_selftest_ip, - * then trigger the INT3, padded with NOPs to match a CALL instruction - * length. + * INT3 padded with NOP to CALL_INSN_SIZE. The int3_exception_nb + * notifier above will emulate CALL for us. */ - asm volatile ("1: int3; nop; nop; nop; nop\n\t" - ".pushsection .init.data,\"aw\"\n\t" - ".align " __ASM_SEL(4, 8) "\n\t" - ".type int3_selftest_ip, @object\n\t" - ".size int3_selftest_ip, " __ASM_SEL(4, 8) "\n\t" - "int3_selftest_ip:\n\t" - __ASM_SEL(.long, .quad) " 1b\n\t" - ".popsection\n\t" + asm volatile ("int3_selftest_ip:\n\t" + ANNOTATE_NOENDBR + " int3; nop; nop; nop; nop\n\t" : ASM_CALL_CONSTRAINT : __ASM_SEL_RAW(a, D) (&val) : "memory"); @@ -831,6 +867,8 @@ void __init alternative_instructions(void) */ apply_alternatives(__alt_instructions, __alt_instructions_end); + apply_ibt_endbr(__ibt_endbr_seal, __ibt_endbr_seal_end); + #ifdef CONFIG_SMP /* Patch to UP if other cpus not imminent. */ if (!noreplace_smp && (num_present_cpus() == 1 || setup_max_cpus <= 1)) { diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index 241dda687eb9..60e330cdbd17 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -232,6 +232,7 @@ #include #include #include +#include #if defined(CONFIG_APM_DISPLAY_BLANK) && defined(CONFIG_VT) extern int (*console_blank_hook)(int); @@ -598,6 +599,7 @@ static long __apm_bios_call(void *_call) struct desc_struct save_desc_40; struct desc_struct *gdt; struct apm_bios_call *call = _call; + u64 ibt; cpu = get_cpu(); BUG_ON(cpu != 0); @@ -607,11 +609,13 @@ static long __apm_bios_call(void *_call) apm_irq_save(flags); firmware_restrict_branch_speculation_start(); + ibt = ibt_save(); APM_DO_SAVE_SEGS; apm_bios_call_asm(call->func, call->ebx, call->ecx, &call->eax, &call->ebx, &call->ecx, &call->edx, &call->esi); APM_DO_RESTORE_SEGS; + ibt_restore(ibt); firmware_restrict_branch_speculation_end(); apm_irq_restore(flags); gdt[0x40 / 8] = save_desc_40; @@ -676,6 +680,7 @@ static long __apm_bios_call_simple(void *_call) struct desc_struct save_desc_40; struct desc_struct *gdt; struct apm_bios_call *call = _call; + u64 ibt; cpu = get_cpu(); BUG_ON(cpu != 0); @@ -685,10 +690,12 @@ static long __apm_bios_call_simple(void *_call) apm_irq_save(flags); firmware_restrict_branch_speculation_start(); + ibt = ibt_save(); APM_DO_SAVE_SEGS; error = apm_bios_call_simple_asm(call->func, call->ebx, call->ecx, &call->eax); APM_DO_RESTORE_SEGS; + ibt_restore(ibt); firmware_restrict_branch_speculation_end(); apm_irq_restore(flags); gdt[0x40 / 8] = save_desc_40; diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 64deb7727d00..ed4417500700 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -59,6 +59,7 @@ #include #include #include +#include #include "cpu.h" @@ -438,7 +439,8 @@ out: /* These bits should not change their value after CPU init is finished. */ static const unsigned long cr4_pinned_mask = - X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE; + X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | + X86_CR4_FSGSBASE | X86_CR4_CET; static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); static unsigned long cr4_pinned_bits __ro_after_init; @@ -592,6 +594,58 @@ static __init int setup_disable_pku(char *arg) __setup("nopku", setup_disable_pku); #endif /* CONFIG_X86_64 */ +#ifdef CONFIG_X86_KERNEL_IBT + +__noendbr u64 ibt_save(void) +{ + u64 msr = 0; + + if (cpu_feature_enabled(X86_FEATURE_IBT)) { + rdmsrl(MSR_IA32_S_CET, msr); + wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN); + } + + return msr; +} + +__noendbr void ibt_restore(u64 save) +{ + u64 msr; + + if (cpu_feature_enabled(X86_FEATURE_IBT)) { + rdmsrl(MSR_IA32_S_CET, msr); + msr &= ~CET_ENDBR_EN; + msr |= (save & CET_ENDBR_EN); + wrmsrl(MSR_IA32_S_CET, msr); + } +} + +#endif + +static __always_inline void setup_cet(struct cpuinfo_x86 *c) +{ + u64 msr = CET_ENDBR_EN; + + if (!HAS_KERNEL_IBT || + !cpu_feature_enabled(X86_FEATURE_IBT)) + return; + + wrmsrl(MSR_IA32_S_CET, msr); + cr4_set_bits(X86_CR4_CET); + + if (!ibt_selftest()) { + pr_err("IBT selftest: Failed!\n"); + setup_clear_cpu_cap(X86_FEATURE_IBT); + return; + } +} + +__noendbr void cet_disable(void) +{ + if (cpu_feature_enabled(X86_FEATURE_IBT)) + wrmsrl(MSR_IA32_S_CET, 0); +} + /* * Some CPU features depend on higher CPUID levels, which may not always * be available due to CPUID level capping or broken virtualization @@ -1709,6 +1763,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) x86_init_rdrand(c); setup_pku(c); + setup_cet(c); /* * Clear/Set all flags overridden by options, need do it @@ -1777,6 +1832,8 @@ void enable_sep_cpu(void) void __init identify_boot_cpu(void) { identify_cpu(&boot_cpu_data); + if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT)) + pr_info("CET detected: Indirect Branch Tracking enabled\n"); #ifdef CONFIG_X86_32 sysenter_setup(); enable_sep_cpu(); diff --git a/arch/x86/kernel/early_printk.c b/arch/x86/kernel/early_printk.c index d3c531d3b244..68b38925a74f 100644 --- a/arch/x86/kernel/early_printk.c +++ b/arch/x86/kernel/early_printk.c @@ -387,7 +387,7 @@ static int __init setup_early_printk(char *buf) #endif #ifdef CONFIG_EARLY_PRINTK_USB_XDBC if (!strncmp(buf, "xdbc", 4)) - early_xdbc_parse_parameter(buf + 4); + early_xdbc_parse_parameter(buf + 4, keep); #endif buf++; diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c index 7cc540e6de0c..1e31c7d21597 100644 --- a/arch/x86/kernel/ftrace.c +++ b/arch/x86/kernel/ftrace.c @@ -316,12 +316,12 @@ create_trampoline(struct ftrace_ops *ops, unsigned int *tramp_size) unsigned long offset; unsigned long npages; unsigned long size; - unsigned long retq; unsigned long *ptr; void *trampoline; void *ip; /* 48 8b 15 is movq (%rip), %rdx */ unsigned const char op_ref[] = { 0x48, 0x8b, 0x15 }; + unsigned const char retq[] = { RET_INSN_OPCODE, INT3_INSN_OPCODE }; union ftrace_op_code_union op_ptr; int ret; @@ -359,12 +359,7 @@ create_trampoline(struct ftrace_ops *ops, unsigned int *tramp_size) goto fail; ip = trampoline + size; - - /* The trampoline ends with ret(q) */ - retq = (unsigned long)ftrace_stub; - ret = copy_from_kernel_nofault(ip, (void *)retq, RET_SIZE); - if (WARN_ON(ret < 0)) - goto fail; + memcpy(ip, retq, RET_SIZE); /* No need to test direct calls on created trampolines */ if (ops->flags & FTRACE_OPS_FL_SAVE_REGS) { diff --git a/arch/x86/kernel/ftrace_64.S b/arch/x86/kernel/ftrace_64.S index 11ac028e30e4..4ec13608d3c6 100644 --- a/arch/x86/kernel/ftrace_64.S +++ b/arch/x86/kernel/ftrace_64.S @@ -145,6 +145,7 @@ SYM_FUNC_START(ftrace_caller) movq %rcx, RSP(%rsp) SYM_INNER_LABEL(ftrace_caller_op_ptr, SYM_L_GLOBAL) + ANNOTATE_NOENDBR /* Load the ftrace_ops into the 3rd parameter */ movq function_trace_op(%rip), %rdx @@ -155,6 +156,7 @@ SYM_INNER_LABEL(ftrace_caller_op_ptr, SYM_L_GLOBAL) movq $0, CS(%rsp) SYM_INNER_LABEL(ftrace_call, SYM_L_GLOBAL) + ANNOTATE_NOENDBR call ftrace_stub /* Handlers can change the RIP */ @@ -169,6 +171,7 @@ SYM_INNER_LABEL(ftrace_call, SYM_L_GLOBAL) * layout here. */ SYM_INNER_LABEL(ftrace_caller_end, SYM_L_GLOBAL) + ANNOTATE_NOENDBR jmp ftrace_epilogue SYM_FUNC_END(ftrace_caller); @@ -176,10 +179,10 @@ SYM_FUNC_END(ftrace_caller); SYM_FUNC_START(ftrace_epilogue) /* * This is weak to keep gas from relaxing the jumps. - * It is also used to copy the RET for trampolines. */ SYM_INNER_LABEL_ALIGN(ftrace_stub, SYM_L_WEAK) UNWIND_HINT_FUNC + ENDBR RET SYM_FUNC_END(ftrace_epilogue) @@ -192,6 +195,7 @@ SYM_FUNC_START(ftrace_regs_caller) /* save_mcount_regs fills in first two parameters */ SYM_INNER_LABEL(ftrace_regs_caller_op_ptr, SYM_L_GLOBAL) + ANNOTATE_NOENDBR /* Load the ftrace_ops into the 3rd parameter */ movq function_trace_op(%rip), %rdx @@ -221,6 +225,7 @@ SYM_INNER_LABEL(ftrace_regs_caller_op_ptr, SYM_L_GLOBAL) leaq (%rsp), %rcx SYM_INNER_LABEL(ftrace_regs_call, SYM_L_GLOBAL) + ANNOTATE_NOENDBR call ftrace_stub /* Copy flags back to SS, to restore them */ @@ -248,6 +253,7 @@ SYM_INNER_LABEL(ftrace_regs_call, SYM_L_GLOBAL) */ testq %rax, %rax SYM_INNER_LABEL(ftrace_regs_caller_jmp, SYM_L_GLOBAL) + ANNOTATE_NOENDBR jnz 1f restore_mcount_regs @@ -261,6 +267,7 @@ SYM_INNER_LABEL(ftrace_regs_caller_jmp, SYM_L_GLOBAL) * to the return. */ SYM_INNER_LABEL(ftrace_regs_caller_end, SYM_L_GLOBAL) + ANNOTATE_NOENDBR jmp ftrace_epilogue /* Swap the flags with orig_rax */ @@ -284,6 +291,7 @@ SYM_FUNC_START(__fentry__) jnz trace SYM_INNER_LABEL(ftrace_stub, SYM_L_GLOBAL) + ENDBR RET trace: @@ -307,7 +315,7 @@ EXPORT_SYMBOL(__fentry__) #ifdef CONFIG_FUNCTION_GRAPH_TRACER SYM_FUNC_START(return_to_handler) - subq $24, %rsp + subq $16, %rsp /* Save the return values */ movq %rax, (%rsp) @@ -319,7 +327,19 @@ SYM_FUNC_START(return_to_handler) movq %rax, %rdi movq 8(%rsp), %rdx movq (%rsp), %rax - addq $24, %rsp - JMP_NOSPEC rdi + + addq $16, %rsp + /* + * Jump back to the old return address. This cannot be JMP_NOSPEC rdi + * since IBT would demand that contain ENDBR, which simply isn't so for + * return addresses. Use a retpoline here to keep the RSB balanced. + */ + ANNOTATE_INTRA_FUNCTION_CALL + call .Ldo_rop + int3 +.Ldo_rop: + mov %rdi, (%rsp) + UNWIND_HINT_FUNC + RET SYM_FUNC_END(return_to_handler) #endif diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 9c63fc5988cd..b8e3019547a5 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -99,6 +99,7 @@ SYM_CODE_END(startup_64) SYM_CODE_START(secondary_startup_64) UNWIND_HINT_EMPTY + ANNOTATE_NOENDBR /* * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, * and someone has loaded a mapped page table. @@ -127,6 +128,7 @@ SYM_CODE_START(secondary_startup_64) */ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) UNWIND_HINT_EMPTY + ANNOTATE_NOENDBR /* * Retrieve the modifier (SME encryption mask if SME is active) to be @@ -192,6 +194,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) jmp *%rax 1: UNWIND_HINT_EMPTY + ANNOTATE_NOENDBR // above /* * We must switch to a new descriptor in kernel space for the GDT @@ -299,6 +302,7 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) pushq %rax # target address in negative space lretq .Lafter_lret: + ANNOTATE_NOENDBR SYM_CODE_END(secondary_startup_64) #include "verify_cpu.S" @@ -328,6 +332,7 @@ SYM_CODE_END(start_cpu0) */ SYM_CODE_START_NOALIGN(vc_boot_ghcb) UNWIND_HINT_IRET_REGS offset=8 + ENDBR /* Build pt_regs */ PUSH_AND_CLEAR_REGS @@ -345,7 +350,6 @@ SYM_CODE_START_NOALIGN(vc_boot_ghcb) /* Remove Error Code */ addq $8, %rsp - /* Pure iret required here - don't use INTERRUPT_RETURN */ iretq SYM_CODE_END(vc_boot_ghcb) #endif @@ -372,9 +376,11 @@ SYM_CODE_START(early_idt_handler_array) .rept NUM_EXCEPTION_VECTORS .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 UNWIND_HINT_IRET_REGS + ENDBR pushq $0 # Dummy error code, to make stack frame uniform .else UNWIND_HINT_IRET_REGS offset=8 + ENDBR .endif pushq $i # 72(%rsp) Vector number jmp early_idt_handler_common @@ -382,10 +388,11 @@ SYM_CODE_START(early_idt_handler_array) i = i + 1 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc .endr - UNWIND_HINT_IRET_REGS offset=16 SYM_CODE_END(early_idt_handler_array) + ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS] SYM_CODE_START_LOCAL(early_idt_handler_common) + UNWIND_HINT_IRET_REGS offset=16 /* * The stack is the hardware frame, an error code or zero, and the * vector number. @@ -426,11 +433,14 @@ SYM_CODE_END(early_idt_handler_common) * early_idt_handler_array can't be used because it returns via the * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. * + * XXX it does, fix this. + * * This handler will end up in the .init.text section and not be * available to boot secondary CPUs. */ SYM_CODE_START_NOALIGN(vc_no_ghcb) UNWIND_HINT_IRET_REGS offset=8 + ENDBR /* Build pt_regs */ PUSH_AND_CLEAR_REGS diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index df0fa695bb09..608eb63bf044 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -10,6 +10,7 @@ #include #include #include +#include #define DPL0 0x0 #define DPL3 0x3 @@ -103,6 +104,10 @@ static const __initconst struct idt_data def_idts[] = { ISTG(X86_TRAP_MC, asm_exc_machine_check, IST_INDEX_MCE), #endif +#ifdef CONFIG_X86_KERNEL_IBT + INTG(X86_TRAP_CP, asm_exc_control_protection), +#endif + #ifdef CONFIG_AMD_MEM_ENCRYPT ISTG(X86_TRAP_VC, asm_exc_vmm_communication, IST_INDEX_VC), #endif @@ -272,7 +277,7 @@ void __init idt_setup_apic_and_irq_gates(void) idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true); for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) { - entry = irq_entries_start + 8 * (i - FIRST_EXTERNAL_VECTOR); + entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR); set_intr_gate(i, entry); } @@ -283,7 +288,7 @@ void __init idt_setup_apic_and_irq_gates(void) * system_vectors bitmap. Otherwise they show up in * /proc/interrupts. */ - entry = spurious_entries_start + 8 * (i - FIRST_SYSTEM_VECTOR); + entry = spurious_entries_start + IDT_ALIGN * (i - FIRST_SYSTEM_VECTOR); set_intr_gate(i, entry); } #endif diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c index 6290712cb36d..8ef933c03afa 100644 --- a/arch/x86/kernel/kprobes/core.c +++ b/arch/x86/kernel/kprobes/core.c @@ -52,6 +52,7 @@ #include #include #include +#include #include "common.h" @@ -193,17 +194,10 @@ static unsigned long __recover_probed_insn(kprobe_opcode_t *buf, unsigned long addr) { struct kprobe *kp; - unsigned long faddr; + bool faddr; kp = get_kprobe((void *)addr); - faddr = ftrace_location(addr); - /* - * Addresses inside the ftrace location are refused by - * arch_check_ftrace_location(). Something went terribly wrong - * if such an address is checked here. - */ - if (WARN_ON(faddr && faddr != addr)) - return 0UL; + faddr = ftrace_location(addr) == addr; /* * Use the current code if it is not modified by Kprobe * and it cannot be modified by ftrace. @@ -301,6 +295,22 @@ static int can_probe(unsigned long paddr) return (addr == paddr); } +/* If x86 supports IBT (ENDBR) it must be skipped. */ +kprobe_opcode_t *arch_adjust_kprobe_addr(unsigned long addr, unsigned long offset, + bool *on_func_entry) +{ + if (is_endbr(*(u32 *)addr)) { + *on_func_entry = !offset || offset == 4; + if (*on_func_entry) + offset = 4; + + } else { + *on_func_entry = !offset; + } + + return (kprobe_opcode_t *)(addr + offset); +} + /* * Copy an instruction with recovering modified instruction by kprobes * and adjust the displacement if the instruction uses the %rip-relative @@ -1023,6 +1033,7 @@ asm( ".type __kretprobe_trampoline, @function\n" "__kretprobe_trampoline:\n" #ifdef CONFIG_X86_64 + ANNOTATE_NOENDBR /* Push a fake return address to tell the unwinder it's a kretprobe. */ " pushq $__kretprobe_trampoline\n" UNWIND_HINT_FUNC diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index d77481ecb0d5..79e0b8d63ffa 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -1029,10 +1029,11 @@ asm( ".global __raw_callee_save___kvm_vcpu_is_preempted;" ".type __raw_callee_save___kvm_vcpu_is_preempted, @function;" "__raw_callee_save___kvm_vcpu_is_preempted:" +ASM_ENDBR "movq __per_cpu_offset(,%rdi,8), %rax;" "cmpb $0, " __stringify(KVM_STEAL_TIME_preempted) "+steal_time(%rax);" "setne %al;" -"ret;" +ASM_RET ".size __raw_callee_save___kvm_vcpu_is_preempted, .-__raw_callee_save___kvm_vcpu_is_preempted;" ".popsection"); diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_kexec_64.c index f5da4a18070a..566bb8e17149 100644 --- a/arch/x86/kernel/machine_kexec_64.c +++ b/arch/x86/kernel/machine_kexec_64.c @@ -27,6 +27,7 @@ #include #include #include +#include #ifdef CONFIG_ACPI /* @@ -310,6 +311,7 @@ void machine_kexec(struct kimage *image) /* Interrupts aren't acceptable while we reboot */ local_irq_disable(); hw_breakpoint_disable(); + cet_disable(); if (image->preserve_context) { #ifdef CONFIG_X86_IO_APIC @@ -325,7 +327,7 @@ void machine_kexec(struct kimage *image) } control_page = page_address(image->control_code_page) + PAGE_SIZE; - memcpy(control_page, relocate_kernel, KEXEC_CONTROL_CODE_MAX_SIZE); + __memcpy(control_page, relocate_kernel, KEXEC_CONTROL_CODE_MAX_SIZE); page_list[PA_CONTROL_PAGE] = virt_to_phys(control_page); page_list[VA_CONTROL_PAGE] = (unsigned long)control_page; diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c index 504ea65987e8..b98ffcf4d250 100644 --- a/arch/x86/kernel/module.c +++ b/arch/x86/kernel/module.c @@ -253,7 +253,7 @@ int module_finalize(const Elf_Ehdr *hdr, { const Elf_Shdr *s, *text = NULL, *alt = NULL, *locks = NULL, *para = NULL, *orc = NULL, *orc_ip = NULL, - *retpolines = NULL; + *retpolines = NULL, *ibt_endbr = NULL; char *secstrings = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; for (s = sechdrs; s < sechdrs + hdr->e_shnum; s++) { @@ -271,6 +271,8 @@ int module_finalize(const Elf_Ehdr *hdr, orc_ip = s; if (!strcmp(".retpoline_sites", secstrings + s->sh_name)) retpolines = s; + if (!strcmp(".ibt_endbr_seal", secstrings + s->sh_name)) + ibt_endbr = s; } /* @@ -290,6 +292,10 @@ int module_finalize(const Elf_Ehdr *hdr, void *aseg = (void *)alt->sh_addr; apply_alternatives(aseg, aseg + alt->sh_size); } + if (ibt_endbr) { + void *iseg = (void *)ibt_endbr->sh_addr; + apply_ibt_endbr(iseg, iseg + ibt_endbr->sh_size); + } if (locks && text) { void *lseg = (void *)locks->sh_addr; void *tseg = (void *)text->sh_addr; diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 4420499f7bb4..7ca2d46c08cc 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -41,6 +41,7 @@ extern void _paravirt_nop(void); asm (".pushsection .entry.text, \"ax\"\n" ".global _paravirt_nop\n" "_paravirt_nop:\n\t" + ASM_ENDBR ASM_RET ".size _paravirt_nop, . - _paravirt_nop\n\t" ".type _paravirt_nop, @function\n\t" @@ -50,6 +51,7 @@ asm (".pushsection .entry.text, \"ax\"\n" asm (".pushsection .entry.text, \"ax\"\n" ".global paravirt_ret0\n" "paravirt_ret0:\n\t" + ASM_ENDBR "xor %" _ASM_AX ", %" _ASM_AX ";\n\t" ASM_RET ".size paravirt_ret0, . - paravirt_ret0\n\t" @@ -69,29 +71,12 @@ noinstr void paravirt_BUG(void) BUG(); } -struct branch { - unsigned char opcode; - u32 delta; -} __attribute__((packed)); - static unsigned paravirt_patch_call(void *insn_buff, const void *target, unsigned long addr, unsigned len) { - const int call_len = 5; - struct branch *b = insn_buff; - unsigned long delta = (unsigned long)target - (addr+call_len); - - if (len < call_len) { - pr_warn("paravirt: Failed to patch indirect CALL at %ps\n", (void *)addr); - /* Kernel might not be viable if patching fails, bail out: */ - BUG_ON(1); - } - - b->opcode = 0xe8; /* call */ - b->delta = delta; - BUILD_BUG_ON(sizeof(*b) != call_len); - - return call_len; + __text_gen_insn(insn_buff, CALL_INSN_OPCODE, + (void *)addr, target, CALL_INSN_SIZE); + return CALL_INSN_SIZE; } #ifdef CONFIG_PARAVIRT_XXL @@ -149,8 +134,6 @@ void paravirt_set_sched_clock(u64 (*func)(void)) } /* These are in entry.S */ -extern void native_iret(void); - static struct resource reserve_ioports = { .start = 0, .end = IO_SPACE_LIMIT, @@ -414,8 +397,6 @@ struct paravirt_patch_template pv_ops = { #ifdef CONFIG_PARAVIRT_XXL NOKPROBE_SYMBOL(native_load_idt); - -void (*paravirt_iret)(void) = native_iret; #endif EXPORT_SYMBOL(pv_ops); diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index e131d71b3cae..b370767f5b19 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -747,7 +747,7 @@ bool xen_set_default_idle(void) } #endif -void stop_this_cpu(void *dummy) +void __noreturn stop_this_cpu(void *dummy) { local_irq_disable(); /* diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 3402edec236c..e459253649be 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -681,7 +681,7 @@ void set_personality_64bit(void) static void __set_personality_x32(void) { -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI if (current->mm) current->mm->context.flags = 0; diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S index 399f075ccdc4..c1d8626c53b6 100644 --- a/arch/x86/kernel/relocate_kernel_64.S +++ b/arch/x86/kernel/relocate_kernel_64.S @@ -42,6 +42,7 @@ .code64 SYM_CODE_START_NOALIGN(relocate_kernel) UNWIND_HINT_EMPTY + ANNOTATE_NOENDBR /* * %rdi indirection_page * %rsi page_list @@ -114,6 +115,14 @@ SYM_CODE_START_LOCAL_NOALIGN(identity_mapped) /* store the start address on the stack */ pushq %rdx + /* + * Clear X86_CR4_CET (if it was set) such that we can clear CR0_WP + * below. + */ + movq %cr4, %rax + andq $~(X86_CR4_CET), %rax + movq %rax, %cr4 + /* * Set cr0 to a known state: * - Paging enabled @@ -215,6 +224,7 @@ SYM_CODE_END(identity_mapped) SYM_CODE_START_LOCAL_NOALIGN(virtual_mapped) UNWIND_HINT_EMPTY + ANNOTATE_NOENDBR // RET target, above movq RSP(%r8), %rsp movq CR4(%r8), %rax movq %rax, %cr4 diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 2e37862e3a8c..1563fb995005 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c @@ -210,6 +210,81 @@ DEFINE_IDTENTRY(exc_overflow) do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL); } +#ifdef CONFIG_X86_KERNEL_IBT + +static __ro_after_init bool ibt_fatal = true; + +extern void ibt_selftest_ip(void); /* code label defined in asm below */ + +enum cp_error_code { + CP_EC = (1 << 15) - 1, + + CP_RET = 1, + CP_IRET = 2, + CP_ENDBR = 3, + CP_RSTRORSSP = 4, + CP_SETSSBSY = 5, + + CP_ENCL = 1 << 15, +}; + +DEFINE_IDTENTRY_ERRORCODE(exc_control_protection) +{ + if (!cpu_feature_enabled(X86_FEATURE_IBT)) { + pr_err("Unexpected #CP\n"); + BUG(); + } + + if (WARN_ON_ONCE(user_mode(regs) || (error_code & CP_EC) != CP_ENDBR)) + return; + + if (unlikely(regs->ip == (unsigned long)&ibt_selftest_ip)) { + regs->ax = 0; + return; + } + + pr_err("Missing ENDBR: %pS\n", (void *)instruction_pointer(regs)); + if (!ibt_fatal) { + printk(KERN_DEFAULT CUT_HERE); + __warn(__FILE__, __LINE__, (void *)regs->ip, TAINT_WARN, regs, NULL); + return; + } + BUG(); +} + +/* Must be noinline to ensure uniqueness of ibt_selftest_ip. */ +noinline bool ibt_selftest(void) +{ + unsigned long ret; + + asm (" lea ibt_selftest_ip(%%rip), %%rax\n\t" + ANNOTATE_RETPOLINE_SAFE + " jmp *%%rax\n\t" + "ibt_selftest_ip:\n\t" + UNWIND_HINT_FUNC + ANNOTATE_NOENDBR + " nop\n\t" + + : "=a" (ret) : : "memory"); + + return !ret; +} + +static int __init ibt_setup(char *str) +{ + if (!strcmp(str, "off")) + setup_clear_cpu_cap(X86_FEATURE_IBT); + + if (!strcmp(str, "warn")) + ibt_fatal = false; + + return 1; +} + +__setup("ibt=", ibt_setup); + +#endif /* CONFIG_X86_KERNEL_IBT */ + #ifdef CONFIG_X86_F00F_BUG void handle_invalid_op(struct pt_regs *regs) #else diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a698196377be..cafacb2e58cc 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1487,6 +1487,9 @@ static unsigned long __init get_loops_per_jiffy(void) static void __init tsc_enable_sched_clock(void) { + loops_per_jiffy = get_loops_per_jiffy(); + use_tsc_delay(); + /* Sanitize TSC ADJUST before cyc2ns gets initialized */ tsc_store_and_check_tsc_adjust(true); cyc2ns_init_boot_cpu(); @@ -1502,8 +1505,6 @@ void __init tsc_early_init(void) return; if (!determine_cpu_tsc_frequencies(true)) return; - loops_per_jiffy = get_loops_per_jiffy(); - tsc_enable_sched_clock(); } @@ -1537,7 +1538,6 @@ void __init tsc_init(void) enable_sched_clock_irqtime(); lpj_fine = get_loops_per_jiffy(); - use_tsc_delay(); check_system_tsc_reliable(); diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index 27f830345b6f..7fda7f27e762 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -285,6 +285,15 @@ SECTIONS } #endif +#ifdef CONFIG_X86_KERNEL_IBT + . = ALIGN(8); + .ibt_endbr_seal : AT(ADDR(.ibt_endbr_seal) - LOAD_OFFSET) { + __ibt_endbr_seal = .; + *(.ibt_endbr_seal) + __ibt_endbr_seal_end = .; + } +#endif + /* * struct alt_inst entries. From the header (alternative.h): * "Alternative instructions for different CPU types or capabilities" diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 7ba4ec77feeb..f9c00c89829b 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "x86.h" #include "tss.h" @@ -189,7 +190,7 @@ #define X16(x...) X8(x), X8(x) #define NR_FASTOP (ilog2(sizeof(ulong)) + 1) -#define FASTOP_SIZE 8 +#define FASTOP_SIZE (8 * (1 + HAS_KERNEL_IBT)) struct opcode { u64 flags; @@ -311,7 +312,8 @@ static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop); #define __FOP_FUNC(name) \ ".align " __stringify(FASTOP_SIZE) " \n\t" \ ".type " name ", @function \n\t" \ - name ":\n\t" + name ":\n\t" \ + ASM_ENDBR #define FOP_FUNC(name) \ __FOP_FUNC(#name) @@ -433,21 +435,23 @@ static int fastop(struct x86_emulate_ctxt *ctxt, fastop_t fop); /* * Depending on .config the SETcc functions look like: * + * ENDBR [4 bytes; CONFIG_X86_KERNEL_IBT] * SETcc %al [3 bytes] * RET [1 byte] * INT3 [1 byte; CONFIG_SLS] * - * Which gives possible sizes 4 or 5. When rounded up to the - * next power-of-two alignment they become 4 or 8. + * Which gives possible sizes 4, 5, 8 or 9. When rounded up to the + * next power-of-two alignment they become 4, 8 or 16 resp. */ -#define SETCC_LENGTH (4 + IS_ENABLED(CONFIG_SLS)) -#define SETCC_ALIGN (4 << IS_ENABLED(CONFIG_SLS)) +#define SETCC_LENGTH (ENDBR_INSN_SIZE + 4 + IS_ENABLED(CONFIG_SLS)) +#define SETCC_ALIGN (4 << IS_ENABLED(CONFIG_SLS) << HAS_KERNEL_IBT) static_assert(SETCC_LENGTH <= SETCC_ALIGN); #define FOP_SETCC(op) \ ".align " __stringify(SETCC_ALIGN) " \n\t" \ ".type " #op ", @function \n\t" \ #op ": \n\t" \ + ASM_ENDBR \ #op " %al \n\t" \ __FOP_RET(#op) diff --git a/arch/x86/lib/error-inject.c b/arch/x86/lib/error-inject.c index 520897061ee0..1e3de0769b81 100644 --- a/arch/x86/lib/error-inject.c +++ b/arch/x86/lib/error-inject.c @@ -3,6 +3,7 @@ #include #include #include +#include asmlinkage void just_return_func(void); @@ -11,6 +12,7 @@ asm( ".type just_return_func, @function\n" ".globl just_return_func\n" "just_return_func:\n" + ANNOTATE_NOENDBR ASM_RET ".size just_return_func, .-just_return_func\n" ); diff --git a/arch/x86/lib/retpoline.S b/arch/x86/lib/retpoline.S index afbdda539b80..5f87bab4fb8d 100644 --- a/arch/x86/lib/retpoline.S +++ b/arch/x86/lib/retpoline.S @@ -55,6 +55,7 @@ SYM_INNER_LABEL(__x86_indirect_thunk_\reg, SYM_L_GLOBAL) .align RETPOLINE_THUNK_SIZE SYM_CODE_START(__x86_indirect_thunk_array) + ANNOTATE_NOENDBR // apply_retpolines #define GEN(reg) THUNK reg #include diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index 6efbb87f65ed..8fe35ed11fd6 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -46,6 +46,12 @@ static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len) #define EMIT4_off32(b1, b2, b3, b4, off) \ do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0) +#ifdef CONFIG_X86_KERNEL_IBT +#define EMIT_ENDBR() EMIT(gen_endbr(), 4) +#else +#define EMIT_ENDBR() +#endif + static bool is_imm8(int value) { return value <= 127 && value >= -128; @@ -241,7 +247,7 @@ struct jit_context { /* Number of bytes emit_patch() needs to generate instructions */ #define X86_PATCH_SIZE 5 /* Number of bytes that will be skipped on tailcall */ -#define X86_TAIL_CALL_OFFSET 11 +#define X86_TAIL_CALL_OFFSET (11 + ENDBR_INSN_SIZE) static void push_callee_regs(u8 **pprog, bool *callee_regs_used) { @@ -286,6 +292,7 @@ static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf, /* BPF trampoline can be made to work without these nops, * but let's waste 5 bytes for now and optimize later */ + EMIT_ENDBR(); memcpy(prog, x86_nops[5], X86_PATCH_SIZE); prog += X86_PATCH_SIZE; if (!ebpf_from_cbpf) { @@ -296,6 +303,10 @@ static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf, } EMIT1(0x55); /* push rbp */ EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ + + /* X86_TAIL_CALL_OFFSET is here */ + EMIT_ENDBR(); + /* sub rsp, rounded_stack_depth */ if (stack_depth) EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8)); @@ -380,6 +391,13 @@ int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t, /* BPF poking in modules is not supported */ return -EINVAL; + /* + * See emit_prologue(), for IBT builds the trampoline hook is preceded + * with an ENDBR instruction. + */ + if (is_endbr(*(u32 *)ip)) + ip += ENDBR_INSN_SIZE; + return __bpf_arch_text_poke(ip, t, old_addr, new_addr); } @@ -2013,14 +2031,18 @@ int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *i ip_off = stack_size; - if (flags & BPF_TRAMP_F_SKIP_FRAME) + if (flags & BPF_TRAMP_F_SKIP_FRAME) { /* skip patched call instruction and point orig_call to actual * body of the kernel function. */ + if (is_endbr(*(u32 *)orig_call)) + orig_call += ENDBR_INSN_SIZE; orig_call += X86_PATCH_SIZE; + } prog = image; + EMIT_ENDBR(); EMIT1(0x55); /* push rbp */ EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */ EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */ diff --git a/arch/x86/platform/efi/Makefile b/arch/x86/platform/efi/Makefile index 84b09c230cbd..a50245157685 100644 --- a/arch/x86/platform/efi/Makefile +++ b/arch/x86/platform/efi/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -OBJECT_FILES_NON_STANDARD_efi_thunk_$(BITS).o := y KASAN_SANITIZE := n GCOV_PROFILE := n diff --git a/arch/x86/platform/efi/efi_thunk_64.S b/arch/x86/platform/efi/efi_thunk_64.S index 25799d768624..854dd81804b7 100644 --- a/arch/x86/platform/efi/efi_thunk_64.S +++ b/arch/x86/platform/efi/efi_thunk_64.S @@ -20,12 +20,14 @@ */ #include +#include #include #include .text .code64 -SYM_CODE_START(__efi64_thunk) +SYM_FUNC_START(__efi64_thunk) +STACK_FRAME_NON_STANDARD __efi64_thunk push %rbp push %rbx @@ -79,7 +81,7 @@ SYM_CODE_START(__efi64_thunk) 2: pushl $__KERNEL_CS pushl %ebp lret -SYM_CODE_END(__efi64_thunk) +SYM_FUNC_END(__efi64_thunk) .bss .balign 8 diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index d47c3d176ae4..5038edb79ad5 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -624,6 +624,9 @@ static struct trap_array_entry trap_array[] = { TRAP_ENTRY(exc_coprocessor_error, false ), TRAP_ENTRY(exc_alignment_check, false ), TRAP_ENTRY(exc_simd_coprocessor_error, false ), +#ifdef CONFIG_X86_KERNEL_IBT + TRAP_ENTRY(exc_control_protection, false ), +#endif }; static bool __ref get_trap_addr(void **addr, unsigned int ist) @@ -1177,6 +1180,8 @@ static void __init xen_domu_set_legacy_features(void) x86_platform.legacy.rtc = 0; } +extern void early_xen_iret_patch(void); + /* First C function to be called on Xen boot */ asmlinkage __visible void __init xen_start_kernel(void) { @@ -1187,6 +1192,10 @@ asmlinkage __visible void __init xen_start_kernel(void) if (!xen_start_info) return; + __text_gen_insn(&early_xen_iret_patch, + JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret, + JMP32_INSN_SIZE); + xen_domain_type = XEN_PV_DOMAIN; xen_start_flags = xen_start_info->flags; @@ -1195,7 +1204,6 @@ asmlinkage __visible void __init xen_start_kernel(void) /* Install Xen paravirt ops */ pv_info = xen_info; pv_ops.cpu = xen_cpu_ops.cpu; - paravirt_iret = xen_iret; xen_init_irq_ops(); /* diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S index e730e6200e64..caa9bc2fa100 100644 --- a/arch/x86/xen/xen-asm.S +++ b/arch/x86/xen/xen-asm.S @@ -122,6 +122,7 @@ SYM_FUNC_END(xen_read_cr2_direct); .macro xen_pv_trap name SYM_CODE_START(xen_\name) UNWIND_HINT_EMPTY + ENDBR pop %rcx pop %r11 jmp \name @@ -147,6 +148,9 @@ xen_pv_trap asm_exc_page_fault xen_pv_trap asm_exc_spurious_interrupt_bug xen_pv_trap asm_exc_coprocessor_error xen_pv_trap asm_exc_alignment_check +#ifdef CONFIG_X86_KERNEL_IBT +xen_pv_trap asm_exc_control_protection +#endif #ifdef CONFIG_X86_MCE xen_pv_trap asm_xenpv_exc_machine_check #endif /* CONFIG_X86_MCE */ @@ -162,6 +166,7 @@ SYM_CODE_START(xen_early_idt_handler_array) i = 0 .rept NUM_EXCEPTION_VECTORS UNWIND_HINT_EMPTY + ENDBR pop %rcx pop %r11 jmp early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE @@ -189,6 +194,7 @@ hypercall_iret = hypercall_page + __HYPERVISOR_iret * 32 */ SYM_CODE_START(xen_iret) UNWIND_HINT_EMPTY + ANNOTATE_NOENDBR pushq $0 jmp hypercall_iret SYM_CODE_END(xen_iret) @@ -230,6 +236,7 @@ SYM_CODE_END(xenpv_restore_regs_and_return_to_usermode) /* Normal 64-bit system call target */ SYM_CODE_START(xen_syscall_target) UNWIND_HINT_EMPTY + ENDBR popq %rcx popq %r11 @@ -249,6 +256,7 @@ SYM_CODE_END(xen_syscall_target) /* 32-bit compat syscall target */ SYM_CODE_START(xen_syscall32_target) UNWIND_HINT_EMPTY + ENDBR popq %rcx popq %r11 @@ -266,6 +274,7 @@ SYM_CODE_END(xen_syscall32_target) /* 32-bit compat sysenter target */ SYM_CODE_START(xen_sysenter_target) UNWIND_HINT_EMPTY + ENDBR /* * NB: Xen is polite and clears TF from EFLAGS for us. This means * that we don't need to guard against single step exceptions here. @@ -289,6 +298,7 @@ SYM_CODE_END(xen_sysenter_target) SYM_CODE_START(xen_syscall32_target) SYM_CODE_START(xen_sysenter_target) UNWIND_HINT_EMPTY + ENDBR lea 16(%rsp), %rsp /* strip %rcx, %r11 */ mov $-ENOSYS, %rax pushq $0 diff --git a/arch/x86/xen/xen-head.S b/arch/x86/xen/xen-head.S index 11d286529fe5..ac17196e2518 100644 --- a/arch/x86/xen/xen-head.S +++ b/arch/x86/xen/xen-head.S @@ -25,8 +25,12 @@ SYM_CODE_START(hypercall_page) .rept (PAGE_SIZE / 32) UNWIND_HINT_FUNC - .skip 31, 0x90 - RET + ANNOTATE_NOENDBR + ret + /* + * Xen will write the hypercall page, and sort out ENDBR. + */ + .skip 31, 0xcc .endr #define HYPERCALL(n) \ @@ -74,6 +78,7 @@ SYM_CODE_END(startup_xen) .pushsection .text SYM_CODE_START(asm_cpu_bringup_and_idle) UNWIND_HINT_EMPTY + ENDBR call cpu_bringup_and_idle SYM_CODE_END(asm_cpu_bringup_and_idle) diff --git a/drivers/leds/flash/leds-sgm3140.c b/drivers/leds/flash/leds-sgm3140.c index f4f831570f11..d3a30ad94ac4 100644 --- a/drivers/leds/flash/leds-sgm3140.c +++ b/drivers/leds/flash/leds-sgm3140.c @@ -290,6 +290,7 @@ static int sgm3140_remove(struct platform_device *pdev) } static const struct of_device_id sgm3140_dt_match[] = { + { .compatible = "ocs,ocp8110" }, { .compatible = "sgmicro,sgm3140" }, { /* sentinel */ } }; diff --git a/drivers/leds/leds-lm3692x.c b/drivers/leds/leds-lm3692x.c index afe6fb297855..87cd24ce3f95 100644 --- a/drivers/leds/leds-lm3692x.c +++ b/drivers/leds/leds-lm3692x.c @@ -494,11 +494,8 @@ static int lm3692x_probe(struct i2c_client *client, static int lm3692x_remove(struct i2c_client *client) { struct lm3692x_led *led = i2c_get_clientdata(client); - int ret; - ret = lm3692x_leds_disable(led); - if (ret) - return ret; + lm3692x_leds_disable(led); mutex_destroy(&led->lock); return 0; diff --git a/drivers/leds/leds-pca955x.c b/drivers/leds/leds-pca955x.c index a6b5699aeae4..81aaf21212d7 100644 --- a/drivers/leds/leds-pca955x.c +++ b/drivers/leds/leds-pca955x.c @@ -37,6 +37,7 @@ * bits the chip supports. */ +#include #include #include #include @@ -118,6 +119,7 @@ struct pca955x { struct pca955x_led *leds; struct pca955x_chipdef *chipdef; struct i2c_client *client; + unsigned long active_pins; #ifdef CONFIG_LEDS_PCA955X_GPIO struct gpio_chip gpio; #endif @@ -360,12 +362,15 @@ static int pca955x_read_input(struct i2c_client *client, int n, u8 *val) static int pca955x_gpio_request_pin(struct gpio_chip *gc, unsigned int offset) { struct pca955x *pca955x = gpiochip_get_data(gc); - struct pca955x_led *led = &pca955x->leds[offset]; - if (led->type == PCA955X_TYPE_GPIO) - return 0; + return test_and_set_bit(offset, &pca955x->active_pins) ? -EBUSY : 0; +} - return -EBUSY; +static void pca955x_gpio_free_pin(struct gpio_chip *gc, unsigned int offset) +{ + struct pca955x *pca955x = gpiochip_get_data(gc); + + clear_bit(offset, &pca955x->active_pins); } static int pca955x_set_value(struct gpio_chip *gc, unsigned int offset, @@ -424,7 +429,7 @@ pca955x_get_pdata(struct i2c_client *client, struct pca955x_chipdef *chip) int count; count = device_get_child_node_count(&client->dev); - if (!count || count > chip->bits) + if (count > chip->bits) return ERR_PTR(-ENODEV); pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); @@ -489,7 +494,6 @@ static int pca955x_probe(struct i2c_client *client) struct i2c_adapter *adapter; int i, err; struct pca955x_platform_data *pdata; - int ngpios = 0; bool set_default_label = false; bool keep_pwm = false; char default_label[8]; @@ -567,9 +571,7 @@ static int pca955x_probe(struct i2c_client *client) switch (pca955x_led->type) { case PCA955X_TYPE_NONE: - break; case PCA955X_TYPE_GPIO: - ngpios++; break; case PCA955X_TYPE_LED: led = &pca955x_led->led_cdev; @@ -613,6 +615,8 @@ static int pca955x_probe(struct i2c_client *client) if (err) return err; + set_bit(i, &pca955x->active_pins); + /* * For default-state == "keep", let the core update the * brightness from the hardware, then check the @@ -650,31 +654,30 @@ static int pca955x_probe(struct i2c_client *client) return err; #ifdef CONFIG_LEDS_PCA955X_GPIO - if (ngpios) { - pca955x->gpio.label = "gpio-pca955x"; - pca955x->gpio.direction_input = pca955x_gpio_direction_input; - pca955x->gpio.direction_output = pca955x_gpio_direction_output; - pca955x->gpio.set = pca955x_gpio_set_value; - pca955x->gpio.get = pca955x_gpio_get_value; - pca955x->gpio.request = pca955x_gpio_request_pin; - pca955x->gpio.can_sleep = 1; - pca955x->gpio.base = -1; - pca955x->gpio.ngpio = ngpios; - pca955x->gpio.parent = &client->dev; - pca955x->gpio.owner = THIS_MODULE; + pca955x->gpio.label = "gpio-pca955x"; + pca955x->gpio.direction_input = pca955x_gpio_direction_input; + pca955x->gpio.direction_output = pca955x_gpio_direction_output; + pca955x->gpio.set = pca955x_gpio_set_value; + pca955x->gpio.get = pca955x_gpio_get_value; + pca955x->gpio.request = pca955x_gpio_request_pin; + pca955x->gpio.free = pca955x_gpio_free_pin; + pca955x->gpio.can_sleep = 1; + pca955x->gpio.base = -1; + pca955x->gpio.ngpio = chip->bits; + pca955x->gpio.parent = &client->dev; + pca955x->gpio.owner = THIS_MODULE; - err = devm_gpiochip_add_data(&client->dev, &pca955x->gpio, - pca955x); - if (err) { - /* Use data->gpio.dev as a flag for freeing gpiochip */ - pca955x->gpio.parent = NULL; - dev_warn(&client->dev, "could not add gpiochip\n"); - return err; - } - dev_info(&client->dev, "gpios %i...%i\n", - pca955x->gpio.base, pca955x->gpio.base + - pca955x->gpio.ngpio - 1); + err = devm_gpiochip_add_data(&client->dev, &pca955x->gpio, + pca955x); + if (err) { + /* Use data->gpio.dev as a flag for freeing gpiochip */ + pca955x->gpio.parent = NULL; + dev_warn(&client->dev, "could not add gpiochip\n"); + return err; } + dev_info(&client->dev, "gpios %i...%i\n", + pca955x->gpio.base, pca955x->gpio.base + + pca955x->gpio.ngpio - 1); #endif return 0; diff --git a/drivers/leds/simple/simatic-ipc-leds.c b/drivers/leds/simple/simatic-ipc-leds.c index ff2c96e73241..078d43f5ba38 100644 --- a/drivers/leds/simple/simatic-ipc-leds.c +++ b/drivers/leds/simple/simatic-ipc-leds.c @@ -39,9 +39,9 @@ static struct simatic_ipc_led simatic_ipc_leds_io[] = { }; /* the actual start will be discovered with PCI, 0 is a placeholder */ -struct resource simatic_ipc_led_mem_res = DEFINE_RES_MEM_NAMED(0, SZ_4K, KBUILD_MODNAME); +static struct resource simatic_ipc_led_mem_res = DEFINE_RES_MEM_NAMED(0, SZ_4K, KBUILD_MODNAME); -static void *simatic_ipc_led_memory; +static void __iomem *simatic_ipc_led_memory; static struct simatic_ipc_led simatic_ipc_leds_mem[] = { {0x500 + 0x1A0, "red:" LED_FUNCTION_STATUS "-1"}, @@ -92,21 +92,22 @@ static void simatic_ipc_led_set_mem(struct led_classdev *led_cd, enum led_brightness brightness) { struct simatic_ipc_led *led = cdev_to_led(led_cd); + void __iomem *reg = simatic_ipc_led_memory + led->value; + u32 val; - u32 *p; - - p = simatic_ipc_led_memory + led->value; - *p = (*p & ~1) | (brightness == LED_OFF); + val = readl(reg); + val = (val & ~1) | (brightness == LED_OFF); + writel(val, reg); } static enum led_brightness simatic_ipc_led_get_mem(struct led_classdev *led_cd) { struct simatic_ipc_led *led = cdev_to_led(led_cd); + void __iomem *reg = simatic_ipc_led_memory + led->value; + u32 val; - u32 *p; - - p = simatic_ipc_led_memory + led->value; - return (*p & 1) ? LED_OFF : led_cd->max_brightness; + val = readl(reg); + return (val & 1) ? LED_OFF : led_cd->max_brightness; } static int simatic_ipc_leds_probe(struct platform_device *pdev) @@ -116,8 +117,9 @@ static int simatic_ipc_leds_probe(struct platform_device *pdev) struct simatic_ipc_led *ipcled; struct led_classdev *cdev; struct resource *res; + void __iomem *reg; int err, type; - u32 *p; + u32 val; switch (plat->devmode) { case SIMATIC_IPC_DEVICE_227D: @@ -157,11 +159,13 @@ static int simatic_ipc_leds_probe(struct platform_device *pdev) return PTR_ERR(simatic_ipc_led_memory); /* initialize power/watchdog LED */ - p = simatic_ipc_led_memory + 0x500 + 0x1D8; /* PM_WDT_OUT */ - *p = (*p & ~1); - p = simatic_ipc_led_memory + 0x500 + 0x1C0; /* PM_BIOS_BOOT_N */ - *p = (*p | 1); + reg = simatic_ipc_led_memory + 0x500 + 0x1D8; /* PM_WDT_OUT */ + val = readl(reg); + writel(val & ~1, reg); + reg = simatic_ipc_led_memory + 0x500 + 0x1C0; /* PM_BIOS_BOOT_N */ + val = readl(reg); + writel(val | 1, reg); break; default: return -ENODEV; diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index d9cd3606040e..05d6fae800e3 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -238,6 +238,15 @@ config STM32_IPCC with hardware for Inter-Processor Communication Controller (IPCC) between processors. Say Y here if you want to have this support. +config MTK_ADSP_MBOX + tristate "MediaTek ADSP Mailbox Controller" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + Say yes here to add support for "MediaTek ADSP Mailbox Controller. + This mailbox driver is used to send notification or short message + between processors with ADSP. It will place the message to share + buffer and will access the ipc control. + config MTK_CMDQ_MBOX tristate "MediaTek CMDQ Mailbox Support" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 338cc05e5431..fc9376117111 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -49,6 +49,8 @@ obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o +obj-$(CONFIG_MTK_ADSP_MBOX) += mtk-adsp-mailbox.o + obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index 544de2db6453..e88f544a1548 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018 Pengutronix, Oleksij Rempel + * Copyright 2022 NXP, Peng Fan */ #include @@ -9,11 +10,13 @@ #include #include #include +#include #include #include #include #include #include +#include #include #define IMX_MU_CHANS 16 @@ -23,11 +26,15 @@ #define IMX_MU_S4_CHANS 2 #define IMX_MU_CHAN_NAME_SIZE 20 +#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000)) +#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000)) + +/* Please not change TX & RX */ enum imx_mu_chan_type { - IMX_MU_TYPE_TX, /* Tx */ - IMX_MU_TYPE_RX, /* Rx */ - IMX_MU_TYPE_TXDB, /* Tx doorbell */ - IMX_MU_TYPE_RXDB, /* Rx doorbell */ + IMX_MU_TYPE_TX = 0, /* Tx */ + IMX_MU_TYPE_RX = 1, /* Rx */ + IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */ + IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */ }; enum imx_mu_xcr { @@ -47,7 +54,7 @@ enum imx_mu_xsr { struct imx_sc_rpc_msg_max { struct imx_sc_rpc_msg hdr; - u32 data[7]; + u32 data[30]; }; struct imx_s4_rpc_msg_max { @@ -75,7 +82,8 @@ struct imx_mu_priv { struct imx_mu_con_priv con_priv[IMX_MU_CHANS]; const struct imx_mu_dcfg *dcfg; struct clk *clk; - int irq; + int irq[IMX_MU_CHANS]; + bool suspend; u32 xcr[4]; @@ -86,11 +94,13 @@ enum imx_mu_type { IMX_MU_V1, IMX_MU_V2 = BIT(1), IMX_MU_V2_S4 = BIT(15), + IMX_MU_V2_IRQ = BIT(16), }; struct imx_mu_dcfg { int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data); int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); + int (*rxdb)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); void (*init)(struct imx_mu_priv *priv); enum imx_mu_type type; u32 xTR; /* Transmit Register0 */ @@ -128,6 +138,55 @@ static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs) return ioread32(priv->base + offs); } +static int imx_mu_tx_waiting_write(struct imx_mu_priv *priv, u32 val, u32 idx) +{ + u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_TX_TOUT; + u32 status; + u32 can_write; + + dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx); + + do { + status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); + can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); + } while (!can_write && time_is_after_jiffies64(timeout_time)); + + if (!can_write) { + dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n", + val, idx, status); + return -ETIME; + } + + imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); + + return 0; +} + +static int imx_mu_rx_waiting_read(struct imx_mu_priv *priv, u32 *val, u32 idx) +{ + u64 timeout_time = get_jiffies_64() + IMX_MU_SECO_RX_TOUT; + u32 status; + u32 can_read; + + dev_dbg(priv->dev, "Trying to read from idx %d\n", idx); + + do { + status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); + can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); + } while (!can_read && time_is_after_jiffies64(timeout_time)); + + if (!can_read) { + dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n", + idx, status); + return -ETIME; + } + + *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); + dev_dbg(priv->dev, "Read %.8x\n", *val); + + return 0; +} + static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, enum imx_mu_xcr type, u32 set, u32 clr) { unsigned long flags; @@ -177,6 +236,16 @@ static int imx_mu_generic_rx(struct imx_mu_priv *priv, return 0; } +static int imx_mu_generic_rxdb(struct imx_mu_priv *priv, + struct imx_mu_con_priv *cp) +{ + imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), + priv->dcfg->xSR[IMX_MU_GSR]); + mbox_chan_received_data(cp->chan, NULL); + + return 0; +} + static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data) { u32 *arg = data; @@ -216,7 +285,7 @@ static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv * ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], xsr, xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr), - 0, 100); + 0, 5 * USEC_PER_SEC); if (ret) { dev_err(priv->dev, "Send data index: %d timeout\n", i); return ret; @@ -261,7 +330,8 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv * for (i = 1; i < size; i++) { ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, - xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, 100); + xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, + 5 * USEC_PER_SEC); if (ret) { dev_err(priv->dev, "timeout read idx %d\n", i); return ret; @@ -275,6 +345,125 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv * return 0; } +static int imx_mu_seco_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, + void *data) +{ + struct imx_sc_rpc_msg_max *msg = data; + u32 *arg = data; + u32 byte_size; + int err; + int i; + + dev_dbg(priv->dev, "Sending message\n"); + + switch (cp->type) { + case IMX_MU_TYPE_TXDB: + byte_size = msg->hdr.size * sizeof(u32); + if (byte_size > sizeof(*msg)) { + /* + * The real message size can be different to + * struct imx_sc_rpc_msg_max size + */ + dev_err(priv->dev, + "Exceed max msg size (%zu) on TX, got: %i\n", + sizeof(*msg), byte_size); + return -EINVAL; + } + + print_hex_dump_debug("from client ", DUMP_PREFIX_OFFSET, 4, 4, + data, byte_size, false); + + /* Send first word */ + dev_dbg(priv->dev, "Sending header\n"); + imx_mu_write(priv, *arg++, priv->dcfg->xTR); + + /* Send signaling */ + dev_dbg(priv->dev, "Sending signaling\n"); + imx_mu_xcr_rmw(priv, IMX_MU_GCR, + IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); + + /* Send words to fill the mailbox */ + for (i = 1; i < 4 && i < msg->hdr.size; i++) { + dev_dbg(priv->dev, "Sending word %d\n", i); + imx_mu_write(priv, *arg++, + priv->dcfg->xTR + (i % 4) * 4); + } + + /* Send rest of message waiting for remote read */ + for (; i < msg->hdr.size; i++) { + dev_dbg(priv->dev, "Sending word %d\n", i); + err = imx_mu_tx_waiting_write(priv, *arg++, i); + if (err) { + dev_err(priv->dev, "Timeout tx %d\n", i); + return err; + } + } + + /* Simulate hack for mbox framework */ + tasklet_schedule(&cp->txdb_tasklet); + + break; + default: + dev_warn_ratelimited(priv->dev, + "Send data on wrong channel type: %d\n", + cp->type); + return -EINVAL; + } + + return 0; +} + +static int imx_mu_seco_rxdb(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp) +{ + struct imx_sc_rpc_msg_max msg; + u32 *data = (u32 *)&msg; + u32 byte_size; + int err = 0; + int i; + + dev_dbg(priv->dev, "Receiving message\n"); + + /* Read header */ + dev_dbg(priv->dev, "Receiving header\n"); + *data++ = imx_mu_read(priv, priv->dcfg->xRR); + byte_size = msg.hdr.size * sizeof(u32); + if (byte_size > sizeof(msg)) { + dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n", + sizeof(msg), byte_size); + err = -EINVAL; + goto error; + } + + /* Read message waiting they are written */ + for (i = 1; i < msg.hdr.size; i++) { + dev_dbg(priv->dev, "Receiving word %d\n", i); + err = imx_mu_rx_waiting_read(priv, data++, i); + if (err) { + dev_err(priv->dev, "Timeout rx %d\n", i); + goto error; + } + } + + /* Clear GIP */ + imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), + priv->dcfg->xSR[IMX_MU_GSR]); + + print_hex_dump_debug("to client ", DUMP_PREFIX_OFFSET, 4, 4, + &msg, byte_size, false); + + /* send data to client */ + dev_dbg(priv->dev, "Sending message to client\n"); + mbox_chan_received_data(cp->chan, (void *)&msg); + + goto exit; + +error: + mbox_chan_received_data(cp->chan, ERR_PTR(err)); + +exit: + return err; +} + static void imx_mu_txdb_tasklet(unsigned long data) { struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data; @@ -326,14 +515,15 @@ static irqreturn_t imx_mu_isr(int irq, void *p) priv->dcfg->rx(priv, cp); } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && (cp->type == IMX_MU_TYPE_RXDB)) { - imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), - priv->dcfg->xSR[IMX_MU_GSR]); - mbox_chan_received_data(chan, NULL); + priv->dcfg->rxdb(priv, cp); } else { dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); return IRQ_NONE; } + if (priv->suspend) + pm_system_wakeup(); + return IRQ_HANDLED; } @@ -349,7 +539,7 @@ static int imx_mu_startup(struct mbox_chan *chan) { struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); struct imx_mu_con_priv *cp = chan->con_priv; - unsigned long irq_flag = IRQF_SHARED; + unsigned long irq_flag = 0; int ret; pm_runtime_get_sync(priv->dev); @@ -364,11 +554,12 @@ static int imx_mu_startup(struct mbox_chan *chan) if (!priv->dev->pm_domain) irq_flag |= IRQF_NO_SUSPEND; - ret = request_irq(priv->irq, imx_mu_isr, irq_flag, - cp->irq_desc, chan); + if (!(priv->dcfg->type & IMX_MU_V2_IRQ)) + irq_flag |= IRQF_SHARED; + + ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan); if (ret) { - dev_err(priv->dev, - "Unable to acquire IRQ %d\n", priv->irq); + dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]); return ret; } @@ -411,7 +602,7 @@ static void imx_mu_shutdown(struct mbox_chan *chan) break; } - free_irq(priv->irq, chan); + free_irq(priv->irq[cp->type], chan); pm_runtime_put_sync(priv->dev); } @@ -479,6 +670,27 @@ static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, return &mbox->chans[chan]; } +static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + u32 type; + + if (sp->args_count < 1) { + dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); + return ERR_PTR(-EINVAL); + } + + type = sp->args[0]; /* channel type */ + + /* Only supports TXDB and RXDB */ + if (type == IMX_MU_TYPE_TX || type == IMX_MU_TYPE_RX) { + dev_err(mbox->dev, "Invalid type: %d\n", type); + return ERR_PTR(-EINVAL); + } + + return imx_mu_xlate(mbox, sp); +} + static void imx_mu_init_generic(struct imx_mu_priv *priv) { unsigned int i; @@ -529,13 +741,19 @@ static void imx_mu_init_specific(struct imx_mu_priv *priv) imx_mu_write(priv, 0, priv->dcfg->xCR[i]); } +static void imx_mu_init_seco(struct imx_mu_priv *priv) +{ + imx_mu_init_generic(priv); + priv->mbox.of_xlate = imx_mu_seco_xlate; +} + static int imx_mu_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct imx_mu_priv *priv; const struct imx_mu_dcfg *dcfg; - int ret; + int i, ret; u32 size; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -548,14 +766,25 @@ static int imx_mu_probe(struct platform_device *pdev) if (IS_ERR(priv->base)) return PTR_ERR(priv->base); - priv->irq = platform_get_irq(pdev, 0); - if (priv->irq < 0) - return priv->irq; - dcfg = of_device_get_match_data(dev); if (!dcfg) return -EINVAL; priv->dcfg = dcfg; + if (priv->dcfg->type & IMX_MU_V2_IRQ) { + priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx"); + if (priv->irq[IMX_MU_TYPE_TX] < 0) + return priv->irq[IMX_MU_TYPE_TX]; + priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx"); + if (priv->irq[IMX_MU_TYPE_RX] < 0) + return priv->irq[IMX_MU_TYPE_RX]; + } else { + ret = platform_get_irq(pdev, 0); + if (ret < 0) + return ret; + + for (i = 0; i < IMX_MU_CHANS; i++) + priv->irq[i] = ret; + } if (priv->dcfg->type & IMX_MU_V2_S4) size = sizeof(struct imx_s4_rpc_msg_max); @@ -633,6 +862,7 @@ static int imx_mu_remove(struct platform_device *pdev) static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { .tx = imx_mu_generic_tx, .rx = imx_mu_generic_rx, + .rxdb = imx_mu_generic_rxdb, .init = imx_mu_init_generic, .xTR = 0x0, .xRR = 0x10, @@ -643,6 +873,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { .tx = imx_mu_generic_tx, .rx = imx_mu_generic_rx, + .rxdb = imx_mu_generic_rxdb, .init = imx_mu_init_generic, .xTR = 0x20, .xRR = 0x40, @@ -653,7 +884,9 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { .tx = imx_mu_generic_tx, .rx = imx_mu_generic_rx, + .rxdb = imx_mu_generic_rxdb, .init = imx_mu_init_generic, + .rxdb = imx_mu_generic_rxdb, .type = IMX_MU_V2, .xTR = 0x200, .xRR = 0x280, @@ -672,10 +905,33 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = { .xCR = {0x110, 0x114, 0x120, 0x128}, }; +static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = { + .tx = imx_mu_specific_tx, + .rx = imx_mu_specific_rx, + .init = imx_mu_init_specific, + .type = IMX_MU_V2 | IMX_MU_V2_S4 | IMX_MU_V2_IRQ, + .xTR = 0x200, + .xRR = 0x280, + .xSR = {0xC, 0x118, 0x124, 0x12C}, + .xCR = {0x110, 0x114, 0x120, 0x128}, +}; + static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = { .tx = imx_mu_specific_tx, .rx = imx_mu_specific_rx, .init = imx_mu_init_specific, + .rxdb = imx_mu_generic_rxdb, + .xTR = 0x0, + .xRR = 0x10, + .xSR = {0x20, 0x20, 0x20, 0x20}, + .xCR = {0x24, 0x24, 0x24, 0x24}, +}; + +static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = { + .tx = imx_mu_seco_tx, + .rx = imx_mu_generic_rx, + .rxdb = imx_mu_seco_rxdb, + .init = imx_mu_init_seco, .xTR = 0x0, .xRR = 0x10, .xSR = {0x20, 0x20, 0x20, 0x20}, @@ -687,7 +943,9 @@ static const struct of_device_id imx_mu_dt_ids[] = { { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx }, { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp }, { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 }, + { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 }, { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu }, + { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco }, { }, }; MODULE_DEVICE_TABLE(of, imx_mu_dt_ids); @@ -702,6 +960,8 @@ static int __maybe_unused imx_mu_suspend_noirq(struct device *dev) priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]); } + priv->suspend = true; + return 0; } @@ -718,11 +978,13 @@ static int __maybe_unused imx_mu_resume_noirq(struct device *dev) * send failed, may lead to system freeze. This issue * is observed by testing freeze mode suspend. */ - if (!imx_mu_read(priv, priv->dcfg->xCR[0]) && !priv->clk) { + if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) { for (i = 0; i < IMX_MU_xCR_MAX; i++) imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]); } + priv->suspend = false; + return 0; } diff --git a/drivers/mailbox/mtk-adsp-mailbox.c b/drivers/mailbox/mtk-adsp-mailbox.c new file mode 100644 index 000000000000..5e7378090c7b --- /dev/null +++ b/drivers/mailbox/mtk-adsp-mailbox.c @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 MediaTek Corporation. All rights reserved. + * Author: Allen-KH Cheng + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct mtk_adsp_mbox_priv { + struct device *dev; + struct mbox_controller mbox; + void __iomem *va_mboxreg; + const struct mtk_adsp_mbox_cfg *cfg; +}; + +struct mtk_adsp_mbox_cfg { + u32 set_in; + u32 set_out; + u32 clr_in; + u32 clr_out; +}; + +static inline struct mtk_adsp_mbox_priv *get_mtk_adsp_mbox_priv(struct mbox_controller *mbox) +{ + return container_of(mbox, struct mtk_adsp_mbox_priv, mbox); +} + +static irqreturn_t mtk_adsp_mbox_irq(int irq, void *data) +{ + struct mbox_chan *chan = data; + struct mtk_adsp_mbox_priv *priv = get_mtk_adsp_mbox_priv(chan->mbox); + u32 op = readl(priv->va_mboxreg + priv->cfg->set_out); + + writel(op, priv->va_mboxreg + priv->cfg->clr_out); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t mtk_adsp_mbox_isr(int irq, void *data) +{ + struct mbox_chan *chan = data; + + mbox_chan_received_data(chan, NULL); + + return IRQ_HANDLED; +} + +static struct mbox_chan *mtk_adsp_mbox_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + return mbox->chans; +} + +static int mtk_adsp_mbox_startup(struct mbox_chan *chan) +{ + struct mtk_adsp_mbox_priv *priv = get_mtk_adsp_mbox_priv(chan->mbox); + + /* Clear ADSP mbox command */ + writel(0xFFFFFFFF, priv->va_mboxreg + priv->cfg->clr_in); + writel(0xFFFFFFFF, priv->va_mboxreg + priv->cfg->clr_out); + + return 0; +} + +static void mtk_adsp_mbox_shutdown(struct mbox_chan *chan) +{ + struct mtk_adsp_mbox_priv *priv = get_mtk_adsp_mbox_priv(chan->mbox); + + /* Clear ADSP mbox command */ + writel(0xFFFFFFFF, priv->va_mboxreg + priv->cfg->clr_in); + writel(0xFFFFFFFF, priv->va_mboxreg + priv->cfg->clr_out); +} + +static int mtk_adsp_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mtk_adsp_mbox_priv *priv = get_mtk_adsp_mbox_priv(chan->mbox); + u32 *msg = data; + + writel(*msg, priv->va_mboxreg + priv->cfg->set_in); + + return 0; +} + +static bool mtk_adsp_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct mtk_adsp_mbox_priv *priv = get_mtk_adsp_mbox_priv(chan->mbox); + + return readl(priv->va_mboxreg + priv->cfg->set_in) == 0; +} + +static const struct mbox_chan_ops mtk_adsp_mbox_chan_ops = { + .send_data = mtk_adsp_mbox_send_data, + .startup = mtk_adsp_mbox_startup, + .shutdown = mtk_adsp_mbox_shutdown, + .last_tx_done = mtk_adsp_mbox_last_tx_done, +}; + +static int mtk_adsp_mbox_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mtk_adsp_mbox_priv *priv; + const struct mtk_adsp_mbox_cfg *cfg; + struct mbox_controller *mbox; + int ret, irq; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mbox = &priv->mbox; + mbox->dev = dev; + mbox->ops = &mtk_adsp_mbox_chan_ops; + mbox->txdone_irq = false; + mbox->txdone_poll = true; + mbox->of_xlate = mtk_adsp_mbox_xlate; + mbox->num_chans = 1; + mbox->chans = devm_kzalloc(dev, sizeof(*mbox->chans), GFP_KERNEL); + if (!mbox->chans) + return -ENOMEM; + + priv->va_mboxreg = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->va_mboxreg)) + return PTR_ERR(priv->va_mboxreg); + + cfg = of_device_get_match_data(dev); + if (!cfg) + return -EINVAL; + priv->cfg = cfg; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_threaded_irq(dev, irq, mtk_adsp_mbox_irq, + mtk_adsp_mbox_isr, IRQF_TRIGGER_NONE, + dev_name(dev), mbox->chans); + if (ret < 0) + return ret; + + platform_set_drvdata(pdev, priv); + + return devm_mbox_controller_register(dev, &priv->mbox); +} + +static const struct mtk_adsp_mbox_cfg mt8195_adsp_mbox_cfg = { + .set_in = 0x00, + .set_out = 0x1c, + .clr_in = 0x04, + .clr_out = 0x20, +}; + +static const struct of_device_id mtk_adsp_mbox_of_match[] = { + { .compatible = "mediatek,mt8195-adsp-mbox", .data = &mt8195_adsp_mbox_cfg }, + {}, +}; +MODULE_DEVICE_TABLE(of, mtk_adsp_mbox_of_match); + +static struct platform_driver mtk_adsp_mbox_driver = { + .probe = mtk_adsp_mbox_probe, + .driver = { + .name = "mtk_adsp_mbox", + .of_match_table = mtk_adsp_mbox_of_match, + }, +}; +module_platform_driver(mtk_adsp_mbox_driver); + +MODULE_AUTHOR("Allen-KH Cheng "); +MODULE_DESCRIPTION("MTK ADSP Mailbox Controller"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 9325d2abc745..80a54d81412e 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -146,6 +146,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data }, + { .compatible = "qcom,msm8976-apcs-kpss-global", .data = &msm8994_apcs_data }, { .compatible = "qcom,msm8994-apcs-kpss-global", .data = &msm8994_apcs_data }, { .compatible = "qcom,msm8996-apcs-hmss-global", .data = &msm8996_apcs_data }, { .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8994_apcs_data }, diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index acd0675da681..78f7265039c6 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -412,6 +412,11 @@ static int tegra_hsp_mailbox_flush(struct mbox_chan *chan, value = tegra_hsp_channel_readl(ch, HSP_SM_SHRD_MBOX); if ((value & HSP_SM_SHRD_MBOX_FULL) == 0) { mbox_chan_txdone(chan, 0); + + /* Wait until channel is empty */ + if (chan->active_req != NULL) + continue; + return 0; } diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index efb43b038596..ddac423ac1a9 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -2,7 +2,7 @@ /* * Texas Instruments' Message Manager Driver * - * Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/ * Nishanth Menon */ @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -100,6 +101,7 @@ struct ti_msgmgr_desc { * @queue_ctrl: Queue Control register * @chan: Mailbox channel * @rx_buff: Receive buffer pointer allocated at probe, max_message_size + * @polled_rx_mode: Use polling for rx instead of interrupts */ struct ti_queue_inst { char name[30]; @@ -113,6 +115,7 @@ struct ti_queue_inst { void __iomem *queue_ctrl; struct mbox_chan *chan; u32 *rx_buff; + bool polled_rx_mode; }; /** @@ -190,56 +193,17 @@ static inline bool ti_msgmgr_queue_is_error(const struct ti_msgmgr_desc *d, return val ? true : false; } -/** - * ti_msgmgr_queue_rx_interrupt() - Interrupt handler for receive Queue - * @irq: Interrupt number - * @p: Channel Pointer - * - * Return: -EINVAL if there is no instance - * IRQ_NONE if the interrupt is not ours. - * IRQ_HANDLED if the rx interrupt was successfully handled. - */ -static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) +static int ti_msgmgr_queue_rx_data(struct mbox_chan *chan, struct ti_queue_inst *qinst, + const struct ti_msgmgr_desc *desc) { - struct mbox_chan *chan = p; - struct device *dev = chan->mbox->dev; - struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); - struct ti_queue_inst *qinst = chan->con_priv; - const struct ti_msgmgr_desc *desc; - int msg_count, num_words; + int num_words; struct ti_msgmgr_message message; void __iomem *data_reg; u32 *word_data; - if (WARN_ON(!inst)) { - dev_err(dev, "no platform drv data??\n"); - return -EINVAL; - } - - /* Do I have an invalid interrupt source? */ - if (qinst->is_tx) { - dev_err(dev, "Cannot handle rx interrupt on tx channel %s\n", - qinst->name); - return IRQ_NONE; - } - - desc = inst->desc; - if (ti_msgmgr_queue_is_error(desc, qinst)) { - dev_err(dev, "Error on Rx channel %s\n", qinst->name); - return IRQ_NONE; - } - - /* Do I actually have messages to read? */ - msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst); - if (!msg_count) { - /* Shared IRQ? */ - dev_dbg(dev, "Spurious event - 0 pending data!\n"); - return IRQ_NONE; - } - /* * I have no idea about the protocol being used to communicate with the - * remote producer - 0 could be valid data, so I won't make a judgement + * remote producer - 0 could be valid data, so I wont make a judgement * of how many bytes I should be reading. Let the client figure this * out.. I just read the full message and pass it on.. */ @@ -273,6 +237,75 @@ static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) */ mbox_chan_received_data(chan, (void *)&message); + return 0; +} + +static int ti_msgmgr_queue_rx_poll_timeout(struct mbox_chan *chan, int timeout_us) +{ + struct device *dev = chan->mbox->dev; + struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); + struct ti_queue_inst *qinst = chan->con_priv; + const struct ti_msgmgr_desc *desc = inst->desc; + int msg_count; + int ret; + + ret = readl_poll_timeout_atomic(qinst->queue_state, msg_count, + (msg_count & desc->status_cnt_mask), + 10, timeout_us); + if (ret != 0) + return ret; + + ti_msgmgr_queue_rx_data(chan, qinst, desc); + + return 0; +} + +/** + * ti_msgmgr_queue_rx_interrupt() - Interrupt handler for receive Queue + * @irq: Interrupt number + * @p: Channel Pointer + * + * Return: -EINVAL if there is no instance + * IRQ_NONE if the interrupt is not ours. + * IRQ_HANDLED if the rx interrupt was successfully handled. + */ +static irqreturn_t ti_msgmgr_queue_rx_interrupt(int irq, void *p) +{ + struct mbox_chan *chan = p; + struct device *dev = chan->mbox->dev; + struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); + struct ti_queue_inst *qinst = chan->con_priv; + const struct ti_msgmgr_desc *desc; + int msg_count; + + if (WARN_ON(!inst)) { + dev_err(dev, "no platform drv data??\n"); + return -EINVAL; + } + + /* Do I have an invalid interrupt source? */ + if (qinst->is_tx) { + dev_err(dev, "Cannot handle rx interrupt on tx channel %s\n", + qinst->name); + return IRQ_NONE; + } + + desc = inst->desc; + if (ti_msgmgr_queue_is_error(desc, qinst)) { + dev_err(dev, "Error on Rx channel %s\n", qinst->name); + return IRQ_NONE; + } + + /* Do I actually have messages to read? */ + msg_count = ti_msgmgr_queue_get_num_messages(desc, qinst); + if (!msg_count) { + /* Shared IRQ? */ + dev_dbg(dev, "Spurious event - 0 pending data!\n"); + return IRQ_NONE; + } + + ti_msgmgr_queue_rx_data(chan, qinst, desc); + return IRQ_HANDLED; } @@ -336,6 +369,17 @@ static bool ti_msgmgr_last_tx_done(struct mbox_chan *chan) return msg_count ? false : true; } +static bool ti_msgmgr_chan_has_polled_queue_rx(struct mbox_chan *chan) +{ + struct ti_queue_inst *qinst; + + if (!chan) + return false; + + qinst = chan->con_priv; + return qinst->polled_rx_mode; +} + /** * ti_msgmgr_send_data() - Send data * @chan: Channel Pointer @@ -353,6 +397,7 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) struct ti_msgmgr_message *message = data; void __iomem *data_reg; u32 *word_data; + int ret = 0; if (WARN_ON(!inst)) { dev_err(dev, "no platform drv data??\n"); @@ -394,7 +439,12 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) if (data_reg <= qinst->queue_buff_end) writel(0, qinst->queue_buff_end); - return 0; + /* If we are in polled mode, wait for a response before proceeding */ + if (ti_msgmgr_chan_has_polled_queue_rx(message->chan_rx)) + ret = ti_msgmgr_queue_rx_poll_timeout(message->chan_rx, + message->timeout_rx_ms * 1000); + + return ret; } /** @@ -642,6 +692,54 @@ static int ti_msgmgr_queue_setup(int idx, struct device *dev, return 0; } +static int ti_msgmgr_queue_rx_set_polled_mode(struct ti_queue_inst *qinst, bool enable) +{ + if (enable) { + disable_irq(qinst->irq); + qinst->polled_rx_mode = true; + } else { + enable_irq(qinst->irq); + qinst->polled_rx_mode = false; + } + + return 0; +} + +static int ti_msgmgr_suspend(struct device *dev) +{ + struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); + struct ti_queue_inst *qinst; + int i; + + /* + * We must switch operation to polled mode now as drivers and the genpd + * layer may make late TI SCI calls to change clock and device states + * from the noirq phase of suspend. + */ + for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues; qinst++, i++) { + if (!qinst->is_tx) + ti_msgmgr_queue_rx_set_polled_mode(qinst, true); + } + + return 0; +} + +static int ti_msgmgr_resume(struct device *dev) +{ + struct ti_msgmgr_inst *inst = dev_get_drvdata(dev); + struct ti_queue_inst *qinst; + int i; + + for (qinst = inst->qinsts, i = 0; i < inst->num_valid_queues; qinst++, i++) { + if (!qinst->is_tx) + ti_msgmgr_queue_rx_set_polled_mode(qinst, false); + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(ti_msgmgr_pm_ops, ti_msgmgr_suspend, ti_msgmgr_resume); + /* Queue operations */ static const struct mbox_chan_ops ti_msgmgr_chan_ops = { .startup = ti_msgmgr_queue_startup, @@ -829,6 +927,7 @@ static struct platform_driver ti_msgmgr_driver = { .driver = { .name = "ti-msgmgr", .of_match_table = of_match_ptr(ti_msgmgr_of_match), + .pm = &ti_msgmgr_pm_ops, }, }; module_platform_driver(ti_msgmgr_driver); diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6fc56d6598e2..f52960d2dfbe 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -527,6 +527,7 @@ source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sprd/Kconfig" source "drivers/pinctrl/stm32/Kconfig" +source "drivers/pinctrl/sunplus/Kconfig" source "drivers/pinctrl/sunxi/Kconfig" source "drivers/pinctrl/tegra/Kconfig" source "drivers/pinctrl/ti/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index f64d29f614ec..e76f5cdc64b0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -62,7 +62,7 @@ obj-y += mediatek/ obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-y += mvebu/ obj-y += nomadik/ -obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ +obj-y += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_PINCTRL_RALINK) += ralink/ @@ -71,6 +71,7 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ +obj-y += sunplus/ obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig index ac1e400bbbac..8f4d89806fcb 100644 --- a/drivers/pinctrl/bcm/Kconfig +++ b/drivers/pinctrl/bcm/Kconfig @@ -29,6 +29,20 @@ config PINCTRL_BCM2835 help Say Y here to enable the Broadcom BCM2835 GPIO driver. +config PINCTRL_BCM4908 + tristate "Broadcom BCM4908 pinmux driver" + depends on OF && (ARCH_BCM4908 || COMPILE_TEST) + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + default ARCH_BCM4908 + help + Driver for BCM4908 family SoCs with integrated pin controller. + + If compiled as module it will be called pinctrl-bcm4908. + config PINCTRL_BCM63XX bool select PINMUX diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile index 00c7b7775e63..82b868ec1471 100644 --- a/drivers/pinctrl/bcm/Makefile +++ b/drivers/pinctrl/bcm/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o +obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o diff --git a/drivers/pinctrl/bcm/pinctrl-bcm4908.c b/drivers/pinctrl/bcm/pinctrl-bcm4908.c new file mode 100644 index 000000000000..cdfa165fc033 --- /dev/null +++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c @@ -0,0 +1,563 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2021 Rafał Miłecki */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../core.h" +#include "../pinmux.h" + +#define BCM4908_NUM_PINS 86 + +#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00 +#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04 +#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08 +#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12 +#define BCM4908_TEST_PORT_COMMAND 0x0c +#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021 + +struct bcm4908_pinctrl { + struct device *dev; + void __iomem *base; + struct mutex mutex; + struct pinctrl_dev *pctldev; + struct pinctrl_desc pctldesc; +}; + +/* + * Groups + */ + +struct bcm4908_pinctrl_pin_setup { + unsigned int number; + unsigned int function; +}; + +static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = { + { 0, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = { + { 1, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = { + { 2, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = { + { 3, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = { + { 4, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = { + { 5, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = { + { 6, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = { + { 7, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = { + { 8, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = { + { 9, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = { + { 10, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = { + { 11, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = { + { 12, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = { + { 13, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = { + { 14, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = { + { 15, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = { + { 16, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = { + { 17, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = { + { 18, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = { + { 19, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = { + { 20, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = { + { 21, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = { + { 22, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = { + { 23, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = { + { 24, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = { + { 25, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = { + { 26, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = { + { 27, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = { + { 28, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = { + { 29, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = { + { 30, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = { + { 31, 3 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = { + { 8, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = { + { 9, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = { + { 0, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = { + { 1, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = { + { 30, 2 }, +}; + +static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = { + { 10, 0 }, /* CTS */ + { 11, 0 }, /* RTS */ + { 12, 0 }, /* RXD */ + { 13, 0 }, /* TXD */ +}; + +static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = { + { 18, 0 }, /* SDA */ + { 19, 0 }, /* SCL */ +}; + +static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = { + { 22, 0 }, /* SDA */ + { 23, 0 }, /* SCL */ +}; + +static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = { + { 27, 0 }, /* MCLK */ + { 28, 0 }, /* LRCK */ + { 29, 0 }, /* SDATA */ + { 30, 0 }, /* SCLK */ +}; + +static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = { + { 32, 0 }, + { 33, 0 }, + { 34, 0 }, + { 43, 0 }, + { 44, 0 }, + { 45, 0 }, + { 56, 1 }, +}; + +static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = { + { 35, 0 }, + { 36, 0 }, + { 37, 0 }, + { 38, 0 }, + { 39, 0 }, + { 40, 0 }, + { 41, 0 }, + { 42, 0 }, +}; + +static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = { + { 46, 0 }, + { 47, 0 }, +}; + +static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = { + { 63, 0 }, + { 64, 0 }, +}; + +static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = { + { 66, 0 }, + { 67, 0 }, +}; + +struct bcm4908_pinctrl_grp { + const char *name; + const struct bcm4908_pinctrl_pin_setup *pins; + const unsigned int num_pins; +}; + +static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = { + { "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) }, + { "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) }, + { "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) }, + { "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) }, + { "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) }, + { "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) }, + { "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) }, + { "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) }, + { "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) }, + { "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) }, + { "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) }, + { "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) }, + { "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) }, + { "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) }, + { "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) }, + { "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) }, + { "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) }, + { "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) }, + { "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) }, + { "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) }, + { "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) }, + { "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) }, + { "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) }, + { "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) }, + { "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) }, + { "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) }, + { "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) }, + { "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) }, + { "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) }, + { "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) }, + { "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) }, + { "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) }, + { "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) }, + { "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) }, + { "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) }, + { "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) }, + { "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) }, + { "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) }, + { "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) }, + { "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) }, + { "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) }, + { "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) }, + { "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) }, + { "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) }, + { "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) }, + { "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) }, +}; + +/* + * Functions + */ + +struct bcm4908_pinctrl_function { + const char *name; + const char * const *groups; + const unsigned int num_groups; +}; + +static const char * const led_0_groups[] = { "led_0_grp_a" }; +static const char * const led_1_groups[] = { "led_1_grp_a" }; +static const char * const led_2_groups[] = { "led_2_grp_a" }; +static const char * const led_3_groups[] = { "led_3_grp_a" }; +static const char * const led_4_groups[] = { "led_4_grp_a" }; +static const char * const led_5_groups[] = { "led_5_grp_a" }; +static const char * const led_6_groups[] = { "led_6_grp_a" }; +static const char * const led_7_groups[] = { "led_7_grp_a" }; +static const char * const led_8_groups[] = { "led_8_grp_a" }; +static const char * const led_9_groups[] = { "led_9_grp_a" }; +static const char * const led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" }; +static const char * const led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" }; +static const char * const led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" }; +static const char * const led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" }; +static const char * const led_14_groups[] = { "led_14_grp_a" }; +static const char * const led_15_groups[] = { "led_15_grp_a" }; +static const char * const led_16_groups[] = { "led_16_grp_a" }; +static const char * const led_17_groups[] = { "led_17_grp_a" }; +static const char * const led_18_groups[] = { "led_18_grp_a" }; +static const char * const led_19_groups[] = { "led_19_grp_a" }; +static const char * const led_20_groups[] = { "led_20_grp_a" }; +static const char * const led_21_groups[] = { "led_21_grp_a" }; +static const char * const led_22_groups[] = { "led_22_grp_a" }; +static const char * const led_23_groups[] = { "led_23_grp_a" }; +static const char * const led_24_groups[] = { "led_24_grp_a" }; +static const char * const led_25_groups[] = { "led_25_grp_a" }; +static const char * const led_26_groups[] = { "led_26_grp_a" }; +static const char * const led_27_groups[] = { "led_27_grp_a" }; +static const char * const led_28_groups[] = { "led_28_grp_a" }; +static const char * const led_29_groups[] = { "led_29_grp_a" }; +static const char * const led_30_groups[] = { "led_30_grp_a" }; +static const char * const led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" }; +static const char * const hs_uart_groups[] = { "hs_uart_grp" }; +static const char * const i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" }; +static const char * const i2s_groups[] = { "i2s_grp" }; +static const char * const nand_ctrl_groups[] = { "nand_ctrl_grp" }; +static const char * const nand_data_groups[] = { "nand_data_grp" }; +static const char * const emmc_ctrl_groups[] = { "emmc_ctrl_grp" }; +static const char * const usb0_pwr_groups[] = { "usb0_pwr_grp" }; +static const char * const usb1_pwr_groups[] = { "usb1_pwr_grp" }; + +static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = { + { "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) }, + { "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) }, + { "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) }, + { "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) }, + { "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) }, + { "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) }, + { "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) }, + { "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) }, + { "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) }, + { "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) }, + { "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) }, + { "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) }, + { "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) }, + { "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) }, + { "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) }, + { "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) }, + { "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) }, + { "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) }, + { "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) }, + { "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) }, + { "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) }, + { "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) }, + { "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) }, + { "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) }, + { "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) }, + { "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) }, + { "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) }, + { "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) }, + { "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) }, + { "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) }, + { "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) }, + { "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) }, + { "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) }, + { "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) }, + { "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) }, + { "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) }, + { "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) }, + { "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) }, + { "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) }, + { "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) }, +}; + +/* + * Groups code + */ + +static const struct pinctrl_ops bcm4908_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +/* + * Functions code + */ + +static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev, + unsigned int func_selector, + unsigned int group_selector) +{ + struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); + const struct bcm4908_pinctrl_grp *group; + struct group_desc *group_desc; + int i; + + group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector); + if (!group_desc) + return -EINVAL; + group = group_desc->data; + + mutex_lock(&bcm4908_pinctrl->mutex); + for (i = 0; i < group->num_pins; i++) { + u32 lsb = 0; + + lsb |= group->pins[i].number; + lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT; + + writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB); + writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB); + writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG, + bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND); + } + mutex_unlock(&bcm4908_pinctrl->mutex); + + return 0; +} + +static const struct pinmux_ops bcm4908_pinctrl_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = bcm4908_pinctrl_set_mux, +}; + +/* + * Controller code + */ + +static struct pinctrl_desc bcm4908_pinctrl_desc = { + .name = "bcm4908-pinctrl", + .pctlops = &bcm4908_pinctrl_ops, + .pmxops = &bcm4908_pinctrl_pmxops, +}; + +static const struct of_device_id bcm4908_pinctrl_of_match_table[] = { + { .compatible = "brcm,bcm4908-pinctrl", }, + { } +}; + +static int bcm4908_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct bcm4908_pinctrl *bcm4908_pinctrl; + struct pinctrl_desc *pctldesc; + struct pinctrl_pin_desc *pins; + char **pin_names; + int i; + + bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL); + if (!bcm4908_pinctrl) + return -ENOMEM; + pctldesc = &bcm4908_pinctrl->pctldesc; + platform_set_drvdata(pdev, bcm4908_pinctrl); + + /* Set basic properties */ + + bcm4908_pinctrl->dev = dev; + + bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(bcm4908_pinctrl->base)) + return PTR_ERR(bcm4908_pinctrl->base); + + mutex_init(&bcm4908_pinctrl->mutex); + + memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc)); + + /* Set pinctrl properties */ + + pin_names = devm_kasprintf_strarray(dev, "pin", BCM4908_NUM_PINS); + if (IS_ERR(pin_names)) + return PTR_ERR(pin_names); + + pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + for (i = 0; i < BCM4908_NUM_PINS; i++) { + pins[i].number = i; + pins[i].name = pin_names[i]; + } + pctldesc->pins = pins; + pctldesc->npins = BCM4908_NUM_PINS; + + /* Register */ + + bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl); + if (IS_ERR(bcm4908_pinctrl->pctldev)) + return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev), + "Failed to register pinctrl\n"); + + /* Groups */ + + for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) { + const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i]; + int *pins; + int j; + + pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + for (j = 0; j < group->num_pins; j++) + pins[j] = group->pins[j].number; + + pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name, + pins, group->num_pins, (void *)group); + } + + /* Functions */ + + for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) { + const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i]; + + pinmux_generic_add_function(bcm4908_pinctrl->pctldev, + function->name, + function->groups, + function->num_groups, NULL); + } + + return 0; +} + +static struct platform_driver bcm4908_pinctrl_driver = { + .probe = bcm4908_pinctrl_probe, + .driver = { + .name = "bcm4908-pinctrl", + .of_match_table = bcm4908_pinctrl_of_match_table, + }, +}; + +module_platform_driver(bcm4908_pinctrl_driver); + +MODULE_AUTHOR("Rafał Miłecki"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table); diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index b17a03cf87be..a073eedd71aa 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -233,6 +233,8 @@ static int berlin_pinctrl_build_state(struct platform_device *pdev) pctrl->functions = krealloc(pctrl->functions, pctrl->nfunctions * sizeof(*pctrl->functions), GFP_KERNEL); + if (!pctrl->functions) + return -ENOMEM; /* map functions to theirs groups */ for (i = 0; i < pctrl->desc->ngroups; i++) { diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 8bdafaf40b29..453dc47f4fa4 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -180,6 +180,13 @@ config PINCTRL_IMXRT1050 help Say Y here to enable the imxrt1050 pinctrl driver +config PINCTRL_IMX93 + tristate "IMX93 pinctrl driver" + depends on ARCH_MXC + select PINCTRL_IMX + help + Say Y here to enable the imx93 pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 565a0350bf09..9f5d1c090338 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o obj-$(CONFIG_PINCTRL_IMX8ULP) += pinctrl-imx8ulp.o +obj-$(CONFIG_PINCTRL_IMX93) += pinctrl-imx93.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index fa3cc0b80ede..3a7d2de10b13 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -661,7 +661,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, func->name = np->name; func->num_group_names = of_get_child_count(np); if (func->num_group_names == 0) { - dev_err(ipctl->dev, "no groups defined in %pOF\n", np); + dev_info(ipctl->dev, "no groups defined in %pOF\n", np); return -EINVAL; } diff --git a/drivers/pinctrl/freescale/pinctrl-imx93.c b/drivers/pinctrl/freescale/pinctrl-imx93.c new file mode 100644 index 000000000000..c0630f69e995 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx93.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +enum imx93_pads { + IMX93_IOMUXC_DAP_TDI = 0, + IMX93_IOMUXC_DAP_TMS_SWDIO = 1, + IMX93_IOMUXC_DAP_TCLK_SWCLK = 2, + IMX93_IOMUXC_DAP_TDO_TRACESWO = 3, + IMX93_IOMUXC_GPIO_IO00 = 4, + IMX93_IOMUXC_GPIO_IO01 = 5, + IMX93_IOMUXC_GPIO_IO02 = 6, + IMX93_IOMUXC_GPIO_IO03 = 7, + IMX93_IOMUXC_GPIO_IO04 = 8, + IMX93_IOMUXC_GPIO_IO05 = 9, + IMX93_IOMUXC_GPIO_IO06 = 10, + IMX93_IOMUXC_GPIO_IO07 = 11, + IMX93_IOMUXC_GPIO_IO08 = 12, + IMX93_IOMUXC_GPIO_IO09 = 13, + IMX93_IOMUXC_GPIO_IO10 = 14, + IMX93_IOMUXC_GPIO_IO11 = 15, + IMX93_IOMUXC_GPIO_IO12 = 16, + IMX93_IOMUXC_GPIO_IO13 = 17, + IMX93_IOMUXC_GPIO_IO14 = 18, + IMX93_IOMUXC_GPIO_IO15 = 19, + IMX93_IOMUXC_GPIO_IO16 = 20, + IMX93_IOMUXC_GPIO_IO17 = 21, + IMX93_IOMUXC_GPIO_IO18 = 22, + IMX93_IOMUXC_GPIO_IO19 = 23, + IMX93_IOMUXC_GPIO_IO20 = 24, + IMX93_IOMUXC_GPIO_IO21 = 25, + IMX93_IOMUXC_GPIO_IO22 = 26, + IMX93_IOMUXC_GPIO_IO23 = 27, + IMX93_IOMUXC_GPIO_IO24 = 28, + IMX93_IOMUXC_GPIO_IO25 = 29, + IMX93_IOMUXC_GPIO_IO26 = 30, + IMX93_IOMUXC_GPIO_IO27 = 31, + IMX93_IOMUXC_GPIO_IO28 = 32, + IMX93_IOMUXC_GPIO_IO29 = 33, + IMX93_IOMUXC_CCM_CLKO1 = 34, + IMX93_IOMUXC_CCM_CLKO2 = 35, + IMX93_IOMUXC_CCM_CLKO3 = 36, + IMX93_IOMUXC_CCM_CLKO4 = 37, + IMX93_IOMUXC_ENET1_MDC = 38, + IMX93_IOMUXC_ENET1_MDIO = 39, + IMX93_IOMUXC_ENET1_TD3 = 40, + IMX93_IOMUXC_ENET1_TD2 = 41, + IMX93_IOMUXC_ENET1_TD1 = 42, + IMX93_IOMUXC_ENET1_TD0 = 43, + IMX93_IOMUXC_ENET1_TX_CTL = 44, + IMX93_IOMUXC_ENET1_TXC = 45, + IMX93_IOMUXC_ENET1_RX_CTL = 46, + IMX93_IOMUXC_ENET1_RXC = 47, + IMX93_IOMUXC_ENET1_RD0 = 48, + IMX93_IOMUXC_ENET1_RD1 = 49, + IMX93_IOMUXC_ENET1_RD2 = 50, + IMX93_IOMUXC_ENET1_RD3 = 51, + IMX93_IOMUXC_ENET2_MDC = 52, + IMX93_IOMUXC_ENET2_MDIO = 53, + IMX93_IOMUXC_ENET2_TD3 = 54, + IMX93_IOMUXC_ENET2_TD2 = 55, + IMX93_IOMUXC_ENET2_TD1 = 56, + IMX93_IOMUXC_ENET2_TD0 = 57, + IMX93_IOMUXC_ENET2_TX_CTL = 58, + IMX93_IOMUXC_ENET2_TXC = 59, + IMX93_IOMUXC_ENET2_RX_CTL = 60, + IMX93_IOMUXC_ENET2_RXC = 61, + IMX93_IOMUXC_ENET2_RD0 = 62, + IMX93_IOMUXC_ENET2_RD1 = 63, + IMX93_IOMUXC_ENET2_RD2 = 64, + IMX93_IOMUXC_ENET2_RD3 = 65, + IMX93_IOMUXC_SD1_CLK = 66, + IMX93_IOMUXC_SD1_CMD = 67, + IMX93_IOMUXC_SD1_DATA0 = 68, + IMX93_IOMUXC_SD1_DATA1 = 69, + IMX93_IOMUXC_SD1_DATA2 = 70, + IMX93_IOMUXC_SD1_DATA3 = 71, + IMX93_IOMUXC_SD1_DATA4 = 72, + IMX93_IOMUXC_SD1_DATA5 = 73, + IMX93_IOMUXC_SD1_DATA6 = 74, + IMX93_IOMUXC_SD1_DATA7 = 75, + IMX93_IOMUXC_SD1_STROBE = 76, + IMX93_IOMUXC_SD2_VSELECT = 77, + IMX93_IOMUXC_SD3_CLK = 78, + IMX93_IOMUXC_SD3_CMD = 79, + IMX93_IOMUXC_SD3_DATA0 = 80, + IMX93_IOMUXC_SD3_DATA1 = 81, + IMX93_IOMUXC_SD3_DATA2 = 82, + IMX93_IOMUXC_SD3_DATA3 = 83, + IMX93_IOMUXC_SD2_CD_B = 84, + IMX93_IOMUXC_SD2_CLK = 85, + IMX93_IOMUXC_SD2_CMD = 86, + IMX93_IOMUXC_SD2_DATA0 = 87, + IMX93_IOMUXC_SD2_DATA1 = 88, + IMX93_IOMUXC_SD2_DATA2 = 89, + IMX93_IOMUXC_SD2_DATA3 = 90, + IMX93_IOMUXC_SD2_RESET_B = 91, + IMX93_IOMUXC_I2C1_SCL = 92, + IMX93_IOMUXC_I2C1_SDA = 93, + IMX93_IOMUXC_I2C2_SCL = 94, + IMX93_IOMUXC_I2C2_SDA = 95, + IMX93_IOMUXC_UART1_RXD = 96, + IMX93_IOMUXC_UART1_TXD = 97, + IMX93_IOMUXC_UART2_RXD = 98, + IMX93_IOMUXC_UART2_TXD = 99, + IMX93_IOMUXC_PDM_CLK = 100, + IMX93_IOMUXC_PDM_BIT_STREAM0 = 101, + IMX93_IOMUXC_PDM_BIT_STREAM1 = 102, + IMX93_IOMUXC_SAI1_TXFS = 103, + IMX93_IOMUXC_SAI1_TXC = 104, + IMX93_IOMUXC_SAI1_TXD0 = 105, + IMX93_IOMUXC_SAI1_RXD0 = 106, + IMX93_IOMUXC_WDOG_ANY = 107, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx93_pinctrl_pads[] = { + IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDI), + IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TMS_SWDIO), + IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TCLK_SWCLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_DAP_TDO_TRACESWO), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO00), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO01), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO02), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO03), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO04), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO05), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO06), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO07), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO08), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO09), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO10), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO11), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO12), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO13), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO14), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO15), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO16), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO17), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO18), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO19), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO20), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO21), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO22), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO23), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO24), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO25), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO26), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO27), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO28), + IMX_PINCTRL_PIN(IMX93_IOMUXC_GPIO_IO29), + IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_CCM_CLKO4), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_MDIO), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TX_CTL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_TXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RX_CTL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET1_RD3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_MDIO), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TX_CTL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_TXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RX_CTL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_ENET2_RD3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_CMD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA4), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA5), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA6), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_DATA7), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD1_STROBE), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_VSELECT), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_CMD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD3_DATA3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CD_B), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_CMD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA2), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_DATA3), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SD2_RESET_B), + IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SCL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C1_SDA), + IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SCL), + IMX_PINCTRL_PIN(IMX93_IOMUXC_I2C2_SDA), + IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_RXD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_UART1_TXD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_RXD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_UART2_TXD), + IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_CLK), + IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_PDM_BIT_STREAM1), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXFS), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXC), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_TXD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_SAI1_RXD0), + IMX_PINCTRL_PIN(IMX93_IOMUXC_WDOG_ANY), +}; + +static const struct imx_pinctrl_soc_info imx93_pinctrl_info = { + .pins = imx93_pinctrl_pads, + .npins = ARRAY_SIZE(imx93_pinctrl_pads), + .gpr_compatible = "fsl,imx93-iomuxc-gpr", +}; + +static const struct of_device_id imx93_pinctrl_of_match[] = { + { .compatible = "fsl,imx93-iomuxc", }, + { /* sentinel */ } +}; + +static int imx93_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx93_pinctrl_info); +} + +static struct platform_driver imx93_pinctrl_driver = { + .driver = { + .name = "imx93-pinctrl", + .of_match_table = imx93_pinctrl_of_match, + .suppress_bind_attrs = true, + }, + .probe = imx93_pinctrl_probe, +}; + +static int __init imx93_pinctrl_init(void) +{ + return platform_driver_register(&imx93_pinctrl_driver); +} +arch_initcall(imx93_pinctrl_init); + +MODULE_AUTHOR("Bai Ping "); +MODULE_DESCRIPTION("NXP i.MX93 pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-alderlake.c b/drivers/pinctrl/intel/pinctrl-alderlake.c index efb664f12b5d..32ba50efbceb 100644 --- a/drivers/pinctrl/intel/pinctrl-alderlake.c +++ b/drivers/pinctrl/intel/pinctrl-alderlake.c @@ -2,7 +2,7 @@ /* * Intel Alder Lake PCH pinctrl/GPIO driver * - * Copyright (C) 2020, Intel Corporation + * Copyright (C) 2020, 2022 Intel Corporation * Author: Andy Shevchenko */ @@ -42,6 +42,319 @@ .ngpps = ARRAY_SIZE(g), \ } +/* Alder Lake-N */ +static const struct pinctrl_pin_desc adln_pins[] = { + /* GPP_B */ + PINCTRL_PIN(0, "CORE_VID_0"), + PINCTRL_PIN(1, "CORE_VID_1"), + PINCTRL_PIN(2, "GPPC_B_2"), + PINCTRL_PIN(3, "GPPC_B_3"), + PINCTRL_PIN(4, "GPPC_B_4"), + PINCTRL_PIN(5, "GPPC_B_5"), + PINCTRL_PIN(6, "GPPC_B_6"), + PINCTRL_PIN(7, "GPPC_B_7"), + PINCTRL_PIN(8, "GPPC_B_8"), + PINCTRL_PIN(9, "GPPC_B_9"), + PINCTRL_PIN(10, "GPPC_B_10"), + PINCTRL_PIN(11, "GPPC_B_11"), + PINCTRL_PIN(12, "SLP_S0B"), + PINCTRL_PIN(13, "PLTRSTB"), + PINCTRL_PIN(14, "GPPC_B_14"), + PINCTRL_PIN(15, "GPPC_B_15"), + PINCTRL_PIN(16, "GPPC_B_16"), + PINCTRL_PIN(17, "GPPC_B_17"), + PINCTRL_PIN(18, "GPPC_B_18"), + PINCTRL_PIN(19, "GPPC_B_19"), + PINCTRL_PIN(20, "GPPC_B_20"), + PINCTRL_PIN(21, "GPPC_B_21"), + PINCTRL_PIN(22, "GPPC_B_22"), + PINCTRL_PIN(23, "GPPC_B_23"), + PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), + /* GPP_T */ + PINCTRL_PIN(26, "GPPC_T_0"), + PINCTRL_PIN(27, "GPPC_T_1"), + PINCTRL_PIN(28, "FUSA_DIAGTEST_EN"), + PINCTRL_PIN(29, "FUSA_DIAGTEST_MODE"), + PINCTRL_PIN(30, "GPPC_T_4"), + PINCTRL_PIN(31, "GPPC_T_5"), + PINCTRL_PIN(32, "GPPC_T_6"), + PINCTRL_PIN(33, "GPPC_T_7"), + PINCTRL_PIN(34, "GPPC_T_8"), + PINCTRL_PIN(35, "GPPC_T_9"), + PINCTRL_PIN(36, "GPPC_T_10"), + PINCTRL_PIN(37, "GPPC_T_11"), + PINCTRL_PIN(38, "GPPC_T_12"), + PINCTRL_PIN(39, "GPPC_T_13"), + PINCTRL_PIN(40, "GPPC_T_14"), + PINCTRL_PIN(41, "GPPC_T_15"), + /* GPP_A */ + PINCTRL_PIN(42, "ESPI_IO_0"), + PINCTRL_PIN(43, "ESPI_IO_1"), + PINCTRL_PIN(44, "ESPI_IO_2"), + PINCTRL_PIN(45, "ESPI_IO_3"), + PINCTRL_PIN(46, "ESPI_CS0B"), + PINCTRL_PIN(47, "ESPI_ALERT0B"), + PINCTRL_PIN(48, "ESPI_ALERT1B"), + PINCTRL_PIN(49, "GPPC_A_7"), + PINCTRL_PIN(50, "GPPC_A_8"), + PINCTRL_PIN(51, "ESPI_CLK"), + PINCTRL_PIN(52, "ESPI_RESETB"), + PINCTRL_PIN(53, "GPPC_A_11"), + PINCTRL_PIN(54, "GPPC_A_12"), + PINCTRL_PIN(55, "GPPC_A_13"), + PINCTRL_PIN(56, "GPPC_A_14"), + PINCTRL_PIN(57, "GPPC_A_15"), + PINCTRL_PIN(58, "GPPC_A_16"), + PINCTRL_PIN(59, "GPPC_A_17"), + PINCTRL_PIN(60, "GPPC_A_18"), + PINCTRL_PIN(61, "GPPC_A_19"), + PINCTRL_PIN(62, "GPPC_A_20"), + PINCTRL_PIN(63, "GPPC_A_21"), + PINCTRL_PIN(64, "GPPC_A_22"), + PINCTRL_PIN(65, "ESPI_CS1B"), + PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), + /* GPP_S */ + PINCTRL_PIN(67, "GPP_S_0"), + PINCTRL_PIN(68, "GPP_S_1"), + PINCTRL_PIN(69, "GPP_S_2"), + PINCTRL_PIN(70, "GPP_S_3"), + PINCTRL_PIN(71, "GPP_S_4"), + PINCTRL_PIN(72, "GPP_S_5"), + PINCTRL_PIN(73, "GPP_S_6"), + PINCTRL_PIN(74, "GPP_S_7"), + /* GPP_I */ + PINCTRL_PIN(75, "GPP_F_0_CNV_BRI_DT_UART0_RTSB"), + PINCTRL_PIN(76, "GPP_F_1_CNV_BRI_RSP_UART0_RXD"), + PINCTRL_PIN(77, "GPP_F_2_CNV_RGI_DT_UART0_TXD"), + PINCTRL_PIN(78, "GPP_F_3_CNV_RGI_RSP_UART0_CTSB"), + PINCTRL_PIN(79, "GPP_F_4_CNV_RF_RESET_B"), + PINCTRL_PIN(80, "GPP_F_5_MODEM_CLKREQ"), + PINCTRL_PIN(81, "GPP_F_6_CNV_PA_BLANKING"), + PINCTRL_PIN(82, "GPP_F_7_EMMC_CMD"), + PINCTRL_PIN(83, "GPP_F_8_EMMC_DATA0"), + PINCTRL_PIN(84, "GPP_F_9_EMMC_DATA1"), + PINCTRL_PIN(85, "GPP_F_10_EMMC_DATA2"), + PINCTRL_PIN(86, "GPP_F_11_EMMC_DATA3"), + PINCTRL_PIN(87, "GPP_F_12_EMMC_DATA4"), + PINCTRL_PIN(88, "GPP_F_13_EMMC_DATA5"), + PINCTRL_PIN(89, "GPP_F_14_EMMC_DATA6"), + PINCTRL_PIN(90, "GPP_F_15_EMMC_DATA7"), + PINCTRL_PIN(91, "GPP_F_16_EMMC_RCLK"), + PINCTRL_PIN(92, "GPP_F_17_EMMC_CLK"), + PINCTRL_PIN(93, "GPP_F_18_EMMC_RESETB"), + PINCTRL_PIN(94, "GPP_F_19_A4WP_PRESENT"), + /* GPP_H */ + PINCTRL_PIN(95, "GPPC_H_0"), + PINCTRL_PIN(96, "GPPC_H_1"), + PINCTRL_PIN(97, "GPPC_H_2"), + PINCTRL_PIN(98, "GPPC_H_3"), + PINCTRL_PIN(99, "GPPC_H_4"), + PINCTRL_PIN(100, "GPPC_H_5"), + PINCTRL_PIN(101, "GPPC_H_6"), + PINCTRL_PIN(102, "GPPC_H_7"), + PINCTRL_PIN(103, "GPPC_H_8"), + PINCTRL_PIN(104, "GPPC_H_9"), + PINCTRL_PIN(105, "GPPC_H_10"), + PINCTRL_PIN(106, "GPPC_H_11"), + PINCTRL_PIN(107, "I2C7_SDA"), + PINCTRL_PIN(108, "I2C7_SCL"), + PINCTRL_PIN(109, "GPPC_H_14"), + PINCTRL_PIN(110, "GPPC_H_15"), + PINCTRL_PIN(111, "GPPC_H_16"), + PINCTRL_PIN(112, "GPPC_H_17"), + PINCTRL_PIN(113, "CPU_C10_GATEB"), + PINCTRL_PIN(114, "GPPC_H_19"), + PINCTRL_PIN(115, "GPPC_H_20"), + PINCTRL_PIN(116, "GPPC_H_21"), + PINCTRL_PIN(117, "GPPC_H_22"), + PINCTRL_PIN(118, "GPPC_H_23"), + /* GPP_D */ + PINCTRL_PIN(119, "GPPC_D_0"), + PINCTRL_PIN(120, "GPPC_D_1"), + PINCTRL_PIN(121, "GPPC_D_2"), + PINCTRL_PIN(122, "GPPC_D_3"), + PINCTRL_PIN(123, "GPPC_D_4"), + PINCTRL_PIN(124, "GPPC_D_5"), + PINCTRL_PIN(125, "GPPC_D_6"), + PINCTRL_PIN(126, "GPPC_D_7"), + PINCTRL_PIN(127, "GPPC_D_8"), + PINCTRL_PIN(128, "BSSB_LS2_RX"), + PINCTRL_PIN(129, "BSSB_LS2_TX"), + PINCTRL_PIN(130, "BSSB_LS3_RX"), + PINCTRL_PIN(131, "BSSB_LS3_TX"), + PINCTRL_PIN(132, "GPPC_D_13"), + PINCTRL_PIN(133, "GPPC_D_14"), + PINCTRL_PIN(134, "GPPC_D_15"), + PINCTRL_PIN(135, "GPPC_D_16"), + PINCTRL_PIN(136, "GPPC_D_17"), + PINCTRL_PIN(137, "GPPC_D_18"), + PINCTRL_PIN(138, "GPPC_D_19"), + PINCTRL_PIN(139, "GSPI2_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(140, "CNV_BTEN"), + PINCTRL_PIN(141, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(142, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(143, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(144, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(145, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(146, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(147, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(148, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(149, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(150, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(151, "vUART0_TXD"), + PINCTRL_PIN(152, "vUART0_RXD"), + PINCTRL_PIN(153, "vUART0_CTS_B"), + PINCTRL_PIN(154, "vUART0_RTS_B"), + PINCTRL_PIN(155, "vISH_UART0_TXD"), + PINCTRL_PIN(156, "vISH_UART0_RXD"), + PINCTRL_PIN(157, "vISH_UART0_CTS_B"), + PINCTRL_PIN(158, "vISH_UART0_RTS_B"), + PINCTRL_PIN(159, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(160, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(161, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(162, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(163, "vI2S2_SCLK"), + PINCTRL_PIN(164, "vI2S2_SFRM"), + PINCTRL_PIN(165, "vI2S2_TXD"), + PINCTRL_PIN(166, "vI2S2_RXD"), + PINCTRL_PIN(167, "THC0_WOT_INT"), + PINCTRL_PIN(168, "THC1_WOT_INT"), + /* GPP_C */ + PINCTRL_PIN(169, "SMBCLK"), + PINCTRL_PIN(170, "SMBDATA"), + PINCTRL_PIN(171, "SMBALERTB"), + PINCTRL_PIN(172, "SML0CLK"), + PINCTRL_PIN(173, "SML0DATA"), + PINCTRL_PIN(174, "GPPC_C_5"), + PINCTRL_PIN(175, "GPPC_C_6"), + PINCTRL_PIN(176, "GPPC_C_7"), + PINCTRL_PIN(177, "GPPC_C_8"), + PINCTRL_PIN(178, "GPPC_C_9"), + PINCTRL_PIN(179, "GPPC_C_10"), + PINCTRL_PIN(180, "GPPC_C_11"), + PINCTRL_PIN(181, "GPPC_C_12"), + PINCTRL_PIN(182, "GPPC_C_13"), + PINCTRL_PIN(183, "GPPC_C_14"), + PINCTRL_PIN(184, "GPPC_C_15"), + PINCTRL_PIN(185, "GPPC_C_16"), + PINCTRL_PIN(186, "GPPC_C_17"), + PINCTRL_PIN(187, "GPPC_C_18"), + PINCTRL_PIN(188, "GPPC_C_19"), + PINCTRL_PIN(189, "GPPC_C_20"), + PINCTRL_PIN(190, "GPPC_C_21"), + PINCTRL_PIN(191, "GPPC_C_22"), + PINCTRL_PIN(192, "GPPC_C_23"), + /* GPP_F */ + PINCTRL_PIN(193, "CNV_BRI_DT"), + PINCTRL_PIN(194, "CNV_BRI_RSP"), + PINCTRL_PIN(195, "CNV_RGI_DT"), + PINCTRL_PIN(196, "CNV_RGI_RSP"), + PINCTRL_PIN(197, "CNV_RF_RESET_B"), + PINCTRL_PIN(198, "MODEM_CLKREQ"), + PINCTRL_PIN(199, "GPPC_F_6"), + PINCTRL_PIN(200, "GPPC_F_7"), + PINCTRL_PIN(201, "GPPC_F_8"), + PINCTRL_PIN(202, "BOOTMPC"), + PINCTRL_PIN(203, "GPPC_F_10"), + PINCTRL_PIN(204, "GPPC_F_11"), + PINCTRL_PIN(205, "GPPC_F_12"), + PINCTRL_PIN(206, "GPPC_F_13"), + PINCTRL_PIN(207, "GPPC_F_14"), + PINCTRL_PIN(208, "GPPC_F_15"), + PINCTRL_PIN(209, "GPPC_F_16"), + PINCTRL_PIN(210, "GPPC_F_17"), + PINCTRL_PIN(211, "GPPC_F_18"), + PINCTRL_PIN(212, "GPPC_F_19"), + PINCTRL_PIN(213, "EXT_PWR_GATEB"), + PINCTRL_PIN(214, "EXT_PWR_GATE2B"), + PINCTRL_PIN(215, "GPPC_F_22"), + PINCTRL_PIN(216, "GPPC_F_23"), + PINCTRL_PIN(217, "GPPF_CLK_LOOPBACK"), + /* HVCMOS */ + PINCTRL_PIN(218, "L_BKLTEN"), + PINCTRL_PIN(219, "L_BKLTCTL"), + PINCTRL_PIN(220, "L_VDDEN"), + PINCTRL_PIN(221, "SYS_PWROK"), + PINCTRL_PIN(222, "SYS_RESETB"), + PINCTRL_PIN(223, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(224, "GPPC_E_0"), + PINCTRL_PIN(225, "GPPC_E_1"), + PINCTRL_PIN(226, "GPPC_E_2"), + PINCTRL_PIN(227, "GPPC_E_3"), + PINCTRL_PIN(228, "GPPC_E_4"), + PINCTRL_PIN(229, "GPPC_E_5"), + PINCTRL_PIN(230, "GPPC_E_6"), + PINCTRL_PIN(231, "GPPC_E_7"), + PINCTRL_PIN(232, "GPPC_E_8"), + PINCTRL_PIN(233, "GPPC_E_9"), + PINCTRL_PIN(234, "GPPC_E_10"), + PINCTRL_PIN(235, "GPPC_E_11"), + PINCTRL_PIN(236, "GPPC_E_12"), + PINCTRL_PIN(237, "GPPC_E_13"), + PINCTRL_PIN(238, "GPPC_E_14"), + PINCTRL_PIN(239, "FIVR_DIGPB_0"), + PINCTRL_PIN(240, "FIVR_DIGPB_1"), + PINCTRL_PIN(241, "GPPC_E_17"), + PINCTRL_PIN(242, "BSSB_LS0_RX"), + PINCTRL_PIN(243, "BSSB_LS0_TX"), + PINCTRL_PIN(244, "BSSB_LS1_RX"), + PINCTRL_PIN(245, "BSSB_LS1_TX"), + PINCTRL_PIN(246, "DNX_FORCE_RELOAD"), + PINCTRL_PIN(247, "GPPC_E_23"), + PINCTRL_PIN(248, "GPPE_CLK_LOOPBACK"), + /* GPP_R */ + PINCTRL_PIN(249, "HDA_BCLK"), + PINCTRL_PIN(250, "HDA_SYNC"), + PINCTRL_PIN(251, "HDA_SDO"), + PINCTRL_PIN(252, "HDA_SDI_0"), + PINCTRL_PIN(253, "HDA_RSTB"), + PINCTRL_PIN(254, "GPP_R_5"), + PINCTRL_PIN(255, "GPP_R_6"), + PINCTRL_PIN(256, "GPP_R_7"), +}; + +static const struct intel_padgroup adln_community0_gpps[] = { + ADL_GPP(0, 0, 25, 0), /* GPP_B */ + ADL_GPP(1, 26, 41, 32), /* GPP_T */ + ADL_GPP(2, 42, 66, 64), /* GPP_A */ +}; + +static const struct intel_padgroup adln_community1_gpps[] = { + ADL_GPP(0, 67, 74, 96), /* GPP_S */ + ADL_GPP(1, 75, 94, 128), /* GPP_I */ + ADL_GPP(2, 95, 118, 160), /* GPP_H */ + ADL_GPP(3, 119, 139, 192), /* GPP_D */ + ADL_GPP(4, 140, 168, 224), /* vGPIO */ +}; + +static const struct intel_padgroup adln_community4_gpps[] = { + ADL_GPP(0, 169, 192, 256), /* GPP_C */ + ADL_GPP(1, 193, 217, 288), /* GPP_F */ + ADL_GPP(2, 218, 223, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + ADL_GPP(3, 224, 248, 320), /* GPP_E */ +}; + +static const struct intel_padgroup adln_community5_gpps[] = { + ADL_GPP(0, 249, 256, 352), /* GPP_R */ +}; + +static const struct intel_community adln_communities[] = { + ADL_COMMUNITY(0, 0, 66, adln_community0_gpps), + ADL_COMMUNITY(1, 67, 168, adln_community1_gpps), + ADL_COMMUNITY(2, 169, 248, adln_community4_gpps), + ADL_COMMUNITY(3, 249, 256, adln_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data adln_soc_data = { + .pins = adln_pins, + .npins = ARRAY_SIZE(adln_pins), + .communities = adln_communities, + .ncommunities = ARRAY_SIZE(adln_communities), +}; + /* Alder Lake-S */ static const struct pinctrl_pin_desc adls_pins[] = { /* GPP_I */ @@ -416,6 +729,8 @@ static const struct intel_pinctrl_soc_data adls_soc_data = { static const struct acpi_device_id adl_pinctrl_acpi_match[] = { { "INTC1056", (kernel_ulong_t)&adls_soc_data }, + { "INTC1057", (kernel_ulong_t)&adln_soc_data }, + { "INTC1085", (kernel_ulong_t)&adls_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, adl_pinctrl_acpi_match); diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 1cc660e6458e..f89c9fcd4e1b 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -32,6 +32,7 @@ #define BYT_VAL_REG 0x008 #define BYT_DFT_REG 0x00c #define BYT_INT_STAT_REG 0x800 +#define BYT_DIRECT_IRQ_REG 0x980 #define BYT_DEBOUNCE_REG 0x9d0 /* BYT_CONF0_REG register bits */ @@ -1475,6 +1476,51 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) chip->irq_eoi(data); } +static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0) +{ + int direct_irq, ioapic_direct_irq_base; + u8 *match, direct_irq_mux[16]; + u32 trig; + + memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, + sizeof(direct_irq_mux)); + match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux)); + if (!match) { + dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin); + return false; + } + + direct_irq = match - direct_irq_mux; + /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ + ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; + dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, + direct_irq, direct_irq + ioapic_direct_irq_base); + + /* + * Testing has shown that the way direct IRQs work is that the combination of the + * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ + * trigger block, which normally sets the status flag in the IRQ status reg at + * 0x800, to one of the IO-APIC pins according to the mux registers. + * + * This means that: + * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block + * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly + * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, + * selecting edge mode operation then on the first edge the IO-APIC pin goes + * high, but since no write-to-clear write will be done to the IRQ status reg + * at 0x800, the detected edge condition will never get cleared. + */ + trig = conf0 & BYT_TRIG_MASK; + if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && + trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { + dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n", + pin, conf0); + return false; + } + + return true; +} + static void byt_init_irq_valid_mask(struct gpio_chip *chip, unsigned long *valid_mask, unsigned int ngpios) @@ -1502,8 +1548,13 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip, value = readl(reg); if (value & BYT_DIRECT_IRQ_EN) { - clear_bit(i, valid_mask); - dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i); + if (byt_direct_irq_sanity_check(vg, i, value)) { + clear_bit(i, valid_mask); + } else { + value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | + BYT_TRIG_NEG | BYT_TRIG_LVL); + writel(value, reg); + } } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { byt_gpio_clear_triggering(vg, i); dev_dbg(vg->dev, "disabling GPIO %d\n", i); diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 429b5a83acf0..27c248cc16f7 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -2,7 +2,7 @@ /* * Intel Ice Lake PCH pinctrl/GPIO driver * - * Copyright (C) 2018, Intel Corporation + * Copyright (C) 2018, 2022 Intel Corporation * Authors: Andy Shevchenko * Mika Westerberg */ @@ -19,7 +19,8 @@ #define ICL_PADCFGLOCK 0x080 #define ICL_HOSTSW_OWN 0x0b0 #define ICL_GPI_IS 0x100 -#define ICL_GPI_IE 0x110 +#define ICL_LP_GPI_IE 0x110 +#define ICL_N_GPI_IE 0x120 #define ICL_GPP(r, s, e, g) \ { \ @@ -29,20 +30,26 @@ .gpio_base = (g), \ } -#define ICL_COMMUNITY(b, s, e, g) \ +#define ICL_COMMUNITY(b, s, e, ie, g) \ { \ .barno = (b), \ .padown_offset = ICL_PAD_OWN, \ .padcfglock_offset = ICL_PADCFGLOCK, \ .hostown_offset = ICL_HOSTSW_OWN, \ .is_offset = ICL_GPI_IS, \ - .ie_offset = ICL_GPI_IE, \ + .ie_offset = (ie), \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ .gpps = (g), \ .ngpps = ARRAY_SIZE(g), \ } +#define ICL_LP_COMMUNITY(b, s, e, g) \ + ICL_COMMUNITY(b, s, e, ICL_LP_GPI_IE, g) + +#define ICL_N_COMMUNITY(b, s, e, g) \ + ICL_COMMUNITY(b, s, e, ICL_N_GPI_IE, g) + /* Ice Lake-LP */ static const struct pinctrl_pin_desc icllp_pins[] = { /* GPP_G */ @@ -329,10 +336,10 @@ static const struct intel_padgroup icllp_community5_gpps[] = { }; static const struct intel_community icllp_communities[] = { - ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps), - ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps), - ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps), - ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps), + ICL_LP_COMMUNITY(0, 0, 58, icllp_community0_gpps), + ICL_LP_COMMUNITY(1, 59, 152, icllp_community1_gpps), + ICL_LP_COMMUNITY(2, 153, 215, icllp_community4_gpps), + ICL_LP_COMMUNITY(3, 216, 240, icllp_community5_gpps), }; static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 }; @@ -403,10 +410,278 @@ static const struct intel_pinctrl_soc_data icllp_soc_data = { .ncommunities = ARRAY_SIZE(icllp_communities), }; +/* Ice Lake-N */ +static const struct pinctrl_pin_desc icln_pins[] = { + /* SPI */ + PINCTRL_PIN(0, "SPI0_IO_2"), + PINCTRL_PIN(1, "SPI0_IO_3"), + PINCTRL_PIN(2, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(3, "SPI0_MISO_IO_1"), + PINCTRL_PIN(4, "SPI0_TPM_CSB"), + PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(7, "SPI0_CLK"), + PINCTRL_PIN(8, "SPI0_CLK_LOOPBK"), + /* GPP_B */ + PINCTRL_PIN(9, "CORE_VID_0"), + PINCTRL_PIN(10, "CORE_VID_1"), + PINCTRL_PIN(11, "VRALERTB"), + PINCTRL_PIN(12, "CPU_GP_2"), + PINCTRL_PIN(13, "CPU_GP_3"), + PINCTRL_PIN(14, "SRCCLKREQB_0"), + PINCTRL_PIN(15, "SRCCLKREQB_1"), + PINCTRL_PIN(16, "SRCCLKREQB_2"), + PINCTRL_PIN(17, "SRCCLKREQB_3"), + PINCTRL_PIN(18, "SRCCLKREQB_4"), + PINCTRL_PIN(19, "SRCCLKREQB_5"), + PINCTRL_PIN(20, "EXT_PWR_GATEB"), + PINCTRL_PIN(21, "SLP_S0B"), + PINCTRL_PIN(22, "PLTRSTB"), + PINCTRL_PIN(23, "SPKR_GSPI0_CS1B"), + PINCTRL_PIN(24, "GSPI0_CS0B"), + PINCTRL_PIN(25, "GSPI0_CLK"), + PINCTRL_PIN(26, "GSPI0_MISO_TBT_LSX3_A"), + PINCTRL_PIN(27, "GSPI0_MOSI_TBT_LSX3_B"), + PINCTRL_PIN(28, "GSPI1_CS0B"), + PINCTRL_PIN(29, "GSPI1_CLK_NFC_CLK"), + PINCTRL_PIN(30, "GSPI1_MISO_NFC_CLKREQ"), + PINCTRL_PIN(31, "GSPI1_MOSI"), + PINCTRL_PIN(32, "GSPI1_CS1B"), + PINCTRL_PIN(33, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(34, "GSPI1_CLK_LOOPBK"), + /* GPP_A */ + PINCTRL_PIN(35, "ESPI_IO_0"), + PINCTRL_PIN(36, "ESPI_IO_1"), + PINCTRL_PIN(37, "ESPI_IO_2"), + PINCTRL_PIN(38, "ESPI_IO_3"), + PINCTRL_PIN(39, "ESPI_CSB"), + PINCTRL_PIN(40, "ESPI_CLK"), + PINCTRL_PIN(41, "ESPI_RESETB"), + PINCTRL_PIN(42, "SMBCLK"), + PINCTRL_PIN(43, "SMBDATA"), + PINCTRL_PIN(44, "SMBALERTB"), + PINCTRL_PIN(45, "CPU_GP_0"), + PINCTRL_PIN(46, "CPU_GP_1"), + PINCTRL_PIN(47, "USB2_OCB_1"), + PINCTRL_PIN(48, "USB2_OCB_2"), + PINCTRL_PIN(49, "USB2_OCB_3"), + PINCTRL_PIN(50, "DDSP_HPD_A_TIME_SYNC_0"), + PINCTRL_PIN(51, "DDSP_HPD_B_TIME_SYNC_1"), + PINCTRL_PIN(52, "DDSP_HPD_C"), + PINCTRL_PIN(53, "USB2_OCB_0"), + PINCTRL_PIN(54, "PCHHOTB"), + PINCTRL_PIN(55, "ESPI_CLK_LOOPBK"), + /* GPP_S */ + PINCTRL_PIN(56, "SNDW1_CLK"), + PINCTRL_PIN(57, "SNDW1_DATA"), + PINCTRL_PIN(58, "SNDW2_CLK"), + PINCTRL_PIN(59, "SNDW2_DATA"), + PINCTRL_PIN(60, "SNDW3_CLK_DMIC_CLK_1"), + PINCTRL_PIN(61, "SNDW3_DATA_DMIC_DATA_1"), + PINCTRL_PIN(62, "SNDW4_CLK_DMIC_CLK_0"), + PINCTRL_PIN(63, "SNDW4_DATA_DMIC_DATA_0"), + /* GPP_R */ + PINCTRL_PIN(64, "HDA_BCLK"), + PINCTRL_PIN(65, "HDA_SYNC"), + PINCTRL_PIN(66, "HDA_SDO"), + PINCTRL_PIN(67, "HDA_SDI_0"), + PINCTRL_PIN(68, "HDA_RSTB"), + PINCTRL_PIN(69, "HDA_SDI_1_I2S1_RXD"), + PINCTRL_PIN(70, "I2S1_SFRM"), + PINCTRL_PIN(71, "I2S1_TXD"), + /* GPP_H */ + PINCTRL_PIN(72, "GPPC_H_0"), + PINCTRL_PIN(73, "CNV_RF_RESET_B"), + PINCTRL_PIN(74, "MODEM_CLKREQ"), + PINCTRL_PIN(75, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(76, "I2C2_SDA"), + PINCTRL_PIN(77, "I2C2_SCL"), + PINCTRL_PIN(78, "I2C3_SDA"), + PINCTRL_PIN(79, "I2C3_SCL"), + PINCTRL_PIN(80, "I2C4_SDA"), + PINCTRL_PIN(81, "I2C4_SCL"), + PINCTRL_PIN(82, "CPU_VCCIO_PWR_GATEB"), + PINCTRL_PIN(83, "I2S2_SCLK"), + PINCTRL_PIN(84, "CNV_RF_RESET_B"), + PINCTRL_PIN(85, "MODEM_CLKREQ"), + PINCTRL_PIN(86, "I2S2_RXD"), + PINCTRL_PIN(87, "I2S1_SCLK"), + PINCTRL_PIN(88, "GPPC_H_16"), + PINCTRL_PIN(89, "GPPC_H_17"), + PINCTRL_PIN(90, "GPPC_H_18"), + PINCTRL_PIN(91, "GPPC_H_19"), + PINCTRL_PIN(92, "GPPC_H_20"), + PINCTRL_PIN(93, "GPPC_H_21"), + PINCTRL_PIN(94, "GPPC_H_22"), + PINCTRL_PIN(95, "GPPC_H_23"), + /* GPP_D */ + PINCTRL_PIN(96, "SPI1_CSB_BK_0_SBK_0"), + PINCTRL_PIN(97, "SPI1_CLK_BK_1_SBK_1"), + PINCTRL_PIN(98, "SPI1_MISO_IO_1_BK_2_SBK_2"), + PINCTRL_PIN(99, "SPI1_MOSI_IO_0_BK_3_SBK_3"), + PINCTRL_PIN(100, "ISH_I2C0_SDA"), + PINCTRL_PIN(101, "ISH_I2C0_SCL"), + PINCTRL_PIN(102, "ISH_I2C1_SDA"), + PINCTRL_PIN(103, "ISH_I2C1_SCL"), + PINCTRL_PIN(104, "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A"), + PINCTRL_PIN(105, "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B"), + PINCTRL_PIN(106, "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A"), + PINCTRL_PIN(107, "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B"), + PINCTRL_PIN(108, "ISH_UART0_RXD_I2C4B_SDA"), + PINCTRL_PIN(109, "ISH_UART0_TXD_I2C4B_SCL"), + PINCTRL_PIN(110, "ISH_UART0_RTSB_GSPI2_CS1B"), + PINCTRL_PIN(111, "ISH_UART0_CTSB_CNV_WCEN"), + PINCTRL_PIN(112, "SPI1_IO_2"), + PINCTRL_PIN(113, "SPI1_IO_3"), + PINCTRL_PIN(114, "I2S_MCLK"), + PINCTRL_PIN(115, "CNV_MFUART2_RXD"), + PINCTRL_PIN(116, "CNV_MFUART2_TXD"), + PINCTRL_PIN(117, "CNV_PA_BLANKING"), + PINCTRL_PIN(118, "I2C5_SDA_ISH_I2C2_SDA"), + PINCTRL_PIN(119, "I2C5_SCL_ISH_I2C2_SCL"), + PINCTRL_PIN(120, "GSPI2_CLK_LOOPBK"), + PINCTRL_PIN(121, "SPI1_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(122, "CNV_BTEN"), + PINCTRL_PIN(123, "CNV_WCEN"), + PINCTRL_PIN(124, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(125, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(126, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(127, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(128, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(129, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(130, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(131, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(132, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(133, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(134, "vUART0_TXD"), + PINCTRL_PIN(135, "vUART0_RXD"), + PINCTRL_PIN(136, "vUART0_CTS_B"), + PINCTRL_PIN(137, "vUART0_RTS_B"), + PINCTRL_PIN(138, "vISH_UART0_TXD"), + PINCTRL_PIN(139, "vISH_UART0_RXD"), + PINCTRL_PIN(140, "vISH_UART0_CTS_B"), + PINCTRL_PIN(141, "vISH_UART0_RTS_B"), + PINCTRL_PIN(142, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(143, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(144, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(145, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(146, "vI2S2_SCLK"), + PINCTRL_PIN(147, "vI2S2_SFRM"), + PINCTRL_PIN(148, "vI2S2_TXD"), + PINCTRL_PIN(149, "vI2S2_RXD"), + PINCTRL_PIN(150, "vSD3_CD_B"), + /* GPP_C */ + PINCTRL_PIN(151, "GPPC_C_0"), + PINCTRL_PIN(152, "GPPC_C_1"), + PINCTRL_PIN(153, "GPPC_C_2"), + PINCTRL_PIN(154, "GPPC_C_3"), + PINCTRL_PIN(155, "GPPC_C_4"), + PINCTRL_PIN(156, "GPPC_C_5"), + PINCTRL_PIN(157, "SUSWARNB_SUSPWRDNACK"), + PINCTRL_PIN(158, "SUSACKB"), + PINCTRL_PIN(159, "UART0_RXD"), + PINCTRL_PIN(160, "UART0_TXD"), + PINCTRL_PIN(161, "UART0_RTSB"), + PINCTRL_PIN(162, "UART0_CTSB"), + PINCTRL_PIN(163, "UART1_RXD_ISH_UART1_RXD"), + PINCTRL_PIN(164, "UART1_TXD_ISH_UART1_TXD"), + PINCTRL_PIN(165, "UART1_RTSB_ISH_UART1_RTSB"), + PINCTRL_PIN(166, "UART1_CTSB_ISH_UART1_CTSB"), + PINCTRL_PIN(167, "I2C0_SDA"), + PINCTRL_PIN(168, "I2C0_SCL"), + PINCTRL_PIN(169, "I2C1_SDA"), + PINCTRL_PIN(170, "I2C1_SCL"), + PINCTRL_PIN(171, "UART2_RXD_CNV_MFUART0_RXD"), + PINCTRL_PIN(172, "UART2_TXD_CNV_MFUART0_TXD"), + PINCTRL_PIN(173, "UART2_RTSB_CNV_MFUART0_RTS_B"), + PINCTRL_PIN(174, "UART2_CTSB_CNV_MFUART0_CTS_B"), + /* HVCMOS */ + PINCTRL_PIN(175, "L_BKLTEN"), + PINCTRL_PIN(176, "L_BKLTCTL"), + PINCTRL_PIN(177, "L_VDDEN"), + PINCTRL_PIN(178, "SYS_PWROK"), + PINCTRL_PIN(179, "SYS_RESETB"), + PINCTRL_PIN(180, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(181, "ISH_GP_0_IMGCLKOUT_0"), + PINCTRL_PIN(182, "ISH_GP_1"), + PINCTRL_PIN(183, "IMGCLKOUT_1"), + PINCTRL_PIN(184, "ISH_GP_2_SATA_DEVSLP_0"), + PINCTRL_PIN(185, "IMGCLKOUT_2"), + PINCTRL_PIN(186, "SATA_LEDB_SPI1_CS1B"), + PINCTRL_PIN(187, "IMGCLKOUT_3"), + PINCTRL_PIN(188, "ISH_GP_3_SATA_DEVSLP_1"), + PINCTRL_PIN(189, "FIVR_DIGPB_0"), + PINCTRL_PIN(190, "SML0CLK"), + PINCTRL_PIN(191, "SML0DATA"), + PINCTRL_PIN(192, "BSSB_LS3_RX"), + PINCTRL_PIN(193, "BSSB_LS3_TX"), + PINCTRL_PIN(194, "BSSB_LS0_RX"), + PINCTRL_PIN(195, "BSSB_LS0_TX"), + PINCTRL_PIN(196, "BSSB_LS1_RX"), + PINCTRL_PIN(197, "BSSB_LS1_TX"), + PINCTRL_PIN(198, "BSSB_LS2_RX"), + PINCTRL_PIN(199, "BSSB_LS2_TX"), + PINCTRL_PIN(200, "FIVR_DIGPB_1"), + PINCTRL_PIN(201, "CNV_BRI_DT"), + PINCTRL_PIN(202, "CNV_BRI_RSP"), + PINCTRL_PIN(203, "CNV_RGI_DT"), + PINCTRL_PIN(204, "CNV_RGI_RSP"), + /* GPP_G */ + PINCTRL_PIN(205, "SD3_CMD"), + PINCTRL_PIN(206, "SD3_D0"), + PINCTRL_PIN(207, "SD3_D1"), + PINCTRL_PIN(208, "SD3_D2"), + PINCTRL_PIN(209, "SD3_D3"), + PINCTRL_PIN(210, "SD3_CDB"), + PINCTRL_PIN(211, "SD3_CLK"), + PINCTRL_PIN(212, "SD3_WP"), +}; + +static const struct intel_padgroup icln_community0_gpps[] = { + ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */ + ICL_GPP(1, 9, 34, 32), /* GPP_B */ + ICL_GPP(2, 35, 55, 64), /* GPP_A */ + ICL_GPP(3, 56, 63, 96), /* GPP_S */ + ICL_GPP(4, 64, 71, 128), /* GPP_R */ +}; + +static const struct intel_padgroup icln_community1_gpps[] = { + ICL_GPP(0, 72, 95, 160), /* GPP_H */ + ICL_GPP(1, 96, 121, 192), /* GPP_D */ + ICL_GPP(2, 122, 150, 224), /* vGPIO */ + ICL_GPP(3, 151, 174, 256), /* GPP_C */ +}; + +static const struct intel_padgroup icln_community4_gpps[] = { + ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + ICL_GPP(1, 181, 204, 288), /* GPP_E */ +}; + +static const struct intel_padgroup icln_community5_gpps[] = { + ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */ +}; + +static const struct intel_community icln_communities[] = { + ICL_N_COMMUNITY(0, 0, 71, icln_community0_gpps), + ICL_N_COMMUNITY(1, 72, 174, icln_community1_gpps), + ICL_N_COMMUNITY(2, 175, 204, icln_community4_gpps), + ICL_N_COMMUNITY(3, 205, 212, icln_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data icln_soc_data = { + .pins = icln_pins, + .npins = ARRAY_SIZE(icln_pins), + .communities = icln_communities, + .ncommunities = ARRAY_SIZE(icln_communities), +}; + static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops); static const struct acpi_device_id icl_pinctrl_acpi_match[] = { { "INT3455", (kernel_ulong_t)&icllp_soc_data }, + { "INT34C3", (kernel_ulong_t)&icln_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match); diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 66db4ac5d169..8dca1ef04965 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -147,6 +147,13 @@ config PINCTRL_MT8183 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT8186 + bool "Mediatek MT8186 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + config PINCTRL_MT8192 bool "Mediatek MT8192 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 1e3931d924e7..29018d6ad0de 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o +obj-$(CONFIG_PINCTRL_MT8186) += pinctrl-mt8186.o obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 5bfaa84839c7..526faaebaf77 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -605,6 +605,7 @@ static int mtk_build_functions(struct mtk_pinctrl *hw) int mtk_moore_pinctrl_probe(struct platform_device *pdev, const struct mtk_pin_soc *soc) { + struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *hw; int err, i; @@ -616,11 +617,9 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, hw->soc = soc; hw->dev = &pdev->dev; - if (!hw->soc->nbase_names) { - dev_err(&pdev->dev, + if (!hw->soc->nbase_names) + return dev_err_probe(dev, -EINVAL, "SoC should be assigned at least one register base\n"); - return -EINVAL; - } hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, sizeof(*hw->base), GFP_KERNEL); @@ -665,17 +664,13 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, /* Setup groups descriptions per SoC types */ err = mtk_build_groups(hw); - if (err) { - dev_err(&pdev->dev, "Failed to build groups\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to build groups\n"); /* Setup functions descriptions per SoC types */ err = mtk_build_functions(hw); - if (err) { - dev_err(&pdev->dev, "Failed to build functions\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to build functions\n"); /* For able to make pinctrl_claim_hogs, we must not enable pinctrl * until all groups and functions are being added one. @@ -691,10 +686,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, /* Build gpiochip should be after pinctrl_enable is done */ err = mtk_build_gpiochip(hw); - if (err) { - dev_err(&pdev->dev, "Failed to add gpio_chip\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to add gpio_chip\n"); platform_set_drvdata(pdev, hw); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index 37228dd5103e..d1583b4fdd9d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -270,13 +270,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */ }; -static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd, - ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = { MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0), MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1), @@ -436,18 +429,6 @@ static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = { MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13), }; -static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set, - ARRAY_SIZE(mt2701_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set, - ARRAY_SIZE(mt2701_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = { MTK_PINMUX_SPEC(22, 0xb10, 3), MTK_PINMUX_SPEC(23, 0xb10, 4), @@ -508,8 +489,14 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp), .pin_drv_grp = mt2701_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv), - .spec_pull_set = mt2701_spec_pull_set, - .spec_ies_smt_set = mt2701_ies_smt_set, + .spec_ies = mt2701_ies_set, + .n_spec_ies = ARRAY_SIZE(mt2701_ies_set), + .spec_pupd = mt2701_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt2701_spec_pupd), + .spec_smt = mt2701_smt_set, + .n_spec_smt = ARRAY_SIZE(mt2701_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .spec_pinmux_set = mt2701_spec_pinmux_set, .spec_dir_set = mt2701_spec_dir_set, .dir_offset = 0x0000, @@ -534,20 +521,15 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { }, }; -static int mt2701_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL); -} - static const struct of_device_id mt2701_pctrl_match[] = { - { .compatible = "mediatek,mt2701-pinctrl", }, - { .compatible = "mediatek,mt7623-pinctrl", }, + { .compatible = "mediatek,mt2701-pinctrl", .data = &mt2701_pinctrl_data }, + { .compatible = "mediatek,mt7623-pinctrl", .data = &mt2701_pinctrl_data }, {} }; MODULE_DEVICE_TABLE(of, mt2701_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { - .probe = mt2701_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt2701-pinctrl", .of_match_table = mt2701_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index ba35fc6cc138..b921068f9e69 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -81,16 +81,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3) }; -static int mt2712_spec_pull_set(struct regmap *regmap, - unsigned int pin, - unsigned char align, - bool isup, - unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd, - ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = { MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2), MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0), @@ -285,19 +275,6 @@ static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = { MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15) }; -static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, - int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set, - ARRAY_SIZE(mt2712_ies_set), pin, align, value); - if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set, - ARRAY_SIZE(mt2712_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_drv_group_desc mt2712_drv_grp[] = { /* 0E4E8SR 4/8/12/16 */ MTK_DRV_GRP(4, 16, 1, 2, 4), @@ -563,8 +540,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt2712_drv_grp), .pin_drv_grp = mt2712_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv), - .spec_pull_set = mt2712_spec_pull_set, - .spec_ies_smt_set = mt2712_ies_smt_set, + .spec_ies = mt2712_ies_set, + .n_spec_ies = ARRAY_SIZE(mt2712_ies_set), + .spec_pupd = mt2712_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt2712_spec_pupd), + .spec_smt = mt2712_smt_set, + .n_spec_smt = ARRAY_SIZE(mt2712_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0100, .pullsel_offset = 0x0200, @@ -587,21 +570,14 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { }, }; -static int mt2712_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL); -} - static const struct of_device_id mt2712_pctrl_match[] = { - { - .compatible = "mediatek,mt2712-pinctrl", - }, + { .compatible = "mediatek,mt2712-pinctrl", .data = &mt2712_pinctrl_data }, { } }; MODULE_DEVICE_TABLE(of, mt2712_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { - .probe = mt2712_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt2712-pinctrl", .of_match_table = mt2712_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c index 2c59d3936256..c57b19fcda03 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c @@ -1082,21 +1082,16 @@ static const struct mtk_pin_soc mt6765_data = { }; static const struct of_device_id mt6765_pinctrl_of_match[] = { - { .compatible = "mediatek,mt6765-pinctrl", }, + { .compatible = "mediatek,mt6765-pinctrl", .data = &mt6765_data }, { } }; -static int mt6765_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt6765_data); -} - static struct platform_driver mt6765_pinctrl_driver = { .driver = { .name = "mt6765-pinctrl", .of_match_table = mt6765_pinctrl_of_match, }, - .probe = mt6765_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt6765_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c b/drivers/pinctrl/mediatek/pinctrl-mt6779.c index bb0851c73304..4ddf8bda6827 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c @@ -758,21 +758,16 @@ static const struct mtk_pin_soc mt6779_data = { }; static const struct of_device_id mt6779_pinctrl_of_match[] = { - { .compatible = "mediatek,mt6779-pinctrl", }, + { .compatible = "mediatek,mt6779-pinctrl", .data = &mt6779_data }, { } }; -static int mt6779_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt6779_data); -} - static struct platform_driver mt6779_pinctrl_driver = { .driver = { .name = "mt6779-pinctrl", .of_match_table = mt6779_pinctrl_of_match, }, - .probe = mt6779_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt6779_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c index adebe4333ed9..53f240491259 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6797.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c @@ -58,21 +58,16 @@ static const struct mtk_pin_soc mt6797_data = { }; static const struct of_device_id mt6797_pinctrl_of_match[] = { - { .compatible = "mediatek,mt6797-pinctrl", }, + { .compatible = "mediatek,mt6797-pinctrl", .data = &mt6797_data }, { } }; -static int mt6797_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt6797_data); -} - static struct platform_driver mt6797_pinctrl_driver = { .driver = { .name = "mt6797-pinctrl", .of_match_table = mt6797_pinctrl_of_match, }, - .probe = mt6797_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt6797_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index eaf5c76b14c7..91c530e7b00e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -172,13 +172,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */ }; -static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd, - ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = { MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0), MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1), @@ -259,19 +252,6 @@ static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = { MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13), }; -static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set, - ARRAY_SIZE(mt8127_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set, - ARRAY_SIZE(mt8127_smt_set), pin, align, value); - return -EINVAL; -} - - static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { .pins = mtk_pins_mt8127, .npins = ARRAY_SIZE(mtk_pins_mt8127), @@ -279,8 +259,14 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp), .pin_drv_grp = mt8127_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv), - .spec_pull_set = mt8127_spec_pull_set, - .spec_ies_smt_set = mt8127_ies_smt_set, + .spec_ies = mt8127_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8127_ies_set), + .spec_pupd = mt8127_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8127_spec_pupd), + .spec_smt = mt8127_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8127_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0100, .pullsel_offset = 0x0200, @@ -303,18 +289,13 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { }, }; -static int mt8127_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL); -} - static const struct of_device_id mt8127_pctrl_match[] = { - { .compatible = "mediatek,mt8127-pinctrl", }, + { .compatible = "mediatek,mt8127-pinctrl", .data = &mt8127_pinctrl_data }, { } }; static struct platform_driver mtk_pinctrl_driver = { - .probe = mt8127_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8127-pinctrl", .of_match_table = mt8127_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index b8f4080aab45..562846756517 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -230,12 +230,14 @@ static const struct mtk_spec_pull_set spec_pupd[] = { SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10) }; -static int spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) +static int spec_pull_set(struct regmap *regmap, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0) { unsigned int i; unsigned int reg_pupd, reg_set_r0, reg_set_r1; unsigned int reg_rst_r0, reg_rst_r1; + unsigned char align = devdata->port_align; bool find = false; for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) { @@ -316,20 +318,13 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { }, }; -static int mt8135_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL); -} - static const struct of_device_id mt8135_pctrl_match[] = { - { - .compatible = "mediatek,mt8135-pinctrl", - }, + { .compatible = "mediatek,mt8135-pinctrl", .data = &mt8135_pinctrl_data }, { } }; static struct platform_driver mtk_pinctrl_driver = { - .probe = mt8135_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8135-pinctrl", .of_match_table = mt8135_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index ba12ef795e52..825167f5d020 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -186,13 +186,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0), }; -static int mt8167_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8167_spec_pupd, - ARRAY_SIZE(mt8167_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = { MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2), MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3), @@ -292,18 +285,6 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = { MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9), }; -static int mt8167_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_ies_set, - ARRAY_SIZE(mt8167_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_smt_set, - ARRAY_SIZE(mt8167_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { .pins = mtk_pins_mt8167, .npins = ARRAY_SIZE(mtk_pins_mt8167), @@ -311,8 +292,14 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8167_drv_grp), .pin_drv_grp = mt8167_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv), - .spec_pull_set = mt8167_spec_pull_set, - .spec_ies_smt_set = mt8167_ies_smt_set, + .spec_ies = mt8167_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8167_ies_set), + .spec_pupd = mt8167_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8167_spec_pupd), + .spec_smt = mt8167_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8167_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0500, .pullsel_offset = 0x0600, @@ -335,22 +322,15 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { }, }; -static int mt8167_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8167_pinctrl_data, NULL); -} - static const struct of_device_id mt8167_pctrl_match[] = { - { - .compatible = "mediatek,mt8167-pinctrl", - }, + { .compatible = "mediatek,mt8167-pinctrl", .data = &mt8167_pinctrl_data }, {} }; MODULE_DEVICE_TABLE(of, mt8167_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { - .probe = mt8167_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8167-pinctrl", .of_match_table = mt8167_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index fc99df8a11c6..1d7d11a32e7d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -61,13 +61,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */ }; -static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd, - ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = { MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1), MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2), @@ -174,18 +167,6 @@ static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = { MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8) }; -static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set, - ARRAY_SIZE(mt8173_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set, - ARRAY_SIZE(mt8173_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_drv_group_desc mt8173_drv_grp[] = { /* 0E4E8SR 4/8/12/16 */ MTK_DRV_GRP(4, 16, 1, 2, 4), @@ -319,8 +300,14 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp), .pin_drv_grp = mt8173_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), - .spec_pull_set = mt8173_spec_pull_set, - .spec_ies_smt_set = mt8173_ies_smt_set, + .spec_ies = mt8173_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8173_ies_set), + .spec_pupd = mt8173_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8173_spec_pupd), + .spec_smt = mt8173_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8173_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0100, .pullsel_offset = 0x0200, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8183.c b/drivers/pinctrl/mediatek/pinctrl-mt8183.c index 60318339b618..fecb1e64fff4 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8183.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8183.c @@ -567,22 +567,17 @@ static const struct mtk_pin_soc mt8183_data = { }; static const struct of_device_id mt8183_pinctrl_of_match[] = { - { .compatible = "mediatek,mt8183-pinctrl", }, + { .compatible = "mediatek,mt8183-pinctrl", .data = &mt8183_data }, { } }; -static int mt8183_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt8183_data); -} - static struct platform_driver mt8183_pinctrl_driver = { .driver = { .name = "mt8183-pinctrl", .of_match_table = mt8183_pinctrl_of_match, .pm = &mtk_paris_pinctrl_pm_ops, }, - .probe = mt8183_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt8183_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8186.c b/drivers/pinctrl/mediatek/pinctrl-mt8186.c new file mode 100644 index 000000000000..a4dd5197abc1 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8186.c @@ -0,0 +1,1267 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 MediaTek Inc. + * + * Author: Guodong Liu + * + */ + +#include "pinctrl-mtk-mt8186.h" +#include "pinctrl-paris.h" + +/* MT8186 have multiple bases to program pin configuration listed as the below: + * iocfg[0]:0x10005000, iocfg[1]:0x10002000, iocfg[2]:0x10002200, + * iocfg[3]:0x10002400, iocfg[4]:0x10002600, iocfg[5]:0x10002800, + * iocfg[6]:0x10002C00. + * _i_based could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 1) + +static const struct mtk_pin_field_calc mt8186_pin_mode_range[] = { + PIN_FIELD(0, 184, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8186_pin_dir_range[] = { + PIN_FIELD(0, 184, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_di_range[] = { + PIN_FIELD(0, 184, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_do_range[] = { + PIN_FIELD(0, 184, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 6, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 6, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(3, 3, 6, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(4, 4, 6, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(5, 5, 6, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0020, 0x10, 19, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0020, 0x10, 20, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0020, 0x10, 21, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0020, 0x10, 22, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0020, 0x10, 16, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0020, 0x10, 17, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0020, 0x10, 18, 1), + PIN_FIELD_BASE(13, 13, 3, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, 5, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(18, 18, 5, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(19, 19, 5, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(20, 20, 5, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 5, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(25, 25, 5, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(26, 26, 5, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, 5, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(28, 28, 5, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(35, 35, 2, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, 5, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(52, 52, 3, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(58, 58, 5, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(59, 59, 5, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(67, 67, 1, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(78, 78, 1, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(79, 79, 5, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(80, 80, 5, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(81, 81, 5, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(82, 82, 5, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(83, 83, 6, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0040, 0x10, 29, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0040, 0x10, 31, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0040, 0x10, 30, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(99, 99, 4, 0x0020, 0x10, 14, 1), + PIN_FIELD_BASE(100, 100, 4, 0x0020, 0x10, 15, 1), + PIN_FIELD_BASE(101, 101, 4, 0x0020, 0x10, 13, 1), + PIN_FIELD_BASE(102, 102, 4, 0x0020, 0x10, 12, 1), + PIN_FIELD_BASE(103, 103, 4, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 4, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(105, 105, 4, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(106, 106, 4, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0020, 0x10, 6, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0020, 0x10, 7, 1), + PIN_FIELD_BASE(109, 109, 4, 0x0020, 0x10, 8, 1), + PIN_FIELD_BASE(110, 110, 4, 0x0020, 0x10, 9, 1), + PIN_FIELD_BASE(111, 111, 4, 0x0020, 0x10, 10, 1), + PIN_FIELD_BASE(112, 112, 4, 0x0020, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 3, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(116, 116, 3, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(117, 117, 3, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(119, 119, 5, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(120, 120, 5, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(121, 121, 5, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(122, 122, 5, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(123, 123, 5, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(124, 124, 5, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 5, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(126, 126, 5, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 3, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(128, 128, 3, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(130, 130, 5, 0x0050, 0x10, 30, 1), + PIN_FIELD_BASE(131, 131, 5, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(132, 132, 5, 0x0050, 0x10, 31, 1), + PIN_FIELD_BASE(133, 133, 1, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(134, 134, 1, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0030, 0x10, 21, 1), + PIN_FIELD_BASE(136, 136, 6, 0x0030, 0x10, 24, 1), + PIN_FIELD_BASE(137, 137, 1, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(138, 138, 1, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(143, 143, 6, 0x0030, 0x10, 22, 1), + PIN_FIELD_BASE(144, 144, 6, 0x0030, 0x10, 25, 1), + PIN_FIELD_BASE(145, 145, 6, 0x0030, 0x10, 23, 1), + PIN_FIELD_BASE(146, 146, 6, 0x0030, 0x10, 26, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0020, 0x10, 23, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0020, 0x10, 24, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0020, 0x10, 25, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0020, 0x10, 26, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0020, 0x10, 27, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0020, 0x10, 28, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0020, 0x10, 29, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0020, 0x10, 30, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0020, 0x10, 31, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(160, 160, 2, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(161, 161, 2, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(162, 162, 2, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(163, 163, 1, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(164, 164, 1, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(165, 165, 1, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(166, 166, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(167, 167, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(168, 168, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(169, 169, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(170, 170, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(171, 171, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(172, 172, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(181, 181, 6, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(182, 182, 6, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(183, 183, 2, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(184, 184, 2, 0x0040, 0x10, 22, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(2, 2, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(3, 3, 6, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(4, 4, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(5, 5, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(13, 13, 3, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(14, 14, 3, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(17, 17, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(19, 19, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(20, 20, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(21, 21, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(22, 22, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(23, 23, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(24, 24, 5, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(25, 25, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(26, 26, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(27, 27, 5, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 5, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(35, 35, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(45, 45, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(46, 46, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(47, 47, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(52, 52, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(53, 53, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(54, 54, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(55, 55, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(56, 56, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(57, 57, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(58, 58, 5, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(59, 59, 5, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(62, 62, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(63, 63, 3, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(64, 64, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(65, 65, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(66, 66, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(67, 67, 1, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(68, 68, 1, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(69, 69, 1, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 1, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 1, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 1, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 1, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 1, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 1, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 1, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 1, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(80, 80, 5, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(81, 81, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(82, 82, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(83, 83, 6, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(84, 84, 3, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 3, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 3, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(87, 87, 3, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, 3, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(91, 91, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(92, 92, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(94, 94, 3, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(95, 95, 3, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(99, 99, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(100, 100, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(101, 101, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(102, 102, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(103, 103, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(104, 104, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(105, 105, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(106, 106, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(109, 109, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(110, 110, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(111, 111, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(112, 112, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(115, 115, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(116, 116, 3, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(117, 117, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(118, 118, 3, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(119, 119, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(120, 120, 5, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(121, 121, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(122, 122, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(123, 123, 5, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(124, 124, 5, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 5, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(126, 126, 5, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 3, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(128, 128, 3, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(129, 129, 5, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(130, 130, 5, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(131, 131, 5, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(132, 132, 5, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(133, 133, 1, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(134, 134, 1, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(136, 136, 6, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(137, 137, 1, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(138, 138, 1, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(143, 143, 6, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(144, 144, 6, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(145, 145, 6, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(146, 146, 6, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(161, 161, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(162, 162, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(163, 163, 1, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(164, 164, 1, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(165, 165, 1, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(166, 166, 1, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(167, 167, 1, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(168, 168, 1, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(169, 169, 1, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(170, 170, 1, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(171, 171, 1, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(172, 172, 1, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(173, 173, 1, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(181, 181, 6, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(182, 182, 6, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(183, 183, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(184, 184, 2, 0x0090, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 6, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 6, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(3, 3, 6, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(4, 4, 6, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(5, 5, 6, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(13, 13, 3, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, 5, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(18, 18, 5, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(19, 19, 5, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(20, 20, 5, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 5, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(25, 25, 5, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(26, 26, 5, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, 5, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(28, 28, 5, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(35, 35, 2, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, 5, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0090, 0x10, 31, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0090, 0x10, 30, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(52, 52, 3, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(58, 58, 5, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(59, 59, 5, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(83, 83, 6, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(99, 99, 4, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(100, 100, 4, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(101, 101, 4, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(102, 102, 4, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(103, 103, 4, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 4, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(105, 105, 4, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(106, 106, 4, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(109, 109, 4, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(110, 110, 4, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(111, 111, 4, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(112, 112, 4, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 3, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(116, 116, 3, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(117, 117, 3, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(119, 119, 5, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(120, 120, 5, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(121, 121, 5, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(122, 122, 5, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(123, 123, 5, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(124, 124, 5, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 5, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(126, 126, 5, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 3, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(128, 128, 3, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(130, 130, 5, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(131, 131, 5, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(132, 132, 5, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(133, 133, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(134, 134, 1, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(136, 136, 6, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(137, 137, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 1, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(143, 143, 6, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(144, 144, 6, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(145, 145, 6, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(146, 146, 6, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0060, 0x10, 27, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0060, 0x10, 28, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0060, 0x10, 29, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0060, 0x10, 30, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0060, 0x10, 31, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(160, 160, 2, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(161, 161, 2, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(162, 162, 2, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(163, 163, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(164, 164, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(165, 165, 1, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(166, 166, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(167, 167, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(168, 168, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(169, 169, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(170, 170, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(171, 171, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(172, 172, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(181, 181, 6, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(182, 182, 6, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(183, 183, 2, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(184, 184, 2, 0x0060, 0x10, 22, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(1, 1, 6, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(2, 2, 6, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(3, 3, 6, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(4, 4, 6, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(5, 5, 6, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(10, 10, 4, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(11, 11, 4, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(12, 12, 4, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(13, 13, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(14, 14, 3, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(16, 16, 6, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, 5, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(18, 18, 5, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(19, 19, 5, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(20, 20, 5, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(21, 21, 5, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(22, 22, 5, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(23, 23, 5, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(24, 24, 5, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(25, 25, 5, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(26, 26, 5, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(27, 27, 5, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(28, 28, 5, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(29, 29, 6, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(30, 30, 6, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(31, 31, 6, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(32, 32, 2, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(33, 33, 2, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(34, 34, 2, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(35, 35, 2, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(40, 40, 2, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(41, 41, 2, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(42, 42, 2, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, 2, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, 5, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(45, 45, 5, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(46, 46, 5, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(47, 47, 5, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(48, 48, 2, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(49, 49, 2, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(50, 50, 2, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(51, 51, 2, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(52, 52, 3, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(53, 53, 3, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(54, 54, 3, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(55, 55, 3, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(56, 56, 5, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 5, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(58, 58, 5, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(59, 59, 5, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(83, 83, 6, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(90, 90, 3, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(91, 91, 3, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(92, 92, 3, 0x0060, 0x10, 25, 1), + PIN_FIELD_BASE(93, 93, 3, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(94, 94, 3, 0x0060, 0x10, 24, 1), + PIN_FIELD_BASE(95, 95, 3, 0x0060, 0x10, 26, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(99, 99, 4, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(100, 100, 4, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(101, 101, 4, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(102, 102, 4, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(103, 103, 4, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, 4, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(105, 105, 4, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(106, 106, 4, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(107, 107, 4, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(108, 108, 4, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(109, 109, 4, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(110, 110, 4, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(111, 111, 4, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(112, 112, 4, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 4, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(114, 114, 4, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(115, 115, 3, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(116, 116, 3, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(117, 117, 3, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(118, 118, 3, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(119, 119, 5, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(120, 120, 5, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(121, 121, 5, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(122, 122, 5, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(123, 123, 5, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(124, 124, 5, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(125, 125, 5, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(126, 126, 5, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, 3, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(128, 128, 3, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(129, 129, 5, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(130, 130, 5, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(131, 131, 5, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(132, 132, 5, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(133, 133, 1, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(134, 134, 1, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(135, 135, 6, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(136, 136, 6, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(137, 137, 1, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(138, 138, 1, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(139, 139, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(141, 141, 3, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(142, 142, 3, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(143, 143, 6, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(144, 144, 6, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(145, 145, 6, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(146, 146, 6, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(147, 147, 4, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(148, 148, 4, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(149, 149, 4, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(150, 150, 4, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(151, 151, 4, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(152, 152, 4, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(153, 153, 4, 0x0040, 0x10, 29, 1), + PIN_FIELD_BASE(154, 154, 4, 0x0040, 0x10, 30, 1), + PIN_FIELD_BASE(155, 155, 4, 0x0040, 0x10, 31, 1), + PIN_FIELD_BASE(156, 156, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(157, 157, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(158, 158, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(159, 159, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(160, 160, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(161, 161, 2, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(162, 162, 2, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(163, 163, 1, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(164, 164, 1, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(165, 165, 1, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(166, 166, 1, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(167, 167, 1, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(168, 168, 1, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(169, 169, 1, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(170, 170, 1, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(171, 171, 1, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(172, 172, 1, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(173, 173, 1, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(174, 174, 6, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(175, 175, 6, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(176, 176, 6, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(177, 177, 6, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(178, 178, 6, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(179, 179, 6, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(180, 180, 6, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(181, 181, 6, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(182, 182, 6, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(183, 183, 2, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(184, 184, 2, 0x0050, 0x10, 22, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_pupd_range[] = { + PIN_FIELD_BASE(67, 67, 1, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 1, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0070, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_r0_range[] = { + PIN_FIELD_BASE(67, 67, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(68, 68, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(69, 69, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 5, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 5, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 5, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 5, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x0090, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_r1_range[] = { + PIN_FIELD_BASE(67, 67, 1, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(68, 68, 1, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(69, 69, 1, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 1, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(71, 71, 1, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 1, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(73, 73, 1, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(74, 74, 1, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(75, 75, 1, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(76, 76, 1, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(77, 77, 1, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(78, 78, 1, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(79, 79, 5, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(80, 80, 5, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(81, 81, 5, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(82, 82, 5, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, 3, 0x00a0, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8186_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(1, 1, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(2, 2, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(3, 3, 6, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(4, 4, 6, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(5, 5, 6, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(6, 6, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(7, 7, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(8, 8, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(9, 9, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(10, 10, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(11, 11, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(12, 12, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(13, 13, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(14, 14, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(16, 16, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(17, 17, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(18, 18, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(19, 19, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(20, 20, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(21, 21, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(22, 22, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(23, 23, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(24, 24, 5, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(25, 25, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(26, 26, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(27, 27, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(28, 28, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(29, 29, 6, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(30, 30, 6, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(31, 31, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(32, 32, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(33, 33, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(34, 34, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(35, 35, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(36, 36, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(37, 37, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(38, 38, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(39, 39, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(40, 40, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(41, 41, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(44, 44, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(45, 45, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(46, 46, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(47, 47, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(48, 48, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(50, 50, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(51, 51, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(52, 52, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(53, 53, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(54, 54, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(55, 55, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(56, 56, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(57, 57, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(58, 58, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(59, 59, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(60, 60, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(61, 61, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(62, 62, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(63, 63, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(64, 64, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(65, 65, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(66, 66, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(67, 67, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(68, 68, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(69, 69, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(71, 71, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(72, 72, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(73, 73, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(74, 74, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(75, 75, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(76, 76, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(77, 77, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(78, 78, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(79, 79, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(80, 80, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(81, 81, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(82, 82, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(83, 83, 6, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(84, 84, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(85, 85, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(86, 86, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(87, 87, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(88, 88, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(89, 89, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(90, 90, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(91, 91, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(92, 92, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(93, 93, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(94, 94, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(95, 95, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(96, 96, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(97, 97, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(98, 98, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(99, 99, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(100, 100, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(101, 101, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(102, 102, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(103, 103, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(104, 104, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(105, 105, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(106, 106, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(107, 107, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(108, 108, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(109, 109, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(110, 110, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(111, 111, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(112, 112, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(113, 113, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(114, 114, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(115, 115, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(116, 116, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(117, 117, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(118, 118, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(119, 119, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(120, 120, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(121, 121, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(122, 122, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(124, 124, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(125, 125, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(126, 126, 5, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(127, 127, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(128, 128, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(129, 129, 5, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(130, 130, 5, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(131, 131, 5, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(132, 132, 5, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(133, 133, 1, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(134, 134, 1, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(135, 135, 6, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(136, 136, 6, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(137, 137, 1, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(138, 138, 1, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(139, 139, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(140, 140, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(143, 143, 6, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(144, 144, 6, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(145, 145, 6, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(146, 146, 6, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(147, 147, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(148, 148, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(149, 149, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(150, 150, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(151, 151, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(152, 152, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(153, 153, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(154, 154, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(155, 155, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(156, 156, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(157, 157, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(158, 158, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(159, 159, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(160, 160, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(161, 161, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(162, 162, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(163, 163, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(165, 165, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(166, 166, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(167, 167, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(168, 168, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(169, 169, 1, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(170, 170, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(171, 171, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(172, 172, 1, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(173, 173, 1, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(174, 174, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(175, 175, 6, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(176, 176, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(177, 177, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(178, 178, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(179, 179, 6, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(180, 180, 6, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(181, 181, 6, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(182, 182, 6, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(183, 183, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(184, 184, 2, 0x0010, 0x10, 0, 3), +}; + +static const struct mtk_pin_field_calc mt8186_pin_drv_adv_range[] = { + PIN_FIELD_BASE(127, 127, 3, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(128, 128, 3, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(129, 129, 5, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(130, 130, 5, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(131, 131, 5, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(132, 132, 5, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(133, 133, 1, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(134, 134, 1, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(135, 135, 6, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(136, 136, 6, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(137, 137, 1, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(138, 138, 1, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(139, 139, 2, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(140, 140, 2, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(141, 141, 3, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(142, 142, 3, 0x0030, 0x10, 9, 3), + PIN_FIELD_BASE(143, 143, 6, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(144, 144, 6, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(145, 145, 6, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(146, 146, 6, 0x0020, 0x10, 15, 3), +}; + +static const struct mtk_pin_field_calc mt8186_pin_rsel_range[] = { + PIN_FIELD_BASE(127, 127, 3, 0x00d0, 0x10, 0, 2), + PIN_FIELD_BASE(128, 128, 3, 0x00d0, 0x10, 4, 2), + PIN_FIELD_BASE(129, 129, 5, 0x00d0, 0x10, 0, 2), + PIN_FIELD_BASE(130, 130, 5, 0x00d0, 0x10, 4, 2), + PIN_FIELD_BASE(131, 131, 5, 0x00d0, 0x10, 2, 2), + PIN_FIELD_BASE(132, 132, 5, 0x00d0, 0x10, 6, 2), + PIN_FIELD_BASE(133, 133, 1, 0x00e0, 0x10, 0, 2), + PIN_FIELD_BASE(134, 134, 1, 0x00e0, 0x10, 4, 2), + PIN_FIELD_BASE(135, 135, 6, 0x0070, 0x10, 0, 2), + PIN_FIELD_BASE(136, 136, 6, 0x0070, 0x10, 6, 2), + PIN_FIELD_BASE(137, 137, 1, 0x00e0, 0x10, 2, 2), + PIN_FIELD_BASE(138, 138, 1, 0x00e0, 0x10, 6, 2), + PIN_FIELD_BASE(139, 139, 2, 0x0080, 0x10, 0, 2), + PIN_FIELD_BASE(140, 140, 2, 0x0080, 0x10, 2, 2), + PIN_FIELD_BASE(141, 141, 3, 0x00d0, 0x10, 2, 2), + PIN_FIELD_BASE(142, 142, 3, 0x00d0, 0x10, 6, 2), + PIN_FIELD_BASE(143, 143, 6, 0x0070, 0x10, 2, 2), + PIN_FIELD_BASE(144, 144, 6, 0x0070, 0x10, 8, 2), + PIN_FIELD_BASE(145, 145, 6, 0x0070, 0x10, 4, 2), + PIN_FIELD_BASE(146, 146, 6, 0x0070, 0x10, 10, 2), +}; + +static const struct mtk_pin_rsel mt8186_pin_rsel_val_range[] = { + PIN_RSEL(127, 128, 0x0, 75000, 75000), + PIN_RSEL(127, 128, 0x1, 10000, 75000), + PIN_RSEL(127, 128, 0x2, 5000, 5000), + PIN_RSEL(127, 128, 0x3, 1000, 5000), + PIN_RSEL(129, 130, 0x0, 75000, 75000), + PIN_RSEL(129, 130, 0x1, 10000, 75000), + PIN_RSEL(129, 130, 0x2, 5000, 5000), + PIN_RSEL(129, 130, 0x3, 1000, 5000), + PIN_RSEL(131, 132, 0x0, 75000, 75000), + PIN_RSEL(131, 132, 0x1, 10000, 75000), + PIN_RSEL(131, 132, 0x2, 5000, 5000), + PIN_RSEL(131, 132, 0x3, 1000, 5000), + PIN_RSEL(133, 134, 0x0, 75000, 75000), + PIN_RSEL(133, 134, 0x1, 10000, 75000), + PIN_RSEL(133, 134, 0x2, 5000, 5000), + PIN_RSEL(133, 134, 0x3, 1000, 5000), + PIN_RSEL(135, 136, 0x0, 75000, 75000), + PIN_RSEL(135, 136, 0x1, 10000, 75000), + PIN_RSEL(135, 136, 0x2, 5000, 5000), + PIN_RSEL(135, 136, 0x3, 1000, 5000), + PIN_RSEL(137, 138, 0x0, 75000, 75000), + PIN_RSEL(137, 138, 0x1, 10000, 75000), + PIN_RSEL(137, 138, 0x2, 5000, 5000), + PIN_RSEL(137, 138, 0x3, 1000, 5000), + PIN_RSEL(139, 140, 0x0, 75000, 75000), + PIN_RSEL(139, 140, 0x1, 10000, 75000), + PIN_RSEL(139, 140, 0x2, 5000, 5000), + PIN_RSEL(139, 140, 0x3, 1000, 5000), + PIN_RSEL(141, 142, 0x0, 75000, 75000), + PIN_RSEL(141, 142, 0x1, 10000, 75000), + PIN_RSEL(141, 142, 0x2, 5000, 5000), + PIN_RSEL(141, 142, 0x3, 1000, 5000), + PIN_RSEL(143, 144, 0x0, 75000, 75000), + PIN_RSEL(143, 144, 0x1, 10000, 75000), + PIN_RSEL(143, 144, 0x2, 5000, 5000), + PIN_RSEL(143, 144, 0x3, 1000, 5000), + PIN_RSEL(145, 146, 0x0, 75000, 75000), + PIN_RSEL(145, 146, 0x1, 10000, 75000), + PIN_RSEL(145, 146, 0x2, 5000, 5000), + PIN_RSEL(145, 146, 0x3, 1000, 5000), +}; + +static const unsigned int mt8186_pull_type[] = { + MTK_PULL_PU_PD_TYPE,/*0*/ MTK_PULL_PU_PD_TYPE,/*1*/ + MTK_PULL_PU_PD_TYPE,/*2*/ MTK_PULL_PU_PD_TYPE,/*3*/ + MTK_PULL_PU_PD_TYPE,/*4*/ MTK_PULL_PU_PD_TYPE,/*5*/ + MTK_PULL_PU_PD_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE,/*7*/ + MTK_PULL_PU_PD_TYPE,/*8*/ MTK_PULL_PU_PD_TYPE,/*9*/ + MTK_PULL_PU_PD_TYPE,/*10*/ MTK_PULL_PU_PD_TYPE,/*11*/ + MTK_PULL_PU_PD_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE,/*13*/ + MTK_PULL_PU_PD_TYPE,/*14*/ MTK_PULL_PU_PD_TYPE,/*15*/ + MTK_PULL_PU_PD_TYPE,/*16*/ MTK_PULL_PU_PD_TYPE,/*17*/ + MTK_PULL_PU_PD_TYPE,/*18*/ MTK_PULL_PU_PD_TYPE,/*19*/ + MTK_PULL_PU_PD_TYPE,/*20*/ MTK_PULL_PU_PD_TYPE,/*21*/ + MTK_PULL_PU_PD_TYPE,/*22*/ MTK_PULL_PU_PD_TYPE,/*23*/ + MTK_PULL_PU_PD_TYPE,/*24*/ MTK_PULL_PU_PD_TYPE,/*25*/ + MTK_PULL_PU_PD_TYPE,/*26*/ MTK_PULL_PU_PD_TYPE,/*27*/ + MTK_PULL_PU_PD_TYPE,/*28*/ MTK_PULL_PU_PD_TYPE,/*29*/ + MTK_PULL_PU_PD_TYPE,/*30*/ MTK_PULL_PU_PD_TYPE,/*31*/ + MTK_PULL_PU_PD_TYPE,/*32*/ MTK_PULL_PU_PD_TYPE,/*33*/ + MTK_PULL_PU_PD_TYPE,/*34*/ MTK_PULL_PU_PD_TYPE,/*35*/ + MTK_PULL_PU_PD_TYPE,/*36*/ MTK_PULL_PU_PD_TYPE,/*37*/ + MTK_PULL_PU_PD_TYPE,/*38*/ MTK_PULL_PU_PD_TYPE,/*39*/ + MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ + MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ + MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ + MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ + MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ + MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ + MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ + MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ + MTK_PULL_PU_PD_TYPE,/*56*/ MTK_PULL_PU_PD_TYPE,/*57*/ + MTK_PULL_PU_PD_TYPE,/*58*/ MTK_PULL_PU_PD_TYPE,/*59*/ + MTK_PULL_PU_PD_TYPE,/*60*/ MTK_PULL_PU_PD_TYPE,/*61*/ + MTK_PULL_PU_PD_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE,/*63*/ + MTK_PULL_PU_PD_TYPE,/*64*/ MTK_PULL_PU_PD_TYPE,/*65*/ + MTK_PULL_PU_PD_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ + MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PUPD_R1R0_TYPE,/*71*/ + MTK_PULL_PUPD_R1R0_TYPE,/*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ + MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PUPD_R1R0_TYPE,/*75*/ + MTK_PULL_PUPD_R1R0_TYPE,/*76*/ MTK_PULL_PUPD_R1R0_TYPE,/*77*/ + MTK_PULL_PUPD_R1R0_TYPE,/*78*/ MTK_PULL_PUPD_R1R0_TYPE,/*79*/ + MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ + MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PUPD_R1R0_TYPE,/*84*/ MTK_PULL_PUPD_R1R0_TYPE,/*85*/ + MTK_PULL_PUPD_R1R0_TYPE,/*86*/ MTK_PULL_PUPD_R1R0_TYPE,/*87*/ + MTK_PULL_PUPD_R1R0_TYPE,/*88*/ MTK_PULL_PUPD_R1R0_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100*/ MTK_PULL_PU_PD_TYPE,/*101*/ + MTK_PULL_PU_PD_TYPE,/*102*/ MTK_PULL_PU_PD_TYPE,/*103*/ + MTK_PULL_PU_PD_TYPE,/*104*/ MTK_PULL_PU_PD_TYPE,/*105*/ + MTK_PULL_PU_PD_TYPE,/*106*/ MTK_PULL_PU_PD_TYPE,/*107*/ + MTK_PULL_PU_PD_TYPE,/*108*/ MTK_PULL_PU_PD_TYPE,/*109*/ + MTK_PULL_PU_PD_TYPE,/*110*/ MTK_PULL_PU_PD_TYPE,/*111*/ + MTK_PULL_PU_PD_TYPE,/*112*/ MTK_PULL_PU_PD_TYPE,/*113*/ + MTK_PULL_PU_PD_TYPE,/*114*/ MTK_PULL_PU_PD_TYPE,/*115*/ + MTK_PULL_PU_PD_TYPE,/*116*/ MTK_PULL_PU_PD_TYPE,/*117*/ + MTK_PULL_PU_PD_TYPE,/*118*/ MTK_PULL_PU_PD_TYPE,/*119*/ + MTK_PULL_PU_PD_TYPE,/*120*/ MTK_PULL_PU_PD_TYPE,/*121*/ + MTK_PULL_PU_PD_TYPE,/*122*/ MTK_PULL_PU_PD_TYPE,/*123*/ + MTK_PULL_PU_PD_TYPE,/*124*/ MTK_PULL_PU_PD_TYPE,/*125*/ + MTK_PULL_PU_PD_TYPE,/*126*/ MTK_PULL_PU_PD_RSEL_TYPE,/*127*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*128*/ MTK_PULL_PU_PD_RSEL_TYPE,/*129*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*130*/ MTK_PULL_PU_PD_RSEL_TYPE,/*131*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*132*/ MTK_PULL_PU_PD_RSEL_TYPE,/*133*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*134*/ MTK_PULL_PU_PD_RSEL_TYPE,/*135*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*136*/ MTK_PULL_PU_PD_RSEL_TYPE,/*137*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*138*/ MTK_PULL_PU_PD_RSEL_TYPE,/*139*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*140*/ MTK_PULL_PU_PD_RSEL_TYPE,/*141*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*142*/ MTK_PULL_PU_PD_RSEL_TYPE,/*143*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*144*/ MTK_PULL_PU_PD_RSEL_TYPE,/*145*/ + MTK_PULL_PU_PD_RSEL_TYPE,/*146*/ MTK_PULL_PU_PD_TYPE,/*147*/ + MTK_PULL_PU_PD_TYPE,/*148*/ MTK_PULL_PU_PD_TYPE,/*149*/ + MTK_PULL_PU_PD_TYPE,/*150*/ MTK_PULL_PU_PD_TYPE,/*151*/ + MTK_PULL_PU_PD_TYPE,/*152*/ MTK_PULL_PU_PD_TYPE,/*153*/ + MTK_PULL_PU_PD_TYPE,/*154*/ MTK_PULL_PU_PD_TYPE,/*155*/ + MTK_PULL_PU_PD_TYPE,/*156*/ MTK_PULL_PU_PD_TYPE,/*157*/ + MTK_PULL_PU_PD_TYPE,/*158*/ MTK_PULL_PU_PD_TYPE,/*159*/ + MTK_PULL_PU_PD_TYPE,/*160*/ MTK_PULL_PU_PD_TYPE,/*161*/ + MTK_PULL_PU_PD_TYPE,/*162*/ MTK_PULL_PU_PD_TYPE,/*163*/ + MTK_PULL_PU_PD_TYPE,/*164*/ MTK_PULL_PU_PD_TYPE,/*165*/ + MTK_PULL_PU_PD_TYPE,/*166*/ MTK_PULL_PU_PD_TYPE,/*167*/ + MTK_PULL_PU_PD_TYPE,/*168*/ MTK_PULL_PU_PD_TYPE,/*169*/ + MTK_PULL_PU_PD_TYPE,/*170*/ MTK_PULL_PU_PD_TYPE,/*171*/ + MTK_PULL_PU_PD_TYPE,/*172*/ MTK_PULL_PU_PD_TYPE,/*173*/ + MTK_PULL_PU_PD_TYPE,/*174*/ MTK_PULL_PU_PD_TYPE,/*175*/ + MTK_PULL_PU_PD_TYPE,/*176*/ MTK_PULL_PU_PD_TYPE,/*177*/ + MTK_PULL_PU_PD_TYPE,/*178*/ MTK_PULL_PU_PD_TYPE,/*179*/ + MTK_PULL_PU_PD_TYPE,/*180*/ MTK_PULL_PU_PD_TYPE,/*181*/ + MTK_PULL_PU_PD_TYPE,/*182*/ MTK_PULL_PU_PD_TYPE,/*183*/ + MTK_PULL_PU_PD_TYPE,/*184*/ +}; + +static const struct mtk_pin_reg_calc mt8186_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8186_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8186_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8186_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8186_pin_do_range), + [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8186_pin_dir_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8186_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8186_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8186_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8186_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8186_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8186_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8186_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8186_pin_r1_range), + [PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8186_pin_drv_adv_range), + [PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8186_pin_rsel_range), + +}; + +static const char * const mt8186_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb", "iocfg_bl", + "iocfg_rb", "iocfg_rt", +}; + +static const struct mtk_eint_hw mt8186_eint_hw = { + .port_mask = 0xf, + .ports = 7, + .ap_num = 217, + .db_cnt = 32, +}; + +static const struct mtk_pin_soc mt8186_data = { + .reg_cal = mt8186_reg_cals, + .pins = mtk_pins_mt8186, + .npins = ARRAY_SIZE(mtk_pins_mt8186), + .ngrps = ARRAY_SIZE(mtk_pins_mt8186), + .nfuncs = 8, + .gpio_m = 0, + .eint_hw = &mt8186_eint_hw, + .base_names = mt8186_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8186_pinctrl_register_base_names), + .pull_type = mt8186_pull_type, + .pin_rsel = mt8186_pin_rsel_val_range, + .npin_rsel = ARRAY_SIZE(mt8186_pin_rsel_val_range), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_drive_get = mtk_pinconf_adv_drive_get_raw, + .adv_drive_set = mtk_pinconf_adv_drive_set_raw, +}; + +static const struct of_device_id mt8186_pinctrl_of_match[] = { + { .compatible = "mediatek,mt8186-pinctrl", .data = &mt8186_data }, + { } +}; + +static struct platform_driver mt8186_pinctrl_driver = { + .driver = { + .name = "mt8186-pinctrl", + .of_match_table = mt8186_pinctrl_of_match, + .pm = &mtk_paris_pinctrl_pm_ops, + }, + .probe = mtk_paris_pinctrl_probe, +}; + +static int __init mt8186_pinctrl_init(void) +{ + return platform_driver_register(&mt8186_pinctrl_driver); +} + +arch_initcall(mt8186_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c index 0c16b2c756bf..acccde9262ba 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8192.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -1381,22 +1381,17 @@ static const struct mtk_pin_soc mt8192_data = { }; static const struct of_device_id mt8192_pinctrl_of_match[] = { - { .compatible = "mediatek,mt8192-pinctrl", }, + { .compatible = "mediatek,mt8192-pinctrl", .data = &mt8192_data }, { } }; -static int mt8192_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt8192_data); -} - static struct platform_driver mt8192_pinctrl_driver = { .driver = { .name = "mt8192-pinctrl", .of_match_table = mt8192_pinctrl_of_match, .pm = &mtk_paris_pinctrl_pm_ops, }, - .probe = mt8192_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt8192_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c index 275b7ba4386d..563693d3d4c2 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8195.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -959,22 +959,17 @@ static const struct mtk_pin_soc mt8195_data = { }; static const struct of_device_id mt8195_pinctrl_of_match[] = { - { .compatible = "mediatek,mt8195-pinctrl", }, + { .compatible = "mediatek,mt8195-pinctrl", .data = &mt8195_data }, { } }; -static int mt8195_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_paris_pinctrl_probe(pdev, &mt8195_data); -} - static struct platform_driver mt8195_pinctrl_driver = { .driver = { .name = "mt8195-pinctrl", .of_match_table = mt8195_pinctrl_of_match, .pm = &mtk_paris_pinctrl_pm_ops, }, - .probe = mt8195_pinctrl_probe, + .probe = mtk_paris_pinctrl_probe, }; static int __init mt8195_pinctrl_init(void) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index 79b1fee5a1eb..727c65221aef 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -416,25 +416,6 @@ static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), }; -static int mt8365_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8365_spec_pupd, - ARRAY_SIZE(mt8365_spec_pupd), pin, align, isup, r1r0); -} - -static int mt8365_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_ies_set, - ARRAY_SIZE(mt8365_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_smt_set, - ARRAY_SIZE(mt8365_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .pins = mtk_pins_mt8365, .npins = ARRAY_SIZE(mtk_pins_mt8365), @@ -442,8 +423,14 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8365_drv_grp), .pin_drv_grp = mt8365_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8365_pin_drv), - .spec_pull_set = mt8365_spec_pull_set, - .spec_ies_smt_set = mt8365_ies_smt_set, + .spec_ies = mt8365_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8365_ies_set), + .spec_smt = mt8365_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8365_smt_set), + .spec_pupd = mt8365_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8365_spec_pupd), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0140, .dout_offset = 0x00A0, .din_offset = 0x0000, @@ -469,20 +456,13 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { }, }; -static int mtk_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8365_pinctrl_data, NULL); -} - static const struct of_device_id mt8365_pctrl_match[] = { - { - .compatible = "mediatek,mt8365-pinctrl", - }, + { .compatible = "mediatek,mt8365-pinctrl", .data = &mt8365_pinctrl_data }, {} }; static struct platform_driver mtk_pinctrl_driver = { - .probe = mtk_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8365-pinctrl", .of_match_table = mt8365_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index 219fb4bc341f..939a1932b8dc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -186,13 +186,6 @@ static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = { MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0), }; -static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd, - ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0); -} - static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = { MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2), MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3), @@ -292,18 +285,6 @@ static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = { MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9), }; -static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set, - ARRAY_SIZE(mt8516_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set, - ARRAY_SIZE(mt8516_smt_set), pin, align, value); - return -EINVAL; -} - static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { .pins = mtk_pins_mt8516, .npins = ARRAY_SIZE(mtk_pins_mt8516), @@ -311,8 +292,14 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp), .pin_drv_grp = mt8516_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv), - .spec_pull_set = mt8516_spec_pull_set, - .spec_ies_smt_set = mt8516_ies_smt_set, + .spec_ies = mt8516_ies_set, + .n_spec_ies = ARRAY_SIZE(mt8516_ies_set), + .spec_pupd = mt8516_spec_pupd, + .n_spec_pupd = ARRAY_SIZE(mt8516_spec_pupd), + .spec_smt = mt8516_smt_set, + .n_spec_smt = ARRAY_SIZE(mt8516_smt_set), + .spec_pull_set = mtk_pctrl_spec_pull_set_samereg, + .spec_ies_smt_set = mtk_pconf_spec_set_ies_smt_range, .dir_offset = 0x0000, .pullen_offset = 0x0500, .pullsel_offset = 0x0600, @@ -335,22 +322,15 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { }, }; -static int mt8516_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL); -} - static const struct of_device_id mt8516_pctrl_match[] = { - { - .compatible = "mediatek,mt8516-pinctrl", - }, + { .compatible = "mediatek,mt8516-pinctrl", .data = &mt8516_pinctrl_data }, {} }; MODULE_DEVICE_TABLE(of, mt8516_pctrl_match); static struct platform_driver mtk_pinctrl_driver = { - .probe = mt8516_pinctrl_probe, + .probe = mtk_pctrl_common_probe, .driver = { .name = "mediatek-mt8516-pinctrl", .of_match_table = mt8516_pctrl_match, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 5f7c421ab6e7..f25b3e09386b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -131,7 +131,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, */ if (pctl->devdata->spec_ies_smt_set) { return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), - pin, pctl->devdata->port_align, value, arg); + pctl->devdata, pin, value, arg); } if (arg == PIN_CONFIG_INPUT_ENABLE) @@ -151,10 +151,27 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, } int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, - const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, - unsigned int pin, unsigned char align, int value) + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, int value, enum pin_config_param arg) { - unsigned int i, reg_addr, bit; + const struct mtk_pin_ies_smt_set *ies_smt_infos = NULL; + unsigned int i, info_num, reg_addr, bit; + + switch (arg) { + case PIN_CONFIG_INPUT_ENABLE: + ies_smt_infos = devdata->spec_ies; + info_num = devdata->n_spec_ies; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + ies_smt_infos = devdata->spec_smt; + info_num = devdata->n_spec_smt; + break; + default: + break; + } + + if (!ies_smt_infos) + return -EINVAL; for (i = 0; i < info_num; i++) { if (pin >= ies_smt_infos[i].start && @@ -167,9 +184,9 @@ int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, return -EINVAL; if (value) - reg_addr = ies_smt_infos[i].offset + align; + reg_addr = ies_smt_infos[i].offset + devdata->port_align; else - reg_addr = ies_smt_infos[i].offset + (align << 1); + reg_addr = ies_smt_infos[i].offset + (devdata->port_align << 1); bit = BIT(ies_smt_infos[i].bit); regmap_write(regmap, reg_addr, bit); @@ -222,9 +239,8 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, } int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, - const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, - unsigned int info_num, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0) { unsigned int i; unsigned int reg_pupd, reg_set, reg_rst; @@ -232,8 +248,11 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin; bool find = false; - for (i = 0; i < info_num; i++) { - if (pin == pupd_infos[i].pin) { + if (!devdata->spec_pupd) + return -EINVAL; + + for (i = 0; i < devdata->n_spec_pupd; i++) { + if (pin == devdata->spec_pupd[i].pin) { find = true; break; } @@ -242,9 +261,9 @@ int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, if (!find) return -EINVAL; - spec_pupd_pin = pupd_infos + i; - reg_set = spec_pupd_pin->offset + align; - reg_rst = spec_pupd_pin->offset + (align << 1); + spec_pupd_pin = devdata->spec_pupd + i; + reg_set = spec_pupd_pin->offset + devdata->port_align; + reg_rst = spec_pupd_pin->offset + (devdata->port_align << 1); if (isup) reg_pupd = reg_rst; @@ -298,7 +317,8 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, */ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00; ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), - pin, pctl->devdata->port_align, isup, r1r0); + pctl->devdata, pin, isup, + r1r0); if (!ret) return 0; } @@ -1013,10 +1033,12 @@ static int mtk_eint_init(struct mtk_pinctrl *pctl, struct platform_device *pdev) return mtk_eint_do_init(pctl->eint); } +/* This is used as a common probe function */ int mtk_pctrl_init(struct platform_device *pdev, const struct mtk_pinctrl_devdata *data, struct regmap *regmap) { + struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *pctl; struct device_node *np = pdev->dev.of_node, *node; @@ -1030,37 +1052,35 @@ int mtk_pctrl_init(struct platform_device *pdev, platform_set_drvdata(pdev, pctl); prop = of_find_property(np, "pins-are-numbered", NULL); - if (!prop) { - dev_err(&pdev->dev, "only support pins-are-numbered format\n"); - return -EINVAL; - } + if (!prop) + return dev_err_probe(dev, -EINVAL, + "only support pins-are-numbered format\n"); node = of_parse_phandle(np, "mediatek,pctl-regmap", 0); if (node) { pctl->regmap1 = syscon_node_to_regmap(node); + of_node_put(node); if (IS_ERR(pctl->regmap1)) return PTR_ERR(pctl->regmap1); } else if (regmap) { pctl->regmap1 = regmap; } else { - dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n"); - return -EINVAL; + return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n"); } /* Only 8135 has two base addr, other SoCs have only one. */ node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); if (node) { pctl->regmap2 = syscon_node_to_regmap(node); + of_node_put(node); if (IS_ERR(pctl->regmap2)) return PTR_ERR(pctl->regmap2); } pctl->devdata = data; ret = mtk_pctrl_build_state(pdev); - if (ret) { - dev_err(&pdev->dev, "build state failed: %d\n", ret); - return -EINVAL; - } + if (ret) + return dev_err_probe(dev, ret, "build state failed\n"); pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins), GFP_KERNEL); @@ -1081,10 +1101,9 @@ int mtk_pctrl_init(struct platform_device *pdev, pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, pctl); - if (IS_ERR(pctl->pctl_dev)) { - dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); - return PTR_ERR(pctl->pctl_dev); - } + if (IS_ERR(pctl->pctl_dev)) + return dev_err_probe(dev, PTR_ERR(pctl->pctl_dev), + "Couldn't register pinctrl driver\n"); pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); if (!pctl->chip) @@ -1118,3 +1137,14 @@ chip_error: gpiochip_remove(pctl->chip); return ret; } + +int mtk_pctrl_common_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct mtk_pinctrl_devdata *data = device_get_match_data(dev); + + if (!data) + return -ENODEV; + + return mtk_pctrl_init(pdev, data, NULL); +} diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 98f27cdc609a..6fe8564334c9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -193,6 +193,12 @@ struct mtk_eint_offsets { * * @grp_desc: The driving group info. * @pin_drv_grp: The driving group for all pins. + * @spec_ies: Special pin setting for input enable + * @n_spec_ies: Number of entries in spec_ies + * @spec_pupd: Special pull up/down setting + * @n_spec_pupd: Number of entries in spec_pupd + * @spec_smt: Special pin setting for schmitt + * @n_spec_smt: Number of entries in spec_smt * @spec_pull_set: Each SoC may have special pins for pull up/down setting, * these pins' pull setting are very different, they have separate pull * up/down bit, R0 and R1 resistor bit, so they need special pull setting. @@ -231,10 +237,18 @@ struct mtk_pinctrl_devdata { unsigned int n_grp_cls; const struct mtk_pin_drv_grp *pin_drv_grp; unsigned int n_pin_drv_grps; - int (*spec_pull_set)(struct regmap *reg, unsigned int pin, - unsigned char align, bool isup, unsigned int arg); - int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg); + const struct mtk_pin_ies_smt_set *spec_ies; + unsigned int n_spec_ies; + const struct mtk_pin_spec_pupd_set_samereg *spec_pupd; + unsigned int n_spec_pupd; + const struct mtk_pin_ies_smt_set *spec_smt; + unsigned int n_spec_smt; + int (*spec_pull_set)(struct regmap *regmap, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0); + int (*spec_ies_smt_set)(struct regmap *reg, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, int value, enum pin_config_param arg); void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, unsigned int mode); void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); @@ -277,14 +291,15 @@ int mtk_pctrl_init(struct platform_device *pdev, const struct mtk_pinctrl_devdata *data, struct regmap *regmap); +int mtk_pctrl_common_probe(struct platform_device *pdev); + int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap, - const struct mtk_pin_spec_pupd_set_samereg *pupd_infos, - unsigned int info_num, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0); + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int r1r0); int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap, - const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num, - unsigned int pin, unsigned char align, int value); + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, int value, enum pin_config_param arg); extern const struct dev_pm_ops mtk_eint_pm_ops; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h new file mode 100644 index 000000000000..464651f7b44b --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8186.h @@ -0,0 +1,2186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 MediaTek Inc. + * + * Author: Guodong Liu + * + */ + +#ifndef __PINCTRL_MTK_MT8186_H +#define __PINCTRL_MTK_MT8186_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt8186[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "SPI0_CLK_B"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "CMFLASH0"), + MTK_FUNCTION(5, "SCP_SPI0_CK"), + MTK_FUNCTION(6, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "dbg_mon_a0") + ), + + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "SPI0_CSB_B"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "CMFLASH1"), + MTK_FUNCTION(5, "SCP_SPI0_CS"), + MTK_FUNCTION(6, "TP_GPIO1_AO") + ), + + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "SPI0_MO_B"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "CMFLASH2"), + MTK_FUNCTION(5, "SCP_SPI0_MO"), + MTK_FUNCTION(6, "TP_GPIO2_AO") + ), + + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "SPI0_MI_B"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "SRCLKENAI1"), + MTK_FUNCTION(5, "SCP_SPI0_MI"), + MTK_FUNCTION(6, "TP_GPIO3_AO") + ), + + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "I2S3_DO"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(6, "TP_GPIO4_AO") + ), + + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "EXT_FRAME_SYNC"), + MTK_FUNCTION(6, "TP_GPIO5_AO") + ), + + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "I2S3_MCK"), + MTK_FUNCTION(2, "SPI1_CLK_B"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "DPI_DATA22"), + MTK_FUNCTION(6, "TP_GPIO6_AO") + ), + + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "I2S3_BCK"), + MTK_FUNCTION(2, "SPI1_CSB_B"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "DPI_DATA23"), + MTK_FUNCTION(6, "TP_GPIO7_AO") + ), + + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "I2S3_LRCK"), + MTK_FUNCTION(2, "SPI1_MO_B"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "CONN_UART0_RXD"), + MTK_FUNCTION(5, "SSPM_URXD_AO"), + MTK_FUNCTION(6, "ADSP_UART_RX"), + MTK_FUNCTION(7, "CONN_MCU_DBGACK_N") + ), + + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "I2S3_DO"), + MTK_FUNCTION(2, "SPI1_MI_B"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "CONN_UART0_TXD"), + MTK_FUNCTION(5, "SSPM_UTXD_AO"), + MTK_FUNCTION(6, "ADSP_UART_TX"), + MTK_FUNCTION(7, "CONN_MCU_DBGI_N") + ), + + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "SPI4_CLK_A"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "SPM_JTAG_TDI"), + MTK_FUNCTION(5, "SCP_JTAG_TDI"), + MTK_FUNCTION(6, "ADSP_JTAG_TDI"), + MTK_FUNCTION(7, "CONN_MCU_TDI") + ), + + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "SPI4_CSB_A"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "SPM_JTAG_TRSTN"), + MTK_FUNCTION(5, "SCP_JTAG_TRSTN"), + MTK_FUNCTION(6, "ADSP_JTAG_TRSTN"), + MTK_FUNCTION(7, "CONN_MCU_TRST_B") + ), + + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "SPI4_MO_A"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "SPM_JTAG_TCK"), + MTK_FUNCTION(5, "SCP_JTAG_TCK"), + MTK_FUNCTION(6, "ADSP_JTAG_TCK"), + MTK_FUNCTION(7, "CONN_MCU_TCK") + ), + + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "SPI4_MI_A"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "SPM_JTAG_TDO"), + MTK_FUNCTION(5, "SCP_JTAG_TDO"), + MTK_FUNCTION(6, "ADSP_JTAG_TDO"), + MTK_FUNCTION(7, "CONN_MCU_TDO") + ), + + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "SPM_JTAG_TMS"), + MTK_FUNCTION(5, "SCP_JTAG_TMS"), + MTK_FUNCTION(6, "ADSP_JTAG_TMS"), + MTK_FUNCTION(7, "CONN_MCU_TMS") + ), + + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "EXT_FRAME_SYNC"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PWM0") + ), + + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "CONN_WIFI_TXD"), + MTK_FUNCTION(2, "SRCLKENAI0"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PWM1") + ), + + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(7, "dbg_mon_a32") + ), + + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(6, "SPI2_CLK_B"), + MTK_FUNCTION(7, "dbg_mon_a26") + ), + + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "SPI2_CSB_B"), + MTK_FUNCTION(7, "dbg_mon_a2") + ), + + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(2, "CMVREF2"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "SPI2_MO_B"), + MTK_FUNCTION(7, "dbg_mon_a3") + ), + + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "I2S3_MCK"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "SPI2_MI_B"), + MTK_FUNCTION(7, "dbg_mon_a4") + ), + + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "TDM_RX_LRCK"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(7, "dbg_mon_a5") + ), + + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "TDM_RX_BCK"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(7, "dbg_mon_a6") + ), + + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "TDM_RX_MCK"), + MTK_FUNCTION(7, "dbg_mon_a7") + ), + + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "I2S2_MCK"), + MTK_FUNCTION(2, "PCM_CLK"), + MTK_FUNCTION(3, "SPI4_CLK_B"), + MTK_FUNCTION(4, "TDM_RX_DATA0"), + MTK_FUNCTION(7, "dbg_mon_a8") + ), + + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "I2S2_BCK"), + MTK_FUNCTION(2, "PCM_SYNC"), + MTK_FUNCTION(3, "SPI4_CSB_B"), + MTK_FUNCTION(4, "TDM_RX_DATA1"), + MTK_FUNCTION(7, "dbg_mon_a9") + ), + + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "I2S2_LRCK"), + MTK_FUNCTION(2, "PCM_DI"), + MTK_FUNCTION(3, "SPI4_MO_B"), + MTK_FUNCTION(4, "TDM_RX_DATA2"), + MTK_FUNCTION(7, "dbg_mon_a10") + ), + + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "I2S2_DI"), + MTK_FUNCTION(2, "PCM_DO"), + MTK_FUNCTION(3, "SPI4_MI_B"), + MTK_FUNCTION(4, "TDM_RX_DATA3") + ), + + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN") + ), + + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "ANT_SEL1") + ), + + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(3, "SRCLKENAI1") + ), + + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(3, "ADSP_UART_RX"), + MTK_FUNCTION(4, "TP_URXD1_AO") + ), + + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0"), + MTK_FUNCTION(3, "ADSP_UART_TX"), + MTK_FUNCTION(4, "TP_UTXD1_AO") + ), + + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "TP_URXD2_AO"), + MTK_FUNCTION(3, "SSPM_URXD_AO"), + MTK_FUNCTION(4, "ADSP_UART_RX"), + MTK_FUNCTION(5, "CONN_UART0_RXD") + ), + + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "TP_UTXD2_AO"), + MTK_FUNCTION(3, "SSPM_UTXD_AO"), + MTK_FUNCTION(4, "ADSP_UART_TX"), + MTK_FUNCTION(5, "CONN_UART0_TXD"), + MTK_FUNCTION(6, "CONN_WIFI_TXD") + ), + + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SPI0_CLK_A"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(4, "SCP_SPI0_CK"), + MTK_FUNCTION(5, "SPINOR_CK"), + MTK_FUNCTION(7, "dbg_mon_a11") + ), + + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "SPI0_CSB_A"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "SCP_SPI0_CS"), + MTK_FUNCTION(5, "SPINOR_CS"), + MTK_FUNCTION(7, "dbg_mon_a12") + ), + + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SPI0_MO_A"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "SCP_SPI0_MO"), + MTK_FUNCTION(5, "SPINOR_IO0"), + MTK_FUNCTION(7, "dbg_mon_a13") + ), + + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "SPI0_MI_A"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "SCP_SPI0_MI"), + MTK_FUNCTION(5, "SPINOR_IO1"), + MTK_FUNCTION(7, "dbg_mon_a14") + ), + + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "SPI1_CLK_A"), + MTK_FUNCTION(2, "SCP_SPI1_CK"), + MTK_FUNCTION(4, "UCTS0"), + MTK_FUNCTION(5, "SPINOR_IO2"), + MTK_FUNCTION(6, "TP_UCTS1_AO"), + MTK_FUNCTION(7, "dbg_mon_a15") + ), + + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "SPI1_CSB_A"), + MTK_FUNCTION(2, "SCP_SPI1_CS"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "URTS0"), + MTK_FUNCTION(5, "SPINOR_IO3"), + MTK_FUNCTION(6, "TP_URTS1_AO"), + MTK_FUNCTION(7, "dbg_mon_a16") + ), + + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "SPI1_MO_A"), + MTK_FUNCTION(2, "SCP_SPI1_MO"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "UCTS1"), + MTK_FUNCTION(6, "TP_UCTS2_AO"), + MTK_FUNCTION(7, "dbg_mon_a17") + ), + + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "SPI1_MI_A"), + MTK_FUNCTION(2, "SCP_SPI1_MI"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "URTS1"), + MTK_FUNCTION(6, "TP_URTS2_AO"), + MTK_FUNCTION(7, "dbg_mon_a18") + ), + + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "SPI2_CLK_A"), + MTK_FUNCTION(2, "SCP_SPI0_CK"), + MTK_FUNCTION(7, "dbg_mon_a19") + ), + + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "SPI2_CSB_A"), + MTK_FUNCTION(2, "SCP_SPI0_CS"), + MTK_FUNCTION(7, "dbg_mon_a20") + ), + + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "SPI2_MO_A"), + MTK_FUNCTION(2, "SCP_SPI0_MO"), + MTK_FUNCTION(7, "dbg_mon_a21") + ), + + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "SPI2_MI_A"), + MTK_FUNCTION(2, "SCP_SPI0_MI"), + MTK_FUNCTION(7, "dbg_mon_a22") + ), + + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SPI3_CLK"), + MTK_FUNCTION(2, "TP_URXD1_AO"), + MTK_FUNCTION(3, "TP_URXD2_AO"), + MTK_FUNCTION(4, "URXD1"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "SCP_SPI0_CK") + ), + + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "SPI3_CSB"), + MTK_FUNCTION(2, "TP_UTXD1_AO"), + MTK_FUNCTION(3, "TP_UTXD2_AO"), + MTK_FUNCTION(4, "UTXD1"), + MTK_FUNCTION(5, "I2S2_BCK"), + MTK_FUNCTION(6, "SCP_SPI0_CS") + ), + + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "SPI3_MO"), + MTK_FUNCTION(5, "I2S2_LRCK"), + MTK_FUNCTION(6, "SCP_SPI0_MO") + ), + + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "SPI3_MI"), + MTK_FUNCTION(5, "I2S2_DI"), + MTK_FUNCTION(6, "SCP_SPI0_MI") + ), + + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "SPI5_CLK"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "SCP_SPI1_CK"), + MTK_FUNCTION(5, "LVTS_26M"), + MTK_FUNCTION(6, "DFD_TCK_XI"), + MTK_FUNCTION(7, "dbg_mon_b30") + ), + + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SPI5_CSB"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "SCP_SPI1_CS"), + MTK_FUNCTION(5, "LVTS_FOUT"), + MTK_FUNCTION(6, "DFD_TDI"), + MTK_FUNCTION(7, "dbg_mon_b31") + ), + + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "SPI5_MO"), + MTK_FUNCTION(2, "I2S2_LRCK"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "SCP_SPI1_MO"), + MTK_FUNCTION(5, "LVTS_SCK"), + MTK_FUNCTION(6, "DFD_TDO"), + MTK_FUNCTION(7, "dbg_mon_a1") + ), + + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SPI5_MI"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "SCP_SPI1_MI"), + MTK_FUNCTION(5, "LVTS_SDO"), + MTK_FUNCTION(6, "DFD_TMS"), + MTK_FUNCTION(7, "dbg_mon_b32") + ), + + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "I2S1_DO"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(7, "dbg_mon_a23") + ), + + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "I2S1_BCK"), + MTK_FUNCTION(2, "I2S3_BCK"), + MTK_FUNCTION(7, "dbg_mon_a24") + ), + + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "I2S1_LRCK"), + MTK_FUNCTION(2, "I2S3_LRCK"), + MTK_FUNCTION(7, "dbg_mon_a25") + ), + + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "I2S1_MCK"), + MTK_FUNCTION(2, "I2S3_MCK"), + MTK_FUNCTION(7, "dbg_mon_a27") + ), + + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "TDM_RX_LRCK"), + MTK_FUNCTION(2, "ANT_SEL3"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N") + ), + + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "TDM_RX_BCK"), + MTK_FUNCTION(2, "ANT_SEL4"), + MTK_FUNCTION(4, "SPINOR_CK"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N") + ), + + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "TDM_RX_MCK"), + MTK_FUNCTION(2, "ANT_SEL5"), + MTK_FUNCTION(4, "SPINOR_CS"), + MTK_FUNCTION(5, "CONN_MCU_TDI") + ), + + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "TDM_RX_DATA0"), + MTK_FUNCTION(2, "ANT_SEL6"), + MTK_FUNCTION(4, "SPINOR_IO0"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B") + ), + + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "TDM_RX_DATA1"), + MTK_FUNCTION(2, "ANT_SEL7"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "SPINOR_IO1"), + MTK_FUNCTION(5, "CONN_MCU_TCK") + ), + + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "TDM_RX_DATA2"), + MTK_FUNCTION(2, "UCTS0"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "SPINOR_IO2"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(6, "TP_UCTS1_AO"), + MTK_FUNCTION(7, "TP_UCTS2_AO") + ), + + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "TDM_RX_DATA3"), + MTK_FUNCTION(2, "URTS0"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "SPINOR_IO3"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "TP_URTS1_AO"), + MTK_FUNCTION(7, "TP_URTS2_AO") + ), + + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "MSDC0_DSL") + ), + + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "MSDC0_CLK") + ), + + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "KPCOL0") + ), + + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "PWM0"), + MTK_FUNCTION(4, "CLKM0") + ), + + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(4, "CLKM1") + ), + + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(4, "CLKM2") + ), + + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "AP_GOOD"), + MTK_FUNCTION(2, "GPS_PPS"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(7, "dbg_mon_a28") + ), + + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "ADSP_JTAG_TCK"), + MTK_FUNCTION(4, "UDI_TCK"), + MTK_FUNCTION(5, "CONN_DSP_JCK"), + MTK_FUNCTION(6, "SSPM_JTAG_TCK"), + MTK_FUNCTION(7, "DFD_TCK_XI") + ), + + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "ADSP_JTAG_TMS"), + MTK_FUNCTION(3, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(4, "UDI_TMS"), + MTK_FUNCTION(5, "CONN_DSP_JMS"), + MTK_FUNCTION(6, "SSPM_JTAG_TMS"), + MTK_FUNCTION(7, "DFD_TMS") + ), + + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "ADSP_JTAG_TDI"), + MTK_FUNCTION(4, "UDI_TDI"), + MTK_FUNCTION(5, "CONN_DSP_JDI"), + MTK_FUNCTION(6, "SSPM_JTAG_TDI"), + MTK_FUNCTION(7, "DFD_TDI") + ), + + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "ADSP_JTAG_TDO"), + MTK_FUNCTION(4, "UDI_TDO"), + MTK_FUNCTION(5, "CONN_DSP_JDO"), + MTK_FUNCTION(6, "SSPM_JTAG_TDO"), + MTK_FUNCTION(7, "DFD_TDO") + ), + + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "ADSP_JTAG_TRSTN"), + MTK_FUNCTION(3, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(4, "UDI_NTRST"), + MTK_FUNCTION(5, "CONN_WIFI_TXD"), + MTK_FUNCTION(6, "SSPM_JTAG_TRSTN") + ), + + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(5, "CONN_DSP_JINTP") + ), + + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "IDDIG_P0"), + MTK_FUNCTION(4, "PGD_HV_HSC_PWR4"), + MTK_FUNCTION(5, "GDU_SUM_TROOP2_2") + ), + + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "USB_DRVVBUS_P0"), + MTK_FUNCTION(4, "PGD_HV_HSC_PWR5"), + MTK_FUNCTION(5, "GDU_TROOPS_DET0") + ), + + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "VBUS_VALID_P0"), + MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY"), + MTK_FUNCTION(5, "GDU_TROOPS_DET1") + ), + + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "IDDIG_P1"), + MTK_FUNCTION(2, "PWM0"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "PGD_DA_EFUSE_RDY_PRE"), + MTK_FUNCTION(5, "GDU_TROOPS_DET2") + ), + + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "USB_DRVVBUS_P1"), + MTK_FUNCTION(2, "PWM1"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PGD_DA_PWRGD_RESET") + ), + + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "VBUS_VALID_P1"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PGD_DA_PWRGD_ENB") + ), + + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "dbg_mon_a29") + ), + + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(7, "dbg_mon_a30") + ), + + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "LCM_RST") + ), + + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "DPI_PCLK"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "SSPM_JTAG_TCK"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR0") + ), + + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "DPI_VSYNC"), + MTK_FUNCTION(2, "KPCOL2"), + MTK_FUNCTION(3, "SSPM_JTAG_TMS"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR1") + ), + + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "DPI_HSYNC"), + MTK_FUNCTION(2, "KPROW2"), + MTK_FUNCTION(3, "SSPM_JTAG_TDI"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "TP_GPIO2_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR2") + ), + + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "DPI_DE"), + MTK_FUNCTION(3, "SSPM_JTAG_TDO"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "TP_GPIO3_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR3") + ), + + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "DPI_DATA0"), + MTK_FUNCTION(3, "SSPM_JTAG_TRSTN"), + MTK_FUNCTION(4, "CLKM0"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "TP_GPIO4_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR4") + ), + + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "DPI_DATA1"), + MTK_FUNCTION(2, "GPS_PPS"), + MTK_FUNCTION(3, "UCTS2"), + MTK_FUNCTION(4, "CLKM1"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "TP_GPIO5_AO"), + MTK_FUNCTION(7, "PGD_LV_LSC_PWR5") + ), + + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "DPI_DATA2"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "URTS2"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(6, "TP_GPIO6_AO"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR0") + ), + + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "DPI_DATA3"), + MTK_FUNCTION(2, "TP_UTXD1_AO"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "PWM0"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "TP_GPIO7_AO"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR1") + ), + + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "DPI_DATA4"), + MTK_FUNCTION(2, "TP_URXD1_AO"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(6, "GDU_SUM_TROOP0_0"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR2") + ), + + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "DPI_DATA5"), + MTK_FUNCTION(2, "TP_UCTS1_AO"), + MTK_FUNCTION(3, "UCTS0"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(6, "GDU_SUM_TROOP0_1"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR3") + ), + + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "DPI_DATA6"), + MTK_FUNCTION(2, "TP_URTS1_AO"), + MTK_FUNCTION(3, "URTS0"), + MTK_FUNCTION(4, "I2S0_DI"), + MTK_FUNCTION(5, "I2S2_DI"), + MTK_FUNCTION(6, "GDU_SUM_TROOP0_2"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR4") + ), + + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "DPI_DATA7"), + MTK_FUNCTION(2, "TP_UCTS2_AO"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "I2S3_BCK"), + MTK_FUNCTION(5, "I2S1_BCK"), + MTK_FUNCTION(6, "GDU_SUM_TROOP1_0"), + MTK_FUNCTION(7, "PGD_LV_HSC_PWR5") + ), + + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "DPI_DATA8"), + MTK_FUNCTION(2, "TP_URTS2_AO"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(4, "I2S3_MCK"), + MTK_FUNCTION(5, "I2S1_MCK"), + MTK_FUNCTION(6, "GDU_SUM_TROOP1_1"), + MTK_FUNCTION(7, "PGD_HV_HSC_PWR0") + ), + + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "DPI_DATA9"), + MTK_FUNCTION(2, "TP_URXD2_AO"), + MTK_FUNCTION(3, "URXD1"), + MTK_FUNCTION(4, "I2S3_LRCK"), + MTK_FUNCTION(5, "I2S1_LRCK"), + MTK_FUNCTION(6, "GDU_SUM_TROOP1_2"), + MTK_FUNCTION(7, "PGD_HV_HSC_PWR1") + ), + + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "DPI_DATA10"), + MTK_FUNCTION(2, "TP_UTXD2_AO"), + MTK_FUNCTION(3, "UTXD1"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "I2S1_DO"), + MTK_FUNCTION(6, "GDU_SUM_TROOP2_0"), + MTK_FUNCTION(7, "PGD_HV_HSC_PWR2") + ), + + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "DPI_DATA11"), + MTK_FUNCTION(6, "GDU_SUM_TROOP2_1"), + MTK_FUNCTION(7, "PGD_HV_HSC_PWR3") + ), + + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "PCM_CLK"), + MTK_FUNCTION(2, "I2S0_BCK"), + MTK_FUNCTION(3, "I2S2_BCK") + ), + + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "PCM_SYNC"), + MTK_FUNCTION(2, "I2S0_LRCK"), + MTK_FUNCTION(3, "I2S2_LRCK") + ), + + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "PCM_DI"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "I2S2_DI") + ), + + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "PCM_DO"), + MTK_FUNCTION(2, "I2S0_MCK"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "I2S1_DO") + ), + + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "JTMS_SEL1"), + MTK_FUNCTION(2, "UDI_TMS"), + MTK_FUNCTION(3, "DFD_TMS"), + MTK_FUNCTION(4, "SPM_JTAG_TMS"), + MTK_FUNCTION(5, "SCP_JTAG_TMS"), + MTK_FUNCTION(6, "ADSP_JTAG_TMS") + ), + + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "JTCK_SEL1"), + MTK_FUNCTION(2, "UDI_TCK"), + MTK_FUNCTION(3, "DFD_TCK_XI"), + MTK_FUNCTION(4, "SPM_JTAG_TCK"), + MTK_FUNCTION(5, "SCP_JTAG_TCK"), + MTK_FUNCTION(6, "ADSP_JTAG_TCK") + ), + + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "JTDI_SEL1"), + MTK_FUNCTION(2, "UDI_TDI"), + MTK_FUNCTION(3, "DFD_TDI"), + MTK_FUNCTION(4, "SPM_JTAG_TDI"), + MTK_FUNCTION(5, "SCP_JTAG_TDI"), + MTK_FUNCTION(6, "ADSP_JTAG_TDI") + ), + + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "JTDO_SEL1"), + MTK_FUNCTION(2, "UDI_TDO"), + MTK_FUNCTION(3, "DFD_TDO"), + MTK_FUNCTION(4, "SPM_JTAG_TDO"), + MTK_FUNCTION(5, "SCP_JTAG_TDO"), + MTK_FUNCTION(6, "ADSP_JTAG_TDO") + ), + + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, 123), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "JTRSTN_SEL1"), + MTK_FUNCTION(2, "UDI_NTRST"), + MTK_FUNCTION(4, "SPM_JTAG_TRSTN"), + MTK_FUNCTION(5, "SCP_JTAG_TRSTN"), + MTK_FUNCTION(6, "ADSP_JTAG_TRSTN") + ), + + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, 124), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "PWM0") + ), + + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "PWM1"), + MTK_FUNCTION(7, "dbg_mon_b0") + ), + + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "PWM2"), + MTK_FUNCTION(7, "dbg_mon_b1") + ), + + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1") + ), + + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1") + ), + + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b4") + ), + + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b5") + ), + + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, 131), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "SSPM_UTXD_AO"), + MTK_FUNCTION(3, "CONN_UART0_TXD"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b6") + ), + + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, 132), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "SSPM_URXD_AO"), + MTK_FUNCTION(3, "CONN_UART0_RXD"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b7") + ), + + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, 133), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b8") + ), + + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, 134), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "GPS_PPS"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b9") + ), + + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, 135), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(2, "TP_UTXD1_AO"), + MTK_FUNCTION(3, "UTXD1"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b10") + ), + + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, 136), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(2, "TP_URXD1_AO"), + MTK_FUNCTION(3, "URXD1"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b11") + ), + + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "SCL5"), + MTK_FUNCTION(2, "UTXD2"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1") + ), + + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "SDA5"), + MTK_FUNCTION(2, "URXD2"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1") + ), + + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(3, "TP_UTXD1_AO"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b12") + ), + + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(3, "TP_URXD1_AO"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b13") + ), + + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(2, "URTS0"), + MTK_FUNCTION(3, "TP_URTS1_AO"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(6, "UDI_TCK"), + MTK_FUNCTION(7, "dbg_mon_b14") + ), + + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(2, "UCTS0"), + MTK_FUNCTION(3, "TP_UCTS1_AO"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1") + ), + + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "SCL8"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b16") + ), + + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "SDA8"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b17") + ), + + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "SCL9"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(3, "GPS_PPS"), + MTK_FUNCTION(4, "SCP_SCL0"), + MTK_FUNCTION(5, "SCP_SCL1"), + MTK_FUNCTION(7, "dbg_mon_b18") + ), + + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "SDA9"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(4, "SCP_SDA0"), + MTK_FUNCTION(5, "SCP_SDA1"), + MTK_FUNCTION(7, "dbg_mon_b19") + ), + + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "LVTS_SDI"), + MTK_FUNCTION(3, "DPI_DATA12"), + MTK_FUNCTION(4, "TP_GPIO0_AO"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "DFD_TCK_XI"), + MTK_FUNCTION(7, "dbg_mon_b20") + ), + + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(2, "LVTS_SCF"), + MTK_FUNCTION(3, "DPI_DATA13"), + MTK_FUNCTION(4, "TP_GPIO1_AO"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "DFD_TMS"), + MTK_FUNCTION(7, "dbg_mon_b21") + ), + + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "DPI_DATA14"), + MTK_FUNCTION(4, "TP_GPIO2_AO"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "DFD_TDI"), + MTK_FUNCTION(7, "dbg_mon_b22") + ), + + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "DPI_DATA15"), + MTK_FUNCTION(4, "TP_GPIO3_AO"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(6, "DFD_TDO"), + MTK_FUNCTION(7, "dbg_mon_b23") + ), + + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "DPI_DATA16"), + MTK_FUNCTION(4, "TP_GPIO4_AO"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "UDI_TMS"), + MTK_FUNCTION(7, "dbg_mon_b24") + ), + + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "DPI_DATA17"), + MTK_FUNCTION(4, "TP_GPIO5_AO") + ), + + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(3, "DPI_DATA18"), + MTK_FUNCTION(4, "TP_GPIO6_AO"), + MTK_FUNCTION(6, "UDI_TDI"), + MTK_FUNCTION(7, "dbg_mon_b26") + ), + + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "PWM0"), + MTK_FUNCTION(2, "CMVREF2"), + MTK_FUNCTION(3, "DPI_DATA19"), + MTK_FUNCTION(4, "TP_GPIO7_AO"), + MTK_FUNCTION(6, "UDI_TDO"), + MTK_FUNCTION(7, "dbg_mon_b27") + ), + + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "CMVREF1"), + MTK_FUNCTION(3, "DPI_DATA20"), + MTK_FUNCTION(6, "UDI_NTRST"), + MTK_FUNCTION(7, "dbg_mon_b28") + ), + + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "CMVREF0"), + MTK_FUNCTION(3, "DPI_DATA21") + ), + + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "SRCLKENA1"), + MTK_FUNCTION(7, "dbg_mon_a31") + ), + + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "SCP_VREQ_VAO"), + MTK_FUNCTION(2, "DVFSRC_EXT_REQ") + ), + + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "WATCHDOG") + ), + + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "I2S1_MCK") + ), + + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(3, "I2S1_BCK") + ), + + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(2, "AUD_DAT_MISO0"), + MTK_FUNCTION(3, "I2S1_LRCK") + ), + + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(2, "AUD_DAT_MISO1"), + MTK_FUNCTION(3, "I2S1_DO") + ), + + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "AUD_CLK_MISO"), + MTK_FUNCTION(2, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "I2S2_MCK") + ), + + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "AUD_SYNC_MISO"), + MTK_FUNCTION(2, "AUD_SYNC_MOSI"), + MTK_FUNCTION(3, "I2S2_BCK") + ), + + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "VOW_DAT_MISO") + ), + + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "VOW_CLK_MISO") + ), + + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(2, "AUXIF_CLK"), + MTK_FUNCTION(3, "DFD_TCK_XI"), + MTK_FUNCTION(7, "dbg_mon_b3") + ), + + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(2, "AUXIF_ST"), + MTK_FUNCTION(3, "DFD_TMS"), + MTK_FUNCTION(7, "dbg_mon_b15") + ), + + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(0, 176), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(3, "DFD_TDI"), + MTK_FUNCTION(7, "dbg_mon_b2") + ), + + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(0, 177), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "CONN_BT_DATA"), + MTK_FUNCTION(3, "DFD_TDO") + ), + + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(7, "dbg_mon_b25") + ), + + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(3, "UDI_TCK"), + MTK_FUNCTION(7, "dbg_mon_b29") + ), + + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "CONN_WF_CTRL0"), + MTK_FUNCTION(3, "UDI_TDI") + ), + + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "CONN_WF_CTRL1"), + MTK_FUNCTION(3, "UDI_TDO") + ), + + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 182), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CONN_WF_CTRL2"), + MTK_FUNCTION(3, "UDI_NTRST") + ), + + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 183), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "SPMI_SCL") + ), + + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 184), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "SPMI_SDA") + ), + + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 197), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 198), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 199), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(0, 200), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(0, 201), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(0, 202), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(0, 203), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(0, 204), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(0, 205), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(0, 206), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(0, 207), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ), + + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 208), + DRV_FIXED, + MTK_FUNCTION(0, NULL) + ) +}; + +#endif /* __PINCTRL_MTK_MT8186_H */ diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index f9f9110f2107..74517e810958 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -48,6 +48,53 @@ static const char * const mtk_gpio_functions[] = { "func12", "func13", "func14", "func15", }; +/* + * This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV + * and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs. + * + * The custom value encodes three hardware bits as follows: + * + * | Bits | + * | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA) + * ------------------------------------------------ + * | x | x | 0 | disabled, use standard drive strength + * ------------------------------------- + * | 0 | 0 | 1 | 125 uA + * | 0 | 1 | 1 | 250 uA + * | 1 | 0 | 1 | 500 uA + * | 1 | 1 | 1 | 1000 uA + */ +static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 }; + +static int mtk_drv_adv_to_uA(int val) +{ + /* This should never happen. */ + if (WARN_ON_ONCE(val < 0 || val > 7)) + return -EINVAL; + + /* Bit 0 simply enables this hardware part */ + if (!(val & BIT(0))) + return -EINVAL; + + return mtk_drv_adv_uA[(val >> 1)]; +} + +static int mtk_drv_uA_to_adv(int val) +{ + switch (val) { + case 125: + return 0x1; + case 250: + return 0x3; + case 500: + return 0x5; + case 1000: + return 0x7; + } + + return -EINVAL; +} + static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int pin) @@ -79,41 +126,34 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); u32 param = pinconf_to_config_param(*config); - int pullup, err, reg, ret = 1; + int pullup, reg, err = -ENOTSUPP, ret = 1; const struct mtk_pin_desc *desc; - if (pin >= hw->soc->npins) { - err = -EINVAL; - goto out; - } + if (pin >= hw->soc->npins) + return -EINVAL; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; switch (param) { case PIN_CONFIG_BIAS_DISABLE: case PIN_CONFIG_BIAS_PULL_UP: case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_get_combo) { - err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); - if (err) - goto out; - if (param == PIN_CONFIG_BIAS_DISABLE) { - if (ret == MTK_PUPD_SET_R1R0_00) - ret = MTK_DISABLE; - } else if (param == PIN_CONFIG_BIAS_PULL_UP) { - /* When desire to get pull-up value, return - * error if current setting is pull-down - */ - if (!pullup) - err = -EINVAL; - } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) { - /* When desire to get pull-down value, return - * error if current setting is pull-up - */ - if (pullup) - err = -EINVAL; - } - } else { - err = -ENOTSUPP; + if (!hw->soc->bias_get_combo) + break; + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + break; + if (ret == MTK_PUPD_SET_R1R0_00) + ret = MTK_DISABLE; + if (param == PIN_CONFIG_BIAS_DISABLE) { + if (ret != MTK_DISABLE) + err = -EINVAL; + } else if (param == PIN_CONFIG_BIAS_PULL_UP) { + if (!pullup || ret == MTK_DISABLE) + err = -EINVAL; + } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) { + if (pullup || ret == MTK_DISABLE) + err = -EINVAL; } break; case PIN_CONFIG_SLEW_RATE: @@ -123,7 +163,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret); if (err) - goto out; + break; /* CONFIG Current direction return value * ------------- ----------------- ---------------------- * OUTPUT_ENABLE output 1 (= HW value) @@ -138,23 +178,48 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_INPUT_SCHMITT_ENABLE: err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret); if (err) - goto out; + break; /* return error when in output mode * because schmitt trigger only work in input mode */ if (ret) { err = -EINVAL; - goto out; + break; } err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret); - break; case PIN_CONFIG_DRIVE_STRENGTH: - if (hw->soc->drive_get) - err = hw->soc->drive_get(hw, desc, &ret); - else - err = -ENOTSUPP; + if (!hw->soc->drive_get) + break; + + if (hw->soc->adv_drive_get) { + err = hw->soc->adv_drive_get(hw, desc, &ret); + if (!err) { + err = mtk_drv_adv_to_uA(ret); + if (err > 0) { + /* PIN_CONFIG_DRIVE_STRENGTH_UA used */ + err = -EINVAL; + break; + } + } + } + + err = hw->soc->drive_get(hw, desc, &ret); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (!hw->soc->adv_drive_get) + break; + + err = hw->soc->adv_drive_get(hw, desc, &ret); + if (err) + break; + err = mtk_drv_adv_to_uA(ret); + if (err < 0) + break; + + ret = err; + err = 0; break; case MTK_PIN_CONFIG_TDSEL: case MTK_PIN_CONFIG_RDSEL: @@ -164,23 +229,18 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, break; case MTK_PIN_CONFIG_PU_ADV: case MTK_PIN_CONFIG_PD_ADV: - if (hw->soc->adv_pull_get) { - pullup = param == MTK_PIN_CONFIG_PU_ADV; - err = hw->soc->adv_pull_get(hw, desc, pullup, &ret); - } else - err = -ENOTSUPP; + if (!hw->soc->adv_pull_get) + break; + pullup = param == MTK_PIN_CONFIG_PU_ADV; + err = hw->soc->adv_pull_get(hw, desc, pullup, &ret); break; case MTK_PIN_CONFIG_DRV_ADV: - if (hw->soc->adv_drive_get) - err = hw->soc->adv_drive_get(hw, desc, &ret); - else - err = -ENOTSUPP; + if (!hw->soc->adv_drive_get) + break; + err = hw->soc->adv_drive_get(hw, desc, &ret); break; - default: - err = -ENOTSUPP; } -out: if (!err) *config = pinconf_to_config_packed(param, ret); @@ -188,38 +248,33 @@ out: } static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - enum pin_config_param param, - enum pin_config_param arg) + enum pin_config_param param, u32 arg) { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); const struct mtk_pin_desc *desc; - int err = 0; + int err = -ENOTSUPP; u32 reg; - if (pin >= hw->soc->npins) { - err = -EINVAL; - goto err; - } + if (pin >= hw->soc->npins) + return -EINVAL; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; switch ((u32)param) { case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_set_combo) - err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); - else - err = -ENOTSUPP; + if (!hw->soc->bias_set_combo) + break; + err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); break; case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_set_combo) - err = hw->soc->bias_set_combo(hw, desc, 1, arg); - else - err = -ENOTSUPP; + if (!hw->soc->bias_set_combo) + break; + err = hw->soc->bias_set_combo(hw, desc, 1, arg); break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_set_combo) - err = hw->soc->bias_set_combo(hw, desc, 0, arg); - else - err = -ENOTSUPP; + if (!hw->soc->bias_set_combo) + break; + err = hw->soc->bias_set_combo(hw, desc, 0, arg); break; case PIN_CONFIG_OUTPUT_ENABLE: err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, @@ -228,7 +283,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, * does not have SMT control */ if (err != -ENOTSUPP) - goto err; + break; err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_OUTPUT); @@ -237,7 +292,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, /* regard all non-zero value as enable */ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg); if (err) - goto err; + break; err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_INPUT); @@ -250,7 +305,7 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, arg); if (err) - goto err; + break; err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, MTK_OUTPUT); @@ -262,15 +317,23 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, */ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg); if (err) - goto err; + break; err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg); break; case PIN_CONFIG_DRIVE_STRENGTH: - if (hw->soc->drive_set) - err = hw->soc->drive_set(hw, desc, arg); - else - err = -ENOTSUPP; + if (!hw->soc->drive_set) + break; + err = hw->soc->drive_set(hw, desc, arg); + break; + case PIN_CONFIG_DRIVE_STRENGTH_UA: + if (!hw->soc->adv_drive_set) + break; + + err = mtk_drv_uA_to_adv(arg); + if (err < 0) + break; + err = hw->soc->adv_drive_set(hw, desc, err); break; case MTK_PIN_CONFIG_TDSEL: case MTK_PIN_CONFIG_RDSEL: @@ -280,26 +343,19 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, break; case MTK_PIN_CONFIG_PU_ADV: case MTK_PIN_CONFIG_PD_ADV: - if (hw->soc->adv_pull_set) { - bool pullup; - - pullup = param == MTK_PIN_CONFIG_PU_ADV; - err = hw->soc->adv_pull_set(hw, desc, pullup, - arg); - } else - err = -ENOTSUPP; + if (!hw->soc->adv_pull_set) + break; + err = hw->soc->adv_pull_set(hw, desc, + (param == MTK_PIN_CONFIG_PU_ADV), + arg); break; case MTK_PIN_CONFIG_DRV_ADV: - if (hw->soc->adv_drive_set) - err = hw->soc->adv_drive_set(hw, desc, arg); - else - err = -ENOTSUPP; + if (!hw->soc->adv_drive_set) + break; + err = hw->soc->adv_drive_set(hw, desc, arg); break; - default: - err = -ENOTSUPP; } -err: return err; } @@ -586,6 +642,9 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, if (gpio >= hw->soc->npins) return -EINVAL; + if (mtk_is_virt_gpio(hw, gpio)) + return -EINVAL; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; pinmux = mtk_pctrl_get_pinmux(hw, gpio); if (pinmux >= hw->soc->nfuncs) @@ -639,14 +698,10 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, pullen, pullup); - if (r1 != -1) { - len += scnprintf(buf + len, buf_len - len, " (%1d %1d)\n", - r1, r0); - } else if (rsel != -1) { - len += scnprintf(buf + len, buf_len - len, " (%1d)\n", rsel); - } else { - len += scnprintf(buf + len, buf_len - len, "\n"); - } + if (r1 != -1) + len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0); + else if (rsel != -1) + len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel); return len; } @@ -737,10 +792,10 @@ static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group, unsigned long *config) { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); + struct mtk_pinctrl_group *grp = &hw->groups[group]; - *config = hw->groups[group].config; - - return 0; + /* One pin per group only */ + return mtk_pinconf_get(pctldev, grp->pin, config); } static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, @@ -748,6 +803,8 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); struct mtk_pinctrl_group *grp = &hw->groups[group]; + bool drive_strength_uA_found = false; + bool adv_drve_strength_found = false; int i, ret; for (i = 0; i < num_configs; i++) { @@ -757,9 +814,21 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, if (ret < 0) return ret; - grp->config = configs[i]; + if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA) + drive_strength_uA_found = true; + if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV) + adv_drve_strength_found = true; } + /* + * Disable advanced drive strength mode if drive-strength-microamp + * is not set. However, mediatek,drive-strength-adv takes precedence + * as its value can explicitly request the mode be enabled or not. + */ + if (hw->soc->adv_drive_set && !drive_strength_uA_found && + !adv_drve_strength_found) + hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0); + return 0; } @@ -952,9 +1021,9 @@ static int mtk_pctrl_build_state(struct platform_device *pdev) return 0; } -int mtk_paris_pinctrl_probe(struct platform_device *pdev, - const struct mtk_pin_soc *soc) +int mtk_paris_pinctrl_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct pinctrl_pin_desc *pins; struct mtk_pinctrl *hw; int err, i; @@ -964,14 +1033,16 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, return -ENOMEM; platform_set_drvdata(pdev, hw); - hw->soc = soc; + + hw->soc = device_get_match_data(dev); + if (!hw->soc) + return -ENOENT; + hw->dev = &pdev->dev; - if (!hw->soc->nbase_names) { - dev_err(&pdev->dev, + if (!hw->soc->nbase_names) + return dev_err_probe(dev, -EINVAL, "SoC should be assigned at least one register base\n"); - return -EINVAL; - } hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names, sizeof(*hw->base), GFP_KERNEL); @@ -988,7 +1059,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, hw->nbase = hw->soc->nbase_names; if (of_find_property(hw->dev->of_node, - "mediatek,rsel_resistance_in_si_unit", NULL)) + "mediatek,rsel-resistance-in-si-unit", NULL)) hw->rsel_si_unit = true; else hw->rsel_si_unit = false; @@ -996,10 +1067,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, spin_lock_init(&hw->lock); err = mtk_pctrl_build_state(pdev); - if (err) { - dev_err(&pdev->dev, "build state failed: %d\n", err); - return -EINVAL; - } + if (err) + return dev_err_probe(dev, err, "build state failed\n"); /* Copy from internal struct mtk_pin_desc to register to the core */ pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins), @@ -1037,10 +1106,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, /* Build gpiochip should be after pinctrl_enable is done */ err = mtk_build_gpiochip(hw); - if (err) { - dev_err(&pdev->dev, "Failed to add gpio_chip\n"); - return err; - } + if (err) + return dev_err_probe(dev, err, "Failed to add gpio_chip\n"); platform_set_drvdata(pdev, hw); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.h b/drivers/pinctrl/mediatek/pinctrl-paris.h index afb7650fd25b..8762ac599329 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.h +++ b/drivers/pinctrl/mediatek/pinctrl-paris.h @@ -57,8 +57,7 @@ id##_funcs, \ } -int mtk_paris_pinctrl_probe(struct platform_device *pdev, - const struct mtk_pin_soc *soc); +int mtk_paris_pinctrl_probe(struct platform_device *pdev); ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, unsigned int gpio, char *buf, unsigned int bufLen); diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index b2855e341a75..d1955c65b4b6 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -61,4 +61,10 @@ config PINCTRL_MESON_A1 select PINCTRL_MESON_AXG_PMX default y +config PINCTRL_MESON_S4 + tristate "Meson s4 Soc pinctrl driver" + depends on ARM64 + select PINCTRL_MESON_AXG_PMX + default y + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 1a5bffe953f9..694f0596bfbc 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PINCTRL_MESON_AXG_PMX) += pinctrl-meson-axg-pmx.o obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o +obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index cd9656b13836..d182a575981e 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -283,6 +283,8 @@ static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 }; static const unsigned int pwm_e_pins[] = { GPIOX_16 }; /* pwm_f */ +static const unsigned int pwm_f_z_pins[] = { GPIOZ_12 }; +static const unsigned int pwm_f_a_pins[] = { GPIOA_11 }; static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; static const unsigned int pwm_f_h_pins[] = { GPIOH_5 }; @@ -618,6 +620,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = { GROUP(tdm_c_dout2_z, 4), GROUP(tdm_c_dout3_z, 4), GROUP(mclk1_z, 4), + GROUP(pwm_f_z, 5), /* bank GPIOX */ GROUP(sdio_d0, 1), @@ -768,6 +771,7 @@ static struct meson_pmx_group meson_g12a_periphs_groups[] = { GROUP(tdm_c_dout3_a, 2), GROUP(mclk0_a, 1), GROUP(mclk1_a, 2), + GROUP(pwm_f_a, 3), }; /* uart_ao_a */ @@ -1069,7 +1073,7 @@ static const char * const pwm_e_groups[] = { }; static const char * const pwm_f_groups[] = { - "pwm_f_x", "pwm_f_h", + "pwm_f_z", "pwm_f_a", "pwm_f_x", "pwm_f_h", }; static const char * const cec_ao_a_h_groups[] = { diff --git a/drivers/pinctrl/meson/pinctrl-meson-s4.c b/drivers/pinctrl/meson/pinctrl-meson-s4.c new file mode 100644 index 000000000000..3c7358f53302 --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-s4.c @@ -0,0 +1,1232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Pin controller and GPIO driver for Amlogic Meson S4 SoC. + * + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song + */ + +#include +#include "pinctrl-meson.h" +#include "pinctrl-meson-axg-pmx.h" + +static const struct pinctrl_pin_desc meson_s4_periphs_pins[] = { + MESON_PIN(GPIOE_0), + MESON_PIN(GPIOE_1), + + MESON_PIN(GPIOB_0), + MESON_PIN(GPIOB_1), + MESON_PIN(GPIOB_2), + MESON_PIN(GPIOB_3), + MESON_PIN(GPIOB_4), + MESON_PIN(GPIOB_5), + MESON_PIN(GPIOB_6), + MESON_PIN(GPIOB_7), + MESON_PIN(GPIOB_8), + MESON_PIN(GPIOB_9), + MESON_PIN(GPIOB_10), + MESON_PIN(GPIOB_11), + MESON_PIN(GPIOB_12), + MESON_PIN(GPIOB_13), + + MESON_PIN(GPIOC_0), + MESON_PIN(GPIOC_1), + MESON_PIN(GPIOC_2), + MESON_PIN(GPIOC_3), + MESON_PIN(GPIOC_4), + MESON_PIN(GPIOC_5), + MESON_PIN(GPIOC_6), + MESON_PIN(GPIOC_7), + + MESON_PIN(GPIOD_0), + MESON_PIN(GPIOD_1), + MESON_PIN(GPIOD_2), + MESON_PIN(GPIOD_3), + MESON_PIN(GPIOD_4), + MESON_PIN(GPIOD_5), + MESON_PIN(GPIOD_6), + MESON_PIN(GPIOD_7), + MESON_PIN(GPIOD_8), + MESON_PIN(GPIOD_9), + MESON_PIN(GPIOD_10), + MESON_PIN(GPIOD_11), + + MESON_PIN(GPIOH_0), + MESON_PIN(GPIOH_1), + MESON_PIN(GPIOH_2), + MESON_PIN(GPIOH_3), + MESON_PIN(GPIOH_4), + MESON_PIN(GPIOH_5), + MESON_PIN(GPIOH_6), + MESON_PIN(GPIOH_7), + MESON_PIN(GPIOH_8), + MESON_PIN(GPIOH_9), + MESON_PIN(GPIOH_10), + MESON_PIN(GPIOH_11), + + MESON_PIN(GPIOX_0), + MESON_PIN(GPIOX_1), + MESON_PIN(GPIOX_2), + MESON_PIN(GPIOX_3), + MESON_PIN(GPIOX_4), + MESON_PIN(GPIOX_5), + MESON_PIN(GPIOX_6), + MESON_PIN(GPIOX_7), + MESON_PIN(GPIOX_8), + MESON_PIN(GPIOX_9), + MESON_PIN(GPIOX_10), + MESON_PIN(GPIOX_11), + MESON_PIN(GPIOX_12), + MESON_PIN(GPIOX_13), + MESON_PIN(GPIOX_14), + MESON_PIN(GPIOX_15), + MESON_PIN(GPIOX_16), + MESON_PIN(GPIOX_17), + MESON_PIN(GPIOX_18), + MESON_PIN(GPIOX_19), + + MESON_PIN(GPIOZ_0), + MESON_PIN(GPIOZ_1), + MESON_PIN(GPIOZ_2), + MESON_PIN(GPIOZ_3), + MESON_PIN(GPIOZ_4), + MESON_PIN(GPIOZ_5), + MESON_PIN(GPIOZ_6), + MESON_PIN(GPIOZ_7), + MESON_PIN(GPIOZ_8), + MESON_PIN(GPIOZ_9), + MESON_PIN(GPIOZ_10), + MESON_PIN(GPIOZ_11), + MESON_PIN(GPIOZ_12), + + MESON_PIN(GPIO_TEST_N), +}; + +/* BANK E func1 */ +static const unsigned int i2c0_sda_pins[] = { GPIOE_0 }; +static const unsigned int i2c0_scl_pins[] = { GPIOE_1 }; + +/* BANK E func2 */ +static const unsigned int uart_b_tx_e_pins[] = { GPIOE_0 }; +static const unsigned int uart_b_rx_e_pins[] = { GPIOE_1 }; + +/* BANK E func3 */ +static const unsigned int pwm_h_pins[] = { GPIOE_0 }; +static const unsigned int pwm_j_pins[] = { GPIOE_1 }; + +/* BANK B func1 */ +static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; +static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; +static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; +static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; +static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; +static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; +static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; +static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; +static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; +static const unsigned int emmc_rst_pins[] = { GPIOB_9 }; +static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; +static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; + +/* Bank B func2 */ +static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 }; +static const unsigned int nand_ale_pins[] = { GPIOB_9 }; +static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 }; +static const unsigned int nand_cle_pins[] = { GPIOB_11 }; +static const unsigned int nand_ce0_pins[] = { GPIOB_12 }; + +/* Bank B func3 */ +static const unsigned int spif_hold_pins[] = { GPIOB_3 }; +static const unsigned int spif_mo_pins[] = { GPIOB_4 }; +static const unsigned int spif_mi_pins[] = { GPIOB_5 }; +static const unsigned int spif_clk_pins[] = { GPIOB_6 }; +static const unsigned int spif_wp_pins[] = { GPIOB_7 }; +static const unsigned int spif_cs_pins[] = { GPIOB_13 }; + +/* Bank C func1 */ +static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 }; +static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 }; +static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 }; +static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 }; +static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 }; +static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 }; +static const unsigned int sdcard_cd_pins[] = { GPIOC_6 }; + +/* Bank C func2 */ +static const unsigned int jtag_2_tdo_pins[] = { GPIOC_0 }; +static const unsigned int jtag_2_tdi_pins[] = { GPIOC_1 }; +static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 }; +static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 }; +static const unsigned int jtag_2_clk_pins[] = { GPIOC_4 }; +static const unsigned int jtag_2_tms_pins[] = { GPIOC_5 }; +static const unsigned int i2c1_sda_c_pins[] = { GPIOC_6 }; +static const unsigned int i2c1_scl_c_pins[] = { GPIOC_7 }; + +/* Bank C func3 */ +static const unsigned int pdm_din1_c_pins[] = { GPIOC_0 }; +static const unsigned int pdm_din0_c_pins[] = { GPIOC_1 }; +static const unsigned int i2c4_sda_c_pins[] = { GPIOC_2 }; +static const unsigned int i2c4_scl_c_pins[] = { GPIOC_3 }; +static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 }; +static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 }; +static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 }; + +/* Bank C func4 */ +static const unsigned int tdm_d2_c_pins[] = { GPIOC_0 }; +static const unsigned int tdm_d3_c_pins[] = { GPIOC_1 }; +static const unsigned int tdm_fs1_c_pins[] = { GPIOC_2 }; +static const unsigned int tdm_sclk1_c_pins[] = { GPIOC_3 }; +static const unsigned int mclk_1_c_pins[] = { GPIOC_4 }; +static const unsigned int tdm_d4_c_pins[] = { GPIOC_5 }; +static const unsigned int tdm_d5_c_pins[] = { GPIOC_6 }; + +/* Bank D func1 */ +static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 }; +static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 }; +static const unsigned int uart_b_cts_d_pins[] = { GPIOD_2 }; +static const unsigned int uart_b_rts_d_pins[] = { GPIOD_3 }; +static const unsigned int remote_out_pins[] = { GPIOD_4 }; +static const unsigned int remote_in_pins[] = { GPIOD_5 }; +static const unsigned int jtag_1_clk_pins[] = { GPIOD_6 }; +static const unsigned int jtag_1_tms_pins[] = { GPIOD_7 }; +static const unsigned int jtag_1_tdi_pins[] = { GPIOD_8 }; +static const unsigned int jtag_1_tdo_pins[] = { GPIOD_9 }; +static const unsigned int clk12_24_pins[] = { GPIOD_10 }; +static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 }; + +/* Bank D func2 */ +static const unsigned int i2c4_sda_d_pins[] = { GPIOD_2 }; +static const unsigned int i2c4_scl_d_pins[] = { GPIOD_3 }; +static const unsigned int mclk_1_d_pins[] = { GPIOD_4 }; +static const unsigned int tdm_sclk1_d_pins[] = { GPIOD_6 }; +static const unsigned int tdm_fs1_d_pins[] = { GPIOD_7 }; +static const unsigned int tdm_d4_d_pins[] = { GPIOD_8 }; +static const unsigned int tdm_d3_d_pins[] = { GPIOD_9 }; +static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 }; +static const unsigned int pwm_g_d_pins[] = { GPIOD_11 }; + +/* Bank D func3 */ +static const unsigned int uart_c_tx_pins[] = { GPIOD_2 }; +static const unsigned int uart_c_rx_pins[] = { GPIOD_3 }; +static const unsigned int pwm_b_d_pins[] = { GPIOD_4 }; +static const unsigned int pwm_a_d_pins[] = { GPIOD_6 }; +static const unsigned int pwm_c_d_pins[] = { GPIOD_7 }; +static const unsigned int pwm_d_d_pins[] = { GPIOD_8 }; +static const unsigned int pwm_i_d_pins[] = { GPIOD_9 }; + +/* Bank D func4 */ +static const unsigned int clk_32k_in_pins[] = { GPIOD_2 }; +static const unsigned int pwm_b_hiz_pins[] = { GPIOD_4 }; +static const unsigned int pwm_a_hiz_pins[] = { GPIOD_6 }; +static const unsigned int pwm_c_hiz_pins[] = { GPIOD_7 }; +static const unsigned int pdm_dclk_d_pins[] = { GPIOD_8 }; +static const unsigned int pdm_din0_d_pins[] = { GPIOD_9 }; +static const unsigned int pdm_din1_d_pins[] = { GPIOD_10 }; + +/* Bank D func5 */ +static const unsigned int mic_mute_en_pins[] = { GPIOD_2 }; +static const unsigned int mic_mute_key_pins[] = { GPIOD_3 }; +static const unsigned int i2c1_sda_d_pins[] = { GPIOD_6 }; +static const unsigned int i2c1_scl_d_pins[] = { GPIOD_7 }; +static const unsigned int i2c2_sda_d_pins[] = { GPIOD_10 }; +static const unsigned int i2c2_scl_d_pins[] = { GPIOD_11 }; + +/* Bank D func6 */ +static const unsigned int gen_clk_d_pins[] = { GPIOD_10 }; +static const unsigned int tsin_b_clk_c_pins[] = { GPIOD_6 }; +static const unsigned int tsin_b_sop_c_pins[] = { GPIOD_7 }; +static const unsigned int tsin_b_valid_c_pins[] = { GPIOD_8 }; +static const unsigned int tsin_b_d0_c_pins[] = { GPIOD_9 }; + +/* Bank H func1 */ +static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 }; +static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 }; +static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 }; +static const unsigned int ao_cec_a_pins[] = { GPIOH_3 }; +static const unsigned int spdif_out_h_pins[] = { GPIOH_4 }; +static const unsigned int spdif_in_pins[] = { GPIOH_5 }; +static const unsigned int i2c1_sda_h_pins[] = { GPIOH_6 }; +static const unsigned int i2c1_scl_h_pins[] = { GPIOH_7 }; +static const unsigned int i2c2_sda_h8_pins[] = { GPIOH_8 }; +static const unsigned int i2c2_scl_h9_pins[] = { GPIOH_9 }; +static const unsigned int eth_link_led_pins[] = { GPIOH_10 }; +static const unsigned int eth_act_led_pins[] = { GPIOH_11 }; + +/* Bank H func2 */ +static const unsigned int i2c2_sda_h0_pins[] = { GPIOH_0 }; +static const unsigned int i2c2_scl_h1_pins[] = { GPIOH_1 }; +static const unsigned int ao_cec_b_pins[] = { GPIOH_3 }; +static const unsigned int uart_d_tx_h_pins[] = { GPIOH_4 }; +static const unsigned int uart_d_rx_h_pins[] = { GPIOH_5 }; +static const unsigned int uart_d_cts_h_pins[] = { GPIOH_6 }; +static const unsigned int uart_d_rts_h_pins[] = { GPIOH_7 }; +static const unsigned int iso7816_clk_h_pins[] = { GPIOH_8 }; +static const unsigned int iso7816_data_h_pins[] = { GPIOH_9 }; +static const unsigned int uart_e_tx_h_pins[] = { GPIOH_10 }; +static const unsigned int uart_e_rx_h_pins[] = { GPIOH_11 }; + +/* Bank H func3 */ +static const unsigned int pwm_d_h_pins[] = { GPIOH_6 }; +static const unsigned int pwm_i_h_pins[] = { GPIOH_7 }; +static const unsigned int pdm_dclk_h_pins[] = { GPIOH_8 }; +static const unsigned int pdm_din0_h_pins[] = { GPIOH_9 }; +static const unsigned int pdm_din1_h_pins[] = { GPIOH_10 }; + +/* Bank H func4 */ +static const unsigned int mclk_1_h_pins[] = { GPIOH_4 }; +static const unsigned int tdm_sclk1_h_pins[] = { GPIOH_5 }; +static const unsigned int tdm_fs1_h_pins[] = { GPIOH_6 }; +static const unsigned int tdm_d2_h_pins[] = { GPIOH_7 }; +static const unsigned int tdm_d3_h_pins[] = { GPIOH_8 }; +static const unsigned int tdm_d4_h_pins[] = { GPIOH_9 }; + +/* Bank H func5 */ +static const unsigned int spi_a_miso_h_pins[] = { GPIOH_4 }; +static const unsigned int spi_a_mosi_h_pins[] = { GPIOH_5 }; +static const unsigned int spi_a_clk_h_pins[] = { GPIOH_6 }; +static const unsigned int spi_a_ss0_h_pins[] = { GPIOH_7 }; + +/* Bank H func6 */ +static const unsigned int gen_clk_h_pins[] = { GPIOH_11 }; +static const unsigned int tsin_b1_clk_pins[] = { GPIOH_4 }; +static const unsigned int tsin_b1_sop_pins[] = { GPIOH_5 }; +static const unsigned int tsin_b1_valid_pins[] = { GPIOH_6 }; +static const unsigned int tsin_b1_d0_pins[] = { GPIOH_7 }; + +/* Bank X func1 */ +static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; +static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; +static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; +static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; +static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; +static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; +static const unsigned int pwm_a_x_pins[] = { GPIOX_6 }; +static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; +static const unsigned int tdm_d1_pins[] = { GPIOX_8 }; +static const unsigned int tdm_d0_pins[] = { GPIOX_9 }; +static const unsigned int tdm_fs0_pins[] = { GPIOX_10 }; +static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 }; +static const unsigned int uart_a_tx_pins[] = { GPIOX_12 }; +static const unsigned int uart_a_rx_pins[] = { GPIOX_13 }; +static const unsigned int uart_a_cts_pins[] = { GPIOX_14 }; +static const unsigned int uart_a_rts_pins[] = { GPIOX_15 }; +static const unsigned int pwm_e_x_pins[] = { GPIOX_16 }; +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_17 }; +static const unsigned int i2c1_scl_x_pins[] = { GPIOX_18 }; +static const unsigned int pwm_b_x_pins[] = { GPIOX_19 }; + +/* Bank X func2 */ +static const unsigned int pdm_din0_x_pins[] = { GPIOX_8 }; +static const unsigned int pdm_din1_x_pins[] = { GPIOX_9 }; +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_11 }; + +/* Bank X func3 */ +static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 }; +static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 }; +static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 }; +static const unsigned int spi_a_clk_x_pins[] = { GPIOX_11 }; + +/* Bank X func4 */ +static const unsigned int pwm_c_x_pins[] = { GPIOX_8 }; +static const unsigned int i2c_slave_scl_pins[] = { GPIOX_10 }; +static const unsigned int i2c_slave_sda_pins[] = { GPIOX_11 }; + +/* Bank X func5 */ +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_10 }; +static const unsigned int i2c3_scl_x_pins[] = { GPIOX_11 }; + +/* Bank Z func1 */ +static const unsigned int tdm_fs2_pins[] = { GPIOZ_0 }; +static const unsigned int tdm_sclk2_pins[] = { GPIOZ_1 }; +static const unsigned int tdm_d4_z_pins[] = { GPIOZ_2 }; +static const unsigned int tdm_d5_z_pins[] = { GPIOZ_3 }; +static const unsigned int tdm_d6_pins[] = { GPIOZ_4 }; +static const unsigned int tdm_d7_pins[] = { GPIOZ_5 }; +static const unsigned int mclk_2_pins[] = { GPIOZ_6 }; +static const unsigned int spdif_out_z_pins[] = { GPIOZ_9 }; +static const unsigned int dtv_a_if_agc_z10_pins[] = { GPIOZ_10 }; +static const unsigned int uart_e_tx_z11_pins[] = { GPIOZ_11 }; +static const unsigned int uart_e_rx_z12_pins[] = { GPIOZ_12 }; + +/* Bank Z func2 */ +static const unsigned int tsin_a_clk_pins[] = { GPIOZ_0 }; +static const unsigned int tsin_a_sop_pins[] = { GPIOZ_1 }; +static const unsigned int tsin_a_valid_pins[] = { GPIOZ_2 }; +static const unsigned int tsin_a_din0_pins[] = { GPIOZ_3 }; +static const unsigned int dtv_a_if_agc_z6_pins[] = { GPIOZ_6 }; +static const unsigned int dtv_b_if_agc_pins[] = { GPIOZ_7 }; +static const unsigned int i2c3_sda_z_pins[] = { GPIOZ_8 }; +static const unsigned int i2c3_scl_z_pins[] = { GPIOZ_9 }; +static const unsigned int dtv_a_rf_agc_pins[] = { GPIOZ_10 }; +static const unsigned int dtv_b_rf_agc_pins[] = { GPIOZ_11 }; + +/* Bank Z func3 */ +static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_0 }; +static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_1 }; +static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_2 }; +static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_3 }; +static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_4 }; +static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_5 }; +static const unsigned int uart_e_tx_z8_pins[] = { GPIOZ_8 }; +static const unsigned int uart_e_rx_z9_pins[] = { GPIOZ_9 }; +static const unsigned int pdm_din1_z_pins[] = { GPIOZ_10 }; +static const unsigned int pdm_din0_z_pins[] = { GPIOZ_11 }; +static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_12 }; + +/* Bank Z func4 */ +static const unsigned int spi_a_miso_z_pins[] = { GPIOZ_0 }; +static const unsigned int spi_a_mosi_z_pins[] = { GPIOZ_1 }; +static const unsigned int spi_a_clk_z_pins[] = { GPIOZ_2 }; +static const unsigned int spi_a_ss0_z_pins[] = { GPIOZ_3 }; +static const unsigned int spi_a_ss1_z_pins[] = { GPIOZ_4 }; +static const unsigned int spi_a_ss2_z_pins[] = { GPIOZ_5 }; +static const unsigned int i2c4_scl_z_pins[] = { GPIOZ_11 }; +static const unsigned int i2c4_sda_z_pins[] = { GPIOZ_12 }; + +/* Bank Z func5 */ +static const unsigned int uart_d_tx_z_pins[] = { GPIOZ_0 }; +static const unsigned int uart_d_rx_z_pins[] = { GPIOZ_1 }; +static const unsigned int uart_d_cts_z_pins[] = { GPIOZ_2 }; +static const unsigned int uart_d_rts_z_pins[] = { GPIOZ_3 }; +static const unsigned int pwm_g_z_pins[] = { GPIOZ_4 }; +static const unsigned int pwm_f_z_pins[] = { GPIOZ_5 }; +static const unsigned int pwm_e_z_pins[] = { GPIOZ_6 }; +static const unsigned int tsin_b_clk_z_pins[] = { GPIOZ_7 }; +static const unsigned int tsin_b_sop_z_pins[] = { GPIOZ_10 }; +static const unsigned int tsin_b_valid_z_pins[] = { GPIOZ_11 }; +static const unsigned int tsin_b_d0_z_pins[] = { GPIOZ_12 }; + +/* Bank Z func6 */ +static const unsigned int s2_demod_gpio7_pins[] = { GPIOZ_0 }; +static const unsigned int s2_demod_gpio6_pins[] = { GPIOZ_1 }; +static const unsigned int s2_demod_gpio5_pins[] = { GPIOZ_2 }; +static const unsigned int s2_demod_gpio4_pins[] = { GPIOZ_3 }; +static const unsigned int s2_demod_gpio3_pins[] = { GPIOZ_4 }; +static const unsigned int s2_demod_gpio2_pins[] = { GPIOZ_5 }; +static const unsigned int diseqc_out_pins[] = { GPIOZ_7 }; +static const unsigned int s2_demod_gpio1_pins[] = { GPIOZ_8 }; +static const unsigned int s2_demod_gpio0_pins[] = { GPIOZ_12 }; + +/* Bank Z func7 */ +static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 }; +static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 }; + +static struct meson_pmx_group meson_s4_periphs_groups[] = { + GPIO_GROUP(GPIOE_0), + GPIO_GROUP(GPIOE_1), + + GPIO_GROUP(GPIOB_0), + GPIO_GROUP(GPIOB_1), + GPIO_GROUP(GPIOB_2), + GPIO_GROUP(GPIOB_3), + GPIO_GROUP(GPIOB_4), + GPIO_GROUP(GPIOB_5), + GPIO_GROUP(GPIOB_6), + GPIO_GROUP(GPIOB_7), + GPIO_GROUP(GPIOB_8), + GPIO_GROUP(GPIOB_9), + GPIO_GROUP(GPIOB_10), + GPIO_GROUP(GPIOB_11), + GPIO_GROUP(GPIOB_12), + GPIO_GROUP(GPIOB_13), + + GPIO_GROUP(GPIOC_0), + GPIO_GROUP(GPIOC_1), + GPIO_GROUP(GPIOC_2), + GPIO_GROUP(GPIOC_3), + GPIO_GROUP(GPIOC_4), + GPIO_GROUP(GPIOC_5), + GPIO_GROUP(GPIOC_6), + GPIO_GROUP(GPIOC_7), + + GPIO_GROUP(GPIOD_0), + GPIO_GROUP(GPIOD_1), + GPIO_GROUP(GPIOD_2), + GPIO_GROUP(GPIOD_3), + GPIO_GROUP(GPIOD_4), + GPIO_GROUP(GPIOD_5), + GPIO_GROUP(GPIOD_6), + GPIO_GROUP(GPIOD_7), + GPIO_GROUP(GPIOD_8), + GPIO_GROUP(GPIOD_9), + GPIO_GROUP(GPIOD_10), + GPIO_GROUP(GPIOD_11), + + GPIO_GROUP(GPIOH_0), + GPIO_GROUP(GPIOH_1), + GPIO_GROUP(GPIOH_2), + GPIO_GROUP(GPIOH_3), + GPIO_GROUP(GPIOH_4), + GPIO_GROUP(GPIOH_5), + GPIO_GROUP(GPIOH_6), + GPIO_GROUP(GPIOH_7), + GPIO_GROUP(GPIOH_8), + GPIO_GROUP(GPIOH_9), + GPIO_GROUP(GPIOH_10), + GPIO_GROUP(GPIOH_11), + + GPIO_GROUP(GPIOX_0), + GPIO_GROUP(GPIOX_1), + GPIO_GROUP(GPIOX_2), + GPIO_GROUP(GPIOX_3), + GPIO_GROUP(GPIOX_4), + GPIO_GROUP(GPIOX_5), + GPIO_GROUP(GPIOX_6), + GPIO_GROUP(GPIOX_7), + GPIO_GROUP(GPIOX_8), + GPIO_GROUP(GPIOX_9), + GPIO_GROUP(GPIOX_10), + GPIO_GROUP(GPIOX_11), + GPIO_GROUP(GPIOX_12), + GPIO_GROUP(GPIOX_13), + GPIO_GROUP(GPIOX_14), + GPIO_GROUP(GPIOX_15), + GPIO_GROUP(GPIOX_16), + GPIO_GROUP(GPIOX_17), + GPIO_GROUP(GPIOX_18), + GPIO_GROUP(GPIOX_19), + + GPIO_GROUP(GPIOZ_0), + GPIO_GROUP(GPIOZ_1), + GPIO_GROUP(GPIOZ_2), + GPIO_GROUP(GPIOZ_3), + GPIO_GROUP(GPIOZ_4), + GPIO_GROUP(GPIOZ_5), + GPIO_GROUP(GPIOZ_6), + GPIO_GROUP(GPIOZ_7), + GPIO_GROUP(GPIOZ_8), + GPIO_GROUP(GPIOZ_9), + GPIO_GROUP(GPIOZ_10), + GPIO_GROUP(GPIOZ_11), + GPIO_GROUP(GPIOZ_12), + + GPIO_GROUP(GPIO_TEST_N), + + /* BANK E func1 */ + GROUP(i2c0_sda, 1), + GROUP(i2c0_scl, 1), + + /* BANK E func2 */ + GROUP(uart_b_tx_e, 2), + GROUP(uart_b_rx_e, 2), + + /* BANK E func3 */ + GROUP(pwm_h, 3), + GROUP(pwm_j, 3), + + /* BANK B func1 */ + GROUP(emmc_nand_d0, 1), + GROUP(emmc_nand_d1, 1), + GROUP(emmc_nand_d2, 1), + GROUP(emmc_nand_d3, 1), + GROUP(emmc_nand_d4, 1), + GROUP(emmc_nand_d5, 1), + GROUP(emmc_nand_d6, 1), + GROUP(emmc_nand_d7, 1), + GROUP(emmc_clk, 1), + GROUP(emmc_rst, 1), + GROUP(emmc_cmd, 1), + GROUP(emmc_nand_ds, 1), + + /* Bank B func2 */ + GROUP(nand_wen_clk, 2), + GROUP(nand_ale, 2), + GROUP(nand_ren_wr, 2), + GROUP(nand_cle, 2), + GROUP(nand_ce0, 2), + + /* Bank B func3 */ + GROUP(spif_hold, 3), + GROUP(spif_mo, 3), + GROUP(spif_mi, 3), + GROUP(spif_clk, 3), + GROUP(spif_wp, 3), + GROUP(spif_cs, 3), + + /* Bank C func1 */ + GROUP(sdcard_d0_c, 1), + GROUP(sdcard_d1_c, 1), + GROUP(sdcard_d2_c, 1), + GROUP(sdcard_d3_c, 1), + GROUP(sdcard_clk_c, 1), + GROUP(sdcard_cmd_c, 1), + GROUP(sdcard_cd, 1), + + /* Bank C func2 */ + GROUP(jtag_2_tdo, 2), + GROUP(jtag_2_tdi, 2), + GROUP(uart_b_rx_c, 2), + GROUP(uart_b_tx_c, 2), + GROUP(jtag_2_clk, 2), + GROUP(jtag_2_tms, 2), + GROUP(i2c1_sda_c, 2), + GROUP(i2c1_scl_c, 2), + + /* Bank C func3 */ + GROUP(pdm_din1_c, 3), + GROUP(pdm_din0_c, 3), + GROUP(i2c4_sda_c, 3), + GROUP(i2c4_scl_c, 3), + GROUP(pdm_dclk_c, 3), + GROUP(iso7816_clk_c, 3), + GROUP(iso7816_data_c, 3), + + /* Bank C func4 */ + GROUP(tdm_d2_c, 4), + GROUP(tdm_d3_c, 4), + GROUP(tdm_fs1_c, 4), + GROUP(mclk_1_c, 4), + GROUP(tdm_d4_c, 4), + GROUP(tdm_d5_c, 4), + + /* Bank D func1 */ + GROUP(uart_b_tx_d, 1), + GROUP(uart_b_rx_d, 1), + GROUP(uart_b_cts_d, 1), + GROUP(uart_b_rts_d, 1), + GROUP(remote_out, 1), + GROUP(remote_in, 1), + GROUP(jtag_1_clk, 1), + GROUP(jtag_1_tms, 1), + GROUP(jtag_1_tdi, 1), + GROUP(jtag_1_tdo, 1), + GROUP(clk12_24, 1), + GROUP(pwm_g_hiz, 1), + + /* Bank D func2 */ + GROUP(i2c4_sda_d, 2), + GROUP(i2c4_scl_d, 2), + GROUP(mclk_1_d, 2), + GROUP(tdm_sclk1_d, 2), + GROUP(tdm_fs1_d, 2), + GROUP(tdm_d4_d, 2), + GROUP(tdm_d3_d, 2), + GROUP(tdm_d2_d, 2), + GROUP(pwm_g_d, 2), + + /* Bank D func3 */ + GROUP(uart_c_tx, 3), + GROUP(uart_c_rx, 3), + GROUP(pwm_b_d, 3), + GROUP(pwm_a_d, 3), + GROUP(pwm_c_d, 3), + GROUP(pwm_d_d, 3), + GROUP(pwm_i_d, 3), + + /* Bank D func4 */ + GROUP(clk_32k_in, 4), + GROUP(pwm_b_hiz, 4), + GROUP(pwm_a_hiz, 4), + GROUP(pwm_c_hiz, 4), + GROUP(pdm_dclk_d, 4), + GROUP(pdm_din0_d, 4), + GROUP(pdm_din1_d, 4), + + /* Bank D func5 */ + GROUP(mic_mute_en, 5), + GROUP(mic_mute_key, 5), + GROUP(i2c1_sda_d, 5), + GROUP(i2c1_scl_d, 5), + GROUP(i2c2_sda_d, 5), + GROUP(i2c2_scl_d, 5), + + /* Bank D func6 */ + GROUP(gen_clk_d, 6), + GROUP(tsin_b_clk_c, 6), + GROUP(tsin_b_sop_c, 6), + GROUP(tsin_b_valid_c, 6), + GROUP(tsin_b_d0_c, 6), + + /* Bank H func1 */ + GROUP(hdmitx_sda, 1), + GROUP(hdmitx_sck, 1), + GROUP(hdmitx_hpd_in, 1), + GROUP(ao_cec_a, 1), + GROUP(spdif_out_h, 1), + GROUP(spdif_in, 1), + GROUP(i2c1_sda_h, 1), + GROUP(i2c1_scl_h, 1), + GROUP(i2c2_sda_h8, 1), + GROUP(i2c2_scl_h9, 1), + GROUP(eth_link_led, 1), + GROUP(eth_act_led, 1), + + /* Bank H func2 */ + GROUP(i2c2_sda_h0, 2), + GROUP(i2c2_scl_h1, 2), + GROUP(ao_cec_b, 2), + GROUP(uart_d_tx_h, 2), + GROUP(uart_d_rx_h, 2), + GROUP(uart_d_cts_h, 2), + GROUP(uart_d_rts_h, 2), + GROUP(iso7816_clk_h, 2), + GROUP(iso7816_data_h, 2), + GROUP(uart_e_tx_h, 2), + GROUP(uart_e_rx_h, 2), + + /* Bank H func3 */ + GROUP(pwm_d_h, 3), + GROUP(pwm_i_h, 3), + GROUP(pdm_dclk_h, 3), + GROUP(pdm_din0_h, 3), + GROUP(pdm_din1_h, 3), + + /* Bank H func4 */ + GROUP(mclk_1_h, 4), + GROUP(tdm_sclk1_h, 4), + GROUP(tdm_fs1_h, 4), + GROUP(tdm_d2_h, 4), + GROUP(tdm_d3_h, 4), + GROUP(tdm_d4_h, 4), + + /* Bank H func5 */ + GROUP(spi_a_miso_h, 5), + GROUP(spi_a_mosi_h, 5), + GROUP(spi_a_clk_h, 5), + GROUP(spi_a_ss0_h, 5), + + /* Bank H func6 */ + GROUP(gen_clk_h, 6), + GROUP(tsin_b1_clk, 6), + GROUP(tsin_b1_sop, 6), + GROUP(tsin_b1_valid, 6), + GROUP(tsin_b1_d0, 6), + + /* Bank X func1 */ + GROUP(sdio_d0, 1), + GROUP(sdio_d1, 1), + GROUP(sdio_d2, 1), + GROUP(sdio_d3, 1), + GROUP(sdio_clk, 1), + GROUP(sdio_cmd, 1), + GROUP(pwm_a_x, 1), + GROUP(pwm_f_x, 1), + GROUP(tdm_d1, 1), + GROUP(tdm_d0, 1), + GROUP(tdm_fs0, 1), + GROUP(tdm_sclk0, 1), + GROUP(uart_a_tx, 1), + GROUP(uart_a_rx, 1), + GROUP(uart_a_cts, 1), + GROUP(uart_a_rts, 1), + GROUP(pwm_e_x, 1), + GROUP(i2c1_sda_x, 1), + GROUP(i2c1_scl_x, 1), + GROUP(pwm_b_x, 1), + + /* Bank X func2 */ + GROUP(pdm_din0_x, 2), + GROUP(pdm_din1_x, 2), + GROUP(pdm_dclk_x, 2), + + /* Bank X func3 */ + GROUP(spi_a_mosi_x, 3), + GROUP(spi_a_miso_x, 3), + GROUP(spi_a_ss0_x, 3), + GROUP(spi_a_clk_x, 3), + + /* Bank X func4 */ + GROUP(pwm_c_x, 4), + GROUP(i2c_slave_scl, 4), + GROUP(i2c_slave_sda, 4), + + /* Bank X func5 */ + GROUP(i2c3_sda_x, 5), + GROUP(i2c3_scl_x, 5), + + /* Bank Z func1 */ + GROUP(tdm_fs2, 1), + GROUP(tdm_sclk2, 1), + GROUP(tdm_d4_z, 1), + GROUP(tdm_d5_z, 1), + GROUP(tdm_d6, 1), + GROUP(tdm_d7, 1), + GROUP(mclk_2, 1), + GROUP(spdif_out_z, 1), + GROUP(dtv_a_if_agc_z10, 1), + GROUP(uart_e_tx_z11, 1), + GROUP(uart_e_rx_z12, 1), + + /* Bank Z func2 */ + GROUP(tsin_a_clk, 2), + GROUP(tsin_a_sop, 2), + GROUP(tsin_a_valid, 2), + GROUP(tsin_a_din0, 2), + GROUP(dtv_a_if_agc_z6, 2), + GROUP(dtv_b_if_agc, 2), + GROUP(i2c3_sda_z, 2), + GROUP(i2c3_scl_z, 2), + GROUP(dtv_a_rf_agc, 2), + GROUP(dtv_b_rf_agc, 2), + + /* Bank Z func3 */ + GROUP(sdcard_d0_z, 3), + GROUP(sdcard_d1_z, 3), + GROUP(sdcard_d2_z, 3), + GROUP(sdcard_d3_z, 3), + GROUP(sdcard_clk_z, 3), + GROUP(sdcard_cmd_z, 3), + GROUP(uart_e_tx_z8, 3), + GROUP(uart_e_rx_z9, 3), + GROUP(pdm_din1_z, 3), + GROUP(pdm_din0_z, 3), + GROUP(pdm_dclk_z, 3), + + /* Bank Z func4 */ + GROUP(spi_a_miso_z, 4), + GROUP(spi_a_mosi_z, 4), + GROUP(spi_a_clk_z, 4), + GROUP(spi_a_ss0_z, 4), + GROUP(spi_a_ss1_z, 4), + GROUP(spi_a_ss2_z, 4), + GROUP(i2c4_scl_z, 4), + GROUP(i2c4_sda_z, 4), + + /* Bank Z func5 */ + GROUP(uart_d_tx_z, 5), + GROUP(uart_d_rx_z, 5), + GROUP(uart_d_cts_z, 5), + GROUP(uart_d_rts_z, 5), + GROUP(pwm_g_z, 5), + GROUP(pwm_f_z, 5), + GROUP(pwm_e_z, 5), + GROUP(tsin_b_clk_z, 5), + GROUP(tsin_b_sop_z, 5), + GROUP(tsin_b_valid_z, 5), + GROUP(tsin_b_d0_z, 5), + + /* Bank Z func6 */ + GROUP(s2_demod_gpio7, 6), + GROUP(s2_demod_gpio6, 6), + GROUP(s2_demod_gpio5, 6), + GROUP(s2_demod_gpio4, 6), + GROUP(s2_demod_gpio3, 6), + GROUP(s2_demod_gpio2, 6), + GROUP(diseqc_out, 6), + GROUP(s2_demod_gpio1, 6), + GROUP(s2_demod_gpio0, 6), + + /* Bank Z func7 */ + GROUP(gen_clk_z9, 7), + GROUP(gen_clk_z12, 7), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOE_0", "GPIOE_1", + + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5", + "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", "GPIOB_11", + "GPIOB_12", "GPIOB_13", + + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5", + "GPIOC_6", "GPIOC_7", + + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5", + "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11", + + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5", + "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", "GPIOH_10", "GPIOH_11", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5", + "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", + "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17", + "GPIOX_18", "GPIOX_19", + + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5", + "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10", + "GPIOZ_11", "GPIOZ_12", + + "GPIO_TEST_N", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sda", "i2c0_scl", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sda_c", "i2c1_scl_c", + "i2c1_sda_d", "i2c1_scl_d", + "i2c1_sda_h", "i2c1_scl_h", + "i2c1_sda_x", "i2c1_scl_x", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sda_d", "i2c2_scl_d", + "i2c2_sda_h8", "i2c2_scl_h9", + "i2c2_sda_h0", "i2c2_scl_h1l," +}; + +static const char * const i2c3_groups[] = { + "i2c3_sda_x", "i2c3_scl_x", + "i2c3_sda_z", "i2c3_scl_z", +}; + +static const char * const i2c4_groups[] = { + "i2c4_sda_c", "i2c4_scl_c", + "i2c4_sda_d", "i2c4_scl_d", + "i2c4_scl_z", "i2c4_sda_z", +}; + +static const char * const uart_a_groups[] = { + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", +}; + +static const char * const uart_b_groups[] = { + "uart_b_tx_e", "uart_b_rx_e", "uart_b_rx_c", "uart_b_tx_c", + "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts_d", "uart_b_rts_d", +}; + +static const char * const uart_c_groups[] = { + "uart_c_tx", "uart_c_rx", +}; + +static const char * const uart_d_groups[] = { + "uart_d_tx_h", "uart_d_rx_h", "uart_d_cts_h", "uart_d_rts_h", + "uart_d_tx_z", "uart_d_rx_z", "uart_d_cts_z", "uart_d_rts_z", +}; + +static const char * const uart_e_groups[] = { + "uart_e_tx_h", "uart_e_rx_h", "uart_e_tx_z11", "uart_e_rx_z12", + "uart_e_tx_z8", "uart_e_rx_z9", +}; + +static const char * const emmc_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds", +}; + +static const char * const nand_groups[] = { + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", + "nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", "nand_ce0", +}; + +static const char * const spif_groups[] = { + "spif_hold", "spif_mo", "spif_mi", "spif_clk", "spif_wp", + "spif_cs", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c", + "sdcard_clk_c", "sdcard_cmd_c", "sdcard_cd", + "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z", + "sdcard_clk_z", "sdcard_cmd_z", +}; + +static const char * const jtag_1_groups[] = { + "jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo", +}; + +static const char * const jtag_2_groups[] = { + "jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms", +}; + +static const char * const pdm_groups[] = { + "pdm_din1_c", "pdm_din0_c", "pdm_dclk_c", + "pdm_dclk_d", "pdm_din0_d", "pdm_din1_d", + "pdm_dclk_h", "pdm_din0_h", "pdm_din1_h", + "pdm_din0_x", "pdm_din1_x", "pdm_dclk_x", + "pdm_din1_z", "pdm_din0_z", "pdm_dclk_z", +}; + +static const char * const iso7816_groups[] = { + "iso7816_clk_c", "iso7816_data_c", + "iso7816_clk_h", "iso7816_data_h", +}; + +static const char * const tdm_groups[] = { + "tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c", + "tdm_fs1_d", "tdm_d4_d", "tdm_d3_d", "tdm_d2_d", "tdm_sclk1_d", + "tdm_sclk1_h", "tdm_fs1_h", "tdm_d2_h", "tdm_d3_h", "tdm_d4_h", + "tdm_d1", "tdm_d0", "tdm_fs0", "tdm_sclk0", "tdm_fs2", "tdm_sclk2", + "tdm_d4_z", "tdm_d5_z", "tdm_d6", "tdm_d7", +}; + +static const char * const mclk_1_groups[] = { + "mclk_1_c", "mclk_1_d", "mclk_1_h", "mclk_2", +}; + +static const char * const mclk_2_groups[] = { + "mclk_2", +}; + +static const char * const remote_out_groups[] = { + "remote_out", +}; + +static const char * const remote_in_groups[] = { + "remote_in", +}; + +static const char * const clk12_24_groups[] = { + "clk12_24", +}; + +static const char * const clk_32k_in_groups[] = { + "clk_32k_in", +}; + +static const char * const pwm_a_hiz_groups[] = { + "pwm_a_hiz", +}; + +static const char * const pwm_b_hiz_groups[] = { + "pwm_b_hiz", +}; + +static const char * const pwm_c_hiz_groups[] = { + "pwm_c_hiz", +}; + +static const char * const pwm_g_hiz_groups[] = { + "pwm_g_hiz", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a_d", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_d", "pwm_b_x", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_d", "pwm_c_x", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d_d", "pwm_d_h", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e_x", "pwm_e_z", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_x", "pwm_f_z", +}; + +static const char * const pwm_g_groups[] = { + "pwm_g_d", "pwm_g_z", +}; + +static const char * const pwm_h_groups[] = { + "pwm_h", +}; + +static const char * const pwm_i_groups[] = { + "pwm_i_d", "pwm_i_h" +}; + +static const char * const pwm_j_groups[] = { + "pwm_j", +}; + +static const char * const mic_mute_groups[] = { + "mic_mute_en", "mic_mute_key", +}; + +static const char * const hdmitx_groups[] = { + "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in", +}; + +static const char * const ao_cec_a_groups[] = { + "ao_cec_a", +}; + +static const char * const ao_cec_b_groups[] = { + "ao_cec_b", +}; + +static const char * const spdif_out_groups[] = { + "spdif_out_h", "spdif_out_z", +}; + +static const char * const spdif_in_groups[] = { + "spdif_in", +}; + +static const char * const eth_groups[] = { + "eth_link_led", "eth_act_led", +}; + +static const char * const spi_a_groups[] = { + "spi_a_miso_h", "spi_a_mosi_h", "spi_a_clk_h", "spi_a_ss0_h", + + "spi_a_mosi_x", "spi_a_miso_x", "spi_a_ss0_x", "spi_a_clk_x", + + "spi_a_miso_z", "spi_a_mosi_z", "spi_a_clk_z", "spi_a_ss0_z", + "spi_a_ss1_z", "spi_a_ss2_z", +}; + +static const char * const gen_clk_groups[] = { + "gen_clk_h", "gen_clk_z9", "gen_clk_z12", +}; + +static const char * const sdio_groups[] = { + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd", +}; + +static const char * const i2c_slave_groups[] = { + "i2c_slave_scl", "i2c_slave_sda", +}; + +static const char * const dtv_groups[] = { + "dtv_a_if_agc_z10", "dtv_a_if_agc_z6", "dtv_b_if_agc", + "dtv_a_rf_agc", "dtv_b_rf_agc", +}; + +static const char * const tsin_a_groups[] = { + "tsin_a_clk", "tsin_a_sop", "tsin_a_valid", "tsin_a_din0", +}; + +static const char * const tsin_b_groups[] = { + "tsin_b_clk_c", "tsin_b_sop_c", "tsin_b_valid_c", "tsin_b_d0_c", + "tsin_b_clk_z", "tsin_b_sop_z", "tsin_b_valid_z", "tsin_b_d0_z", +}; + +static const char * const tsin_b1_groups[] = { + "tsin_b1_clk", "tsin_b1_sop", "tsin_b1_valid", "tsin_b1_d0", +}; + +static const char * const diseqc_out_groups[] = { + "diseqc_out", +}; + +static const char * const s2_demod_groups[] = { + "s2_demod_gpio7", "s2_demod_gpio6", "s2_demod_gpio5", "s2_demod_gpio4", + "s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0", +}; + +static struct meson_pmx_func meson_s4_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(i2c4), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(uart_d), + FUNCTION(uart_e), + FUNCTION(emmc), + FUNCTION(nand), + FUNCTION(spif), + FUNCTION(sdcard), + FUNCTION(jtag_1), + FUNCTION(jtag_2), + FUNCTION(pdm), + FUNCTION(iso7816), + FUNCTION(tdm), + FUNCTION(mclk_1), + FUNCTION(mclk_2), + FUNCTION(remote_out), + FUNCTION(remote_in), + FUNCTION(clk12_24), + FUNCTION(clk_32k_in), + FUNCTION(pwm_a_hiz), + FUNCTION(pwm_b_hiz), + FUNCTION(pwm_c_hiz), + FUNCTION(pwm_g_hiz), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(pwm_g), + FUNCTION(pwm_h), + FUNCTION(pwm_i), + FUNCTION(pwm_j), + FUNCTION(mic_mute), + FUNCTION(hdmitx), + FUNCTION(ao_cec_a), + FUNCTION(ao_cec_b), + FUNCTION(spdif_out), + FUNCTION(spdif_in), + FUNCTION(eth), + FUNCTION(spi_a), + FUNCTION(gen_clk), + FUNCTION(sdio), + FUNCTION(i2c_slave), + FUNCTION(dtv), + FUNCTION(tsin_a), + FUNCTION(tsin_b), + FUNCTION(tsin_b1), + FUNCTION(diseqc_out), + FUNCTION(s2_demod), +}; + +static struct meson_bank meson_s4_periphs_banks[] = { + /* name first last irq pullen pull dir out in */ + BANK_DS("B", GPIOB_0, GPIOB_13, 0, 13, + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0), + BANK_DS("C", GPIOC_0, GPIOC_7, 14, 21, + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0), + BANK_DS("E", GPIOE_0, GPIOE_1, 22, 23, + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0), + BANK_DS("D", GPIOD_0, GPIOD_11, 24, 35, + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0), + BANK_DS("H", GPIOH_0, GPIOH_11, 36, 47, + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0), + BANK_DS("X", GPIOX_0, GPIOX_19, 48, 67, + 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0), + BANK_DS("Z", GPIOZ_0, GPIOZ_12, 68, 80, + 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0), + BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, -1, -1, + 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0), +}; + +static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = { + /*name first lask reg offset*/ + BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0), + BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0), + BANK_PMX("E", GPIOE_0, GPIOE_1, 0x12, 0), + BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0), + BANK_PMX("H", GPIOH_0, GPIOH_11, 0xb, 0), + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0), + BANK_PMX("Z", GPIOZ_0, GPIOZ_12, 0x6, 0), + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0) +}; + +static struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = { + .pmx_banks = meson_s4_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks), +}; + +static struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = { + .name = "periphs-banks", + .pins = meson_s4_periphs_pins, + .groups = meson_s4_periphs_groups, + .funcs = meson_s4_periphs_functions, + .banks = meson_s4_periphs_banks, + .num_pins = ARRAY_SIZE(meson_s4_periphs_pins), + .num_groups = ARRAY_SIZE(meson_s4_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_s4_periphs_functions), + .num_banks = ARRAY_SIZE(meson_s4_periphs_banks), + .pmx_ops = &meson_axg_pmx_ops, + .pmx_data = &meson_s4_periphs_pmx_banks_data, + .parse_dt = &meson_a1_parse_dt_extra, +}; + +static const struct of_device_id meson_s4_pinctrl_dt_match[] = { + { + .compatible = "amlogic,meson-s4-periphs-pinctrl", + .data = &meson_s4_periphs_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, meson_s4_pinctrl_dt_match); + +static struct platform_driver meson_s4_pinctrl_driver = { + .probe = meson_pinctrl_probe, + .driver = { + .name = "meson-s4-pinctrl", + .of_match_table = meson_s4_pinctrl_dt_match, + }, +}; +module_platform_driver(meson_s4_pinctrl_driver); + +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index 39828e9c3120..4757bf964d3c 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1883,8 +1883,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev) } prcm_np = of_parse_phandle(np, "prcm", 0); - if (prcm_np) + if (prcm_np) { npct->prcm_base = of_iomap(prcm_np, 0); + of_node_put(prcm_np); + } if (!npct->prcm_base) { if (version == PINCTRL_NMK_STN8815) { dev_info(&pdev->dev, diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig index 48ba0469edda..852b0d0eb08e 100644 --- a/drivers/pinctrl/nuvoton/Kconfig +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -1,4 +1,24 @@ # SPDX-License-Identifier: GPL-2.0-only + +config PINCTRL_WPCM450 + tristate "Pinctrl and GPIO driver for Nuvoton WPCM450" + depends on ARCH_WPCM450 || COMPILE_TEST + depends on OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GPIOLIB + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say Y or M here to enable pin controller and GPIO support for + the Nuvoton WPCM450 SoC. This is strongly recommended when + building a kernel that will run on this chip. + + If this driver is compiled as a module, it will be named + pinctrl-wpcm450. + config PINCTRL_NPCM7XX bool "Pinctrl and GPIO driver for Nuvoton NPCM7XX" depends on (ARCH_NPCM7XX || COMPILE_TEST) && OF diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile index 886d00784cef..9e66f5dc74bf 100644 --- a/drivers/pinctrl/nuvoton/Makefile +++ b/drivers/pinctrl/nuvoton/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 # Nuvoton pinctrl support +obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index ba536fd4d674..9557fac5d11c 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -216,7 +216,7 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) struct gpio_chip *gc; struct irq_chip *chip; struct npcm7xx_gpio *bank; - u32 sts, en, bit; + unsigned long sts, en, bit; gc = irq_desc_get_handler_data(desc); bank = gpiochip_get_data(gc); @@ -225,11 +225,11 @@ static void npcmgpio_irq_handler(struct irq_desc *desc) chained_irq_enter(chip, desc); sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); - dev_dbg(bank->gc.parent, "==> got irq sts %.8x %.8x\n", sts, + dev_dbg(bank->gc.parent, "==> got irq sts %.8lx %.8lx\n", sts, en); sts &= en; - for_each_set_bit(bit, (const void *)&sts, NPCM7XX_GPIO_PER_BANK) + for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK) generic_handle_domain_irq(gc->irq.domain, bit); chained_irq_exit(chip, desc); } @@ -894,7 +894,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = { }; #define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \ - [a] { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \ + [a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \ .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \ .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \ .flag = k } @@ -904,7 +904,7 @@ static struct npcm7xx_func npcm7xx_funcs[] = { #define DRIVE_STRENGTH_HI_SHIFT 12 #define DRIVE_STRENGTH_MASK 0x0000FF00 -#define DS(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ +#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ ((hi) << DRIVE_STRENGTH_HI_SHIFT)) #define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF) #define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF) @@ -924,31 +924,31 @@ struct npcm7xx_pincfg { static const struct npcm7xx_pincfg pincfg[] = { /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */ NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), - NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), @@ -964,12 +964,12 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DS(2, 4) | GPO), + NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO), NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), - NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DS(2, 8)), + NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), + NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO), NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0), NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), @@ -979,8 +979,8 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), - NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO), @@ -1003,19 +1003,19 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), - NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DS(2, 4)), + NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), @@ -1061,34 +1061,34 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0), - NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */ - NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */ - NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), - NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DS(8, 12)), - NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)), + NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), @@ -1101,25 +1101,25 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), + NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DS(8, 12)), - NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DS(2, 4)), - NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ + NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ - NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DS(8, 12)), /* XX */ + NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), @@ -1130,11 +1130,11 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), - NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), + NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), @@ -1146,20 +1146,20 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DS(4, 8)), + NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW | GPO), - NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DS(8, 12) | SLEW), - NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DS(8, 12)), + NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), + NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */ NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */ @@ -1560,7 +1560,7 @@ static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev) { struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); - dev_dbg(npcm->dev, "group size: %d\n", ARRAY_SIZE(npcm7xx_groups)); + dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups)); return ARRAY_SIZE(npcm7xx_groups); } diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c new file mode 100644 index 000000000000..0dbeb91f0bf2 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -0,0 +1,1151 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2016-2018 Nuvoton Technology corporation. +// Copyright (c) 2016, Dell Inc +// Copyright (c) 2021-2022 Jonathan Neuschäfer +// +// This driver uses the following registers: +// - Pin mux registers, in the GCR (general control registers) block +// - GPIO registers, specific to each GPIO bank +// - GPIO event (interrupt) registers, located centrally in the GPIO register +// block, shared between all GPIO banks + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "../core.h" + +/* GCR registers */ +#define WPCM450_GCR_MFSEL1 0x0c +#define WPCM450_GCR_MFSEL2 0x10 +#define WPCM450_GCR_NONE 0 + +/* GPIO event (interrupt) registers */ +#define WPCM450_GPEVTYPE 0x00 +#define WPCM450_GPEVPOL 0x04 +#define WPCM450_GPEVDBNC 0x08 +#define WPCM450_GPEVEN 0x0c +#define WPCM450_GPEVST 0x10 + +#define WPCM450_NUM_BANKS 8 +#define WPCM450_NUM_GPIOS 128 +#define WPCM450_NUM_GPIO_IRQS 4 + +struct wpcm450_pinctrl; +struct wpcm450_bank; + +struct wpcm450_gpio { + struct gpio_chip gc; + struct wpcm450_pinctrl *pctrl; + struct irq_chip irqc; + const struct wpcm450_bank *bank; +}; + +struct wpcm450_pinctrl { + struct pinctrl_dev *pctldev; + struct device *dev; + struct irq_domain *domain; + struct regmap *gcr_regmap; + void __iomem *gpio_base; + struct wpcm450_gpio gpio_bank[WPCM450_NUM_BANKS]; + unsigned long both_edges; + + /* + * This spin lock protects registers and struct wpcm450_pinctrl fields + * against concurrent access. + */ + raw_spinlock_t lock; +}; + +struct wpcm450_bank { + /* Range of GPIOs in this port */ + u8 base; + u8 length; + + /* Register offsets (0 = register doesn't exist in this port) */ + u8 cfg0, cfg1, cfg2; + u8 blink; + u8 dataout, datain; + + /* Interrupt bit mapping */ + u8 first_irq_bit; /* First bit in GPEVST that belongs to this bank */ + u8 num_irqs; /* Number of IRQ-capable GPIOs in this bank */ + u8 first_irq_gpio; /* First IRQ-capable GPIO in this bank */ +}; + +static const struct wpcm450_bank wpcm450_banks[WPCM450_NUM_BANKS] = { + /* range cfg0 cfg1 cfg2 blink out in IRQ map */ + { 0, 16, 0x14, 0x18, 0, 0, 0x1c, 0x20, 0, 16, 0 }, + { 16, 16, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 16, 2, 8 }, + { 32, 16, 0x3c, 0x40, 0x44, 0, 0x48, 0x4c, 0, 0, 0 }, + { 48, 16, 0x50, 0x54, 0x58, 0, 0x5c, 0x60, 0, 0, 0 }, + { 64, 16, 0x64, 0x68, 0x6c, 0, 0x70, 0x74, 0, 0, 0 }, + { 80, 16, 0x78, 0x7c, 0x80, 0, 0x84, 0x88, 0, 0, 0 }, + { 96, 18, 0, 0, 0, 0, 0, 0x8c, 0, 0, 0 }, + { 114, 14, 0x90, 0x94, 0x98, 0, 0x9c, 0xa0, 0, 0, 0 }, +}; + +static int wpcm450_gpio_irq_bitnum(struct wpcm450_gpio *gpio, struct irq_data *d) +{ + const struct wpcm450_bank *bank = gpio->bank; + int hwirq = irqd_to_hwirq(d); + + if (hwirq < bank->first_irq_gpio) + return -EINVAL; + + if (hwirq - bank->first_irq_gpio >= bank->num_irqs) + return -EINVAL; + + return hwirq - bank->first_irq_gpio + bank->first_irq_bit; +} + +static int wpcm450_irq_bitnum_to_gpio(struct wpcm450_gpio *gpio, int bitnum) +{ + const struct wpcm450_bank *bank = gpio->bank; + + if (bitnum < bank->first_irq_bit) + return -EINVAL; + + if (bitnum - bank->first_irq_bit > bank->num_irqs) + return -EINVAL; + + return bitnum - bank->first_irq_bit + bank->first_irq_gpio; +} + +static void wpcm450_gpio_irq_ack(struct irq_data *d) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_irq_mask(struct irq_data *d) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + unsigned long even; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + __assign_bit(bit, &even, 0); + iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static void wpcm450_gpio_irq_unmask(struct irq_data *d) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long flags; + unsigned long even; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + __assign_bit(bit, &even, 1); + iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +/* + * This is an implementation of the gpio_chip->get() function, for use in + * wpcm450_gpio_fix_evpol. Unfortunately, we can't use the bgpio-provided + * implementation there, because it would require taking gpio_chip->bgpio_lock, + * which is a spin lock, but wpcm450_gpio_fix_evpol must work in contexts where + * a raw spin lock is held. + */ +static int wpcm450_gpio_get(struct wpcm450_gpio *gpio, int offset) +{ + void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain; + unsigned long flags; + u32 level; + + raw_spin_lock_irqsave(&gpio->pctrl->lock, flags); + level = !!(ioread32(reg) & BIT(offset)); + raw_spin_unlock_irqrestore(&gpio->pctrl->lock, flags); + + return level; +} + +/* + * Since the GPIO controller does not support dual-edge triggered interrupts + * (IRQ_TYPE_EDGE_BOTH), they are emulated using rising/falling edge triggered + * interrupts. wpcm450_gpio_fix_evpol sets the interrupt polarity for the + * specified emulated dual-edge triggered interrupts, so that the next edge can + * be detected. + */ +static void wpcm450_gpio_fix_evpol(struct wpcm450_gpio *gpio, unsigned long all) +{ + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned int bit; + + for_each_set_bit(bit, &all, 32) { + int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); + unsigned long evpol; + unsigned long flags; + int level; + + do { + level = wpcm450_gpio_get(gpio, offset); + + /* Switch event polarity to the opposite of the current level */ + raw_spin_lock_irqsave(&pctrl->lock, flags); + evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); + __assign_bit(bit, &evpol, !level); + iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + } while (wpcm450_gpio_get(gpio, offset) != level); + } +} + +static int wpcm450_gpio_set_irq_type(struct irq_data *d, unsigned int flow_type) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_data_get_irq_chip_data(d)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + unsigned long evtype, evpol; + unsigned long flags; + int ret = 0; + int bit; + + bit = wpcm450_gpio_irq_bitnum(gpio, d); + if (bit < 0) + return bit; + + irq_set_handler_locked(d, handle_level_irq); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE); + evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL); + __assign_bit(bit, &pctrl->both_edges, 0); + switch (flow_type) { + case IRQ_TYPE_LEVEL_LOW: + __assign_bit(bit, &evtype, 1); + __assign_bit(bit, &evpol, 0); + break; + case IRQ_TYPE_LEVEL_HIGH: + __assign_bit(bit, &evtype, 1); + __assign_bit(bit, &evpol, 1); + break; + case IRQ_TYPE_EDGE_FALLING: + __assign_bit(bit, &evtype, 0); + __assign_bit(bit, &evpol, 0); + break; + case IRQ_TYPE_EDGE_RISING: + __assign_bit(bit, &evtype, 0); + __assign_bit(bit, &evpol, 1); + break; + case IRQ_TYPE_EDGE_BOTH: + __assign_bit(bit, &evtype, 0); + __assign_bit(bit, &pctrl->both_edges, 1); + break; + default: + ret = -EINVAL; + } + iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE); + iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL); + + /* clear the event status for good measure */ + iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST); + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + /* fix event polarity after clearing event status */ + wpcm450_gpio_fix_evpol(gpio, BIT(bit)); + + return ret; +} + +static const struct irq_chip wpcm450_gpio_irqchip = { + .name = "WPCM450-GPIO-IRQ", + .irq_ack = wpcm450_gpio_irq_ack, + .irq_unmask = wpcm450_gpio_irq_unmask, + .irq_mask = wpcm450_gpio_irq_mask, + .irq_set_type = wpcm450_gpio_set_irq_type, +}; + +static void wpcm450_gpio_irqhandler(struct irq_desc *desc) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(irq_desc_get_handler_data(desc)); + struct wpcm450_pinctrl *pctrl = gpio->pctrl; + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long pending; + unsigned long flags; + unsigned long ours; + unsigned int bit; + + ours = GENMASK(gpio->bank->num_irqs - 1, 0) << gpio->bank->first_irq_bit; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + + pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST); + pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN); + pending &= ours; + + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + if (pending & pctrl->both_edges) + wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges); + + chained_irq_enter(chip, desc); + for_each_set_bit(bit, &pending, 32) { + int offset = wpcm450_irq_bitnum_to_gpio(gpio, bit); + + generic_handle_domain_irq(gpio->gc.irq.domain, offset); + } + chained_irq_exit(chip, desc); +} + +static int smb0_pins[] = { 115, 114 }; +static int smb1_pins[] = { 117, 116 }; +static int smb2_pins[] = { 119, 118 }; +static int smb3_pins[] = { 30, 31 }; +static int smb4_pins[] = { 28, 29 }; +static int smb5_pins[] = { 26, 27 }; + +static int scs1_pins[] = { 32 }; +static int scs2_pins[] = { 33 }; +static int scs3_pins[] = { 34 }; + +static int bsp_pins[] = { 41, 42 }; +static int hsp1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 }; +static int hsp2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; + +static int r1err_pins[] = { 56 }; +static int r1md_pins[] = { 57, 58 }; +static int rmii2_pins[] = { 84, 85, 86, 87, 88, 89 }; +static int r2err_pins[] = { 90 }; +static int r2md_pins[] = { 91, 92 }; + +static int kbcc_pins[] = { 94, 93 }; +static int clko_pins[] = { 96 }; +static int smi_pins[] = { 97 }; +static int uinc_pins[] = { 19 }; +static int mben_pins[] = {}; + +static int gspi_pins[] = { 12, 13, 14, 15 }; +static int sspi_pins[] = { 12, 13, 14, 15 }; + +static int xcs1_pins[] = { 35 }; +static int xcs2_pins[] = { 36 }; + +static int sdio_pins[] = { 7, 22, 43, 44, 45, 46, 47, 60 }; + +static int fi0_pins[] = { 64 }; +static int fi1_pins[] = { 65 }; +static int fi2_pins[] = { 66 }; +static int fi3_pins[] = { 67 }; +static int fi4_pins[] = { 68 }; +static int fi5_pins[] = { 69 }; +static int fi6_pins[] = { 70 }; +static int fi7_pins[] = { 71 }; +static int fi8_pins[] = { 72 }; +static int fi9_pins[] = { 73 }; +static int fi10_pins[] = { 74 }; +static int fi11_pins[] = { 75 }; +static int fi12_pins[] = { 76 }; +static int fi13_pins[] = { 77 }; +static int fi14_pins[] = { 78 }; +static int fi15_pins[] = { 79 }; + +static int pwm0_pins[] = { 80 }; +static int pwm1_pins[] = { 81 }; +static int pwm2_pins[] = { 82 }; +static int pwm3_pins[] = { 83 }; +static int pwm4_pins[] = { 20 }; +static int pwm5_pins[] = { 21 }; +static int pwm6_pins[] = { 16 }; +static int pwm7_pins[] = { 17 }; + +static int hg0_pins[] = { 20 }; +static int hg1_pins[] = { 21 }; +static int hg2_pins[] = { 22 }; +static int hg3_pins[] = { 23 }; +static int hg4_pins[] = { 24 }; +static int hg5_pins[] = { 25 }; +static int hg6_pins[] = { 59 }; +static int hg7_pins[] = { 60 }; + +#define WPCM450_GRPS \ + WPCM450_GRP(smb3), \ + WPCM450_GRP(smb4), \ + WPCM450_GRP(smb5), \ + WPCM450_GRP(scs1), \ + WPCM450_GRP(scs2), \ + WPCM450_GRP(scs3), \ + WPCM450_GRP(smb0), \ + WPCM450_GRP(smb1), \ + WPCM450_GRP(smb2), \ + WPCM450_GRP(bsp), \ + WPCM450_GRP(hsp1), \ + WPCM450_GRP(hsp2), \ + WPCM450_GRP(r1err), \ + WPCM450_GRP(r1md), \ + WPCM450_GRP(rmii2), \ + WPCM450_GRP(r2err), \ + WPCM450_GRP(r2md), \ + WPCM450_GRP(kbcc), \ + WPCM450_GRP(clko), \ + WPCM450_GRP(smi), \ + WPCM450_GRP(uinc), \ + WPCM450_GRP(gspi), \ + WPCM450_GRP(mben), \ + WPCM450_GRP(xcs2), \ + WPCM450_GRP(xcs1), \ + WPCM450_GRP(sdio), \ + WPCM450_GRP(sspi), \ + WPCM450_GRP(fi0), \ + WPCM450_GRP(fi1), \ + WPCM450_GRP(fi2), \ + WPCM450_GRP(fi3), \ + WPCM450_GRP(fi4), \ + WPCM450_GRP(fi5), \ + WPCM450_GRP(fi6), \ + WPCM450_GRP(fi7), \ + WPCM450_GRP(fi8), \ + WPCM450_GRP(fi9), \ + WPCM450_GRP(fi10), \ + WPCM450_GRP(fi11), \ + WPCM450_GRP(fi12), \ + WPCM450_GRP(fi13), \ + WPCM450_GRP(fi14), \ + WPCM450_GRP(fi15), \ + WPCM450_GRP(pwm0), \ + WPCM450_GRP(pwm1), \ + WPCM450_GRP(pwm2), \ + WPCM450_GRP(pwm3), \ + WPCM450_GRP(pwm4), \ + WPCM450_GRP(pwm5), \ + WPCM450_GRP(pwm6), \ + WPCM450_GRP(pwm7), \ + WPCM450_GRP(hg0), \ + WPCM450_GRP(hg1), \ + WPCM450_GRP(hg2), \ + WPCM450_GRP(hg3), \ + WPCM450_GRP(hg4), \ + WPCM450_GRP(hg5), \ + WPCM450_GRP(hg6), \ + WPCM450_GRP(hg7), \ + +enum { +#define WPCM450_GRP(x) fn_ ## x + WPCM450_GRPS + /* add placeholder for none/gpio */ + WPCM450_GRP(gpio), + WPCM450_GRP(none), +#undef WPCM450_GRP +}; + +static struct group_desc wpcm450_groups[] = { +#define WPCM450_GRP(x) { .name = #x, .pins = x ## _pins, \ + .num_pins = ARRAY_SIZE(x ## _pins) } + WPCM450_GRPS +#undef WPCM450_GRP +}; + +#define WPCM450_SFUNC(a) WPCM450_FUNC(a, #a) +#define WPCM450_FUNC(a, b...) static const char *a ## _grp[] = { b } +#define WPCM450_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ + .groups = nm ## _grp } +struct wpcm450_func { + const char *name; + const unsigned int ngroups; + const char *const *groups; +}; + +WPCM450_SFUNC(smb3); +WPCM450_SFUNC(smb4); +WPCM450_SFUNC(smb5); +WPCM450_SFUNC(scs1); +WPCM450_SFUNC(scs2); +WPCM450_SFUNC(scs3); +WPCM450_SFUNC(smb0); +WPCM450_SFUNC(smb1); +WPCM450_SFUNC(smb2); +WPCM450_SFUNC(bsp); +WPCM450_SFUNC(hsp1); +WPCM450_SFUNC(hsp2); +WPCM450_SFUNC(r1err); +WPCM450_SFUNC(r1md); +WPCM450_SFUNC(rmii2); +WPCM450_SFUNC(r2err); +WPCM450_SFUNC(r2md); +WPCM450_SFUNC(kbcc); +WPCM450_SFUNC(clko); +WPCM450_SFUNC(smi); +WPCM450_SFUNC(uinc); +WPCM450_SFUNC(gspi); +WPCM450_SFUNC(mben); +WPCM450_SFUNC(xcs2); +WPCM450_SFUNC(xcs1); +WPCM450_SFUNC(sdio); +WPCM450_SFUNC(sspi); +WPCM450_SFUNC(fi0); +WPCM450_SFUNC(fi1); +WPCM450_SFUNC(fi2); +WPCM450_SFUNC(fi3); +WPCM450_SFUNC(fi4); +WPCM450_SFUNC(fi5); +WPCM450_SFUNC(fi6); +WPCM450_SFUNC(fi7); +WPCM450_SFUNC(fi8); +WPCM450_SFUNC(fi9); +WPCM450_SFUNC(fi10); +WPCM450_SFUNC(fi11); +WPCM450_SFUNC(fi12); +WPCM450_SFUNC(fi13); +WPCM450_SFUNC(fi14); +WPCM450_SFUNC(fi15); +WPCM450_SFUNC(pwm0); +WPCM450_SFUNC(pwm1); +WPCM450_SFUNC(pwm2); +WPCM450_SFUNC(pwm3); +WPCM450_SFUNC(pwm4); +WPCM450_SFUNC(pwm5); +WPCM450_SFUNC(pwm6); +WPCM450_SFUNC(pwm7); +WPCM450_SFUNC(hg0); +WPCM450_SFUNC(hg1); +WPCM450_SFUNC(hg2); +WPCM450_SFUNC(hg3); +WPCM450_SFUNC(hg4); +WPCM450_SFUNC(hg5); +WPCM450_SFUNC(hg6); +WPCM450_SFUNC(hg7); + +#define WPCM450_GRP(x) #x +WPCM450_FUNC(gpio, WPCM450_GRPS); +#undef WPCM450_GRP + +/* Function names */ +static struct wpcm450_func wpcm450_funcs[] = { + WPCM450_MKFUNC(smb3), + WPCM450_MKFUNC(smb4), + WPCM450_MKFUNC(smb5), + WPCM450_MKFUNC(scs1), + WPCM450_MKFUNC(scs2), + WPCM450_MKFUNC(scs3), + WPCM450_MKFUNC(smb0), + WPCM450_MKFUNC(smb1), + WPCM450_MKFUNC(smb2), + WPCM450_MKFUNC(bsp), + WPCM450_MKFUNC(hsp1), + WPCM450_MKFUNC(hsp2), + WPCM450_MKFUNC(r1err), + WPCM450_MKFUNC(r1md), + WPCM450_MKFUNC(rmii2), + WPCM450_MKFUNC(r2err), + WPCM450_MKFUNC(r2md), + WPCM450_MKFUNC(kbcc), + WPCM450_MKFUNC(clko), + WPCM450_MKFUNC(smi), + WPCM450_MKFUNC(uinc), + WPCM450_MKFUNC(gspi), + WPCM450_MKFUNC(mben), + WPCM450_MKFUNC(xcs2), + WPCM450_MKFUNC(xcs1), + WPCM450_MKFUNC(sdio), + WPCM450_MKFUNC(sspi), + WPCM450_MKFUNC(fi0), + WPCM450_MKFUNC(fi1), + WPCM450_MKFUNC(fi2), + WPCM450_MKFUNC(fi3), + WPCM450_MKFUNC(fi4), + WPCM450_MKFUNC(fi5), + WPCM450_MKFUNC(fi6), + WPCM450_MKFUNC(fi7), + WPCM450_MKFUNC(fi8), + WPCM450_MKFUNC(fi9), + WPCM450_MKFUNC(fi10), + WPCM450_MKFUNC(fi11), + WPCM450_MKFUNC(fi12), + WPCM450_MKFUNC(fi13), + WPCM450_MKFUNC(fi14), + WPCM450_MKFUNC(fi15), + WPCM450_MKFUNC(pwm0), + WPCM450_MKFUNC(pwm1), + WPCM450_MKFUNC(pwm2), + WPCM450_MKFUNC(pwm3), + WPCM450_MKFUNC(pwm4), + WPCM450_MKFUNC(pwm5), + WPCM450_MKFUNC(pwm6), + WPCM450_MKFUNC(pwm7), + WPCM450_MKFUNC(hg0), + WPCM450_MKFUNC(hg1), + WPCM450_MKFUNC(hg2), + WPCM450_MKFUNC(hg3), + WPCM450_MKFUNC(hg4), + WPCM450_MKFUNC(hg5), + WPCM450_MKFUNC(hg6), + WPCM450_MKFUNC(hg7), + WPCM450_MKFUNC(gpio), +}; + +#define WPCM450_PINCFG(a, b, c, d, e, f, g) \ + [a] = { .fn0 = fn_ ## b, .reg0 = WPCM450_GCR_ ## c, .bit0 = d, \ + .fn1 = fn_ ## e, .reg1 = WPCM450_GCR_ ## f, .bit1 = g } + +struct wpcm450_pincfg { + int fn0, reg0, bit0; + int fn1, reg1, bit1; +}; + +static const struct wpcm450_pincfg pincfg[] = { + /* PIN FUNCTION 1 FUNCTION 2 */ + WPCM450_PINCFG(0, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(1, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(2, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(3, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(4, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(5, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(6, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(7, none, NONE, 0, sdio, MFSEL1, 30), + WPCM450_PINCFG(8, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(9, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(10, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(11, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(12, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(13, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(14, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(15, gspi, MFSEL1, 24, sspi, MFSEL1, 31), + WPCM450_PINCFG(16, none, NONE, 0, pwm6, MFSEL2, 22), + WPCM450_PINCFG(17, none, NONE, 0, pwm7, MFSEL2, 23), + WPCM450_PINCFG(18, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(19, uinc, MFSEL1, 23, none, NONE, 0), + WPCM450_PINCFG(20, hg0, MFSEL2, 24, pwm4, MFSEL2, 20), + WPCM450_PINCFG(21, hg1, MFSEL2, 25, pwm5, MFSEL2, 21), + WPCM450_PINCFG(22, hg2, MFSEL2, 26, none, NONE, 0), + WPCM450_PINCFG(23, hg3, MFSEL2, 27, none, NONE, 0), + WPCM450_PINCFG(24, hg4, MFSEL2, 28, none, NONE, 0), + WPCM450_PINCFG(25, hg5, MFSEL2, 29, none, NONE, 0), + WPCM450_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0), + WPCM450_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0), + WPCM450_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0), + WPCM450_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0), + WPCM450_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0), + WPCM450_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0), + + WPCM450_PINCFG(32, scs1, MFSEL1, 3, none, NONE, 0), + WPCM450_PINCFG(33, scs2, MFSEL1, 4, none, NONE, 0), + WPCM450_PINCFG(34, scs3, MFSEL1, 5, none, NONE, 0), + WPCM450_PINCFG(35, xcs1, MFSEL1, 29, none, NONE, 0), + WPCM450_PINCFG(36, xcs2, MFSEL1, 28, none, NONE, 0), + WPCM450_PINCFG(37, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(38, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(39, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(40, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(41, bsp, MFSEL1, 9, none, NONE, 0), + WPCM450_PINCFG(42, bsp, MFSEL1, 9, none, NONE, 0), + WPCM450_PINCFG(43, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(44, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(45, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(46, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(47, hsp1, MFSEL1, 10, sdio, MFSEL1, 30), + WPCM450_PINCFG(48, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(49, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(50, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(51, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(52, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(53, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(54, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(55, hsp2, MFSEL1, 11, none, NONE, 0), + WPCM450_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0), + WPCM450_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0), + WPCM450_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0), + WPCM450_PINCFG(59, hg6, MFSEL2, 30, none, NONE, 0), + WPCM450_PINCFG(60, hg7, MFSEL2, 31, sdio, MFSEL1, 30), + WPCM450_PINCFG(61, hsp1, MFSEL1, 10, none, NONE, 0), + WPCM450_PINCFG(62, hsp1, MFSEL1, 10, none, NONE, 0), + WPCM450_PINCFG(63, hsp1, MFSEL1, 10, none, NONE, 0), + + WPCM450_PINCFG(64, fi0, MFSEL2, 0, none, NONE, 0), + WPCM450_PINCFG(65, fi1, MFSEL2, 1, none, NONE, 0), + WPCM450_PINCFG(66, fi2, MFSEL2, 2, none, NONE, 0), + WPCM450_PINCFG(67, fi3, MFSEL2, 3, none, NONE, 0), + WPCM450_PINCFG(68, fi4, MFSEL2, 4, none, NONE, 0), + WPCM450_PINCFG(69, fi5, MFSEL2, 5, none, NONE, 0), + WPCM450_PINCFG(70, fi6, MFSEL2, 6, none, NONE, 0), + WPCM450_PINCFG(71, fi7, MFSEL2, 7, none, NONE, 0), + WPCM450_PINCFG(72, fi8, MFSEL2, 8, none, NONE, 0), + WPCM450_PINCFG(73, fi9, MFSEL2, 9, none, NONE, 0), + WPCM450_PINCFG(74, fi10, MFSEL2, 10, none, NONE, 0), + WPCM450_PINCFG(75, fi11, MFSEL2, 11, none, NONE, 0), + WPCM450_PINCFG(76, fi12, MFSEL2, 12, none, NONE, 0), + WPCM450_PINCFG(77, fi13, MFSEL2, 13, none, NONE, 0), + WPCM450_PINCFG(78, fi14, MFSEL2, 14, none, NONE, 0), + WPCM450_PINCFG(79, fi15, MFSEL2, 15, none, NONE, 0), + WPCM450_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0), + WPCM450_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0), + WPCM450_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0), + WPCM450_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0), + WPCM450_PINCFG(84, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(85, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(86, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(87, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(88, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(89, rmii2, MFSEL1, 14, none, NONE, 0), + WPCM450_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0), + WPCM450_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0), + WPCM450_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0), + WPCM450_PINCFG(93, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(94, kbcc, MFSEL1, 17, none, NONE, 0), + WPCM450_PINCFG(95, none, NONE, 0, none, NONE, 0), + + WPCM450_PINCFG(96, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(97, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(98, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(99, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(100, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(101, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(102, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(103, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(104, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(105, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(106, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(107, none, NONE, 0, none, NONE, 0), + WPCM450_PINCFG(108, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(109, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(110, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(111, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(112, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(113, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0), + WPCM450_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0), + WPCM450_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0), + WPCM450_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0), + WPCM450_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0), + WPCM450_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0), + WPCM450_PINCFG(120, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(121, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(122, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(123, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(124, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(125, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(126, none, NONE, 0, none, NONE, 0), /* DVO */ + WPCM450_PINCFG(127, none, NONE, 0, none, NONE, 0), /* DVO */ +}; + +#define WPCM450_PIN(n) PINCTRL_PIN(n, "gpio" #n) + +static const struct pinctrl_pin_desc wpcm450_pins[] = { + WPCM450_PIN(0), WPCM450_PIN(1), WPCM450_PIN(2), WPCM450_PIN(3), + WPCM450_PIN(4), WPCM450_PIN(5), WPCM450_PIN(6), WPCM450_PIN(7), + WPCM450_PIN(8), WPCM450_PIN(9), WPCM450_PIN(10), WPCM450_PIN(11), + WPCM450_PIN(12), WPCM450_PIN(13), WPCM450_PIN(14), WPCM450_PIN(15), + WPCM450_PIN(16), WPCM450_PIN(17), WPCM450_PIN(18), WPCM450_PIN(19), + WPCM450_PIN(20), WPCM450_PIN(21), WPCM450_PIN(22), WPCM450_PIN(23), + WPCM450_PIN(24), WPCM450_PIN(25), WPCM450_PIN(26), WPCM450_PIN(27), + WPCM450_PIN(28), WPCM450_PIN(29), WPCM450_PIN(30), WPCM450_PIN(31), + WPCM450_PIN(32), WPCM450_PIN(33), WPCM450_PIN(34), WPCM450_PIN(35), + WPCM450_PIN(36), WPCM450_PIN(37), WPCM450_PIN(38), WPCM450_PIN(39), + WPCM450_PIN(40), WPCM450_PIN(41), WPCM450_PIN(42), WPCM450_PIN(43), + WPCM450_PIN(44), WPCM450_PIN(45), WPCM450_PIN(46), WPCM450_PIN(47), + WPCM450_PIN(48), WPCM450_PIN(49), WPCM450_PIN(50), WPCM450_PIN(51), + WPCM450_PIN(52), WPCM450_PIN(53), WPCM450_PIN(54), WPCM450_PIN(55), + WPCM450_PIN(56), WPCM450_PIN(57), WPCM450_PIN(58), WPCM450_PIN(59), + WPCM450_PIN(60), WPCM450_PIN(61), WPCM450_PIN(62), WPCM450_PIN(63), + WPCM450_PIN(64), WPCM450_PIN(65), WPCM450_PIN(66), WPCM450_PIN(67), + WPCM450_PIN(68), WPCM450_PIN(69), WPCM450_PIN(70), WPCM450_PIN(71), + WPCM450_PIN(72), WPCM450_PIN(73), WPCM450_PIN(74), WPCM450_PIN(75), + WPCM450_PIN(76), WPCM450_PIN(77), WPCM450_PIN(78), WPCM450_PIN(79), + WPCM450_PIN(80), WPCM450_PIN(81), WPCM450_PIN(82), WPCM450_PIN(83), + WPCM450_PIN(84), WPCM450_PIN(85), WPCM450_PIN(86), WPCM450_PIN(87), + WPCM450_PIN(88), WPCM450_PIN(89), WPCM450_PIN(90), WPCM450_PIN(91), + WPCM450_PIN(92), WPCM450_PIN(93), WPCM450_PIN(94), WPCM450_PIN(95), + WPCM450_PIN(96), WPCM450_PIN(97), WPCM450_PIN(98), WPCM450_PIN(99), + WPCM450_PIN(100), WPCM450_PIN(101), WPCM450_PIN(102), WPCM450_PIN(103), + WPCM450_PIN(104), WPCM450_PIN(105), WPCM450_PIN(106), WPCM450_PIN(107), + WPCM450_PIN(108), WPCM450_PIN(109), WPCM450_PIN(110), WPCM450_PIN(111), + WPCM450_PIN(112), WPCM450_PIN(113), WPCM450_PIN(114), WPCM450_PIN(115), + WPCM450_PIN(116), WPCM450_PIN(117), WPCM450_PIN(118), WPCM450_PIN(119), + WPCM450_PIN(120), WPCM450_PIN(121), WPCM450_PIN(122), WPCM450_PIN(123), + WPCM450_PIN(124), WPCM450_PIN(125), WPCM450_PIN(126), WPCM450_PIN(127), +}; + +/* Enable mode in pin group */ +static void wpcm450_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, + int npins, int func) +{ + const struct wpcm450_pincfg *cfg; + int i; + + for (i = 0; i < npins; i++) { + cfg = &pincfg[pin[i]]; + if (func == fn_gpio || cfg->fn0 == func || cfg->fn1 == func) { + if (cfg->reg0) + regmap_update_bits(gcr_regmap, cfg->reg0, + BIT(cfg->bit0), + (cfg->fn0 == func) ? BIT(cfg->bit0) : 0); + if (cfg->reg1) + regmap_update_bits(gcr_regmap, cfg->reg1, + BIT(cfg->bit1), + (cfg->fn1 == func) ? BIT(cfg->bit1) : 0); + } + } +} + +static int wpcm450_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(wpcm450_groups); +} + +static const char *wpcm450_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return wpcm450_groups[selector].name; +} + +static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) +{ + *npins = wpcm450_groups[selector].num_pins; + *pins = wpcm450_groups[selector].pins; + + return 0; +} + +static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + u32 *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, + map, num_maps, + PIN_MAP_TYPE_INVALID); +} + +static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, u32 num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops wpcm450_pinctrl_ops = { + .get_groups_count = wpcm450_get_groups_count, + .get_group_name = wpcm450_get_group_name, + .get_group_pins = wpcm450_get_group_pins, + .dt_node_to_map = wpcm450_dt_node_to_map, + .dt_free_map = wpcm450_dt_free_map, +}; + +static int wpcm450_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(wpcm450_funcs); +} + +static const char *wpcm450_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return wpcm450_funcs[function].name; +} + +static int wpcm450_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const ngroups) +{ + *ngroups = wpcm450_funcs[function].ngroups; + *groups = wpcm450_funcs[function].groups; + + return 0; +} + +static int wpcm450_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + + wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins, + wpcm450_groups[group].num_pins, function); + + return 0; +} + +static const struct pinmux_ops wpcm450_pinmux_ops = { + .get_functions_count = wpcm450_get_functions_count, + .get_function_name = wpcm450_get_function_name, + .get_function_groups = wpcm450_get_function_groups, + .set_mux = wpcm450_pinmux_set_mux, +}; + +static int debounce_bitnum(int gpio) +{ + if (gpio >= 0 && gpio < 16) + return gpio; + return -EINVAL; +} + +static int wpcm450_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned long flags; + int bit; + u32 reg; + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + bit = debounce_bitnum(pin); + if (bit < 0) + return bit; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + *config = pinconf_to_config_packed(param, !!(reg & BIT(bit))); + return 0; + default: + return -ENOTSUPP; + } +} + +static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl, + unsigned int pin, unsigned long config) +{ + enum pin_config_param param = pinconf_to_config_param(config); + unsigned long flags; + unsigned long reg; + int bit; + int arg; + + switch (param) { + case PIN_CONFIG_INPUT_DEBOUNCE: + bit = debounce_bitnum(pin); + if (bit < 0) + return bit; + + arg = pinconf_to_config_argument(config); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC); + __assign_bit(bit, ®, arg); + iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + return 0; + default: + return -ENOTSUPP; + } +} + +static int wpcm450_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + int ret; + + while (num_configs--) { + ret = wpcm450_config_set_one(pctrl, pin, *configs++); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops wpcm450_pinconf_ops = { + .is_generic = true, + .pin_config_get = wpcm450_config_get, + .pin_config_set = wpcm450_config_set, +}; + +static struct pinctrl_desc wpcm450_pinctrl_desc = { + .name = "wpcm450-pinctrl", + .pins = wpcm450_pins, + .npins = ARRAY_SIZE(wpcm450_pins), + .pctlops = &wpcm450_pinctrl_ops, + .pmxops = &wpcm450_pinmux_ops, + .confops = &wpcm450_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int wpcm450_gpio_set_config(struct gpio_chip *chip, + unsigned int offset, unsigned long config) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(chip); + + return wpcm450_config_set_one(gpio->pctrl, offset, config); +} + +static int wpcm450_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + struct wpcm450_gpio *gpio = gpiochip_get_data(chip); + const struct wpcm450_bank *bank = gpio->bank; + + return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev), + 0, bank->base, bank->length); +} + +static int wpcm450_gpio_register(struct platform_device *pdev, + struct wpcm450_pinctrl *pctrl) +{ + struct device *dev = &pdev->dev; + struct fwnode_handle *child; + int ret; + + pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->gpio_base)) + return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base), + "Resource fail for GPIO controller\n"); + + device_for_each_child_node(dev, child) { + void __iomem *dat = NULL; + void __iomem *set = NULL; + void __iomem *dirout = NULL; + unsigned long flags = 0; + const struct wpcm450_bank *bank; + struct wpcm450_gpio *gpio; + struct gpio_irq_chip *girq; + u32 reg; + int i; + + if (!fwnode_property_read_bool(child, "gpio-controller")) + continue; + + ret = fwnode_property_read_u32(child, "reg", ®); + if (ret < 0) + return ret; + + gpio = &pctrl->gpio_bank[reg]; + gpio->pctrl = pctrl; + + if (reg >= WPCM450_NUM_BANKS) + return dev_err_probe(dev, -EINVAL, + "GPIO index %d out of range!\n", reg); + + bank = &wpcm450_banks[reg]; + gpio->bank = bank; + + dat = pctrl->gpio_base + bank->datain; + if (bank->dataout) { + set = pctrl->gpio_base + bank->dataout; + dirout = pctrl->gpio_base + bank->cfg0; + } else { + flags = BGPIOF_NO_OUTPUT; + } + ret = bgpio_init(&gpio->gc, dev, 4, + dat, set, NULL, dirout, NULL, flags); + if (ret < 0) + return dev_err_probe(dev, ret, "GPIO initialization failed\n"); + + gpio->gc.ngpio = bank->length; + gpio->gc.set_config = wpcm450_gpio_set_config; + gpio->gc.fwnode = child; + gpio->gc.add_pin_ranges = wpcm450_gpio_add_pin_ranges; + + gpio->irqc = wpcm450_gpio_irqchip; + girq = &gpio->gc.irq; + girq->chip = &gpio->irqc; + girq->parent_handler = wpcm450_gpio_irqhandler; + girq->parents = devm_kcalloc(dev, WPCM450_NUM_GPIO_IRQS, + sizeof(*girq->parents), GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + + girq->num_parents = 0; + for (i = 0; i < WPCM450_NUM_GPIO_IRQS; i++) { + int irq = fwnode_irq_get(child, i); + + if (irq < 0) + break; + + girq->parents[i] = irq; + girq->num_parents++; + } + + ret = devm_gpiochip_add_data(dev, &gpio->gc, gpio); + if (ret) + return dev_err_probe(dev, ret, "Failed to add GPIO chip\n"); + } + + return 0; +} + +static int wpcm450_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct wpcm450_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = &pdev->dev; + raw_spin_lock_init(&pctrl->lock); + dev_set_drvdata(dev, pctrl); + + pctrl->gcr_regmap = + syscon_regmap_lookup_by_compatible("nuvoton,wpcm450-gcr"); + if (IS_ERR(pctrl->gcr_regmap)) + return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap), + "Failed to find nuvoton,wpcm450-gcr\n"); + + pctrl->pctldev = devm_pinctrl_register(dev, + &wpcm450_pinctrl_desc, pctrl); + if (IS_ERR(pctrl->pctldev)) + return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), + "Failed to register pinctrl device\n"); + + ret = wpcm450_gpio_register(pdev, pctrl); + if (ret < 0) + return ret; + + return 0; +} + +static const struct of_device_id wpcm450_pinctrl_match[] = { + { .compatible = "nuvoton,wpcm450-pinctrl" }, + { } +}; +MODULE_DEVICE_TABLE(of, wpcm450_pinctrl_match); + +static struct platform_driver wpcm450_pinctrl_driver = { + .probe = wpcm450_pinctrl_probe, + .driver = { + .name = "wpcm450-pinctrl", + .of_match_table = wpcm450_pinctrl_match, + }, +}; +module_platform_driver(wpcm450_pinctrl_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Jonathan Neuschäfer "); +MODULE_DESCRIPTION("Nuvoton WPCM450 Pinctrl and GPIO driver"); diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index f8edcc88ac01..415d1df8f46a 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -30,10 +30,10 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_BIAS_BUS_HOLD, "input bias bus hold", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_DISABLE, "input bias disabled", NULL, false), PCONFDUMP(PIN_CONFIG_BIAS_HIGH_IMPEDANCE, "input bias high impedance", NULL, false), - PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", NULL, false), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_DOWN, "input bias pull down", "ohms", true), PCONFDUMP(PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, - "input bias pull to pin specific state", NULL, false), - PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", NULL, false), + "input bias pull to pin specific state", "ohms", true), + PCONFDUMP(PIN_CONFIG_BIAS_PULL_UP, "input bias pull up", "ohms", true), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL, false), PCONFDUMP(PIN_CONFIG_DRIVE_PUSH_PULL, "output drive push pull", NULL, false), diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index fafd1f55cba7..517f2a6330ad 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1045,7 +1045,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) const char **group_names; const struct of_device_id *match; int i, ret; - struct resource *res; struct atmel_pioctrl *atmel_pioctrl; const struct atmel_pioctrl_data *atmel_pioctrl_data; @@ -1164,16 +1163,15 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) /* There is one controller but each bank has its own irq line. */ for (i = 0; i < atmel_pioctrl->nbanks; i++) { - res = platform_get_resource(pdev, IORESOURCE_IRQ, i); - if (!res) { - dev_err(dev, "missing irq resource for group %c\n", + ret = platform_get_irq(pdev, i); + if (ret < 0) { + dev_dbg(dev, "missing irq resource for group %c\n", 'A' + i); - return -EINVAL; + return ret; } - atmel_pioctrl->irqs[i] = res->start; - irq_set_chained_handler_and_data(res->start, - atmel_gpio_irq_handler, atmel_pioctrl); - dev_dbg(dev, "bank %i: irq=%pr\n", i, res); + atmel_pioctrl->irqs[i] = ret; + irq_set_chained_handler_and_data(ret, atmel_gpio_irq_handler, atmel_pioctrl); + dev_dbg(dev, "bank %i: irq=%d\n", i, ret); } atmel_pioctrl->irq_domain = irq_domain_add_linear(dev->of_node, diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 2712f51eb238..fa6becca1788 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -119,6 +119,8 @@ struct ingenic_chip_info { unsigned int num_functions; const u32 *pull_ups, *pull_downs; + + const struct regmap_access_table *access_table; }; struct ingenic_pinctrl { @@ -2179,6 +2181,17 @@ static const struct function_desc x1000_functions[] = { { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, }; +static const struct regmap_range x1000_access_ranges[] = { + regmap_reg_range(0x000, 0x400 - 4), + regmap_reg_range(0x700, 0x800 - 4), +}; + +/* shared with X1500 */ +static const struct regmap_access_table x1000_access_table = { + .yes_ranges = x1000_access_ranges, + .n_yes_ranges = ARRAY_SIZE(x1000_access_ranges), +}; + static const struct ingenic_chip_info x1000_chip_info = { .num_chips = 4, .reg_offset = 0x100, @@ -2189,6 +2202,7 @@ static const struct ingenic_chip_info x1000_chip_info = { .num_functions = ARRAY_SIZE(x1000_functions), .pull_ups = x1000_pull_ups, .pull_downs = x1000_pull_downs, + .access_table = &x1000_access_table, }; static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; @@ -2300,6 +2314,7 @@ static const struct ingenic_chip_info x1500_chip_info = { .num_functions = ARRAY_SIZE(x1500_functions), .pull_ups = x1000_pull_ups, .pull_downs = x1000_pull_downs, + .access_table = &x1000_access_table, }; static const u32 x1830_pull_ups[4] = { @@ -2506,6 +2521,16 @@ static const struct function_desc x1830_functions[] = { { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, }; +static const struct regmap_range x1830_access_ranges[] = { + regmap_reg_range(0x0000, 0x4000 - 4), + regmap_reg_range(0x7000, 0x8000 - 4), +}; + +static const struct regmap_access_table x1830_access_table = { + .yes_ranges = x1830_access_ranges, + .n_yes_ranges = ARRAY_SIZE(x1830_access_ranges), +}; + static const struct ingenic_chip_info x1830_chip_info = { .num_chips = 4, .reg_offset = 0x1000, @@ -2516,6 +2541,7 @@ static const struct ingenic_chip_info x1830_chip_info = { .num_functions = ARRAY_SIZE(x1830_functions), .pull_ups = x1830_pull_ups, .pull_downs = x1830_pull_downs, + .access_table = &x1830_access_table, }; static const u32 x2000_pull_ups[5] = { @@ -2969,6 +2995,17 @@ static const struct function_desc x2000_functions[] = { { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), }, }; +static const struct regmap_range x2000_access_ranges[] = { + regmap_reg_range(0x000, 0x500 - 4), + regmap_reg_range(0x700, 0x800 - 4), +}; + +/* shared with X2100 */ +static const struct regmap_access_table x2000_access_table = { + .yes_ranges = x2000_access_ranges, + .n_yes_ranges = ARRAY_SIZE(x2000_access_ranges), +}; + static const struct ingenic_chip_info x2000_chip_info = { .num_chips = 5, .reg_offset = 0x100, @@ -2979,6 +3016,7 @@ static const struct ingenic_chip_info x2000_chip_info = { .num_functions = ARRAY_SIZE(x2000_functions), .pull_ups = x2000_pull_ups, .pull_downs = x2000_pull_downs, + .access_table = &x2000_access_table, }; static const u32 x2100_pull_ups[5] = { @@ -3189,6 +3227,7 @@ static const struct ingenic_chip_info x2100_chip_info = { .num_functions = ARRAY_SIZE(x2100_functions), .pull_ups = x2100_pull_ups, .pull_downs = x2100_pull_downs, + .access_table = &x2000_access_table, }; static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) @@ -4168,7 +4207,12 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) return PTR_ERR(base); regmap_config = ingenic_pinctrl_regmap_config; - regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset; + if (chip_info->access_table) { + regmap_config.rd_table = chip_info->access_table; + regmap_config.wr_table = chip_info->access_table; + } else { + regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset - 4; + } jzpc->map = devm_regmap_init_mmio(dev, base, ®map_config); if (IS_ERR(jzpc->map)) { diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index 639f1130e989..80a8939ad0c0 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "core.h" #include "pinconf.h" @@ -63,11 +64,13 @@ struct sgpio_properties { #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) #define SGPIO_OCELOT_AUTO_REPEAT BIT(10) +#define SGPIO_OCELOT_SINGLE_SHOT BIT(11) #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) #define SGPIO_SPARX5_AUTO_REPEAT BIT(6) +#define SGPIO_SPARX5_SINGLE_SHOT BIT(7) #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) @@ -116,6 +119,9 @@ struct sgpio_priv { u32 clock; struct regmap *regs; const struct sgpio_properties *properties; + spinlock_t lock; + /* protects the config register and single shot mode */ + struct mutex poll_lock; }; struct sgpio_port_addr { @@ -166,12 +172,11 @@ static void sgpio_writel(struct sgpio_priv *priv, static inline void sgpio_clrsetbits(struct sgpio_priv *priv, u32 rno, u32 off, u32 clear, u32 set) { - u32 val = sgpio_readl(priv, rno, off); + u32 addr = sgpio_get_addr(priv, rno, off); + int ret; - val &= ~clear; - val |= set; - - sgpio_writel(priv, val, rno, off); + ret = regmap_update_bits(priv->regs, addr, clear | set, set); + WARN_ONCE(ret, "error updating sgpio reg %d\n", ret); } static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) @@ -224,12 +229,64 @@ static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); } -static void sgpio_output_set(struct sgpio_priv *priv, - struct sgpio_port_addr *addr, - int value) +static int sgpio_single_shot(struct sgpio_priv *priv) +{ + u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0); + int ret, ret2; + u32 ctrl; + unsigned int single_shot; + unsigned int auto_repeat; + + switch (priv->properties->arch) { + case SGPIO_ARCH_LUTON: + /* not supported for now */ + return 0; + case SGPIO_ARCH_OCELOT: + single_shot = SGPIO_OCELOT_SINGLE_SHOT; + auto_repeat = SGPIO_OCELOT_AUTO_REPEAT; + break; + case SGPIO_ARCH_SPARX5: + single_shot = SGPIO_SPARX5_SINGLE_SHOT; + auto_repeat = SGPIO_SPARX5_AUTO_REPEAT; + break; + default: + return -EINVAL; + } + + /* + * Trigger immediate burst. This only works when auto repeat is turned + * off. Otherwise, the single shot bit will never be cleared by the + * hardware. Measurements showed that an update might take as long as + * the burst gap. On a LAN9668 this is about 50ms for the largest + * setting. + * After the manual burst, reenable the auto repeat mode again. + */ + mutex_lock(&priv->poll_lock); + ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat, + single_shot); + if (ret) + goto out; + + ret = regmap_read_poll_timeout(priv->regs, addr, ctrl, + !(ctrl & single_shot), 100, 60000); + + /* reenable auto repeat mode even if there was an error */ + ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat); +out: + mutex_unlock(&priv->poll_lock); + + return ret ?: ret2; +} + +static int sgpio_output_set(struct sgpio_priv *priv, + struct sgpio_port_addr *addr, + int value) { unsigned int bit = SGPIO_SRC_BITS * addr->bit; + u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port); + bool changed; u32 clr, set; + int ret; switch (priv->properties->arch) { case SGPIO_ARCH_LUTON: @@ -245,9 +302,21 @@ static void sgpio_output_set(struct sgpio_priv *priv, set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); break; default: - return; + return -EINVAL; } - sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set); + + ret = regmap_update_bits_check(priv->regs, reg, clr | set, set, + &changed); + if (ret) + return ret; + + if (changed) { + ret = sgpio_single_shot(priv); + if (ret) + return ret; + } + + return 0; } static int sgpio_output_get(struct sgpio_priv *priv, @@ -333,7 +402,7 @@ static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, case PIN_CONFIG_OUTPUT: if (bank->is_input) return -EINVAL; - sgpio_output_set(priv, &addr, arg); + err = sgpio_output_set(priv, &addr, arg); break; default: @@ -473,9 +542,7 @@ static int microchip_sgpio_direction_output(struct gpio_chip *gc, sgpio_pin_to_addr(priv, gpio, &addr); - sgpio_output_set(priv, &addr, value); - - return 0; + return sgpio_output_set(priv, &addr, value); } static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) @@ -575,10 +642,13 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, struct sgpio_bank *bank = gpiochip_get_data(chip); unsigned int gpio = irqd_to_hwirq(data); struct sgpio_port_addr addr; + unsigned long flags; u32 ena; sgpio_pin_to_addr(bank->priv, gpio, &addr); + spin_lock_irqsave(&bank->priv->lock, flags); + /* Disable interrupt while changing type */ ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); @@ -595,6 +665,8 @@ static void microchip_sgpio_irq_settype(struct irq_data *data, /* Possibly re-enable interrupts */ sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); + + spin_unlock_irqrestore(&bank->priv->lock, flags); } static void microchip_sgpio_irq_setreg(struct irq_data *data, @@ -626,7 +698,14 @@ static void microchip_sgpio_irq_unmask(struct irq_data *data) static void microchip_sgpio_irq_ack(struct irq_data *data) { - microchip_sgpio_irq_setreg(data, REG_INT_ACK, false); + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct sgpio_bank *bank = gpiochip_get_data(chip); + unsigned int gpio = irqd_to_hwirq(data); + struct sgpio_port_addr addr; + + sgpio_pin_to_addr(bank->priv, gpio, &addr); + + sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit); } static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) @@ -774,6 +853,7 @@ static int microchip_sgpio_register_bank(struct device *dev, gc->of_gpio_n_cells = 3; gc->base = -1; gc->ngpio = ngpios; + gc->can_sleep = !bank->is_input; if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { int irq = fwnode_irq_get(fwnode, 0); @@ -833,6 +913,8 @@ static int microchip_sgpio_probe(struct platform_device *pdev) return -ENOMEM; priv->dev = dev; + spin_lock_init(&priv->lock); + mutex_init(&priv->poll_lock); reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); if (IS_ERR(reset)) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index fc969208d904..003fb0e34153 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -695,6 +695,98 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = { JAGUAR2_PIN(63), }; +#define SERVALT_P(p, f0, f1, f2) \ +static struct ocelot_pin_caps servalt_pin_##p = { \ + .pin = p, \ + .functions = { \ + FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \ + }, \ +} + +SERVALT_P(0, SG0, NONE, NONE); +SERVALT_P(1, SG0, NONE, NONE); +SERVALT_P(2, SG0, NONE, NONE); +SERVALT_P(3, SG0, NONE, NONE); +SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M); +SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M); +SERVALT_P(6, UART, NONE, NONE); +SERVALT_P(7, UART, NONE, NONE); +SERVALT_P(8, SI, SFP, TWI_SCL_M); +SERVALT_P(9, PCI_WAKE, SFP, SI); +SERVALT_P(10, PTP0, SFP, TWI_SCL_M); +SERVALT_P(11, PTP1, SFP, TWI_SCL_M); +SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M); +SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M); +SERVALT_P(14, REF_CLK, IRQ0_OUT, SI); +SERVALT_P(15, REF_CLK, IRQ1_OUT, SI); +SERVALT_P(16, TACHO, SFP, SI); +SERVALT_P(17, PWM, NONE, TWI_SCL_M); +SERVALT_P(18, PTP2, SFP, SI); +SERVALT_P(19, PTP3, SFP, SI); +SERVALT_P(20, UART2, SFP, SI); +SERVALT_P(21, UART2, NONE, NONE); +SERVALT_P(22, MIIM, SFP, TWI2); +SERVALT_P(23, MIIM, SFP, TWI2); +SERVALT_P(24, TWI, NONE, NONE); +SERVALT_P(25, TWI, SFP, TWI_SCL_M); +SERVALT_P(26, TWI_SCL_M, SFP, SI); +SERVALT_P(27, TWI_SCL_M, SFP, SI); +SERVALT_P(28, TWI_SCL_M, SFP, SI); +SERVALT_P(29, TWI_SCL_M, NONE, NONE); +SERVALT_P(30, TWI_SCL_M, NONE, NONE); +SERVALT_P(31, TWI_SCL_M, NONE, NONE); +SERVALT_P(32, TWI_SCL_M, NONE, NONE); +SERVALT_P(33, RCVRD_CLK, NONE, NONE); +SERVALT_P(34, RCVRD_CLK, NONE, NONE); +SERVALT_P(35, RCVRD_CLK, NONE, NONE); +SERVALT_P(36, RCVRD_CLK, NONE, NONE); + +#define SERVALT_PIN(n) { \ + .number = n, \ + .name = "GPIO_"#n, \ + .drv_data = &servalt_pin_##n \ +} + +static const struct pinctrl_pin_desc servalt_pins[] = { + SERVALT_PIN(0), + SERVALT_PIN(1), + SERVALT_PIN(2), + SERVALT_PIN(3), + SERVALT_PIN(4), + SERVALT_PIN(5), + SERVALT_PIN(6), + SERVALT_PIN(7), + SERVALT_PIN(8), + SERVALT_PIN(9), + SERVALT_PIN(10), + SERVALT_PIN(11), + SERVALT_PIN(12), + SERVALT_PIN(13), + SERVALT_PIN(14), + SERVALT_PIN(15), + SERVALT_PIN(16), + SERVALT_PIN(17), + SERVALT_PIN(18), + SERVALT_PIN(19), + SERVALT_PIN(20), + SERVALT_PIN(21), + SERVALT_PIN(22), + SERVALT_PIN(23), + SERVALT_PIN(24), + SERVALT_PIN(25), + SERVALT_PIN(26), + SERVALT_PIN(27), + SERVALT_PIN(28), + SERVALT_PIN(29), + SERVALT_PIN(30), + SERVALT_PIN(31), + SERVALT_PIN(32), + SERVALT_PIN(33), + SERVALT_PIN(34), + SERVALT_PIN(35), + SERVALT_PIN(36), +}; + #define SPARX5_P(p, f0, f1, f2) \ static struct ocelot_pin_caps sparx5_pin_##p = { \ .pin = p, \ @@ -1497,6 +1589,15 @@ static struct pinctrl_desc jaguar2_desc = { .owner = THIS_MODULE, }; +static struct pinctrl_desc servalt_desc = { + .name = "servalt-pinctrl", + .pins = servalt_pins, + .npins = ARRAY_SIZE(servalt_pins), + .pctlops = &ocelot_pctl_ops, + .pmxops = &ocelot_pmx_ops, + .owner = THIS_MODULE, +}; + static struct pinctrl_desc sparx5_desc = { .name = "sparx5-pinctrl", .pins = sparx5_pins, @@ -1750,8 +1851,8 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, gc->base = -1; gc->label = "ocelot-gpio"; - irq = irq_of_parse_and_map(gc->of_node, 0); - if (irq) { + irq = platform_get_irq_optional(pdev, 0); + if (irq > 0) { girq = &gc->irq; girq->chip = &ocelot_irqchip; girq->parent_handler = ocelot_irq_handler; @@ -1774,6 +1875,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { { .compatible = "mscc,serval-pinctrl", .data = &serval_desc }, { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc }, { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc }, + { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, {}, @@ -1788,9 +1890,10 @@ static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev) .val_bits = 32, .reg_stride = 4, .max_register = 32, + .name = "pincfg", }; - base = devm_platform_ioremap_resource(pdev, 0); + base = devm_platform_ioremap_resource(pdev, 1); if (IS_ERR(base)) { dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n"); return NULL; diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index d8dd8415fa81..a1b598b86aa9 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2693,6 +2693,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) node = of_parse_phandle(np, "rockchip,grf", 0); if (node) { info->regmap_base = syscon_node_to_regmap(node); + of_node_put(node); if (IS_ERR(info->regmap_base)) return PTR_ERR(info->regmap_base); } else { @@ -2725,6 +2726,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev) node = of_parse_phandle(np, "rockchip,pmu", 0); if (node) { info->regmap_pmu = syscon_node_to_regmap(node); + of_node_put(node); if (IS_ERR(info->regmap_pmu)) return PTR_ERR(info->regmap_pmu); } diff --git a/drivers/pinctrl/pinctrl-starfive.c b/drivers/pinctrl/pinctrl-starfive.c index ab4b2ee9f217..c586cfd09fa8 100644 --- a/drivers/pinctrl/pinctrl-starfive.c +++ b/drivers/pinctrl/pinctrl-starfive.c @@ -1026,7 +1026,7 @@ static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio, break; default: return -ENOTSUPP; - }; + } starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value); return 0; diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c index a96af8a76a7a..0e8de27d0de8 100644 --- a/drivers/pinctrl/pinctrl-zynq.c +++ b/drivers/pinctrl/pinctrl-zynq.c @@ -8,6 +8,7 @@ */ #include #include +#include #include #include #include @@ -1210,8 +1211,4 @@ static struct platform_driver zynq_pinctrl_driver = { .probe = zynq_pinctrl_probe, }; -static int __init zynq_pinctrl_init(void) -{ - return platform_driver_register(&zynq_pinctrl_driver); -} -arch_initcall(zynq_pinctrl_init); +module_platform_driver(zynq_pinctrl_driver); diff --git a/drivers/pinctrl/pxa/pinctrl-pxa27x.c b/drivers/pinctrl/pxa/pinctrl-pxa27x.c index 48ccfb50b23e..ff9302e4803a 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa27x.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa27x.c @@ -504,7 +504,7 @@ static const struct pxa_desc_pin pxa27x_pins[] = { static int pxa27x_pinctrl_probe(struct platform_device *pdev) { - int ret, i; + int i; void __iomem *base_af[8]; void __iomem *base_dir[4]; void __iomem *base_sleep[4]; @@ -532,9 +532,8 @@ static int pxa27x_pinctrl_probe(struct platform_device *pdev) for (i = 0; i < ARRAY_SIZE(base_sleep); i++) base_sleep[i] = base_sleep[0] + sizeof(base_af[0]) * i; - ret = pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins), + return pxa2xx_pinctrl_init(pdev, pxa27x_pins, ARRAY_SIZE(pxa27x_pins), base_af, base_dir, base_sleep); - return ret; } static const struct of_device_id pxa27x_pinctrl_match[] = { diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index ca6f68a061a8..c51ef54a9f61 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -248,6 +248,15 @@ config PINCTRL_SC8180X Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SC8180x platform. +config PINCTRL_SC8280XP + tristate "Qualcomm Technologies Inc SC8280xp pin controller driver" + depends on OF + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SC8280xp platform. + config PINCTRL_SDM660 tristate "Qualcomm Technologies Inc SDM660 pin controller driver" depends on OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 709882f54d25..5efbfd9f6248 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o +obj-$(CONFIG_PINCTRL_SC8280XP) += pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 780878dede9e..966ea6622ff3 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -615,6 +615,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, int drive; int pull; int val; + int egpio_enable; u32 ctl_reg, io_reg; static const char * const pulls_keeper[] = { @@ -641,12 +642,20 @@ static void msm_gpio_dbg_show_one(struct seq_file *s, func = (ctl_reg >> g->mux_bit) & 7; drive = (ctl_reg >> g->drv_bit) & 7; pull = (ctl_reg >> g->pull_bit) & 3; + egpio_enable = 0; + if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) + egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); if (is_out) val = !!(io_reg & BIT(g->out_bit)); else val = !!(io_reg & BIT(g->in_bit)); + if (egpio_enable) { + seq_printf(s, " %-8s: egpio\n", g->name); + return; + } + seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in"); seq_printf(s, " %-4s func%d", val ? "high" : "low", func); seq_printf(s, " %dmA", msm_regval_to_drive(drive)); @@ -1168,7 +1177,7 @@ static int msm_gpio_irq_set_affinity(struct irq_data *d, if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) return irq_chip_set_affinity_parent(d, dest, force); - return 0; + return -EINVAL; } static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) @@ -1179,7 +1188,7 @@ static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) return irq_chip_set_vcpu_affinity_parent(d, vcpu_info); - return 0; + return -EINVAL; } static void msm_gpio_irq_handler(struct irq_desc *desc) diff --git a/drivers/pinctrl/qcom/pinctrl-qcm2290.c b/drivers/pinctrl/qcom/pinctrl-qcm2290.c index 3f05c0a24b79..aa9325f333fb 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcm2290.c +++ b/drivers/pinctrl/qcom/pinctrl-qcm2290.c @@ -1083,6 +1083,16 @@ static const struct msm_pingroup qcm2290_groups[] = { [133] = SDC_QDSD_PINGROUP(sdc2_data, 0x86000, 9, 0), }; +static const struct msm_gpio_wakeirq_map qcm2290_mpm_map[] = { + { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, + { 13, 18 }, { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 }, + { 25, 71 }, { 27, 73 }, { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 }, + { 34, 56 }, { 35, 57 }, { 36, 58 }, { 39, 28 }, { 46, 29 }, { 62, 60 }, + { 63, 61 }, { 64, 62 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 }, + { 79, 36 }, { 80, 21 }, { 81, 38 }, { 86, 19 }, { 87, 42 }, { 88, 43 }, + { 89, 45 }, { 91, 74 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 }, +}; + static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { .pins = qcm2290_pins, .npins = ARRAY_SIZE(qcm2290_pins), @@ -1091,6 +1101,8 @@ static const struct msm_pinctrl_soc_data qcm2290_pinctrl = { .groups = qcm2290_groups, .ngroups = ARRAY_SIZE(qcm2290_groups), .ngpios = 127, + .wakeirq_map = qcm2290_mpm_map, + .nwakeirq_map = ARRAY_SIZE(qcm2290_mpm_map), }; static int qcm2290_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c index 0d9654b4ab60..6bec7f143134 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -1622,8 +1622,8 @@ static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = { }; /* - * ACPI DSDT has one single memory resource for TLMM, which voilates the - * hardware layout of 3 sepearte tiles. Let's split the memory resource into + * ACPI DSDT has one single memory resource for TLMM, which violates the + * hardware layout of 3 separate tiles. Let's split the memory resource into * 3 named ones, so that msm_pinctrl_probe() can map memory for ACPI in the * same way as for DT probe. */ diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp.c b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c new file mode 100644 index 000000000000..aa2075390f3e --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp.c @@ -0,0 +1,1953 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Linaro Ltd. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + }, \ + .nfuncs = 8, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sc8280xp_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), + PINCTRL_PIN(184, "GPIO_184"), + PINCTRL_PIN(185, "GPIO_185"), + PINCTRL_PIN(186, "GPIO_186"), + PINCTRL_PIN(187, "GPIO_187"), + PINCTRL_PIN(188, "GPIO_188"), + PINCTRL_PIN(189, "GPIO_189"), + PINCTRL_PIN(190, "GPIO_190"), + PINCTRL_PIN(191, "GPIO_191"), + PINCTRL_PIN(192, "GPIO_192"), + PINCTRL_PIN(193, "GPIO_193"), + PINCTRL_PIN(194, "GPIO_194"), + PINCTRL_PIN(195, "GPIO_195"), + PINCTRL_PIN(196, "GPIO_196"), + PINCTRL_PIN(197, "GPIO_197"), + PINCTRL_PIN(198, "GPIO_198"), + PINCTRL_PIN(199, "GPIO_199"), + PINCTRL_PIN(200, "GPIO_200"), + PINCTRL_PIN(201, "GPIO_201"), + PINCTRL_PIN(202, "GPIO_202"), + PINCTRL_PIN(203, "GPIO_203"), + PINCTRL_PIN(204, "GPIO_204"), + PINCTRL_PIN(205, "GPIO_205"), + PINCTRL_PIN(206, "GPIO_206"), + PINCTRL_PIN(207, "GPIO_207"), + PINCTRL_PIN(208, "GPIO_208"), + PINCTRL_PIN(209, "GPIO_209"), + PINCTRL_PIN(210, "GPIO_210"), + PINCTRL_PIN(211, "GPIO_211"), + PINCTRL_PIN(212, "GPIO_212"), + PINCTRL_PIN(213, "GPIO_213"), + PINCTRL_PIN(214, "GPIO_214"), + PINCTRL_PIN(215, "GPIO_215"), + PINCTRL_PIN(216, "GPIO_216"), + PINCTRL_PIN(217, "GPIO_217"), + PINCTRL_PIN(218, "GPIO_218"), + PINCTRL_PIN(219, "GPIO_219"), + PINCTRL_PIN(220, "GPIO_220"), + PINCTRL_PIN(221, "GPIO_221"), + PINCTRL_PIN(222, "GPIO_222"), + PINCTRL_PIN(223, "GPIO_223"), + PINCTRL_PIN(224, "GPIO_224"), + PINCTRL_PIN(225, "GPIO_225"), + PINCTRL_PIN(226, "GPIO_226"), + PINCTRL_PIN(227, "GPIO_227"), + PINCTRL_PIN(228, "UFS_RESET"), + PINCTRL_PIN(229, "UFS1_RESET"), + PINCTRL_PIN(230, "SDC2_CLK"), + PINCTRL_PIN(231, "SDC2_CMD"), + PINCTRL_PIN(232, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); +DECLARE_MSM_GPIO_PINS(180); +DECLARE_MSM_GPIO_PINS(181); +DECLARE_MSM_GPIO_PINS(182); +DECLARE_MSM_GPIO_PINS(183); +DECLARE_MSM_GPIO_PINS(184); +DECLARE_MSM_GPIO_PINS(185); +DECLARE_MSM_GPIO_PINS(186); +DECLARE_MSM_GPIO_PINS(187); +DECLARE_MSM_GPIO_PINS(188); +DECLARE_MSM_GPIO_PINS(189); +DECLARE_MSM_GPIO_PINS(190); +DECLARE_MSM_GPIO_PINS(191); +DECLARE_MSM_GPIO_PINS(192); +DECLARE_MSM_GPIO_PINS(193); +DECLARE_MSM_GPIO_PINS(194); +DECLARE_MSM_GPIO_PINS(195); +DECLARE_MSM_GPIO_PINS(196); +DECLARE_MSM_GPIO_PINS(197); +DECLARE_MSM_GPIO_PINS(198); +DECLARE_MSM_GPIO_PINS(199); +DECLARE_MSM_GPIO_PINS(200); +DECLARE_MSM_GPIO_PINS(201); +DECLARE_MSM_GPIO_PINS(202); +DECLARE_MSM_GPIO_PINS(203); +DECLARE_MSM_GPIO_PINS(204); +DECLARE_MSM_GPIO_PINS(205); +DECLARE_MSM_GPIO_PINS(206); +DECLARE_MSM_GPIO_PINS(207); +DECLARE_MSM_GPIO_PINS(208); +DECLARE_MSM_GPIO_PINS(209); +DECLARE_MSM_GPIO_PINS(210); +DECLARE_MSM_GPIO_PINS(211); +DECLARE_MSM_GPIO_PINS(212); +DECLARE_MSM_GPIO_PINS(213); +DECLARE_MSM_GPIO_PINS(214); +DECLARE_MSM_GPIO_PINS(215); +DECLARE_MSM_GPIO_PINS(216); +DECLARE_MSM_GPIO_PINS(217); +DECLARE_MSM_GPIO_PINS(218); +DECLARE_MSM_GPIO_PINS(219); +DECLARE_MSM_GPIO_PINS(220); +DECLARE_MSM_GPIO_PINS(221); +DECLARE_MSM_GPIO_PINS(222); +DECLARE_MSM_GPIO_PINS(223); +DECLARE_MSM_GPIO_PINS(224); +DECLARE_MSM_GPIO_PINS(225); +DECLARE_MSM_GPIO_PINS(226); +DECLARE_MSM_GPIO_PINS(227); + +static const unsigned int ufs_reset_pins[] = { 228 }; +static const unsigned int ufs1_reset_pins[] = { 229 }; +static const unsigned int sdc2_clk_pins[] = { 230 }; +static const unsigned int sdc2_cmd_pins[] = { 231 }; +static const unsigned int sdc2_data_pins[] = { 232 }; + +enum sc8280xp_functions { + msm_mux_atest_char, + msm_mux_atest_usb, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cci_timer5, + msm_mux_cci_timer6, + msm_mux_cci_timer7, + msm_mux_cci_timer8, + msm_mux_cci_timer9, + msm_mux_cmu_rng, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_ddr_pxi4, + msm_mux_ddr_pxi5, + msm_mux_ddr_pxi6, + msm_mux_ddr_pxi7, + msm_mux_dp2_hot, + msm_mux_dp3_hot, + msm_mux_edp0_lcd, + msm_mux_edp1_lcd, + msm_mux_edp2_lcd, + msm_mux_edp3_lcd, + msm_mux_edp_hot, + msm_mux_egpio, + msm_mux_emac0_dll, + msm_mux_emac0_mcg0, + msm_mux_emac0_mcg1, + msm_mux_emac0_mcg2, + msm_mux_emac0_mcg3, + msm_mux_emac0_phy, + msm_mux_emac0_ptp, + msm_mux_emac1_dll0, + msm_mux_emac1_dll1, + msm_mux_emac1_mcg0, + msm_mux_emac1_mcg1, + msm_mux_emac1_mcg2, + msm_mux_emac1_mcg3, + msm_mux_emac1_phy, + msm_mux_emac1_ptp, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gcc_gp4, + msm_mux_gcc_gp5, + msm_mux_gpio, + msm_mux_hs1_mi2s, + msm_mux_hs2_mi2s, + msm_mux_hs3_mi2s, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp0_vsync0, + msm_mux_mdp0_vsync1, + msm_mux_mdp0_vsync2, + msm_mux_mdp0_vsync3, + msm_mux_mdp0_vsync4, + msm_mux_mdp0_vsync5, + msm_mux_mdp0_vsync6, + msm_mux_mdp0_vsync7, + msm_mux_mdp0_vsync8, + msm_mux_mdp1_vsync0, + msm_mux_mdp1_vsync1, + msm_mux_mdp1_vsync2, + msm_mux_mdp1_vsync3, + msm_mux_mdp1_vsync4, + msm_mux_mdp1_vsync5, + msm_mux_mdp1_vsync6, + msm_mux_mdp1_vsync7, + msm_mux_mdp1_vsync8, + msm_mux_mdp_vsync, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_mi2s_mclk1, + msm_mux_mi2s_mclk2, + msm_mux_pcie2a_clkreq, + msm_mux_pcie2b_clkreq, + msm_mux_pcie3a_clkreq, + msm_mux_pcie3b_clkreq, + msm_mux_pcie4_clkreq, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_clk, + msm_mux_prng_rosc0, + msm_mux_prng_rosc1, + msm_mux_prng_rosc2, + msm_mux_prng_rosc3, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qspi, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup20, + msm_mux_qup21, + msm_mux_qup22, + msm_mux_qup23, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_rgmii_0, + msm_mux_rgmii_1, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_tb_trig, + msm_mux_tgu, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsense_pwm3, + msm_mux_tsense_pwm4, + msm_mux_usb0_dp, + msm_mux_usb0_phy, + msm_mux_usb0_sbrx, + msm_mux_usb0_sbtx, + msm_mux_usb0_usb4, + msm_mux_usb1_dp, + msm_mux_usb1_phy, + msm_mux_usb1_sbrx, + msm_mux_usb1_sbtx, + msm_mux_usb1_usb4, + msm_mux_usb2phy_ac, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78", + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", "gpio85", + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", + "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", + "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", + "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", + "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio123", + "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", "gpio129", + "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", "gpio135", + "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141", + "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", "gpio147", + "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", "gpio153", + "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", "gpio159", + "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", + "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", + "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", + "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", "gpio183", + "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", "gpio189", + "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", "gpio195", + "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", "gpio201", + "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", "gpio207", + "gpio208", "gpio209", "gpio210", "gpio211", "gpio212", "gpio213", + "gpio214", "gpio215", "gpio216", "gpio217", "gpio218", "gpio219", + "gpio220", "gpio221", "gpio222", "gpio223", "gpio224", "gpio225", + "gpio226", "gpio227", +}; + +static const char * const atest_char_groups[] = { + "gpio134", "gpio139", "gpio140", "gpio142", "gpio143", +}; + +static const char * const atest_usb_groups[] = { + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio78", + "gpio79", "gpio97", "gpio98", "gpio101", "gpio102", "gpio103", + "gpio104", "gpio105", "gpio110", "gpio111", "gpio112", "gpio113", + "gpio114", "gpio121", "gpio122", "gpio130", "gpio131", "gpio135", + "gpio137", "gpio138", "gpio148", "gpio149", +}; + +static const char * const audio_ref_groups[] = { + "gpio80", +}; + +static const char * const cam_mclk_groups[] = { + "gpio6", "gpio7", "gpio16", "gpio17", "gpio33", "gpio34", "gpio119", + "gpio120", +}; + +static const char * const cci_async_groups[] = { + "gpio15", "gpio119", "gpio120", "gpio160", "gpio161", "gpio167", +}; + +static const char * const cci_i2c_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio113", "gpio114", + "gpio115", "gpio116", "gpio117", "gpio118", "gpio123", "gpio124", + "gpio145", "gpio146", "gpio164", "gpio165", +}; + +static const char * const cci_timer0_groups[] = { + "gpio119", +}; + +static const char * const cci_timer1_groups[] = { + "gpio120", +}; + +static const char * const cci_timer2_groups[] = { + "gpio14", +}; + +static const char * const cci_timer3_groups[] = { + "gpio15", +}; + +static const char * const cci_timer4_groups[] = { + "gpio161", +}; + +static const char * const cci_timer5_groups[] = { + "gpio139", +}; + +static const char * const cci_timer6_groups[] = { + "gpio162", +}; + +static const char * const cci_timer7_groups[] = { + "gpio163", +}; + +static const char * const cci_timer8_groups[] = { + "gpio167", +}; + +static const char * const cci_timer9_groups[] = { + "gpio160", +}; + +static const char * const cmu_rng_groups[] = { + "gpio123", "gpio124", "gpio126", "gpio136", +}; + +static const char * const cri_trng0_groups[] = { + "gpio187", +}; + +static const char * const cri_trng1_groups[] = { + "gpio188", +}; + +static const char * const cri_trng_groups[] = { + "gpio190", +}; + +static const char * const dbg_out_groups[] = { + "gpio125", +}; + +static const char * const ddr_bist_groups[] = { + "gpio42", "gpio45", "gpio46", "gpio47", +}; + +static const char * const ddr_pxi0_groups[] = { + "gpio121", "gpio126", +}; + +static const char * const ddr_pxi1_groups[] = { + "gpio124", "gpio125", +}; + +static const char * const ddr_pxi2_groups[] = { + "gpio123", "gpio138", +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio120", "gpio137", +}; + +static const char * const ddr_pxi4_groups[] = { + "gpio216", "gpio217", +}; + +static const char * const ddr_pxi5_groups[] = { + "gpio214", "gpio215", +}; + +static const char * const ddr_pxi6_groups[] = { + "gpio79", "gpio218", +}; + +static const char * const ddr_pxi7_groups[] = { + "gpio135", "gpio136", +}; + +static const char * const dp2_hot_groups[] = { + "gpio20", +}; + +static const char * const dp3_hot_groups[] = { + "gpio45", +}; + +static const char * const edp0_lcd_groups[] = { + "gpio26", +}; + +static const char * const edp1_lcd_groups[] = { + "gpio27", +}; + +static const char * const edp2_lcd_groups[] = { + "gpio28", +}; + +static const char * const edp3_lcd_groups[] = { + "gpio29", +}; + +static const char * const edp_hot_groups[] = { + "gpio2", "gpio3", "gpio6", "gpio7", +}; + +static const char * const egpio_groups[] = { + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", "gpio210", "gpio211", "gpio212", + "gpio213", "gpio214", "gpio215", "gpio216", "gpio217", "gpio218", + "gpio219", "gpio220", "gpio221", "gpio222", "gpio223", "gpio224", + "gpio225", "gpio226", "gpio227", +}; + +static const char * const emac0_dll_groups[] = { + "gpio216", "gpio217", +}; + +static const char * const emac0_mcg0_groups[] = { + "gpio160", +}; + +static const char * const emac0_mcg1_groups[] = { + "gpio161", +}; + +static const char * const emac0_mcg2_groups[] = { + "gpio162", +}; + +static const char * const emac0_mcg3_groups[] = { + "gpio163", +}; + +static const char * const emac0_phy_groups[] = { + "gpio127", +}; + +static const char * const emac0_ptp_groups[] = { + "gpio130", "gpio130", "gpio131", "gpio131", "gpio156", "gpio156", + "gpio157", "gpio157", "gpio158", "gpio158", "gpio159", "gpio159", +}; + +static const char * const emac1_dll0_groups[] = { + "gpio215", +}; + +static const char * const emac1_dll1_groups[] = { + "gpio218", +}; + +static const char * const emac1_mcg0_groups[] = { + "gpio57", +}; + +static const char * const emac1_mcg1_groups[] = { + "gpio58", +}; + +static const char * const emac1_mcg2_groups[] = { + "gpio68", +}; + +static const char * const emac1_mcg3_groups[] = { + "gpio69", +}; + +static const char * const emac1_phy_groups[] = { + "gpio54", +}; + +static const char * const emac1_ptp_groups[] = { + "gpio55", "gpio55", "gpio56", "gpio56", "gpio93", "gpio93", "gpio94", + "gpio94", "gpio95", "gpio95", "gpio96", "gpio96", +}; + +static const char * const gcc_gp1_groups[] = { + "gpio119", "gpio149", +}; + +static const char * const gcc_gp2_groups[] = { + "gpio114", "gpio120", +}; + +static const char * const gcc_gp3_groups[] = { + "gpio115", "gpio139", +}; + +static const char * const gcc_gp4_groups[] = { + "gpio160", "gpio162", +}; + +static const char * const gcc_gp5_groups[] = { + "gpio167", "gpio168", +}; + +static const char * const hs1_mi2s_groups[] = { + "gpio208", "gpio209", "gpio210", "gpio211", +}; + +static const char * const hs2_mi2s_groups[] = { + "gpio91", "gpio92", "gpio218", "gpio219", +}; + +static const char * const hs3_mi2s_groups[] = { + "gpio224", "gpio225", "gpio226", "gpio227", +}; + +static const char * const ibi_i3c_groups[] = { + "gpio4", "gpio5", "gpio36", "gpio37", "gpio128", "gpio129", "gpio154", + "gpio155", +}; + +static const char * const jitter_bist_groups[] = { + "gpio140", +}; + +static const char * const lpass_slimbus_groups[] = { + "gpio220", "gpio221", +}; + +static const char * const mdp0_vsync0_groups[] = { + "gpio1", +}; + +static const char * const mdp0_vsync1_groups[] = { + "gpio2", +}; + +static const char * const mdp0_vsync2_groups[] = { + "gpio8", +}; + +static const char * const mdp0_vsync3_groups[] = { + "gpio9", +}; + +static const char * const mdp0_vsync4_groups[] = { + "gpio10", +}; + +static const char * const mdp0_vsync5_groups[] = { + "gpio11", +}; + +static const char * const mdp0_vsync6_groups[] = { + "gpio12", +}; + +static const char * const mdp0_vsync7_groups[] = { + "gpio13", +}; + +static const char * const mdp0_vsync8_groups[] = { + "gpio16", +}; + +static const char * const mdp1_vsync0_groups[] = { + "gpio17", +}; + +static const char * const mdp1_vsync1_groups[] = { + "gpio18", +}; + +static const char * const mdp1_vsync2_groups[] = { + "gpio19", +}; + +static const char * const mdp1_vsync3_groups[] = { + "gpio20", +}; + +static const char * const mdp1_vsync4_groups[] = { + "gpio36", +}; + +static const char * const mdp1_vsync5_groups[] = { + "gpio37", +}; + +static const char * const mdp1_vsync6_groups[] = { + "gpio38", +}; + +static const char * const mdp1_vsync7_groups[] = { + "gpio39", +}; + +static const char * const mdp1_vsync8_groups[] = { + "gpio40", +}; + +static const char * const mdp_vsync_groups[] = { + "gpio8", "gpio100", "gpio101", +}; + +static const char * const mi2s0_data0_groups[] = { + "gpio95", +}; + +static const char * const mi2s0_data1_groups[] = { + "gpio96", +}; + +static const char * const mi2s0_sck_groups[] = { + "gpio93", +}; + +static const char * const mi2s0_ws_groups[] = { + "gpio94", +}; + +static const char * const mi2s1_data0_groups[] = { + "gpio222", +}; + +static const char * const mi2s1_data1_groups[] = { + "gpio223", +}; + +static const char * const mi2s1_sck_groups[] = { + "gpio220", +}; + +static const char * const mi2s1_ws_groups[] = { + "gpio221", +}; + +static const char * const mi2s2_data0_groups[] = { + "gpio214", +}; + +static const char * const mi2s2_data1_groups[] = { + "gpio215", +}; + +static const char * const mi2s2_sck_groups[] = { + "gpio212", +}; + +static const char * const mi2s2_ws_groups[] = { + "gpio213", +}; + +static const char * const mi2s_mclk1_groups[] = { + "gpio80", "gpio216", +}; + +static const char * const mi2s_mclk2_groups[] = { + "gpio217", +}; + +static const char * const pcie2a_clkreq_groups[] = { + "gpio142", +}; + +static const char * const pcie2b_clkreq_groups[] = { + "gpio144", +}; + +static const char * const pcie3a_clkreq_groups[] = { + "gpio150", +}; + +static const char * const pcie3b_clkreq_groups[] = { + "gpio152", +}; + +static const char * const pcie4_clkreq_groups[] = { + "gpio140", +}; + +static const char * const phase_flag_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio83", "gpio87", "gpio88", "gpio89", + "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio132", + "gpio144", "gpio145", "gpio146", "gpio147", "gpio195", "gpio196", + "gpio197", "gpio198", "gpio202", "gpio219", "gpio220", "gpio221", + "gpio222", "gpio223", "gpio224", "gpio225", "gpio226", "gpio227", +}; + +static const char * const pll_bist_groups[] = { + "gpio84", +}; + +static const char * const pll_clk_groups[] = { + "gpio84", "gpio86", +}; + +static const char * const prng_rosc0_groups[] = { + "gpio189", +}; + +static const char * const prng_rosc1_groups[] = { + "gpio191", +}; + +static const char * const prng_rosc2_groups[] = { + "gpio193", +}; + +static const char * const prng_rosc3_groups[] = { + "gpio194", +}; + +static const char * const qdss_cti_groups[] = { + "gpio3", "gpio4", "gpio7", "gpio21", "gpio30", "gpio30", "gpio31", + "gpio31", +}; + +static const char * const qdss_gpio_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", + "gpio17", "gpio80", "gpio96", "gpio115", "gpio116", "gpio117", + "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", "gpio161", + "gpio162", "gpio195", "gpio196", "gpio197", "gpio198", "gpio201", + "gpio202", "gpio206", "gpio207", "gpio212", "gpio213", "gpio214", + "gpio215", "gpio216", "gpio217", "gpio222", "gpio223", +}; + +static const char * const qspi_clk_groups[] = { + "gpio74", +}; + +static const char * const qspi_cs_groups[] = { + "gpio75", "gpio81", +}; + +static const char * const qspi_groups[] = { + "gpio76", "gpio78", "gpio79", +}; + +static const char * const qup0_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const qup10_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", +}; + +static const char * const qup11_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; + +static const char * const qup12_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; + +static const char * const qup13_groups[] = { + "gpio26", "gpio27", "gpio28", "gpio29", +}; + +static const char * const qup14_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; + +static const char * const qup15_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; + +static const char * const qup16_groups[] = { + "gpio70", "gpio71", "gpio72", "gpio73", +}; + +static const char * const qup17_groups[] = { + "gpio61", "gpio62", "gpio63", "gpio64", +}; + +static const char * const qup18_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio69", +}; + +static const char * const qup19_groups[] = { + "gpio55", "gpio56", "gpio57", "gpio58", +}; + +static const char * const qup1_groups[] = { + "gpio158", "gpio159", "gpio160", "gpio161", +}; + +static const char * const qup20_groups[] = { + "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", "gpio92", "gpio110", +}; + +static const char * const qup21_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; + +static const char * const qup22_groups[] = { + "gpio83", "gpio84", "gpio85", "gpio86", +}; + +static const char * const qup23_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", +}; + +static const char * const qup2_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", +}; + +static const char * const qup3_groups[] = { + "gpio135", "gpio136", "gpio137", "gpio138", +}; + +static const char * const qup4_groups[] = { + "gpio111", "gpio112", "gpio171", "gpio172", "gpio173", "gpio174", + "gpio175", +}; + +static const char * const qup5_groups[] = { + "gpio111", "gpio112", "gpio145", "gpio146", +}; + +static const char * const qup6_groups[] = { + "gpio154", "gpio155", "gpio156", "gpio157", +}; + +static const char * const qup7_groups[] = { + "gpio125", "gpio126", "gpio128", "gpio129", +}; + +static const char * const qup8_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46", +}; + +static const char * const qup9_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; + +static const char * const rgmii_0_groups[] = { + "gpio175", "gpio176", "gpio177", "gpio178", "gpio179", "gpio180", + "gpio181", "gpio182", "gpio183", "gpio184", "gpio185", "gpio186", + "gpio187", "gpio188", +}; + +static const char * const rgmii_1_groups[] = { + "gpio97", "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", + "gpio103", "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", + "gpio109", "gpio110", +}; + +static const char * const sd_write_groups[] = { + "gpio130", +}; + +static const char * const sdc40_groups[] = { + "gpio76", +}; + +static const char * const sdc42_groups[] = { + "gpio78", +}; + +static const char * const sdc43_groups[] = { + "gpio79", +}; + +static const char * const sdc4_clk_groups[] = { + "gpio74", +}; + +static const char * const sdc4_cmd_groups[] = { + "gpio75", +}; + +static const char * const tb_trig_groups[] = { + "gpio153", "gpio157", +}; + +static const char * const tgu_groups[] = { + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", +}; + +static const char * const tsense_pwm1_groups[] = { + "gpio70", +}; + +static const char * const tsense_pwm2_groups[] = { + "gpio69", +}; + +static const char * const tsense_pwm3_groups[] = { + "gpio67", +}; + +static const char * const tsense_pwm4_groups[] = { + "gpio65", +}; + +static const char * const usb0_dp_groups[] = { + "gpio21", +}; + +static const char * const usb0_phy_groups[] = { + "gpio166", +}; + +static const char * const usb0_sbrx_groups[] = { + "gpio170", +}; + +static const char * const usb0_sbtx_groups[] = { + "gpio168", "gpio169", +}; + +static const char * const usb0_usb4_groups[] = { + "gpio132", +}; + +static const char * const usb1_dp_groups[] = { + "gpio9", +}; + +static const char * const usb1_phy_groups[] = { + "gpio49", +}; + +static const char * const usb1_sbrx_groups[] = { + "gpio53", +}; + +static const char * const usb1_sbtx_groups[] = { + "gpio51", "gpio52", +}; + +static const char * const usb1_usb4_groups[] = { + "gpio32", +}; + +static const char * const usb2phy_ac_groups[] = { + "gpio24", "gpio25", "gpio133", "gpio134", "gpio148", "gpio149", +}; + +static const char * const vsense_trigger_groups[] = { + "gpio81", +}; + +static const struct msm_function sc8280xp_functions[] = { + FUNCTION(atest_char), + FUNCTION(atest_usb), + FUNCTION(audio_ref), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cci_timer5), + FUNCTION(cci_timer6), + FUNCTION(cci_timer7), + FUNCTION(cci_timer8), + FUNCTION(cci_timer9), + FUNCTION(cmu_rng), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(ddr_pxi4), + FUNCTION(ddr_pxi5), + FUNCTION(ddr_pxi6), + FUNCTION(ddr_pxi7), + FUNCTION(dp2_hot), + FUNCTION(dp3_hot), + FUNCTION(edp0_lcd), + FUNCTION(edp1_lcd), + FUNCTION(edp2_lcd), + FUNCTION(edp3_lcd), + FUNCTION(edp_hot), + FUNCTION(egpio), + FUNCTION(emac0_dll), + FUNCTION(emac0_mcg0), + FUNCTION(emac0_mcg1), + FUNCTION(emac0_mcg2), + FUNCTION(emac0_mcg3), + FUNCTION(emac0_phy), + FUNCTION(emac0_ptp), + FUNCTION(emac1_dll0), + FUNCTION(emac1_dll1), + FUNCTION(emac1_mcg0), + FUNCTION(emac1_mcg1), + FUNCTION(emac1_mcg2), + FUNCTION(emac1_mcg3), + FUNCTION(emac1_phy), + FUNCTION(emac1_ptp), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gcc_gp4), + FUNCTION(gcc_gp5), + FUNCTION(gpio), + FUNCTION(hs1_mi2s), + FUNCTION(hs2_mi2s), + FUNCTION(hs3_mi2s), + FUNCTION(ibi_i3c), + FUNCTION(jitter_bist), + FUNCTION(lpass_slimbus), + FUNCTION(mdp0_vsync0), + FUNCTION(mdp0_vsync1), + FUNCTION(mdp0_vsync2), + FUNCTION(mdp0_vsync3), + FUNCTION(mdp0_vsync4), + FUNCTION(mdp0_vsync5), + FUNCTION(mdp0_vsync6), + FUNCTION(mdp0_vsync7), + FUNCTION(mdp0_vsync8), + FUNCTION(mdp1_vsync0), + FUNCTION(mdp1_vsync1), + FUNCTION(mdp1_vsync2), + FUNCTION(mdp1_vsync3), + FUNCTION(mdp1_vsync4), + FUNCTION(mdp1_vsync5), + FUNCTION(mdp1_vsync6), + FUNCTION(mdp1_vsync7), + FUNCTION(mdp1_vsync8), + FUNCTION(mdp_vsync), + FUNCTION(mi2s0_data0), + FUNCTION(mi2s0_data1), + FUNCTION(mi2s0_sck), + FUNCTION(mi2s0_ws), + FUNCTION(mi2s1_data0), + FUNCTION(mi2s1_data1), + FUNCTION(mi2s1_sck), + FUNCTION(mi2s1_ws), + FUNCTION(mi2s2_data0), + FUNCTION(mi2s2_data1), + FUNCTION(mi2s2_sck), + FUNCTION(mi2s2_ws), + FUNCTION(mi2s_mclk1), + FUNCTION(mi2s_mclk2), + FUNCTION(pcie2a_clkreq), + FUNCTION(pcie2b_clkreq), + FUNCTION(pcie3a_clkreq), + FUNCTION(pcie3b_clkreq), + FUNCTION(pcie4_clkreq), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_clk), + FUNCTION(prng_rosc0), + FUNCTION(prng_rosc1), + FUNCTION(prng_rosc2), + FUNCTION(prng_rosc3), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qspi), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup2), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(qup6), + FUNCTION(qup7), + FUNCTION(qup8), + FUNCTION(qup9), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup16), + FUNCTION(qup17), + FUNCTION(qup18), + FUNCTION(qup19), + FUNCTION(qup20), + FUNCTION(qup21), + FUNCTION(qup22), + FUNCTION(qup23), + FUNCTION(rgmii_0), + FUNCTION(rgmii_1), + FUNCTION(sd_write), + FUNCTION(sdc40), + FUNCTION(sdc42), + FUNCTION(sdc43), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(tb_trig), + FUNCTION(tgu), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(tsense_pwm3), + FUNCTION(tsense_pwm4), + FUNCTION(usb0_dp), + FUNCTION(usb0_phy), + FUNCTION(usb0_sbrx), + FUNCTION(usb0_sbtx), + FUNCTION(usb0_usb4), + FUNCTION(usb1_dp), + FUNCTION(usb1_phy), + FUNCTION(usb1_sbrx), + FUNCTION(usb1_sbtx), + FUNCTION(usb1_usb4), + FUNCTION(usb2phy_ac), + FUNCTION(vsense_trigger), +}; + +static const struct msm_pingroup sc8280xp_groups[] = { + [0] = PINGROUP(0, qup12, _, _, _, _, _, _), + [1] = PINGROUP(1, qup12, mdp0_vsync0, _, _, _, _, _), + [2] = PINGROUP(2, edp_hot, qup12, mdp0_vsync1, _, _, _, _), + [3] = PINGROUP(3, edp_hot, qup12, qdss_cti, _, _, _, _), + [4] = PINGROUP(4, qup14, ibi_i3c, qdss_cti, _, _, _, _), + [5] = PINGROUP(5, qup14, ibi_i3c, _, _, _, _, _), + [6] = PINGROUP(6, edp_hot, qup14, cam_mclk, _, _, _, _), + [7] = PINGROUP(7, edp_hot, qup14, qdss_cti, cam_mclk, _, _, _), + [8] = PINGROUP(8, mdp_vsync, mdp0_vsync2, _, _, _, _, _), + [9] = PINGROUP(9, usb1_dp, mdp0_vsync3, _, _, _, _, _), + [10] = PINGROUP(10, cci_i2c, mdp0_vsync4, _, qdss_gpio, _, _, _), + [11] = PINGROUP(11, cci_i2c, mdp0_vsync5, _, qdss_gpio, _, _, _), + [12] = PINGROUP(12, cci_i2c, mdp0_vsync6, _, qdss_gpio, _, _, _), + [13] = PINGROUP(13, cci_i2c, mdp0_vsync7, _, qdss_gpio, _, _, _), + [14] = PINGROUP(14, cci_timer2, qdss_gpio, _, _, _, _, _), + [15] = PINGROUP(15, cci_timer3, cci_async, _, qdss_gpio, _, _, _), + [16] = PINGROUP(16, cam_mclk, mdp0_vsync8, _, qdss_gpio, _, _, _), + [17] = PINGROUP(17, cam_mclk, mdp1_vsync0, _, qdss_gpio, _, _, _), + [18] = PINGROUP(18, qup11, mdp1_vsync1, _, _, _, _, _), + [19] = PINGROUP(19, qup11, mdp1_vsync2, _, _, _, _, _), + [20] = PINGROUP(20, qup11, dp2_hot, mdp1_vsync3, _, _, _, _), + [21] = PINGROUP(21, qup11, usb0_dp, qdss_cti, _, _, _, _), + [22] = PINGROUP(22, qup10, _, _, _, _, _, _), + [23] = PINGROUP(23, qup10, _, _, _, _, _, _), + [24] = PINGROUP(24, qup10, usb2phy_ac, _, _, _, _, _), + [25] = PINGROUP(25, qup10, usb2phy_ac, _, _, _, _, _), + [26] = PINGROUP(26, qup13, edp0_lcd, _, _, _, _, _), + [27] = PINGROUP(27, qup13, edp1_lcd, _, _, _, _, _), + [28] = PINGROUP(28, qup13, edp2_lcd, _, _, _, _, _), + [29] = PINGROUP(29, qup13, edp3_lcd, _, _, _, _, _), + [30] = PINGROUP(30, qdss_cti, qdss_cti, _, _, _, _, _), + [31] = PINGROUP(31, qdss_cti, qdss_cti, _, _, _, _, _), + [32] = PINGROUP(32, usb1_usb4, _, _, _, _, _, _), + [33] = PINGROUP(33, cam_mclk, _, _, _, _, _, _), + [34] = PINGROUP(34, cam_mclk, _, _, _, _, _, _), + [35] = PINGROUP(35, _, _, _, _, _, _, _), + [36] = PINGROUP(36, qup15, ibi_i3c, mdp1_vsync4, _, _, _, _), + [37] = PINGROUP(37, qup15, ibi_i3c, mdp1_vsync5, _, _, _, _), + [38] = PINGROUP(38, qup15, mdp1_vsync6, _, _, _, _, _), + [39] = PINGROUP(39, qup15, mdp1_vsync7, _, _, _, _, _), + [40] = PINGROUP(40, mdp1_vsync8, _, _, _, _, _, _), + [41] = PINGROUP(41, qup9, _, _, _, _, _, _), + [42] = PINGROUP(42, qup9, ddr_bist, _, _, _, _, _), + [43] = PINGROUP(43, qup8, qup9, _, _, _, _, _), + [44] = PINGROUP(44, qup8, qup9, _, _, _, _, _), + [45] = PINGROUP(45, qup8, dp3_hot, ddr_bist, _, _, _, _), + [46] = PINGROUP(46, qup8, ddr_bist, _, _, _, _, _), + [47] = PINGROUP(47, ddr_bist, _, _, _, _, _, _), + [48] = PINGROUP(48, _, _, _, _, _, _, _), + [49] = PINGROUP(49, usb1_phy, _, _, _, _, _, _), + [50] = PINGROUP(50, _, _, _, _, _, _, _), + [51] = PINGROUP(51, usb1_sbtx, _, _, _, _, _, _), + [52] = PINGROUP(52, usb1_sbtx, _, _, _, _, _, _), + [53] = PINGROUP(53, usb1_sbrx, _, _, _, _, _, _), + [54] = PINGROUP(54, emac1_phy, _, _, _, _, _, _), + [55] = PINGROUP(55, emac1_ptp, emac1_ptp, qup19, _, _, _, _), + [56] = PINGROUP(56, emac1_ptp, emac1_ptp, qup19, _, _, _, _), + [57] = PINGROUP(57, qup19, emac1_mcg0, _, _, _, _, _), + [58] = PINGROUP(58, qup19, emac1_mcg1, _, _, _, _, _), + [59] = PINGROUP(59, qup23, _, _, _, _, _, _), + [60] = PINGROUP(60, qup23, _, _, _, _, _, _), + [61] = PINGROUP(61, qup23, qup17, _, _, _, _, _), + [62] = PINGROUP(62, qup23, qup17, _, _, _, _, _), + [63] = PINGROUP(63, qup17, _, _, _, _, _, _), + [64] = PINGROUP(64, qup17, _, _, _, _, _, _), + [65] = PINGROUP(65, tsense_pwm4, _, _, _, _, _, _), + [66] = PINGROUP(66, qup18, _, _, _, _, _, _), + [67] = PINGROUP(67, qup18, tsense_pwm3, _, _, _, _, _), + [68] = PINGROUP(68, qup18, emac1_mcg2, _, _, _, _, _), + [69] = PINGROUP(69, qup18, emac1_mcg3, tsense_pwm2, _, _, _, _), + [70] = PINGROUP(70, qup16, tsense_pwm1, _, _, _, _, _), + [71] = PINGROUP(71, qup16, atest_usb, _, _, _, _, _), + [72] = PINGROUP(72, qup16, atest_usb, _, _, _, _, _), + [73] = PINGROUP(73, qup16, atest_usb, _, _, _, _, _), + [74] = PINGROUP(74, qspi_clk, sdc4_clk, atest_usb, _, _, _, _), + [75] = PINGROUP(75, qspi_cs, sdc4_cmd, atest_usb, _, _, _, _), + [76] = PINGROUP(76, qspi, sdc40, atest_usb, _, _, _, _), + [77] = PINGROUP(77, _, _, _, _, _, _, _), + [78] = PINGROUP(78, qspi, sdc42, atest_usb, _, _, _, _), + [79] = PINGROUP(79, qspi, sdc43, atest_usb, ddr_pxi6, _, _, _), + [80] = PINGROUP(80, mi2s_mclk1, audio_ref, phase_flag, _, qdss_gpio, _, _), + [81] = PINGROUP(81, qup21, qspi_cs, phase_flag, _, vsense_trigger, _, _), + [82] = PINGROUP(82, qup21, phase_flag, _, _, _, _, _), + [83] = PINGROUP(83, qup21, qup22, phase_flag, _, _, _, _), + [84] = PINGROUP(84, qup21, qup22, pll_bist, pll_clk, _, _, _), + [85] = PINGROUP(85, qup22, _, _, _, _, _, _), + [86] = PINGROUP(86, qup22, _, pll_clk, _, _, _, _), + [87] = PINGROUP(87, qup20, phase_flag, _, _, _, _, _), + [88] = PINGROUP(88, qup20, phase_flag, _, _, _, _, _), + [89] = PINGROUP(89, qup20, phase_flag, _, _, _, _, _), + [90] = PINGROUP(90, qup20, phase_flag, _, _, _, _, _), + [91] = PINGROUP(91, qup20, hs2_mi2s, phase_flag, _, _, _, _), + [92] = PINGROUP(92, qup20, hs2_mi2s, phase_flag, _, _, _, _), + [93] = PINGROUP(93, mi2s0_sck, emac1_ptp, emac1_ptp, phase_flag, _, _, _), + [94] = PINGROUP(94, mi2s0_ws, emac1_ptp, emac1_ptp, phase_flag, _, _, _), + [95] = PINGROUP(95, mi2s0_data0, emac1_ptp, emac1_ptp, phase_flag, _, _, _), + [96] = PINGROUP(96, mi2s0_data1, emac1_ptp, emac1_ptp, qdss_gpio, _, _, _), + [97] = PINGROUP(97, rgmii_1, atest_usb, _, _, _, _, _), + [98] = PINGROUP(98, rgmii_1, atest_usb, _, _, _, _, _), + [99] = PINGROUP(99, rgmii_1, _, _, _, _, _, _), + [100] = PINGROUP(100, mdp_vsync, rgmii_1, _, _, _, _, _), + [101] = PINGROUP(101, mdp_vsync, rgmii_1, tgu, atest_usb, _, _, _), + [102] = PINGROUP(102, rgmii_1, tgu, atest_usb, _, _, _, _), + [103] = PINGROUP(103, rgmii_1, tgu, atest_usb, _, _, _, _), + [104] = PINGROUP(104, rgmii_1, tgu, atest_usb, _, _, _, _), + [105] = PINGROUP(105, rgmii_1, tgu, atest_usb, _, _, _, _), + [106] = PINGROUP(106, rgmii_1, tgu, _, _, _, _, _), + [107] = PINGROUP(107, rgmii_1, tgu, _, _, _, _, _), + [108] = PINGROUP(108, rgmii_1, tgu, _, _, _, _, _), + [109] = PINGROUP(109, rgmii_1, _, _, _, _, _, _), + [110] = PINGROUP(110, qup20, rgmii_1, atest_usb, _, _, _, _), + [111] = PINGROUP(111, qup4, qup5, atest_usb, _, _, _, _), + [112] = PINGROUP(112, qup4, qup5, atest_usb, _, _, _, _), + [113] = PINGROUP(113, cci_i2c, atest_usb, _, _, _, _, _), + [114] = PINGROUP(114, cci_i2c, gcc_gp2, atest_usb, _, _, _, _), + [115] = PINGROUP(115, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _), + [116] = PINGROUP(116, cci_i2c, qdss_gpio, _, _, _, _, _), + [117] = PINGROUP(117, cci_i2c, _, qdss_gpio, _, _, _, _), + [118] = PINGROUP(118, cci_i2c, _, qdss_gpio, _, _, _, _), + [119] = PINGROUP(119, cam_mclk, cci_timer0, cci_async, gcc_gp1, qdss_gpio, _, _), + [120] = PINGROUP(120, cam_mclk, cci_timer1, cci_async, gcc_gp2, qdss_gpio, ddr_pxi3, _), + [121] = PINGROUP(121, qup2, qdss_gpio, _, atest_usb, ddr_pxi0, _, _), + [122] = PINGROUP(122, qup2, qdss_gpio, atest_usb, _, _, _, _), + [123] = PINGROUP(123, qup2, cci_i2c, cmu_rng, ddr_pxi2, _, _, _), + [124] = PINGROUP(124, qup2, cci_i2c, cmu_rng, ddr_pxi1, _, _, _), + [125] = PINGROUP(125, qup7, dbg_out, ddr_pxi1, _, _, _, _), + [126] = PINGROUP(126, qup7, cmu_rng, ddr_pxi0, _, _, _, _), + [127] = PINGROUP(127, emac0_phy, _, _, _, _, _, _), + [128] = PINGROUP(128, qup7, ibi_i3c, _, _, _, _, _), + [129] = PINGROUP(129, qup7, ibi_i3c, _, _, _, _, _), + [130] = PINGROUP(130, emac0_ptp, emac0_ptp, sd_write, atest_usb, _, _, _), + [131] = PINGROUP(131, emac0_ptp, emac0_ptp, atest_usb, _, _, _, _), + [132] = PINGROUP(132, usb0_usb4, phase_flag, _, _, _, _, _), + [133] = PINGROUP(133, usb2phy_ac, _, _, _, _, _, _), + [134] = PINGROUP(134, usb2phy_ac, atest_char, _, _, _, _, _), + [135] = PINGROUP(135, qup0, qup3, _, atest_usb, ddr_pxi7, _, _), + [136] = PINGROUP(136, qup0, qup3, cmu_rng, ddr_pxi7, _, _, _), + [137] = PINGROUP(137, qup3, qup0, _, atest_usb, ddr_pxi3, _, _), + [138] = PINGROUP(138, qup3, qup0, _, atest_usb, ddr_pxi2, _, _), + [139] = PINGROUP(139, cci_timer5, gcc_gp3, atest_char, _, _, _, _), + [140] = PINGROUP(140, pcie4_clkreq, jitter_bist, atest_char, _, _, _, _), + [141] = PINGROUP(141, _, _, _, _, _, _, _), + [142] = PINGROUP(142, pcie2a_clkreq, atest_char, _, _, _, _, _), + [143] = PINGROUP(143, _, atest_char, _, _, _, _, _), + [144] = PINGROUP(144, pcie2b_clkreq, phase_flag, _, _, _, _, _), + [145] = PINGROUP(145, qup5, cci_i2c, phase_flag, _, _, _, _), + [146] = PINGROUP(146, qup5, cci_i2c, phase_flag, _, _, _, _), + [147] = PINGROUP(147, _, phase_flag, _, _, _, _, _), + [148] = PINGROUP(148, usb2phy_ac, _, atest_usb, _, _, _, _), + [149] = PINGROUP(149, usb2phy_ac, gcc_gp1, atest_usb, _, _, _, _), + [150] = PINGROUP(150, pcie3a_clkreq, _, _, _, _, _, _), + [151] = PINGROUP(151, _, _, _, _, _, _, _), + [152] = PINGROUP(152, pcie3b_clkreq, _, _, _, _, _, _), + [153] = PINGROUP(153, _, tb_trig, _, _, _, _, _), + [154] = PINGROUP(154, qup6, ibi_i3c, _, _, _, _, _), + [155] = PINGROUP(155, qup6, ibi_i3c, _, _, _, _, _), + [156] = PINGROUP(156, qup6, emac0_ptp, emac0_ptp, _, _, _, _), + [157] = PINGROUP(157, qup6, emac0_ptp, emac0_ptp, tb_trig, _, _, _), + [158] = PINGROUP(158, qup1, emac0_ptp, emac0_ptp, _, _, _, _), + [159] = PINGROUP(159, qup1, emac0_ptp, emac0_ptp, _, _, _, _), + [160] = PINGROUP(160, cci_timer9, qup1, cci_async, emac0_mcg0, gcc_gp4, _, _), + [161] = PINGROUP(161, cci_timer4, cci_async, qup1, emac0_mcg1, qdss_gpio, _, _), + [162] = PINGROUP(162, cci_timer6, emac0_mcg2, gcc_gp4, qdss_gpio, _, _, _), + [163] = PINGROUP(163, cci_timer7, emac0_mcg3, _, _, _, _, _), + [164] = PINGROUP(164, cci_i2c, _, _, _, _, _, _), + [165] = PINGROUP(165, cci_i2c, _, _, _, _, _, _), + [166] = PINGROUP(166, usb0_phy, _, _, _, _, _, _), + [167] = PINGROUP(167, cci_timer8, cci_async, gcc_gp5, _, _, _, _), + [168] = PINGROUP(168, usb0_sbtx, gcc_gp5, _, _, _, _, _), + [169] = PINGROUP(169, usb0_sbtx, _, _, _, _, _, _), + [170] = PINGROUP(170, usb0_sbrx, _, _, _, _, _, _), + [171] = PINGROUP(171, qup4, _, _, _, _, _, _), + [172] = PINGROUP(172, qup4, _, _, _, _, _, _), + [173] = PINGROUP(173, qup4, _, _, _, _, _, _), + [174] = PINGROUP(174, qup4, _, _, _, _, _, _), + [175] = PINGROUP(175, qup4, rgmii_0, _, _, _, _, _), + [176] = PINGROUP(176, rgmii_0, _, _, _, _, _, _), + [177] = PINGROUP(177, rgmii_0, _, _, _, _, _, _), + [178] = PINGROUP(178, rgmii_0, _, _, _, _, _, _), + [179] = PINGROUP(179, rgmii_0, _, _, _, _, _, _), + [180] = PINGROUP(180, rgmii_0, _, _, _, _, _, _), + [181] = PINGROUP(181, rgmii_0, _, _, _, _, _, _), + [182] = PINGROUP(182, rgmii_0, _, _, _, _, _, _), + [183] = PINGROUP(183, rgmii_0, _, _, _, _, _, _), + [184] = PINGROUP(184, rgmii_0, _, _, _, _, _, _), + [185] = PINGROUP(185, rgmii_0, _, _, _, _, _, _), + [186] = PINGROUP(186, rgmii_0, _, _, _, _, _, _), + [187] = PINGROUP(187, rgmii_0, cri_trng0, _, _, _, _, _), + [188] = PINGROUP(188, rgmii_0, cri_trng1, _, _, _, _, _), + [189] = PINGROUP(189, prng_rosc0, _, _, _, _, _, egpio), + [190] = PINGROUP(190, cri_trng, _, _, _, _, _, egpio), + [191] = PINGROUP(191, prng_rosc1, _, _, _, _, _, egpio), + [192] = PINGROUP(192, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, prng_rosc2, _, _, _, _, _, egpio), + [194] = PINGROUP(194, prng_rosc3, _, _, _, _, _, egpio), + [195] = PINGROUP(195, phase_flag, _, qdss_gpio, _, _, _, egpio), + [196] = PINGROUP(196, phase_flag, _, qdss_gpio, _, _, _, egpio), + [197] = PINGROUP(197, phase_flag, _, qdss_gpio, _, _, _, egpio), + [198] = PINGROUP(198, phase_flag, _, qdss_gpio, _, _, _, egpio), + [199] = PINGROUP(199, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, qdss_gpio, _, _, _, _, _, egpio), + [202] = PINGROUP(202, phase_flag, _, qdss_gpio, _, _, _, egpio), + [203] = PINGROUP(203, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, qdss_gpio, _, _, _, _, _, egpio), + [207] = PINGROUP(207, qdss_gpio, _, _, _, _, _, egpio), + [208] = PINGROUP(208, hs1_mi2s, _, _, _, _, _, egpio), + [209] = PINGROUP(209, hs1_mi2s, _, _, _, _, _, egpio), + [210] = PINGROUP(210, hs1_mi2s, _, _, _, _, _, egpio), + [211] = PINGROUP(211, hs1_mi2s, _, _, _, _, _, egpio), + [212] = PINGROUP(212, mi2s2_sck, qdss_gpio, _, _, _, _, egpio), + [213] = PINGROUP(213, mi2s2_ws, qdss_gpio, _, _, _, _, egpio), + [214] = PINGROUP(214, mi2s2_data0, qdss_gpio, ddr_pxi5, _, _, _, egpio), + [215] = PINGROUP(215, mi2s2_data1, qdss_gpio, emac1_dll0, ddr_pxi5, _, _, egpio), + [216] = PINGROUP(216, mi2s_mclk1, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio), + [217] = PINGROUP(217, mi2s_mclk2, qdss_gpio, emac0_dll, ddr_pxi4, _, _, egpio), + [218] = PINGROUP(218, hs2_mi2s, emac1_dll1, ddr_pxi6, _, _, _, egpio), + [219] = PINGROUP(219, hs2_mi2s, phase_flag, _, _, _, _, egpio), + [220] = PINGROUP(220, lpass_slimbus, mi2s1_sck, phase_flag, _, _, _, egpio), + [221] = PINGROUP(221, lpass_slimbus, mi2s1_ws, phase_flag, _, _, _, egpio), + [222] = PINGROUP(222, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, egpio), + [223] = PINGROUP(223, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, egpio), + [224] = PINGROUP(224, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [225] = PINGROUP(225, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [226] = PINGROUP(226, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [227] = PINGROUP(227, hs3_mi2s, phase_flag, _, _, _, _, egpio), + [228] = UFS_RESET(ufs_reset, 0xf1004), + [229] = UFS_RESET(ufs1_reset, 0xf3004), + [230] = SDC_QDSD_PINGROUP(sdc2_clk, 0xe8000, 14, 6), + [231] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xe8000, 11, 3), + [232] = SDC_QDSD_PINGROUP(sdc2_data, 0xe8000, 9, 0), +}; + +static const struct msm_gpio_wakeirq_map sc8280xp_pdc_map[] = { + { 3, 245 }, { 4, 263 }, { 7, 254 }, { 21, 220 }, { 25, 244 }, + { 26, 211 }, { 27, 172 }, { 29, 203 }, { 30, 169 }, { 31, 180 }, + { 32, 181 }, { 33, 182 }, { 36, 206 }, { 39, 246 }, { 40, 183 }, + { 42, 179 }, { 46, 247 }, { 53, 248 }, { 54, 190 }, { 55, 249 }, + { 56, 250 }, { 58, 251 }, { 59, 207 }, { 62, 252 }, { 63, 191 }, + { 64, 192 }, { 65, 193 }, { 69, 253 }, { 73, 255 }, { 84, 256 }, + { 85, 208 }, { 90, 257 }, { 102, 214 }, { 103, 215 }, { 104, 216 }, + { 107, 217 }, { 110, 218 }, { 124, 224 }, { 125, 189 }, + { 126, 200 }, { 127, 225 }, { 128, 262 }, { 129, 201 }, + { 130, 209 }, { 131, 173 }, { 132, 202 }, { 136, 210 }, + { 138, 171 }, { 139, 226 }, { 140, 227 }, { 142, 228 }, + { 144, 229 }, { 145, 230 }, { 146, 231 }, { 148, 232 }, + { 149, 233 }, { 150, 234 }, { 152, 235 }, { 154, 212 }, + { 157, 213 }, { 161, 219 }, { 170, 236 }, { 171, 221 }, + { 174, 222 }, { 175, 237 }, { 176, 223 }, { 177, 170 }, + { 180, 238 }, { 181, 239 }, { 182, 240 }, { 183, 241 }, + { 184, 242 }, { 185, 243 }, { 190, 178 }, { 193, 184 }, + { 196, 185 }, { 198, 186 }, { 200, 174 }, { 201, 175 }, + { 205, 176 }, { 206, 177 }, { 208, 187 }, { 210, 198 }, + { 211, 199 }, { 212, 204 }, { 215, 205 }, { 220, 188 }, + { 221, 194 }, { 223, 195 }, { 225, 196 }, { 227, 197 }, +}; + +static struct msm_pinctrl_soc_data sc8280xp_pinctrl = { + .pins = sc8280xp_pins, + .npins = ARRAY_SIZE(sc8280xp_pins), + .functions = sc8280xp_functions, + .nfunctions = ARRAY_SIZE(sc8280xp_functions), + .groups = sc8280xp_groups, + .ngroups = ARRAY_SIZE(sc8280xp_groups), + .ngpios = 230, + .wakeirq_map = sc8280xp_pdc_map, + .nwakeirq_map = ARRAY_SIZE(sc8280xp_pdc_map), + .egpio_func = 7, +}; + +static int sc8280xp_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sc8280xp_pinctrl); +} + +static const struct of_device_id sc8280xp_pinctrl_of_match[] = { + { .compatible = "qcom,sc8280xp-tlmm", }, + { }, +}; +MODULE_DEVICE_TABLE(of, sc8280xp_pinctrl_of_match); + +static struct platform_driver sc8280xp_pinctrl_driver = { + .driver = { + .name = "sc8280xp-tlmm", + .of_match_table = sc8280xp_pinctrl_of_match, + }, + .probe = sc8280xp_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sc8280xp_pinctrl_init(void) +{ + return platform_driver_register(&sc8280xp_pinctrl_driver); +} +arch_initcall(sc8280xp_pinctrl_init); + +static void __exit sc8280xp_pinctrl_exit(void) +{ + platform_driver_unregister(&sc8280xp_pinctrl_driver); +} +module_exit(sc8280xp_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm SC8280XP TLMM pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c index 724fa5a34465..170d4ffbb919 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6125.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -1,4 +1,4 @@ -//SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) #include #include diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450.c b/drivers/pinctrl/qcom/pinctrl-sm8450.c index c6fa3dbc14a1..3110d7bf5698 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450.c @@ -46,6 +46,8 @@ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ + .egpio_enable = 12, \ + .egpio_present = 11, \ .oe_bit = 9, \ .in_bit = 0, \ .out_bit = 1, \ @@ -567,6 +569,7 @@ enum sm8450_functions { msm_mux_ddr_pxi2, msm_mux_ddr_pxi3, msm_mux_dp_hot, + msm_mux_egpio, msm_mux_gcc_gp1, msm_mux_gcc_gp2, msm_mux_gcc_gp3, @@ -719,6 +722,17 @@ static const char * const gpio_groups[] = { "gpio207", "gpio208", "gpio209", }; +static const char * const egpio_groups[] = { + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182", + "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188", + "gpio189", "gpio190", "gpio191", "gpio192", "gpio193", "gpio194", + "gpio195", "gpio196", "gpio197", "gpio198", "gpio199", "gpio200", + "gpio201", "gpio202", "gpio203", "gpio204", "gpio205", "gpio206", + "gpio207", "gpio208", "gpio209", +}; + static const char * const aon_cam_groups[] = { "gpio108", }; @@ -1285,6 +1299,7 @@ static const struct msm_function sm8450_functions[] = { FUNCTION(ddr_pxi2), FUNCTION(ddr_pxi3), FUNCTION(dp_hot), + FUNCTION(egpio), FUNCTION(gcc_gp1), FUNCTION(gcc_gp2), FUNCTION(gcc_gp3), @@ -1571,51 +1586,51 @@ static const struct msm_pingroup sm8450_groups[] = { [162] = PINGROUP(162, qlink2_request, _, _, _, _, _, _, _, _), [163] = PINGROUP(163, qlink2_enable, _, _, _, _, _, _, _, _), [164] = PINGROUP(164, qlink2_wmss, _, _, _, _, _, _, _, _), - [165] = PINGROUP(165, _, _, _, _, _, _, _, _, _), - [166] = PINGROUP(166, _, _, _, _, _, _, _, _, _), - [167] = PINGROUP(167, _, _, _, _, _, _, _, _, _), - [168] = PINGROUP(168, _, _, _, _, _, _, _, _, _), - [169] = PINGROUP(169, _, _, _, _, _, _, _, _, _), - [170] = PINGROUP(170, _, _, _, _, _, _, _, _, _), - [171] = PINGROUP(171, _, _, _, _, _, _, _, _, _), - [172] = PINGROUP(172, _, _, _, _, _, _, _, _, _), - [173] = PINGROUP(173, _, _, _, _, _, _, _, _, _), - [174] = PINGROUP(174, _, _, _, _, _, _, _, _, _), - [175] = PINGROUP(175, _, _, _, _, _, _, _, _, _), - [176] = PINGROUP(176, _, _, _, _, _, _, _, _, _), - [177] = PINGROUP(177, _, _, _, _, _, _, _, _, _), - [178] = PINGROUP(178, _, _, _, _, _, _, _, _, _), - [179] = PINGROUP(179, _, _, _, _, _, _, _, _, _), - [180] = PINGROUP(180, _, _, _, _, _, _, _, _, _), - [181] = PINGROUP(181, _, _, _, _, _, _, _, _, _), - [182] = PINGROUP(182, _, _, _, _, _, _, _, _, _), - [183] = PINGROUP(183, _, _, _, _, _, _, _, _, _), - [184] = PINGROUP(184, _, _, _, _, _, _, _, _, _), - [185] = PINGROUP(185, _, _, _, _, _, _, _, _, _), - [186] = PINGROUP(186, _, _, _, _, _, _, _, _, _), - [187] = PINGROUP(187, _, _, _, _, _, _, _, _, _), - [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, _), - [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, _), - [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, _), - [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, _), - [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, _), - [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, _), - [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, _), - [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, _), - [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, _), - [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, _), - [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, _), - [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, _), - [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, _), - [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, _), - [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, _), - [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, _), - [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, _), - [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, _), - [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, _), - [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, _), - [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, _), - [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, _, _, _, _, _, _, _, _, egpio), + [166] = PINGROUP(166, _, _, _, _, _, _, _, _, egpio), + [167] = PINGROUP(167, _, _, _, _, _, _, _, _, egpio), + [168] = PINGROUP(168, _, _, _, _, _, _, _, _, egpio), + [169] = PINGROUP(169, _, _, _, _, _, _, _, _, egpio), + [170] = PINGROUP(170, _, _, _, _, _, _, _, _, egpio), + [171] = PINGROUP(171, _, _, _, _, _, _, _, _, egpio), + [172] = PINGROUP(172, _, _, _, _, _, _, _, _, egpio), + [173] = PINGROUP(173, _, _, _, _, _, _, _, _, egpio), + [174] = PINGROUP(174, _, _, _, _, _, _, _, _, egpio), + [175] = PINGROUP(175, _, _, _, _, _, _, _, _, egpio), + [176] = PINGROUP(176, _, _, _, _, _, _, _, _, egpio), + [177] = PINGROUP(177, _, _, _, _, _, _, _, _, egpio), + [178] = PINGROUP(178, _, _, _, _, _, _, _, _, egpio), + [179] = PINGROUP(179, _, _, _, _, _, _, _, _, egpio), + [180] = PINGROUP(180, _, _, _, _, _, _, _, _, egpio), + [181] = PINGROUP(181, _, _, _, _, _, _, _, _, egpio), + [182] = PINGROUP(182, _, _, _, _, _, _, _, _, egpio), + [183] = PINGROUP(183, _, _, _, _, _, _, _, _, egpio), + [184] = PINGROUP(184, _, _, _, _, _, _, _, _, egpio), + [185] = PINGROUP(185, _, _, _, _, _, _, _, _, egpio), + [186] = PINGROUP(186, _, _, _, _, _, _, _, _, egpio), + [187] = PINGROUP(187, _, _, _, _, _, _, _, _, egpio), + [188] = PINGROUP(188, _, qdss_gpio, _, _, _, _, _, _, egpio), + [189] = PINGROUP(189, _, qdss_gpio, _, _, _, _, _, _, egpio), + [190] = PINGROUP(190, qdss_gpio, _, _, _, _, _, _, _, egpio), + [191] = PINGROUP(191, qdss_gpio, _, _, _, _, _, _, _, egpio), + [192] = PINGROUP(192, _, qdss_gpio, _, _, _, _, _, _, egpio), + [193] = PINGROUP(193, _, qdss_gpio, _, _, _, _, _, _, egpio), + [194] = PINGROUP(194, _, qdss_gpio, _, _, _, _, _, _, egpio), + [195] = PINGROUP(195, _, qdss_gpio, _, _, _, _, _, _, egpio), + [196] = PINGROUP(196, _, qdss_gpio, _, _, _, _, _, _, egpio), + [197] = PINGROUP(197, _, qdss_gpio, _, _, _, _, _, _, egpio), + [198] = PINGROUP(198, _, qdss_gpio, _, _, _, _, _, _, egpio), + [199] = PINGROUP(199, _, qdss_gpio, _, _, _, _, _, _, egpio), + [200] = PINGROUP(200, _, qdss_gpio, _, _, _, _, _, _, egpio), + [201] = PINGROUP(201, _, qdss_gpio, _, _, _, _, _, _, egpio), + [202] = PINGROUP(202, qdss_gpio, _, _, _, _, _, _, _, egpio), + [203] = PINGROUP(203, qdss_gpio, _, _, _, _, _, _, _, egpio), + [204] = PINGROUP(204, qdss_gpio, _, _, _, _, _, _, _, egpio), + [205] = PINGROUP(205, qdss_gpio, _, _, _, _, _, _, _, egpio), + [206] = PINGROUP(206, qup5, _, _, _, _, _, _, _, egpio), + [207] = PINGROUP(207, qup5, _, _, _, _, _, _, _, egpio), + [208] = PINGROUP(208, cci_i2c, _, _, _, _, _, _, _, egpio), + [209] = PINGROUP(209, cci_i2c, _, _, _, _, _, _, _, egpio), [210] = UFS_RESET(ufs_reset, 0xde000), [211] = SDC_QDSD_PINGROUP(sdc2_clk, 0xd6000, 14, 6), [212] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xd6000, 11, 3), @@ -1651,6 +1666,7 @@ static const struct msm_pinctrl_soc_data sm8450_tlmm = { .ngpios = 211, .wakeirq_map = sm8450_pdc_map, .nwakeirq_map = ARRAY_SIZE(sm8450_pdc_map), + .egpio_func = 9, }; static int sm8450_tlmm_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index f2eac3b05d67..4fbf8d3938ef 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1164,6 +1164,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 }, { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, + { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 }, /* pm8950 has 8 GPIOs with holes on 3 */ diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index b80723928b7e..6937157f50b3 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -961,6 +961,7 @@ static int pmic_mpp_remove(struct platform_device *pdev) static const struct of_device_id pmic_mpp_of_match[] = { { .compatible = "qcom,pm8019-mpp", .data = (void *) 6 }, + { .compatible = "qcom,pm8226-mpp", .data = (void *) 8 }, { .compatible = "qcom,pm8841-mpp", .data = (void *) 4 }, { .compatible = "qcom,pm8916-mpp", .data = (void *) 4 }, { .compatible = "qcom,pm8941-mpp", .data = (void *) 8 }, diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 9a72999084b3..6b38720c56e3 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -37,7 +37,9 @@ config PINCTRL_RENESAS select PINCTRL_PFC_R8A77990 if ARCH_R8A77990 select PINCTRL_PFC_R8A77995 if ARCH_R8A77995 select PINCTRL_PFC_R8A779A0 if ARCH_R8A779A0 + select PINCTRL_PFC_R8A779F0 if ARCH_R8A779F0 select PINCTRL_RZG2L if ARCH_R9A07G044 + select PINCTRL_RZG2L if ARCH_R9A07G054 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 select PINCTRL_PFC_SH7269 if CPU_SUBTYPE_SH7269 @@ -132,6 +134,10 @@ config PINCTRL_PFC_R8A77961 bool "pin control support for R-Car M3-W+" if COMPILE_TEST select PINCTRL_SH_PFC +config PINCTRL_PFC_R8A779F0 + bool "pin control support for R-Car S4-8" if COMPILE_TEST + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7792 bool "pin control support for R-Car V2H" if COMPILE_TEST select PINCTRL_SH_PFC @@ -178,14 +184,15 @@ config PINCTRL_RZA2 This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. config PINCTRL_RZG2L - bool "pin control support for RZ/G2L" if COMPILE_TEST + bool "pin control support for RZ/{G2L,V2L}" if COMPILE_TEST depends on OF select GPIOLIB select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help - This selects GPIO and pinctrl driver for Renesas RZ/G2L platforms. + This selects GPIO and pinctrl driver for Renesas RZ/{G2L,V2L} + platforms. config PINCTRL_PFC_R8A77470 bool "pin control support for RZ/G1C" if COMPILE_TEST diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 7d9238a9ef57..5d936c154a6f 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o obj-$(CONFIG_PINCTRL_PFC_R8A77990) += pfc-r8a77990.o obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o +obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o diff --git a/drivers/pinctrl/renesas/core.c b/drivers/pinctrl/renesas/core.c index 0d4ea2e22a53..d0d4714731c1 100644 --- a/drivers/pinctrl/renesas/core.c +++ b/drivers/pinctrl/renesas/core.c @@ -636,6 +636,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a779a0_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A779F0 + { + .compatible = "renesas,pfc-r8a779f0", + .data = &r8a779f0_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_SH73A0 { .compatible = "renesas,pfc-sh73a0", @@ -741,10 +747,13 @@ static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; } #ifdef DEBUG #define SH_PFC_MAX_REGS 300 -#define SH_PFC_MAX_ENUMS 3000 +#define SH_PFC_MAX_ENUMS 5000 static unsigned int sh_pfc_errors __initdata; static unsigned int sh_pfc_warnings __initdata; +static bool sh_pfc_bias_done __initdata; +static bool sh_pfc_drive_done __initdata; +static bool sh_pfc_power_done __initdata; static struct { u32 reg; u32 bits; @@ -758,6 +767,15 @@ static u32 sh_pfc_num_enums __initdata; pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \ sh_pfc_errors++; \ } while (0) + +#define sh_pfc_err_once(type, fmt, ...) \ + do { \ + if (!sh_pfc_ ## type ## _done) { \ + sh_pfc_ ## type ## _done = true; \ + sh_pfc_err(fmt, ##__VA_ARGS__); \ + } \ + } while (0) + #define sh_pfc_warn(fmt, ...) \ do { \ pr_warn("%s: " fmt, drvname, ##__VA_ARGS__); \ @@ -777,10 +795,7 @@ static bool __init is0s(const u16 *enum_ids, unsigned int n) static bool __init same_name(const char *a, const char *b) { - if (!a || !b) - return false; - - return !strcmp(a, b); + return a && b && !strcmp(a, b); } static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits) @@ -839,21 +854,22 @@ static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg, } } -static void __init sh_pfc_check_pin(const struct sh_pfc_soc_info *info, - u32 reg, unsigned int pin) +static const struct sh_pfc_pin __init *sh_pfc_find_pin( + const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin) { const char *drvname = info->name; unsigned int i; if (pin == SH_PFC_PIN_NONE) - return; + return NULL; for (i = 0; i < info->nr_pins; i++) { if (pin == info->pins[i].pin) - return; + return &info->pins[i]; } sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin); + return NULL; } static void __init sh_pfc_check_cfg_reg(const char *drvname, @@ -865,7 +881,8 @@ static void __init sh_pfc_check_cfg_reg(const char *drvname, GENMASK(cfg_reg->reg_width - 1, 0)); if (cfg_reg->field_width) { - n = cfg_reg->reg_width / cfg_reg->field_width; + fw = cfg_reg->field_width; + n = (cfg_reg->reg_width / fw) << fw; /* Skip field checks (done at build time) */ goto check_enum_ids; } @@ -893,6 +910,8 @@ check_enum_ids: static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, const struct pinmux_drive_reg *drive) { + const char *drvname = info->name; + const struct sh_pfc_pin *pin; unsigned int i; for (i = 0; i < ARRAY_SIZE(drive->fields); i++) { @@ -905,13 +924,18 @@ static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info, GENMASK(field->offset + field->size - 1, field->offset)); - sh_pfc_check_pin(info, drive->reg, field->pin); + pin = sh_pfc_find_pin(info, drive->reg, field->pin); + if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH)) + sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n", + drive->reg, i, pin->name); } } static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, const struct pinmux_bias_reg *bias) { + const char *drvname = info->name; + const struct sh_pfc_pin *pin; unsigned int i; u32 bits; @@ -923,12 +947,66 @@ static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info, sh_pfc_check_reg(info->name, bias->puen, bits); if (bias->pud) sh_pfc_check_reg(info->name, bias->pud, bits); - for (i = 0; i < ARRAY_SIZE(bias->pins); i++) - sh_pfc_check_pin(info, bias->puen, bias->pins[i]); + for (i = 0; i < ARRAY_SIZE(bias->pins); i++) { + pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]); + if (!pin) + continue; + + if (bias->puen && bias->pud) { + /* + * Pull-enable and pull-up/down control registers + * As some SoCs have pins that support only pull-up + * or pull-down, we just check for one of them + */ + if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN)) + sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n", + bias->puen, i, pin->name); + } else if (bias->puen) { + /* Pull-up control register only */ + if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP)) + sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n", + bias->puen, i, pin->name); + } else if (bias->pud) { + /* Pull-down control register only */ + if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN)) + sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n", + bias->pud, i, pin->name); + } + } +} + +static void __init sh_pfc_compare_groups(const char *drvname, + const struct sh_pfc_pin_group *a, + const struct sh_pfc_pin_group *b) +{ + unsigned int i; + size_t len; + + if (same_name(a->name, b->name)) + sh_pfc_err("group %s: name conflict\n", a->name); + + if (a->nr_pins > b->nr_pins) + swap(a, b); + + len = a->nr_pins * sizeof(a->pins[0]); + for (i = 0; i <= b->nr_pins - a->nr_pins; i++) { + if (a->pins == b->pins + i || a->mux == b->mux + i || + memcmp(a->pins, b->pins + i, len) || + memcmp(a->mux, b->mux + i, len)) + continue; + + if (a->nr_pins == b->nr_pins) + sh_pfc_warn("group %s can be an alias for %s\n", + a->name, b->name); + else + sh_pfc_warn("group %s is a subset of %s\n", a->name, + b->name); + } } static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) { + const struct pinmux_drive_reg *drive_regs = info->drive_regs; const struct pinmux_bias_reg *bias_regs = info->bias_regs; const char *drvname = info->name; unsigned int *refcnts; @@ -937,10 +1015,14 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) pr_info("sh_pfc: Checking %s\n", drvname); sh_pfc_num_regs = 0; sh_pfc_num_enums = 0; + sh_pfc_bias_done = false; + sh_pfc_drive_done = false; + sh_pfc_power_done = false; /* Check pins */ for (i = 0; i < info->nr_pins; i++) { const struct sh_pfc_pin *pin = &info->pins[i]; + unsigned int x; if (!pin->name) { sh_pfc_err("empty pin %u\n", i); @@ -962,6 +1044,65 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) pin->name, pin2->name, pin->enum_id); } + + if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) { + if (!info->ops || !info->ops->get_bias || + !info->ops->set_bias) + sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n"); + + if (!bias_regs && + (!info->ops || !info->ops->pin_to_portcr)) + sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n"); + } + + if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) { + const struct pinmux_bias_reg *bias_reg = + rcar_pin_to_bias_reg(info, pin->pin, &x); + + if (!bias_reg || + ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) && + !bias_reg->puen)) + sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n", + pin->name); + + if (!bias_reg || + ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) && + !bias_reg->pud)) + sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n", + pin->name); + } + + if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) { + if (!drive_regs) { + sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n"); + } else { + for (j = 0; drive_regs[j / 8].reg; j++) { + if (!drive_regs[j / 8].fields[j % 8].pin && + !drive_regs[j / 8].fields[j % 8].offset && + !drive_regs[j / 8].fields[j % 8].size) + continue; + + if (drive_regs[j / 8].fields[j % 8].pin == pin->pin) + break; + } + + if (!drive_regs[j / 8].reg) + sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n", + pin->name); + } + } + + if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) { + if (!info->ops || !info->ops->pin_to_pocctrl) + sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n"); + else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0) + sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n", + pin->name); + } else if (info->ops && info->ops->pin_to_pocctrl && + info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) { + sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n", + pin->name); + } } /* Check groups and functions */ @@ -1003,11 +1144,9 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) sh_pfc_err("empty group %u\n", i); continue; } - for (j = 0; j < i; j++) { - if (same_name(group->name, info->groups[j].name)) - sh_pfc_err("group %s: name conflict\n", - group->name); - } + for (j = 0; j < i; j++) + sh_pfc_compare_groups(drvname, group, &info->groups[j]); + if (!refcnts[i]) sh_pfc_err("orphan group %s\n", group->name); else if (refcnts[i] > 1) @@ -1022,13 +1161,53 @@ static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info) sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]); /* Check drive strength registers */ - for (i = 0; info->drive_regs && info->drive_regs[i].reg; i++) - sh_pfc_check_drive_reg(info, &info->drive_regs[i]); + for (i = 0; drive_regs && drive_regs[i].reg; i++) + sh_pfc_check_drive_reg(info, &drive_regs[i]); + + for (i = 0; drive_regs && drive_regs[i / 8].reg; i++) { + if (!drive_regs[i / 8].fields[i % 8].pin && + !drive_regs[i / 8].fields[i % 8].offset && + !drive_regs[i / 8].fields[i % 8].size) + continue; + + for (j = 0; j < i; j++) { + if (drive_regs[i / 8].fields[i % 8].pin == + drive_regs[j / 8].fields[j % 8].pin && + drive_regs[j / 8].fields[j % 8].offset && + drive_regs[j / 8].fields[j % 8].size) { + sh_pfc_err("drive_reg 0x%x:%u/0x%x:%u: pin conflict\n", + drive_regs[i / 8].reg, i % 8, + drive_regs[j / 8].reg, j % 8); + } + } + } /* Check bias registers */ for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++) sh_pfc_check_bias_reg(info, &bias_regs[i]); + for (i = 0; bias_regs && + (bias_regs[i / 32].puen || bias_regs[i / 32].pud); i++) { + if (bias_regs[i / 32].pins[i % 32] == SH_PFC_PIN_NONE) + continue; + + for (j = 0; j < i; j++) { + if (bias_regs[i / 32].pins[i % 32] != + bias_regs[j / 32].pins[j % 32]) + continue; + + if (bias_regs[i / 32].puen && bias_regs[j / 32].puen) + sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", + bias_regs[i / 32].puen, i % 32, + bias_regs[j / 32].puen, j % 32); + if (bias_regs[i / 32].pud && bias_regs[j / 32].pud) + sh_pfc_err("bias_reg 0x%x:%u/0x%x:%u: pin conflict\n", + bias_regs[i / 32].pud, i % 32, + bias_regs[j / 32].pud, j % 32); + } + + } + /* Check ioctrl registers */ for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++) sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX); diff --git a/drivers/pinctrl/renesas/pfc-emev2.c b/drivers/pinctrl/renesas/pfc-emev2.c index 6c66fc335d2f..2326d348447d 100644 --- a/drivers/pinctrl/renesas/pfc-emev2.c +++ b/drivers/pinctrl/renesas/pfc-emev2.c @@ -749,23 +749,14 @@ static const unsigned int cf_ctrl_mux[] = { CF_CDB2_MARK, }; -static const unsigned int cf_data8_pins[] = { - /* CF_D[0:7] */ - 77, 78, 79, 80, - 81, 82, 83, 84, -}; -static const unsigned int cf_data8_mux[] = { - CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK, - CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK, -}; -static const unsigned int cf_data16_pins[] = { +static const unsigned int cf_data_pins[] = { /* CF_D[0:15] */ 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, }; -static const unsigned int cf_data16_mux[] = { +static const unsigned int cf_data_mux[] = { CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK, CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK, CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK, @@ -895,26 +886,12 @@ static const unsigned int sdi0_ctrl_mux[] = { SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK, }; -static const unsigned int sdi0_data1_pins[] = { - /* SDI0_DATA[0] */ - 53, -}; -static const unsigned int sdi0_data1_mux[] = { - SDI0_DATA0_MARK, -}; -static const unsigned int sdi0_data4_pins[] = { - /* SDI0_DATA[0:3] */ - 53, 54, 55, 56, -}; -static const unsigned int sdi0_data4_mux[] = { - SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK, -}; -static const unsigned int sdi0_data8_pins[] = { +static const unsigned int sdi0_data_pins[] = { /* SDI0_DATA[0:7] */ 53, 54, 55, 56, 57, 58, 59, 60 }; -static const unsigned int sdi0_data8_mux[] = { +static const unsigned int sdi0_data_mux[] = { SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK, }; @@ -928,18 +905,11 @@ static const unsigned int sdi1_ctrl_mux[] = { SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK, }; -static const unsigned int sdi1_data1_pins[] = { - /* SDI1_DATA[0] */ - 64, -}; -static const unsigned int sdi1_data1_mux[] = { - SDI1_DATA0_MARK, -}; -static const unsigned int sdi1_data4_pins[] = { +static const unsigned int sdi1_data_pins[] = { /* SDI1_DATA[0:3] */ 64, 65, 66, 67, }; -static const unsigned int sdi1_data4_mux[] = { +static const unsigned int sdi1_data_mux[] = { SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK, }; @@ -952,18 +922,11 @@ static const unsigned int sdi2_ctrl_mux[] = { SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK, }; -static const unsigned int sdi2_data1_pins[] = { - /* SDI2_DATA[0] */ - 89, -}; -static const unsigned int sdi2_data1_mux[] = { - SDI2_DATA0_MARK, -}; -static const unsigned int sdi2_data4_pins[] = { +static const unsigned int sdi2_data_pins[] = { /* SDI2_DATA[0:3] */ 89, 90, 91, 92, }; -static const unsigned int sdi2_data4_mux[] = { +static const unsigned int sdi2_data_mux[] = { SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK, }; @@ -1131,8 +1094,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(cam), SH_PFC_PIN_GROUP(cf_ctrl), - SH_PFC_PIN_GROUP(cf_data8), - SH_PFC_PIN_GROUP(cf_data16), + BUS_DATA_PIN_GROUP(cf_data, 8), + BUS_DATA_PIN_GROUP(cf_data, 16), SH_PFC_PIN_GROUP(dtv_a), SH_PFC_PIN_GROUP(dtv_b), @@ -1161,17 +1124,17 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sd_cki), SH_PFC_PIN_GROUP(sdi0_ctrl), - SH_PFC_PIN_GROUP(sdi0_data1), - SH_PFC_PIN_GROUP(sdi0_data4), - SH_PFC_PIN_GROUP(sdi0_data8), + BUS_DATA_PIN_GROUP(sdi0_data, 1), + BUS_DATA_PIN_GROUP(sdi0_data, 4), + BUS_DATA_PIN_GROUP(sdi0_data, 8), SH_PFC_PIN_GROUP(sdi1_ctrl), - SH_PFC_PIN_GROUP(sdi1_data1), - SH_PFC_PIN_GROUP(sdi1_data4), + BUS_DATA_PIN_GROUP(sdi1_data, 1), + BUS_DATA_PIN_GROUP(sdi1_data, 4), SH_PFC_PIN_GROUP(sdi2_ctrl), - SH_PFC_PIN_GROUP(sdi2_data1), - SH_PFC_PIN_GROUP(sdi2_data4), + BUS_DATA_PIN_GROUP(sdi2_data, 1), + BUS_DATA_PIN_GROUP(sdi2_data, 4), SH_PFC_PIN_GROUP(tp33), diff --git a/drivers/pinctrl/renesas/pfc-r8a73a4.c b/drivers/pinctrl/renesas/pfc-r8a73a4.c index b26ff9d6ead4..ba3a1857f80a 100644 --- a/drivers/pinctrl/renesas/pfc-r8a73a4.c +++ b/drivers/pinctrl/renesas/pfc-r8a73a4.c @@ -1449,25 +1449,11 @@ IRQC_PINS_MUX(327, 55); IRQC_PINS_MUX(328, 56); IRQC_PINS_MUX(329, 57); /* - MMCIF0 ----------------------------------------------------------------- */ -static const unsigned int mmc0_data1_pins[] = { - /* D[0] */ - 164, -}; -static const unsigned int mmc0_data1_mux[] = { - MMCD0_0_MARK, -}; -static const unsigned int mmc0_data4_pins[] = { - /* D[0:3] */ - 164, 165, 166, 167, -}; -static const unsigned int mmc0_data4_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, -}; -static const unsigned int mmc0_data8_pins[] = { +static const unsigned int mmc0_data_pins[] = { /* D[0:7] */ 164, 165, 166, 167, 168, 169, 170, 171, }; -static const unsigned int mmc0_data8_mux[] = { +static const unsigned int mmc0_data_mux[] = { MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, }; @@ -1479,25 +1465,11 @@ static const unsigned int mmc0_ctrl_mux[] = { MMCCMD0_MARK, MMCCLK0_MARK, }; /* - MMCIF1 ----------------------------------------------------------------- */ -static const unsigned int mmc1_data1_pins[] = { - /* D[0] */ - 199, -}; -static const unsigned int mmc1_data1_mux[] = { - MMCD1_0_MARK, -}; -static const unsigned int mmc1_data4_pins[] = { - /* D[0:3] */ - 199, 198, 197, 196, -}; -static const unsigned int mmc1_data4_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, -}; -static const unsigned int mmc1_data8_pins[] = { +static const unsigned int mmc1_data_pins[] = { /* D[0:7] */ 199, 198, 197, 196, 195, 194, 193, 192, }; -static const unsigned int mmc1_data8_mux[] = { +static const unsigned int mmc1_data_mux[] = { MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, }; @@ -1704,18 +1676,11 @@ static const unsigned int scifb3_ctrl_b_mux[] = { SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 302, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHID0_0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ 302, 303, 304, 305, }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -1740,18 +1705,11 @@ static const unsigned int sdhi0_wp_mux[] = { SDHIWP0_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 289, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHID1_0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ 289, 290, 291, 292, }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -1762,18 +1720,11 @@ static const unsigned int sdhi1_ctrl_mux[] = { SDHICLK1_MARK, SDHICMD1_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 295, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHID2_0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ 295, 296, 297, 298, }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -1843,13 +1794,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(irqc_irq55), SH_PFC_PIN_GROUP(irqc_irq56), SH_PFC_PIN_GROUP(irqc_irq57), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), + BUS_DATA_PIN_GROUP(mmc0_data, 1), + BUS_DATA_PIN_GROUP(mmc0_data, 4), + BUS_DATA_PIN_GROUP(mmc0_data, 8), SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), + BUS_DATA_PIN_GROUP(mmc1_data, 1), + BUS_DATA_PIN_GROUP(mmc1_data, 4), + BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), SH_PFC_PIN_GROUP(scifa0_data), SH_PFC_PIN_GROUP(scifa0_clk), @@ -1878,16 +1829,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb3_data_b), SH_PFC_PIN_GROUP(scifb3_clk_b), SH_PFC_PIN_GROUP(scifb3_ctrl_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), }; @@ -2655,9 +2606,9 @@ static const unsigned int r8a73a4_portcr_offsets[] = { 0x00002000, 0x00003000, 0x00003000, }; -static void __iomem *r8a73a4_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) +static int r8a73a4_pin_to_portcr(unsigned int pin) { - return pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; + return r8a73a4_portcr_offsets[pin >> 5] + pin; } static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a7740.c b/drivers/pinctrl/renesas/pfc-r8a7740.c index 4eac3899d69b..e8b9fb74a802 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7740.c +++ b/drivers/pinctrl/renesas/pfc-r8a7740.c @@ -1638,33 +1638,14 @@ static const struct sh_pfc_pin pinmux_pins[] = { }; /* - BSC -------------------------------------------------------------------- */ -static const unsigned int bsc_data8_pins[] = { - /* D[0:7] */ - 157, 156, 155, 154, 153, 152, 151, 150, -}; -static const unsigned int bsc_data8_mux[] = { - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, - D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, -}; -static const unsigned int bsc_data16_pins[] = { - /* D[0:15] */ - 157, 156, 155, 154, 153, 152, 151, 150, - 149, 148, 147, 146, 145, 144, 143, 142, -}; -static const unsigned int bsc_data16_mux[] = { - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, - D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, - D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, - D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK, -}; -static const unsigned int bsc_data32_pins[] = { +static const unsigned int bsc_data_pins[] = { /* D[0:31] */ 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, 145, 144, 143, 142, 171, 170, 169, 168, 167, 166, 173, 172, 165, 164, 163, 162, 161, 160, 159, 158, }; -static const unsigned int bsc_data32_mux[] = { +static const unsigned int bsc_data_mux[] = { D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, @@ -1723,25 +1704,11 @@ static const unsigned int bsc_cs6a_pins[] = { static const unsigned int bsc_cs6a_mux[] = { CS6A_MARK, }; -static const unsigned int bsc_rd_we8_pins[] = { - /* RD, WE[0] */ - 115, 113, -}; -static const unsigned int bsc_rd_we8_mux[] = { - RD_FSC_MARK, WE0_FWE_MARK, -}; -static const unsigned int bsc_rd_we16_pins[] = { - /* RD, WE[0:1] */ - 115, 113, 112, -}; -static const unsigned int bsc_rd_we16_mux[] = { - RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, -}; -static const unsigned int bsc_rd_we32_pins[] = { +static const unsigned int bsc_rd_we_pins[] = { /* RD, WE[0:3] */ 115, 113, 112, 108, 107, }; -static const unsigned int bsc_rd_we32_mux[] = { +static const unsigned int bsc_rd_we_mux[] = { RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK, }; static const unsigned int bsc_bs_pins[] = { @@ -2064,58 +2031,6 @@ IRQC_PINS_MUX(31, 0, 41); IRQC_PINS_MUX(31, 1, 167); /* - LCD0 ------------------------------------------------------------------- */ -static const unsigned int lcd0_data8_pins[] = { - /* D[0:7] */ - 58, 57, 56, 55, 54, 53, 52, 51, -}; -static const unsigned int lcd0_data8_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, -}; -static const unsigned int lcd0_data9_pins[] = { - /* D[0:8] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, -}; -static const unsigned int lcd0_data9_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, -}; -static const unsigned int lcd0_data12_pins[] = { - /* D[0:11] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, -}; -static const unsigned int lcd0_data12_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, -}; -static const unsigned int lcd0_data16_pins[] = { - /* D[0:15] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, 46, 45, 44, 43, -}; -static const unsigned int lcd0_data16_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, - LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, -}; -static const unsigned int lcd0_data18_pins[] = { - /* D[0:17] */ - 58, 57, 56, 55, 54, 53, 52, 51, - 50, 49, 48, 47, 46, 45, 44, 43, - 42, 41, -}; -static const unsigned int lcd0_data18_mux[] = { - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, - LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, - LCD0_D16_MARK, LCD0_D17_MARK, -}; static const unsigned int lcd0_data24_0_pins[] = { /* D[0:23] */ 58, 57, 56, 55, 54, 53, 52, 51, @@ -2182,65 +2097,13 @@ static const unsigned int lcd0_sys_mux[] = { LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK, }; /* - LCD1 ------------------------------------------------------------------- */ -static const unsigned int lcd1_data8_pins[] = { - /* D[0:7] */ - 4, 3, 2, 1, 0, 91, 92, 23, -}; -static const unsigned int lcd1_data8_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, -}; -static const unsigned int lcd1_data9_pins[] = { - /* D[0:8] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, -}; -static const unsigned int lcd1_data9_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, -}; -static const unsigned int lcd1_data12_pins[] = { - /* D[0:11] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, -}; -static const unsigned int lcd1_data12_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, -}; -static const unsigned int lcd1_data16_pins[] = { - /* D[0:15] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, 200, 199, 196, 195, -}; -static const unsigned int lcd1_data16_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, - LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, -}; -static const unsigned int lcd1_data18_pins[] = { - /* D[0:17] */ - 4, 3, 2, 1, 0, 91, 92, 23, - 93, 94, 21, 201, 200, 199, 196, 195, - 194, 193, -}; -static const unsigned int lcd1_data18_mux[] = { - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, - LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, - LCD1_D16_MARK, LCD1_D17_MARK, -}; -static const unsigned int lcd1_data24_pins[] = { +static const unsigned int lcd1_data_pins[] = { /* D[0:23] */ 4, 3, 2, 1, 0, 91, 92, 23, 93, 94, 21, 201, 200, 199, 196, 195, 194, 193, 198, 197, 75, 74, 15, 14, }; -static const unsigned int lcd1_data24_mux[] = { +static const unsigned int lcd1_data_mux[] = { LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, @@ -2277,25 +2140,11 @@ static const unsigned int lcd1_sys_mux[] = { LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK, }; /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_0_pins[] = { - /* D[0] */ - 68, -}; -static const unsigned int mmc0_data1_0_mux[] = { - MMC0_D0_PORT68_MARK, -}; -static const unsigned int mmc0_data4_0_pins[] = { - /* D[0:3] */ - 68, 69, 70, 71, -}; -static const unsigned int mmc0_data4_0_mux[] = { - MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, -}; -static const unsigned int mmc0_data8_0_pins[] = { +static const unsigned int mmc0_data_0_pins[] = { /* D[0:7] */ 68, 69, 70, 71, 72, 73, 74, 75, }; -static const unsigned int mmc0_data8_0_mux[] = { +static const unsigned int mmc0_data_0_mux[] = { MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, }; @@ -2307,25 +2156,11 @@ static const unsigned int mmc0_ctrl_0_mux[] = { MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK, }; -static const unsigned int mmc0_data1_1_pins[] = { - /* D[0] */ - 149, -}; -static const unsigned int mmc0_data1_1_mux[] = { - MMC1_D0_PORT149_MARK, -}; -static const unsigned int mmc0_data4_1_pins[] = { - /* D[0:3] */ - 149, 148, 147, 146, -}; -static const unsigned int mmc0_data4_1_mux[] = { - MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, -}; -static const unsigned int mmc0_data8_1_pins[] = { +static const unsigned int mmc0_data_1_pins[] = { /* D[0:7] */ 149, 148, 147, 146, 145, 144, 143, 142, }; -static const unsigned int mmc0_data8_1_mux[] = { +static const unsigned int mmc0_data_1_mux[] = { MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, }; @@ -2591,18 +2426,11 @@ static const unsigned int scifb_ctrl_1_mux[] = { SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 77, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHI0_D0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ 77, 78, 79, 80, }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -2627,18 +2455,11 @@ static const unsigned int sdhi0_wp_mux[] = { SDHI0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 68, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHI1_D0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ 68, 69, 70, 71, }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -2663,18 +2484,11 @@ static const unsigned int sdhi1_wp_mux[] = { SDHI1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 205, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHI2_D0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ 205, 206, 207, 208, }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -2750,9 +2564,9 @@ static const unsigned int tpu0_to3_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(bsc_data8), - SH_PFC_PIN_GROUP(bsc_data16), - SH_PFC_PIN_GROUP(bsc_data32), + BUS_DATA_PIN_GROUP(bsc_data, 8), + BUS_DATA_PIN_GROUP(bsc_data, 16), + BUS_DATA_PIN_GROUP(bsc_data, 32), SH_PFC_PIN_GROUP(bsc_cs0), SH_PFC_PIN_GROUP(bsc_cs2), SH_PFC_PIN_GROUP(bsc_cs4), @@ -2760,9 +2574,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(bsc_cs5a_1), SH_PFC_PIN_GROUP(bsc_cs5b), SH_PFC_PIN_GROUP(bsc_cs6a), - SH_PFC_PIN_GROUP(bsc_rd_we8), - SH_PFC_PIN_GROUP(bsc_rd_we16), - SH_PFC_PIN_GROUP(bsc_rd_we32), + SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we8, bsc_rd_we, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we16, bsc_rd_we, 0, 3), + SH_PFC_PIN_GROUP_SUBSET(bsc_rd_we32, bsc_rd_we, 0, 5), SH_PFC_PIN_GROUP(bsc_bs), SH_PFC_PIN_GROUP(bsc_rdwr), SH_PFC_PIN_GROUP(ceu0_data_0_7), @@ -2847,11 +2661,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq30_1), SH_PFC_PIN_GROUP(intc_irq31_0), SH_PFC_PIN_GROUP(intc_irq31_1), - SH_PFC_PIN_GROUP(lcd0_data8), - SH_PFC_PIN_GROUP(lcd0_data9), - SH_PFC_PIN_GROUP(lcd0_data12), - SH_PFC_PIN_GROUP(lcd0_data16), - SH_PFC_PIN_GROUP(lcd0_data18), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data8, lcd0_data24_0, 0, 8), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data9, lcd0_data24_0, 0, 9), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data12, lcd0_data24_0, 0, 12), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data16, lcd0_data24_0, 0, 16), + SH_PFC_PIN_GROUP_SUBSET(lcd0_data18, lcd0_data24_0, 0, 18), SH_PFC_PIN_GROUP(lcd0_data24_0), SH_PFC_PIN_GROUP(lcd0_data24_1), SH_PFC_PIN_GROUP(lcd0_display), @@ -2859,23 +2673,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lcd0_lclk_1), SH_PFC_PIN_GROUP(lcd0_sync), SH_PFC_PIN_GROUP(lcd0_sys), - SH_PFC_PIN_GROUP(lcd1_data8), - SH_PFC_PIN_GROUP(lcd1_data9), - SH_PFC_PIN_GROUP(lcd1_data12), - SH_PFC_PIN_GROUP(lcd1_data16), - SH_PFC_PIN_GROUP(lcd1_data18), - SH_PFC_PIN_GROUP(lcd1_data24), + BUS_DATA_PIN_GROUP(lcd1_data, 8), + BUS_DATA_PIN_GROUP(lcd1_data, 9), + BUS_DATA_PIN_GROUP(lcd1_data, 12), + BUS_DATA_PIN_GROUP(lcd1_data, 16), + BUS_DATA_PIN_GROUP(lcd1_data, 18), + BUS_DATA_PIN_GROUP(lcd1_data, 24), SH_PFC_PIN_GROUP(lcd1_display), SH_PFC_PIN_GROUP(lcd1_lclk), SH_PFC_PIN_GROUP(lcd1_sync), SH_PFC_PIN_GROUP(lcd1_sys), - SH_PFC_PIN_GROUP(mmc0_data1_0), - SH_PFC_PIN_GROUP(mmc0_data4_0), - SH_PFC_PIN_GROUP(mmc0_data8_0), + BUS_DATA_PIN_GROUP(mmc0_data, 1, _0), + BUS_DATA_PIN_GROUP(mmc0_data, 4, _0), + BUS_DATA_PIN_GROUP(mmc0_data, 8, _0), SH_PFC_PIN_GROUP(mmc0_ctrl_0), - SH_PFC_PIN_GROUP(mmc0_data1_1), - SH_PFC_PIN_GROUP(mmc0_data4_1), - SH_PFC_PIN_GROUP(mmc0_data8_1), + BUS_DATA_PIN_GROUP(mmc0_data, 1, _1), + BUS_DATA_PIN_GROUP(mmc0_data, 4, _1), + BUS_DATA_PIN_GROUP(mmc0_data, 8, _1), SH_PFC_PIN_GROUP(mmc0_ctrl_1), SH_PFC_PIN_GROUP(scifa0_data), SH_PFC_PIN_GROUP(scifa0_clk), @@ -2912,18 +2726,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb_data_1), SH_PFC_PIN_GROUP(scifb_clk_1), SH_PFC_PIN_GROUP(scifb_ctrl_1), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_0), SH_PFC_PIN_GROUP(sdhi2_wp_0), @@ -3681,7 +3495,7 @@ static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = { { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 }, }; -static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) +static int r8a7740_pin_to_portcr(unsigned int pin) { unsigned int i; @@ -3690,10 +3504,10 @@ static void __iomem *r8a7740_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) &r8a7740_portcr_offsets[i]; if (pin <= group->end_pin) - return pfc->windows->virt + group->offset + pin; + return group->offset + pin; } - return NULL; + return -1; } static const struct sh_pfc_soc_operations r8a7740_pfc_ops = { diff --git a/drivers/pinctrl/renesas/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c index e6e5487691c1..ee6e8fabab24 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77470.c +++ b/drivers/pinctrl/renesas/pfc-r8a77470.c @@ -1595,30 +1595,14 @@ static const unsigned int i2c4_e_mux[] = { SCL4_E_MARK, SDA4_E_MARK, }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(0, 15), -}; -static const unsigned int mmc_data1_mux[] = { - MMC0_D0_SDHI1_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), - RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), -}; -static const unsigned int mmc_data4_mux[] = { - MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, - MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D4_MARK, MMC0_D5_MARK, @@ -1639,19 +1623,12 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -1662,19 +1639,12 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -1917,19 +1887,12 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(0, 7), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -1954,29 +1917,6 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(0, 15), -}; -static const unsigned int sdhi1_data1_mux[] = { - MMC0_D0_SDHI1_D0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), - RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), -}; -static const unsigned int sdhi1_data4_mux[] = { - MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, - MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, -}; -static const unsigned int sdhi1_ctrl_pins[] = { - /* CLK, CMD */ - RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), -}; -static const unsigned int sdhi1_ctrl_mux[] = { - MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK, -}; static const unsigned int sdhi1_cd_pins[] = { /* CD */ RCAR_GP_PIN(0, 19), @@ -1992,19 +1932,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 16), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -2047,43 +1980,39 @@ static const unsigned int usb1_mux[] = { USB1_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), - RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), - RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), - RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), - /* G */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), - RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8), - RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), - /* R */ - RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), - RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), - RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), - RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), + RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), + RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), + RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), + /* G */ + RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), + /* R */ + RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12), + RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -2140,25 +2069,21 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), - RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), - RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), - RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), - RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), - RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), }; -static const union vin_data vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { RCAR_GP_PIN(3, 11), /* HSYNC */ @@ -2243,16 +2168,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c4_c), SH_PFC_PIN_GROUP(i2c4_d), SH_PFC_PIN_GROUP(i2c4_e), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -2286,37 +2211,37 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_f), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP_SUBSET(sdhi1_data1, mmc_data, 0, 1), + SH_PFC_PIN_GROUP_SUBSET(sdhi1_data4, mmc_data, 0, 4), + SH_PFC_PIN_GROUP_ALIAS(sdhi1_ctrl, mmc_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -3420,8 +3345,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77470_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -3683,7 +3607,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ } }; -static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77470_pfc_ops = { .pin_to_pocctrl = r8a77470_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -3692,7 +3616,7 @@ static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A77470 const struct sh_pfc_soc_info r8a77470_pinmux_info = { .name = "r8a77470_pfc", - .ops = &r8a77470_pinmux_ops, + .ops = &r8a77470_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index d641e408f1bd..a24672ca3c01 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -1427,25 +1427,17 @@ I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); /* - MMC macro -------------------------------------------------------------- */ #define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args) #define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) -#define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) -#define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) /* - MMC -------------------------------------------------------------------- */ MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); -MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); -MMC_PFC_DAT1(mmc_data1, MMC_D0); -MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), - RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); -MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, - MMC_D2, MMC_D3); -MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), +MMC_PFC_PINS(mmc_data, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); -MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1, +MMC_PFC_DAT8(mmc_data, MMC_D0, MMC_D1, MMC_D2, MMC_D3, MMC_D4, MMC_D5, MMC_D6, MMC_D7); @@ -1530,7 +1522,6 @@ SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); /* - SDHI macro ------------------------------------------------------------- */ #define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) -#define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) #define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) #define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) #define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd) @@ -1541,11 +1532,9 @@ SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17)); SDHI_PFC_CDPN(sdhi0_cd, SD0_CD); SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12)); SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD); -SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13)); -SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0); -SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), +SDHI_PFC_PINS(sdhi0_data, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16)); -SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1, +SDHI_PFC_DAT4(sdhi0_data, SD0_DAT0, SD0_DAT1, SD0_DAT2, SD0_DAT3); SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18)); SDHI_PFC_WPPN(sdhi0_wp, SD0_WP); @@ -1559,17 +1548,13 @@ SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A); SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B); -SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7)); -SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A); -SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18)); -SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B); -SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), +SDHI_PFC_PINS(sdhi1_data_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); -SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A, +SDHI_PFC_DAT4(sdhi1_data_a, SD1_DAT0_A, SD1_DAT1_A, SD1_DAT2_A, SD1_DAT3_A); -SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), +SDHI_PFC_PINS(sdhi1_data_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); -SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B, +SDHI_PFC_DAT4(sdhi1_data_b, SD1_DAT0_B, SD1_DAT1_B, SD1_DAT2_B, SD1_DAT3_B); SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31)); SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A); @@ -1585,17 +1570,13 @@ SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A); SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B); -SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19)); -SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A); -SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7)); -SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B); -SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), +SDHI_PFC_PINS(sdhi2_data_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22)); -SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A, +SDHI_PFC_DAT4(sdhi2_data_a, SD2_DAT0_A, SD2_DAT1_A, SD2_DAT2_A, SD2_DAT3_A); -SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), +SDHI_PFC_PINS(sdhi2_data_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26)); -SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B, +SDHI_PFC_DAT4(sdhi2_data_b, SD2_DAT0_B, SD2_DAT1_B, SD2_DAT2_B, SD2_DAT3_B); SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24)); SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A); @@ -1744,9 +1725,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3_b), SH_PFC_PIN_GROUP(i2c3_c), SH_PFC_PIN_GROUP(mmc_ctrl), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_data_b), @@ -1781,27 +1762,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_data_b), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_wp), SH_PFC_PIN_GROUP(sdhi1_cd_a), SH_PFC_PIN_GROUP(sdhi1_cd_b), SH_PFC_PIN_GROUP(sdhi1_ctrl_a), SH_PFC_PIN_GROUP(sdhi1_ctrl_b), - SH_PFC_PIN_GROUP(sdhi1_data1_a), - SH_PFC_PIN_GROUP(sdhi1_data1_b), - SH_PFC_PIN_GROUP(sdhi1_data4_a), - SH_PFC_PIN_GROUP(sdhi1_data4_b), + BUS_DATA_PIN_GROUP(sdhi1_data, 1, _a), + BUS_DATA_PIN_GROUP(sdhi1_data, 1, _b), + BUS_DATA_PIN_GROUP(sdhi1_data, 4, _a), + BUS_DATA_PIN_GROUP(sdhi1_data, 4, _b), SH_PFC_PIN_GROUP(sdhi1_wp_a), SH_PFC_PIN_GROUP(sdhi1_wp_b), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_ctrl_a), SH_PFC_PIN_GROUP(sdhi2_ctrl_b), - SH_PFC_PIN_GROUP(sdhi2_data1_a), - SH_PFC_PIN_GROUP(sdhi2_data1_b), - SH_PFC_PIN_GROUP(sdhi2_data4_a), - SH_PFC_PIN_GROUP(sdhi2_data4_b), + BUS_DATA_PIN_GROUP(sdhi2_data, 1, _a), + BUS_DATA_PIN_GROUP(sdhi2_data, 1, _b), + BUS_DATA_PIN_GROUP(sdhi2_data, 4, _a), + BUS_DATA_PIN_GROUP(sdhi2_data, 4, _b), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(ssi012_ctrl), diff --git a/drivers/pinctrl/renesas/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c index 3e47cdc1411d..296b5fb0f349 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7779.c +++ b/drivers/pinctrl/renesas/pfc-r8a7779.c @@ -1928,28 +1928,13 @@ static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_MARK, }; /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(0, 19), -}; -static const unsigned int mmc0_data1_mux[] = { - MMC0_D0_MARK, -}; -static const unsigned int mmc0_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), - RCAR_GP_PIN(0, 2), -}; -static const unsigned int mmc0_data4_mux[] = { - MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, -}; -static const unsigned int mmc0_data8_pins[] = { +static const unsigned int mmc0_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), }; -static const unsigned int mmc0_data8_mux[] = { +static const unsigned int mmc0_data_mux[] = { MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, }; @@ -1960,28 +1945,13 @@ static const unsigned int mmc0_ctrl_pins[] = { static const unsigned int mmc0_ctrl_mux[] = { MMC0_CMD_MARK, MMC0_CLK_MARK, }; -static const unsigned int mmc1_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(2, 8), -}; -static const unsigned int mmc1_data1_mux[] = { - MMC1_D0_MARK, -}; -static const unsigned int mmc1_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), - RCAR_GP_PIN(2, 11), -}; -static const unsigned int mmc1_data4_mux[] = { - MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, -}; -static const unsigned int mmc1_data8_pins[] = { +static const unsigned int mmc1_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), }; -static const unsigned int mmc1_data8_mux[] = { +static const unsigned int mmc1_data_mux[] = { MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, }; @@ -2386,19 +2356,12 @@ static const unsigned int scif_clk_d_mux[] = { SCIF_CLK_D_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 21), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -2423,19 +2386,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(0, 19), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 2), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -2460,19 +2416,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 1), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -2497,19 +2446,12 @@ static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(1, 18), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), }; -static const unsigned int sdhi3_data4_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, }; static const unsigned int sdhi3_ctrl_pins[] = { @@ -2749,13 +2691,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lbsc_ex_cs3), SH_PFC_PIN_GROUP(lbsc_ex_cs4), SH_PFC_PIN_GROUP(lbsc_ex_cs5), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), + BUS_DATA_PIN_GROUP(mmc0_data, 1), + BUS_DATA_PIN_GROUP(mmc0_data, 4), + BUS_DATA_PIN_GROUP(mmc0_data, 8), SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), + BUS_DATA_PIN_GROUP(mmc1_data, 1), + BUS_DATA_PIN_GROUP(mmc1_data, 4), + BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), @@ -2812,23 +2754,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif_clk_b), SH_PFC_PIN_GROUP(scif_clk_c), SH_PFC_PIN_GROUP(scif_clk_d), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -3133,10 +3075,6 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(lbsc), SH_PFC_FUNCTION(mmc0), SH_PFC_FUNCTION(mmc1), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -3144,6 +3082,10 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(scif4), SH_PFC_FUNCTION(scif5), SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), SH_PFC_FUNCTION(usb0), SH_PFC_FUNCTION(usb1), SH_PFC_FUNCTION(usb2), diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index 08c0a23edf68..9db9e61d96bc 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -194,24 +194,24 @@ enum { FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, - FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_WE0_N, FN_IECLK, FN_CAN_CLK, FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, - FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, FN_SSI_WS78_B, /* IPSR6 */ - FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, - FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_SSI_WS6_B, FN_SSI_SDATA8_C, FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, - FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, @@ -568,23 +568,23 @@ enum { CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, - INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, + WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, - IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, + IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, SSI_WS78_B_MARK, - DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK, VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, - INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, - MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, @@ -1094,7 +1094,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5), PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), - PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP5_20_18, WE0_N), PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), @@ -1111,7 +1110,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), PINMUX_IPSR_GPSR(IP5_26_24, IRQ3), - PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N), PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), @@ -1125,7 +1123,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_2_0, DACK0), PINMUX_IPSR_GPSR(IP6_2_0, IRQ0), - PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N), PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), @@ -1137,7 +1134,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), PINMUX_IPSR_GPSR(IP6_8_6, DACK1), PINMUX_IPSR_GPSR(IP6_8_6, IRQ1), - PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N), PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N), @@ -1146,7 +1142,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), PINMUX_IPSR_GPSR(IP6_13_11, DACK2), PINMUX_IPSR_GPSR(IP6_13_11, IRQ2), - PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N), PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), @@ -2410,29 +2405,14 @@ static const unsigned int mlb_3pin_mux[] = { #endif /* CONFIG_PINCTRL_PFC_R8A7790 */ /* - MMCIF0 ----------------------------------------------------------------- */ -static const unsigned int mmc0_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(3, 18), -}; -static const unsigned int mmc0_data1_mux[] = { - MMC0_D0_MARK, -}; -static const unsigned int mmc0_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), - RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), -}; -static const unsigned int mmc0_data4_mux[] = { - MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, -}; -static const unsigned int mmc0_data8_pins[] = { +static const unsigned int mmc0_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), }; -static const unsigned int mmc0_data8_mux[] = { +static const unsigned int mmc0_data_mux[] = { MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, }; @@ -2444,29 +2424,14 @@ static const unsigned int mmc0_ctrl_mux[] = { MMC0_CLK_MARK, MMC0_CMD_MARK, }; /* - MMCIF1 ----------------------------------------------------------------- */ -static const unsigned int mmc1_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(3, 26), -}; -static const unsigned int mmc1_data1_mux[] = { - MMC1_D0_MARK, -}; -static const unsigned int mmc1_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), - RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), -}; -static const unsigned int mmc1_data4_mux[] = { - MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, -}; -static const unsigned int mmc1_data8_pins[] = { +static const unsigned int mmc1_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), }; -static const unsigned int mmc1_data8_mux[] = { +static const unsigned int mmc1_data_mux[] = { MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, }; @@ -2813,19 +2778,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -3322,18 +3280,11 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -3358,18 +3309,11 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 10), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -3394,18 +3338,11 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 18), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -3430,18 +3367,11 @@ static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 26), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), }; -static const unsigned int sdhi3_data4_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, }; static const unsigned int sdhi3_ctrl_pins[] = { @@ -3679,18 +3609,11 @@ static const unsigned int tpu0_to3_mux[] = { }; /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { - /* PWEN, OVC/VBUS */ - RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), + /* OVC/VBUS, PWEN */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18), }; static const unsigned int usb0_mux[] = { - USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, -}; -static const unsigned int usb0_ovc_vbus_pins[] = { - /* OVC/VBUS */ - RCAR_GP_PIN(5, 19), -}; -static const unsigned int usb0_ovc_vbus_mux[] = { - USB0_OVC_VBUS_MARK, + USB0_OVC_VBUS_MARK, USB0_PWEN_MARK, }; /* - USB1 ------------------------------------------------------------------- */ static const unsigned int usb1_pins[] = { @@ -3700,13 +3623,6 @@ static const unsigned int usb1_pins[] = { static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; -static const unsigned int usb1_pwen_pins[] = { - /* PWEN */ - RCAR_GP_PIN(5, 20), -}; -static const unsigned int usb1_pwen_mux[] = { - USB1_PWEN_MARK, -}; /* - USB2 ------------------------------------------------------------------- */ static const unsigned int usb2_pins[] = { /* PWEN, OVC */ @@ -3716,43 +3632,39 @@ static const unsigned int usb2_mux[] = { USB2_PWEN_MARK, USB2_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), - RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), - RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), - /* G */ - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - /* R */ - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), - RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + /* G */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + /* R */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -3809,43 +3721,39 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data vin1_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), - RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), - /* G */ - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), - /* R */ - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), - }, +static const unsigned int vin1_data_pins[] = { + /* B */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), }; -static const union vin_data vin1_data_mux = { - .data24 = { - /* B */ - VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, - VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, - VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, - VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, - /* G */ - VI1_G0_MARK, VI1_G1_MARK, - VI1_G2_MARK, VI1_G3_MARK, - VI1_G4_MARK, VI1_G5_MARK, - VI1_G6_MARK, VI1_G7_MARK, - /* R */ - VI1_R0_MARK, VI1_R1_MARK, - VI1_R2_MARK, VI1_R3_MARK, - VI1_R4_MARK, VI1_R5_MARK, - VI1_R6_MARK, VI1_R7_MARK, - }, +static const unsigned int vin1_data_mux[] = { + /* B */ + VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, + VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, + VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, + VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, + /* G */ + VI1_G0_MARK, VI1_G1_MARK, + VI1_G2_MARK, VI1_G3_MARK, + VI1_G4_MARK, VI1_G5_MARK, + VI1_G6_MARK, VI1_G7_MARK, + /* R */ + VI1_R0_MARK, VI1_R1_MARK, + VI1_R2_MARK, VI1_R3_MARK, + VI1_R4_MARK, VI1_R5_MARK, + VI1_R6_MARK, VI1_R7_MARK, }; static const unsigned int vin1_data18_pins[] = { /* B */ @@ -3875,43 +3783,39 @@ static const unsigned int vin1_data18_mux[] = { VI1_R4_MARK, VI1_R5_MARK, VI1_R6_MARK, VI1_R7_MARK, }; -static const union vin_data vin1_data_b_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), - RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - /* G */ - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), - /* R */ - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), - }, +static const unsigned int vin1_data_b_pins[] = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), }; -static const union vin_data vin1_data_b_mux = { - .data24 = { - /* B */ - VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK, - VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, - VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, - VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, - /* G */ - VI1_G0_B_MARK, VI1_G1_B_MARK, - VI1_G2_B_MARK, VI1_G3_B_MARK, - VI1_G4_B_MARK, VI1_G5_B_MARK, - VI1_G6_B_MARK, VI1_G7_B_MARK, - /* R */ - VI1_R0_B_MARK, VI1_R1_B_MARK, - VI1_R2_B_MARK, VI1_R3_B_MARK, - VI1_R4_B_MARK, VI1_R5_B_MARK, - VI1_R6_B_MARK, VI1_R7_B_MARK, - }, +static const unsigned int vin1_data_b_mux[] = { + /* B */ + VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK, + VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, }; static const unsigned int vin1_data18_b_pins[] = { /* B */ @@ -3994,43 +3898,39 @@ static const unsigned int vin1_clk_b_mux[] = { VI1_CLK_B_MARK, }; /* - VIN2 ----------------------------------------------------------------- */ -static const union vin_data vin2_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - /* G */ - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - /* R */ - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), - }, +static const unsigned int vin2_data_pins[] = { + /* B */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + /* G */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), }; -static const union vin_data vin2_data_mux = { - .data24 = { - /* B */ - VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, - VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, - VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, - VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, - /* G */ - VI2_G0_MARK, VI2_G1_MARK, - VI2_G2_MARK, VI2_G3_MARK, - VI2_G4_MARK, VI2_G5_MARK, - VI2_G6_MARK, VI2_G7_MARK, - /* R */ - VI2_R0_MARK, VI2_R1_MARK, - VI2_R2_MARK, VI2_R3_MARK, - VI2_R4_MARK, VI2_R5_MARK, - VI2_R6_MARK, VI2_R7_MARK, - }, +static const unsigned int vin2_data_mux[] = { + /* B */ + VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, + VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, + VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, + /* G */ + VI2_G0_MARK, VI2_G1_MARK, + VI2_G2_MARK, VI2_G3_MARK, + VI2_G4_MARK, VI2_G5_MARK, + VI2_G6_MARK, VI2_G7_MARK, + /* R */ + VI2_R0_MARK, VI2_R1_MARK, + VI2_R2_MARK, VI2_R3_MARK, + VI2_R4_MARK, VI2_R5_MARK, + VI2_R6_MARK, VI2_R7_MARK, }; static const unsigned int vin2_data18_pins[] = { /* B */ @@ -4060,18 +3960,6 @@ static const unsigned int vin2_data18_mux[] = { VI2_R4_MARK, VI2_R5_MARK, VI2_R6_MARK, VI2_R7_MARK, }; -static const unsigned int vin2_g8_pins[] = { - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), -}; -static const unsigned int vin2_g8_mux[] = { - VI2_G0_MARK, VI2_G1_MARK, - VI2_G2_MARK, VI2_G3_MARK, - VI2_G4_MARK, VI2_G5_MARK, - VI2_G6_MARK, VI2_G7_MARK, -}; static const unsigned int vin2_sync_pins[] = { RCAR_GP_PIN(1, 16), /* HSYNC */ RCAR_GP_PIN(1, 21), /* VSYNC */ @@ -4223,13 +4111,13 @@ static const struct { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), + BUS_DATA_PIN_GROUP(mmc0_data, 1), + BUS_DATA_PIN_GROUP(mmc0_data, 4), + BUS_DATA_PIN_GROUP(mmc0_data, 8), SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), + BUS_DATA_PIN_GROUP(mmc1_data, 1), + BUS_DATA_PIN_GROUP(mmc1_data, 4), + BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -4279,8 +4167,8 @@ static const struct { SH_PFC_PIN_GROUP(pwm5), SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4350,23 +4238,23 @@ static const struct { SH_PFC_PIN_GROUP(scifb2_data_c), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4401,38 +4289,38 @@ static const struct { SH_PFC_PIN_GROUP(tpu0_to2), SH_PFC_PIN_GROUP(tpu0_to3), SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb0_ovc_vbus), + SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1), SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb1_pwen), + SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1), SH_PFC_PIN_GROUP(usb2), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 4), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 4), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), + BUS_DATA_PIN_GROUP(vin1_data, 24), + BUS_DATA_PIN_GROUP(vin1_data, 20), SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 4), - VIN_DATA_PIN_GROUP(vin1_data, 24, _b), - VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 4), + BUS_DATA_PIN_GROUP(vin1_data, 24, _b), + BUS_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data, 16, _b), - VIN_DATA_PIN_GROUP(vin1_data, 12, _b), - VIN_DATA_PIN_GROUP(vin1_data, 10, _b), - VIN_DATA_PIN_GROUP(vin1_data, 8, _b), - VIN_DATA_PIN_GROUP(vin1_data, 4, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16, _b), + BUS_DATA_PIN_GROUP(vin1_data, 12, _b), + BUS_DATA_PIN_GROUP(vin1_data, 10, _b), + BUS_DATA_PIN_GROUP(vin1_data, 8, _b), + BUS_DATA_PIN_GROUP(vin1_data, 4, _b), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_sync_b), SH_PFC_PIN_GROUP(vin1_field), @@ -4441,12 +4329,12 @@ static const struct { SH_PFC_PIN_GROUP(vin1_clkenb_b), SH_PFC_PIN_GROUP(vin1_clk), SH_PFC_PIN_GROUP(vin1_clk_b), - VIN_DATA_PIN_GROUP(vin2_data, 24), + BUS_DATA_PIN_GROUP(vin2_data, 24), SH_PFC_PIN_GROUP(vin2_data18), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 8), - VIN_DATA_PIN_GROUP(vin2_data, 4), - SH_PFC_PIN_GROUP(vin2_g8), + BUS_DATA_PIN_GROUP(vin2_data, 16), + BUS_DATA_PIN_GROUP(vin2_data, 8), + BUS_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8), SH_PFC_PIN_GROUP(vin2_sync), SH_PFC_PIN_GROUP(vin2_field), SH_PFC_PIN_GROUP(vin2_clkenb), @@ -4964,10 +4852,10 @@ static const struct { .common = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(du2), @@ -5415,9 +5303,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, /* IP5_26_24 [3] */ - FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, - FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, - FN_MSIOF0_SCK_B, 0, + FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B, + FN_HRX0_B, FN_MSIOF0_SCK_B, 0, /* IP5_23_21 [3] */ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, @@ -5426,7 +5313,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, /* IP5_17_15 [3] */ FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, - FN_INTC_IRQ4_N, 0, 0, + 0, 0, 0, /* IP5_14_13 [2] */ FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, /* IP5_12_10 [3] */ @@ -5467,19 +5354,18 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, FN_I2C2_SCL_E, 0, /* IP6_13_11 [3] */ - FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, - FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B, + FN_MSIOF0_RXD_B, 0, 0, /* IP6_10_9 [2] */ FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, /* IP6_8_6 [3] */ - FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, - FN_SSI_SDATA8_C, 0, 0, 0, + FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0, /* IP6_5_3 [3] */ FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, /* IP6_2_0 [3] */ - FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, - FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) + FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N, + FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), @@ -5987,7 +5873,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31)) return -EINVAL; @@ -6289,7 +6175,7 @@ static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) return 0; } -static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7790_pfc_ops = { .init = r8a7790_pinmux_soc_init, .pin_to_pocctrl = r8a7790_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, @@ -6299,7 +6185,7 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A7742 const struct sh_pfc_soc_info r8a7742_pinmux_info = { .name = "r8a77420_pfc", - .ops = &r8a7790_pinmux_ops, + .ops = &r8a7790_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6322,7 +6208,7 @@ const struct sh_pfc_soc_info r8a7742_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7790 const struct sh_pfc_soc_info r8a7790_pinmux_info = { .name = "r8a77900_pfc", - .ops = &r8a7790_pinmux_ops, + .ops = &r8a7790_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index fe4ccab6b0b8..076a8b7d71de 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -234,11 +234,11 @@ enum { FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, FN_SCIFA2_RXD, FN_FMIN_E, FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, - FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, - FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, - FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, - FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, - FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + FN_IRQ0, FN_SCIFB1_RXD_D, + FN_IRQ1, FN_SCIFB1_SCK_C, + FN_IRQ2, FN_SCIFB1_TXD_D, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, + FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, @@ -606,12 +606,12 @@ enum { AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, SCIFA2_RXD_MARK, FMIN_E_MARK, AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, - IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, - IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, - IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, - IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, + IRQ0_MARK, SCIFB1_RXD_D_MARK, + IRQ1_MARK, SCIFB1_SCK_C_MARK, + IRQ2_MARK, SCIFB1_TXD_D_MARK, + IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK, - MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, + MSIOF2_RXD_E_MARK, IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK, IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK, @@ -1140,22 +1140,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N), PINMUX_IPSR_GPSR(IP6_11_10, IRQ1), PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), - PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N), PINMUX_IPSR_GPSR(IP6_13_12, IRQ2), PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), PINMUX_IPSR_GPSR(IP6_15_14, IRQ3), PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_18_16, IRQ4), PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_20_19, IRQ5), PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4), @@ -2303,13 +2298,6 @@ static const unsigned int hscif1_data_d_pins[] = { static const unsigned int hscif1_data_d_mux[] = { HRX1_D_MARK, HTX1_D_MARK, }; -static const unsigned int hscif1_data_e_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), -}; -static const unsigned int hscif1_data_e_mux[] = { - HRX1_C_MARK, HTX1_C_MARK, -}; static const unsigned int hscif1_clk_e_pins[] = { /* SCK */ RCAR_GP_PIN(2, 6), @@ -2604,40 +2592,25 @@ static const unsigned int mlb_3pin_mux[] = { #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), - RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, }; -static const unsigned int mmc_data8_b_pins[] = { +static const unsigned int mmc_data_b_pins[] = { /* D[0:7] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), }; -static const unsigned int mmc_data8_b_mux[] = { +static const unsigned int mmc_data_b_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK, }; @@ -3225,19 +3198,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; @@ -3248,19 +3214,12 @@ static const unsigned int qspi_ctrl_b_pins[] = { static const unsigned int qspi_ctrl_b_mux[] = { SPCLK_B_MARK, SSL_B_MARK, }; -static const unsigned int qspi_data2_b_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), -}; -static const unsigned int qspi_data2_b_mux[] = { - MOSI_IO0_B_MARK, MISO_IO1_B_MARK, -}; -static const unsigned int qspi_data4_b_pins[] = { +static const unsigned int qspi_data_b_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), }; -static const unsigned int qspi_data4_b_mux[] = { +static const unsigned int qspi_data_b_mux[] = { MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -3821,19 +3780,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DATA0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -3858,19 +3810,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DATA0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -3895,19 +3840,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DATA0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -4230,43 +4168,39 @@ static const unsigned int usb1_mux[] = { USB1_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), - RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), - /* G */ - RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), - RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), - RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), - RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), - /* R */ - RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), - RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), - RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), - RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + /* G */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + /* R */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), + RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -4361,43 +4295,39 @@ static const unsigned int vin1_clk_pins[] = { static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; -static const union vin_data vin1_data_b_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), - RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), - /* G */ - RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), - RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), - RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), - RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), - /* R */ - RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), - RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), - RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), - RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), - }, +static const unsigned int vin1_data_b_pins[] = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + /* G */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), + RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), + /* R */ + RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), }; -static const union vin_data vin1_data_b_mux = { - .data24 = { - /* B */ - VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, - VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, - VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, - VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, - /* G */ - VI1_G0_B_MARK, VI1_G1_B_MARK, - VI1_G2_B_MARK, VI1_G3_B_MARK, - VI1_G4_B_MARK, VI1_G5_B_MARK, - VI1_G6_B_MARK, VI1_G7_B_MARK, - /* R */ - VI1_R0_B_MARK, VI1_R1_B_MARK, - VI1_R2_B_MARK, VI1_R3_B_MARK, - VI1_R4_B_MARK, VI1_R5_B_MARK, - VI1_R6_B_MARK, VI1_R7_B_MARK, - }, +static const unsigned int vin1_data_b_mux[] = { + /* B */ + VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, + VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, + VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, + VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, }; static const unsigned int vin1_data18_b_pins[] = { /* B */ @@ -4556,7 +4486,7 @@ static const struct { SH_PFC_PIN_GROUP(hscif1_clk_c), SH_PFC_PIN_GROUP(hscif1_ctrl_c), SH_PFC_PIN_GROUP(hscif1_data_d), - SH_PFC_PIN_GROUP(hscif1_data_e), + SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c), SH_PFC_PIN_GROUP(hscif1_clk_e), SH_PFC_PIN_GROUP(hscif1_ctrl_e), SH_PFC_PIN_GROUP(hscif2_data), @@ -4596,10 +4526,10 @@ static const struct { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), - SH_PFC_PIN_GROUP(mmc_data8_b), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), + BUS_DATA_PIN_GROUP(mmc_data, 8, _b), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -4683,11 +4613,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(qspi_ctrl_b), - SH_PFC_PIN_GROUP(qspi_data2_b), - SH_PFC_PIN_GROUP(qspi_data4_b), + BUS_DATA_PIN_GROUP(qspi_data, 2, _b), + BUS_DATA_PIN_GROUP(qspi_data, 4, _b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -4765,18 +4695,18 @@ static const struct { SH_PFC_PIN_GROUP(scifb2_data_d), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), @@ -4814,13 +4744,13 @@ static const struct { SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), @@ -4830,13 +4760,13 @@ static const struct { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24, _b), - VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + BUS_DATA_PIN_GROUP(vin1_data, 24, _b), + BUS_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data, 16, _b), - VIN_DATA_PIN_GROUP(vin1_data, 12, _b), - VIN_DATA_PIN_GROUP(vin1_data, 10, _b), - VIN_DATA_PIN_GROUP(vin1_data, 8, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16, _b), + BUS_DATA_PIN_GROUP(vin1_data, 12, _b), + BUS_DATA_PIN_GROUP(vin1_data, 10, _b), + BUS_DATA_PIN_GROUP(vin1_data, 8, _b), SH_PFC_PIN_GROUP(vin1_sync_b), SH_PFC_PIN_GROUP(vin1_field_b), SH_PFC_PIN_GROUP(vin1_clkenb_b), @@ -6033,15 +5963,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, /* IP6_18_16 [3] */ FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, - FN_INTC_IRQ4_N, 0, 0, 0, + 0, 0, 0, 0, /* IP6_15_14 [2] */ - FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0, /* IP6_13_12 [2] */ - FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, + FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0, /* IP6_11_10 [2] */ - FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, + FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0, /* IP6_9_8 [2] */ - FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, + FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0, /* IP6_7_6 [2] */ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, /* IP6_5_3 [3] */ @@ -6672,7 +6602,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) return -EINVAL; @@ -6994,7 +6924,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7791_pfc_ops = { .pin_to_pocctrl = r8a7791_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -7003,7 +6933,7 @@ static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A7743 const struct sh_pfc_soc_info r8a7743_pinmux_info = { .name = "r8a77430_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -7026,7 +6956,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7744 const struct sh_pfc_soc_info r8a7744_pinmux_info = { .name = "r8a77440_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -7049,7 +6979,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -7074,7 +7004,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7793 const struct sh_pfc_soc_info r8a7793_pinmux_info = { .name = "r8a77930_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 3ab56dc768de..3e101f630148 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -1116,19 +1116,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -1206,19 +1199,12 @@ static const unsigned int scif3_clk_mux[] = { SCK3_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* DAT0 */ - RCAR_GP_PIN(11, 7), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* DAT[0-3] */ RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8), RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -1243,43 +1229,39 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), - RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), - RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), - RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), - /* G */ - RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), - RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), - RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2), - RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4), - /* R */ - RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), - RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), - RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), - RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + /* G */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2), + RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4), + /* R */ + RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), + RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, - VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK, - VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, - VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, - /* G */ - VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, - VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK, - VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK, - VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK, - /* R */ - VI0_D16_R0_MARK, VI0_D17_R1_MARK, - VI0_D18_R2_MARK, VI0_D19_R3_MARK, - VI0_D20_R4_MARK, VI0_D21_R5_MARK, - VI0_D22_R6_MARK, VI0_D23_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, + VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK, + VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, + VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, + /* G */ + VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, + VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK, + VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK, + VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK, + /* R */ + VI0_D16_R0_MARK, VI0_D17_R1_MARK, + VI0_D18_R2_MARK, VI0_D19_R3_MARK, + VI0_D20_R4_MARK, VI0_D21_R5_MARK, + VI0_D22_R6_MARK, VI0_D23_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -1335,43 +1317,39 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data vin1_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), - RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), - RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), - RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), - /* G */ - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), - RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), - RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), - RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), - /* R */ - RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), - RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), - RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), - RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), - }, +static const unsigned int vin1_data_pins[] = { + /* B */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + /* R */ + RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), }; -static const union vin_data vin1_data_mux = { - .data24 = { - /* B */ - VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, - VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, - VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, - VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, - /* G */ - VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, - VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, - VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK, - VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK, - /* R */ - VI1_D16_R0_MARK, VI1_D17_R1_MARK, - VI1_D18_R2_MARK, VI1_D19_R3_MARK, - VI1_D20_R4_MARK, VI1_D21_R5_MARK, - VI1_D22_R6_MARK, VI1_D23_R7_MARK, - }, +static const unsigned int vin1_data_mux[] = { + /* B */ + VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK, + VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK, + /* R */ + VI1_D16_R0_MARK, VI1_D17_R1_MARK, + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, }; static const unsigned int vin1_data18_pins[] = { /* B */ @@ -1401,43 +1379,39 @@ static const unsigned int vin1_data18_mux[] = { VI1_D20_R4_MARK, VI1_D21_R5_MARK, VI1_D22_R6_MARK, VI1_D23_R7_MARK, }; -static const union vin_data vin1_data_b_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), - RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), - RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), - RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), - /* G */ - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), - RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), - RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2), - RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4), - /* R */ - RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), - RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), - RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), - RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), - }, +static const unsigned int vin1_data_b_pins[] = { + /* B */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2), + RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4), + /* R */ + RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), }; -static const union vin_data vin1_data_b_mux = { - .data24 = { - /* B */ - VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, - VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, - VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, - VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, - /* G */ - VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, - VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, - VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK, - VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK, - /* R */ - VI1_D16_R0_MARK, VI1_D17_R1_MARK, - VI1_D18_R2_MARK, VI1_D19_R3_MARK, - VI1_D20_R4_MARK, VI1_D21_R5_MARK, - VI1_D22_R6_MARK, VI1_D23_R7_MARK, - }, +static const unsigned int vin1_data_b_mux[] = { + /* B */ + VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK, + VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK, + /* R */ + VI1_D16_R0_MARK, VI1_D17_R1_MARK, + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, }; static const unsigned int vin1_data18_b_pins[] = { /* B */ @@ -1493,29 +1467,25 @@ static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; /* - VIN2 ------------------------------------------------------------------- */ -static const union vin_data16 vin2_data_pins = { - .data16 = { - RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), - RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), - RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), - RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), - RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), - RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), - RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), - RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), - }, +static const unsigned int vin2_data_pins[] = { + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), + RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), + RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), }; -static const union vin_data16 vin2_data_mux = { - .data16 = { - VI2_D0_C0_MARK, VI2_D1_C1_MARK, - VI2_D2_C2_MARK, VI2_D3_C3_MARK, - VI2_D4_C4_MARK, VI2_D5_C5_MARK, - VI2_D6_C6_MARK, VI2_D7_C7_MARK, - VI2_D8_Y0_MARK, VI2_D9_Y1_MARK, - VI2_D10_Y2_MARK, VI2_D11_Y3_MARK, - VI2_D12_Y4_MARK, VI2_D13_Y5_MARK, - VI2_D14_Y6_MARK, VI2_D15_Y7_MARK, - }, +static const unsigned int vin2_data_mux[] = { + VI2_D0_C0_MARK, VI2_D1_C1_MARK, + VI2_D2_C2_MARK, VI2_D3_C3_MARK, + VI2_D4_C4_MARK, VI2_D5_C5_MARK, + VI2_D6_C6_MARK, VI2_D7_C7_MARK, + VI2_D8_Y0_MARK, VI2_D9_Y1_MARK, + VI2_D10_Y2_MARK, VI2_D11_Y3_MARK, + VI2_D12_Y4_MARK, VI2_D13_Y5_MARK, + VI2_D14_Y6_MARK, VI2_D15_Y7_MARK, }; static const unsigned int vin2_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1543,29 +1513,25 @@ static const unsigned int vin2_clk_mux[] = { VI2_CLK_MARK, }; /* - VIN3 ------------------------------------------------------------------- */ -static const union vin_data16 vin3_data_pins = { - .data16 = { - RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), - RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), - RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), - RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), - RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13), - RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), - RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14), - RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16), - }, +static const unsigned int vin3_data_pins[] = { + RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), + RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), + RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), + RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), + RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13), + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), + RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14), + RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16), }; -static const union vin_data16 vin3_data_mux = { - .data16 = { - VI3_D0_C0_MARK, VI3_D1_C1_MARK, - VI3_D2_C2_MARK, VI3_D3_C3_MARK, - VI3_D4_C4_MARK, VI3_D5_C5_MARK, - VI3_D6_C6_MARK, VI3_D7_C7_MARK, - VI3_D8_Y0_MARK, VI3_D9_Y1_MARK, - VI3_D10_Y2_MARK, VI3_D11_Y3_MARK, - VI3_D12_Y4_MARK, VI3_D13_Y5_MARK, - VI3_D14_Y6_MARK, VI3_D15_Y7_MARK, - }, +static const unsigned int vin3_data_mux[] = { + VI3_D0_C0_MARK, VI3_D1_C1_MARK, + VI3_D2_C2_MARK, VI3_D3_C3_MARK, + VI3_D4_C4_MARK, VI3_D5_C5_MARK, + VI3_D6_C6_MARK, VI3_D7_C7_MARK, + VI3_D8_Y0_MARK, VI3_D9_Y1_MARK, + VI3_D10_Y2_MARK, VI3_D11_Y3_MARK, + VI3_D12_Y4_MARK, VI3_D13_Y5_MARK, + VI3_D14_Y6_MARK, VI3_D15_Y7_MARK, }; static const unsigned int vin3_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1593,25 +1559,21 @@ static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, }; /* - VIN4 ------------------------------------------------------------------- */ -static const union vin_data12 vin4_data_pins = { - .data12 = { - RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), - RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), - RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), - RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), - RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13), - RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15), - }, +static const unsigned int vin4_data_pins[] = { + RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), + RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), + RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), + RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), + RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13), + RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15), }; -static const union vin_data12 vin4_data_mux = { - .data12 = { - VI4_D0_C0_MARK, VI4_D1_C1_MARK, - VI4_D2_C2_MARK, VI4_D3_C3_MARK, - VI4_D4_C4_MARK, VI4_D5_C5_MARK, - VI4_D6_C6_MARK, VI4_D7_C7_MARK, - VI4_D8_Y0_MARK, VI4_D9_Y1_MARK, - VI4_D10_Y2_MARK, VI4_D11_Y3_MARK, - }, +static const unsigned int vin4_data_mux[] = { + VI4_D0_C0_MARK, VI4_D1_C1_MARK, + VI4_D2_C2_MARK, VI4_D3_C3_MARK, + VI4_D4_C4_MARK, VI4_D5_C5_MARK, + VI4_D6_C6_MARK, VI4_D7_C7_MARK, + VI4_D8_Y0_MARK, VI4_D9_Y1_MARK, + VI4_D10_Y2_MARK, VI4_D11_Y3_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1639,25 +1601,21 @@ static const unsigned int vin4_clk_mux[] = { VI4_CLK_MARK, }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data12 vin5_data_pins = { - .data12 = { - RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), - RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), - RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), - RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), - RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13), - RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15), - }, +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), + RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), + RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), + RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), + RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13), + RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15), }; -static const union vin_data12 vin5_data_mux = { - .data12 = { - VI5_D0_C0_MARK, VI5_D1_C1_MARK, - VI5_D2_C2_MARK, VI5_D3_C3_MARK, - VI5_D4_C4_MARK, VI5_D5_C5_MARK, - VI5_D6_C6_MARK, VI5_D7_C7_MARK, - VI5_D8_Y0_MARK, VI5_D9_Y1_MARK, - VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, - }, +static const unsigned int vin5_data_mux[] = { + VI5_D0_C0_MARK, VI5_D1_C1_MARK, + VI5_D2_C2_MARK, VI5_D3_C3_MARK, + VI5_D4_C4_MARK, VI5_D5_C5_MARK, + VI5_D6_C6_MARK, VI5_D7_C7_MARK, + VI5_D8_Y0_MARK, VI5_D9_Y1_MARK, + VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, }; static const unsigned int vin5_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1728,8 +1686,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof1_rx), SH_PFC_PIN_GROUP(msiof1_tx), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -1740,63 +1698,63 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif2_clk), SH_PFC_PIN_GROUP(scif3_data), SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), + BUS_DATA_PIN_GROUP(vin1_data, 24), + BUS_DATA_PIN_GROUP(vin1_data, 20), SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 24, _b), - VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 24, _b), + BUS_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data, 16, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16, _b), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 12), - VIN_DATA_PIN_GROUP(vin2_data, 10), - VIN_DATA_PIN_GROUP(vin2_data, 8), + BUS_DATA_PIN_GROUP(vin2_data, 16), + BUS_DATA_PIN_GROUP(vin2_data, 12), + BUS_DATA_PIN_GROUP(vin2_data, 10), + BUS_DATA_PIN_GROUP(vin2_data, 8), SH_PFC_PIN_GROUP(vin2_sync), SH_PFC_PIN_GROUP(vin2_field), SH_PFC_PIN_GROUP(vin2_clkenb), SH_PFC_PIN_GROUP(vin2_clk), - VIN_DATA_PIN_GROUP(vin3_data, 16), - VIN_DATA_PIN_GROUP(vin3_data, 12), - VIN_DATA_PIN_GROUP(vin3_data, 10), - VIN_DATA_PIN_GROUP(vin3_data, 8), + BUS_DATA_PIN_GROUP(vin3_data, 16), + BUS_DATA_PIN_GROUP(vin3_data, 12), + BUS_DATA_PIN_GROUP(vin3_data, 10), + BUS_DATA_PIN_GROUP(vin3_data, 8), SH_PFC_PIN_GROUP(vin3_sync), SH_PFC_PIN_GROUP(vin3_field), SH_PFC_PIN_GROUP(vin3_clkenb), SH_PFC_PIN_GROUP(vin3_clk), - VIN_DATA_PIN_GROUP(vin4_data, 12), - VIN_DATA_PIN_GROUP(vin4_data, 10), - VIN_DATA_PIN_GROUP(vin4_data, 8), + BUS_DATA_PIN_GROUP(vin4_data, 12), + BUS_DATA_PIN_GROUP(vin4_data, 10), + BUS_DATA_PIN_GROUP(vin4_data, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -3281,14 +3239,14 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ } }; -static const struct sh_pfc_soc_operations r8a7792_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7792_pfc_ops = { .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a7792_pinmux_info = { .name = "r8a77920_pfc", - .ops = &r8a7792_pinmux_ops, + .ops = &r8a7792_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index fbb5b3b68f34..d1b0e6517382 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -2388,29 +2388,14 @@ static const unsigned int intc_irq9_mux[] = { IRQ9_MARK, }; /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), - RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, }; @@ -2745,19 +2730,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -3232,19 +3210,12 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DATA0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -3269,19 +3240,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DATA0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -3306,19 +3270,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DATA0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -3673,43 +3630,39 @@ static const unsigned int usb1_mux[] = { USB1_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), - RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), - RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), - RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), - /* G */ - RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), - RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), - RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), - RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), - /* R */ - RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), - RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), - RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), - RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + /* G */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + /* R */ + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -3766,25 +3719,21 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data12 vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), - RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), - RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), - RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), }; -static const union vin_data12 vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { RCAR_GP_PIN(5, 22), /* HSYNC */ @@ -3923,9 +3872,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq7), SH_PFC_PIN_GROUP(intc_irq8), SH_PFC_PIN_GROUP(intc_irq9), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -3975,8 +3924,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -4042,18 +3991,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb2_ctrl), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), @@ -4105,20 +4054,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to3_c), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -5621,8 +5570,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { + if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) + return -EINVAL; + *pocctrl = 0xe606006c; switch (pin & 0x1f) { @@ -5932,7 +5884,7 @@ static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc) return 0; } -static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7794_pfc_ops = { .init = r8a7794_pinmux_soc_init, .pin_to_pocctrl = r8a7794_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, @@ -5942,7 +5894,7 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A7745 const struct sh_pfc_soc_info r8a7745_pinmux_info = { .name = "r8a77450_pfc", - .ops = &r8a7794_pinmux_ops, + .ops = &r8a7794_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -5965,7 +5917,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7794 const struct sh_pfc_soc_info r8a7794_pinmux_info = { .name = "r8a77940_pfc", - .ops = &r8a7794_pinmux_ops, + .ops = &r8a7794_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c index c86064900c6e..63c9f6d6468b 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77950.c +++ b/drivers/pinctrl/renesas/pfc-r8a77950.c @@ -3140,18 +3140,11 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3163,18 +3156,11 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3395,19 +3381,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3433,19 +3412,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3471,30 +3443,14 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3543,30 +3499,14 @@ static const unsigned int sdhi2_ds_mux[] = { SD2_DS_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4103,11 +4043,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4137,28 +4077,28 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif5_clk), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -5574,8 +5514,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77950_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -5832,7 +5771,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77950_pfc_ops = { .pin_to_pocctrl = r8a77950_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -5840,7 +5779,7 @@ static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = { const struct sh_pfc_soc_info r8a77950_pinmux_info = { .name = "r8a77950_pfc", - .ops = &r8a77950_pinmux_ops, + .ops = &r8a77950_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index ee9ce5f8eb86..9d6eef4e9d18 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -3268,20 +3268,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, /* QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3293,20 +3286,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, /* QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3541,19 +3527,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3579,19 +3558,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3617,30 +3589,14 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3689,30 +3645,14 @@ static const unsigned int sdhi2_ds_mux[] = { SD2_DS_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4071,81 +4011,61 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, -}; -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; -static const unsigned int vin4_g8_pins[] = { - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), -}; -static const unsigned int vin4_g8_mux[] = { +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, VI4_DATA8_MARK, VI4_DATA9_MARK, VI4_DATA10_MARK, VI4_DATA11_MARK, VI4_DATA12_MARK, VI4_DATA13_MARK, VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -4177,37 +4097,21 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_pins = { - .data16 = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - }, -}; -static const union vin_data16 vin5_data_mux = { - .data16 = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, - }, -}; -static const unsigned int vin5_high8_pins[] = { +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), }; -static const unsigned int vin5_high8_mux[] = { +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, VI5_DATA8_MARK, VI5_DATA9_MARK, VI5_DATA10_MARK, VI5_DATA11_MARK, VI5_DATA12_MARK, VI5_DATA13_MARK, @@ -4449,11 +4353,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4485,28 +4389,28 @@ static const struct { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4549,30 +4453,30 @@ static const struct { SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ch3), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_g8), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP(vin5_high8), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -6058,8 +5962,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc, - unsigned int pin, u32 *pocctrl) +static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6316,7 +6219,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77951_pfc_ops = { .pin_to_pocctrl = r8a77951_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -6325,7 +6228,7 @@ static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774E1 const struct sh_pfc_soc_info r8a774e1_pinmux_info = { .name = "r8a774e1_pfc", - .ops = &r8a77951_pinmux_ops, + .ops = &r8a77951_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6350,7 +6253,7 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77951 const struct sh_pfc_soc_info r8a77951_pinmux_info = { .name = "r8a77951_pfc", - .ops = &r8a77951_pinmux_ops, + .ops = &r8a77951_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index de3df502f971..75ea36829a70 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -3274,20 +3274,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, /* QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3299,20 +3292,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, /* QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3532,19 +3518,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3570,19 +3549,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3608,30 +3580,14 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3680,30 +3636,14 @@ static const unsigned int sdhi2_ds_mux[] = { SD2_DS_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4046,81 +3986,61 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, -}; -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; -static const unsigned int vin4_g8_pins[] = { - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), -}; -static const unsigned int vin4_g8_mux[] = { +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, VI4_DATA8_MARK, VI4_DATA9_MARK, VI4_DATA10_MARK, VI4_DATA11_MARK, VI4_DATA12_MARK, VI4_DATA13_MARK, VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -4152,37 +4072,21 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_pins = { - .data16 = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - }, -}; -static const union vin_data16 vin5_data_mux = { - .data16 = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, - }, -}; -static const unsigned int vin5_high8_pins[] = { +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), }; -static const unsigned int vin5_high8_mux[] = { +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, VI5_DATA8_MARK, VI5_DATA9_MARK, VI5_DATA10_MARK, VI5_DATA11_MARK, VI5_DATA12_MARK, VI5_DATA13_MARK, @@ -4424,11 +4328,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4458,28 +4362,28 @@ static const struct { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4520,30 +4424,30 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_g8), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP(vin5_high8), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -6009,8 +5913,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, - unsigned int pin, u32 *pocctrl) +static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6267,7 +6170,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7796_pfc_ops = { .pin_to_pocctrl = r8a7796_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -6276,7 +6179,7 @@ static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774A1 const struct sh_pfc_soc_info r8a774a1_pinmux_info = { .name = "r8a774a1_pfc", - .ops = &r8a7796_pinmux_ops, + .ops = &r8a7796_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6301,7 +6204,7 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77960 const struct sh_pfc_soc_info r8a77960_pinmux_info = { .name = "r8a77960_pfc", - .ops = &r8a7796_pinmux_ops, + .ops = &r8a7796_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6328,7 +6231,7 @@ const struct sh_pfc_soc_info r8a77960_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77961 const struct sh_pfc_soc_info r8a77961_pinmux_info = { .name = "r8a77961_pfc", - .ops = &r8a7796_pinmux_ops, + .ops = &r8a7796_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index 268129f82929..6bb7f7543c37 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -3424,20 +3424,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, /* QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3449,20 +3442,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, /* QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3698,22 +3684,13 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; - -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; - -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3746,22 +3723,13 @@ static const unsigned int sdhi0_wp_mux[] = { }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; - -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; - -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3794,27 +3762,7 @@ static const unsigned int sdhi1_wp_mux[] = { }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; - -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; - -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; - -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; - -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), @@ -3822,7 +3770,7 @@ static const unsigned int sdhi2_data8_pins[] = { RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3884,27 +3832,7 @@ static const unsigned int sdhi2_ds_mux[] = { }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; - -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; - -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; - -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; - -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), @@ -3912,7 +3840,7 @@ static const unsigned int sdhi3_data8_pins[] = { RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4254,38 +4182,34 @@ static const unsigned int vin4_data18_a_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_data18_b_pins[] = { @@ -4312,52 +4236,34 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; - -static const unsigned int vin4_g8_pins[] = { - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), -}; - -static const unsigned int vin4_g8_mux[] = { - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { @@ -4394,40 +4300,22 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_pins = { - .data16 = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - }, -}; - -static const union vin_data16 vin5_data_mux = { - .data16 = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, - }, -}; - -static const unsigned int vin5_high8_pins[] = { +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), }; -static const unsigned int vin5_high8_mux[] = { +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, VI5_DATA8_MARK, VI5_DATA9_MARK, VI5_DATA10_MARK, VI5_DATA11_MARK, VI5_DATA12_MARK, VI5_DATA13_MARK, @@ -4674,11 +4562,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4710,28 +4598,28 @@ static const struct { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4772,30 +4660,30 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_g8), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), - SH_PFC_PIN_GROUP(vin5_high8), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -6266,8 +6154,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, - unsigned int pin, u32 *pocctrl) +static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6524,7 +6411,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77965_pfc_ops = { .pin_to_pocctrl = r8a77965_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -6533,7 +6420,7 @@ static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774B1 const struct sh_pfc_soc_info r8a774b1_pinmux_info = { .name = "r8a774b1_pfc", - .ops = &r8a77965_pinmux_ops, + .ops = &r8a77965_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6558,7 +6445,7 @@ const struct sh_pfc_soc_info r8a774b1_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77965 const struct sh_pfc_soc_info r8a77965_pinmux_info = { .name = "r8a77965_pfc", - .ops = &r8a77965_pinmux_ops, + .ops = &r8a77965_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 45b0b235c5cc..94f90c13989e 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -1102,30 +1102,14 @@ static const unsigned int intc_ex_irq5_mux[] = { }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 6), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -1393,22 +1377,6 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), - RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), -}; -static const unsigned int qspi0_data4_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, - QSPI0_IO2_MARK, QSPI0_IO3_MARK -}; /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { @@ -1418,36 +1386,14 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), - RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), -}; -static const unsigned int qspi1_data4_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, - QSPI1_IO2_MARK, QSPI1_IO3_MARK -}; /* - RPC -------------------------------------------------------------------- */ -static const unsigned int rpc_clk1_pins[] = { +static const unsigned int rpc_clk_pins[] = { /* Octal-SPI flash: C/SCLK */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int rpc_clk1_mux[] = { - QSPI0_SPCLK_MARK, -}; -static const unsigned int rpc_clk2_pins[] = { /* HyperFlash: CK, CK# */ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), }; -static const unsigned int rpc_clk2_mux[] = { +static const unsigned int rpc_clk_mux[] = { QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, }; static const unsigned int rpc_ctrl_pins[] = { @@ -1639,25 +1585,21 @@ static const unsigned int tmu_tclk2_b_mux[] = { }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data12 vin0_data_pins = { - .data12 = { - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), - }, +static const unsigned int vin0_data_pins[] = { + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), }; -static const union vin_data12 vin0_data_mux = { - .data12 = { - VI0_DATA0_MARK, VI0_DATA1_MARK, - VI0_DATA2_MARK, VI0_DATA3_MARK, - VI0_DATA4_MARK, VI0_DATA5_MARK, - VI0_DATA6_MARK, VI0_DATA7_MARK, - VI0_DATA8_MARK, VI0_DATA9_MARK, - VI0_DATA10_MARK, VI0_DATA11_MARK, - }, +static const unsigned int vin0_data_mux[] = { + VI0_DATA0_MARK, VI0_DATA1_MARK, + VI0_DATA2_MARK, VI0_DATA3_MARK, + VI0_DATA4_MARK, VI0_DATA5_MARK, + VI0_DATA6_MARK, VI0_DATA7_MARK, + VI0_DATA8_MARK, VI0_DATA9_MARK, + VI0_DATA10_MARK, VI0_DATA11_MARK, }; static const unsigned int vin0_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1689,25 +1631,21 @@ static const unsigned int vin0_clk_mux[] = { }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data12 vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), - RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), - RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), }; -static const union vin_data12 vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1783,9 +1721,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -1822,13 +1760,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), - SH_PFC_PIN_GROUP(rpc_clk1), - SH_PFC_PIN_GROUP(rpc_clk2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), SH_PFC_PIN_GROUP(rpc_ctrl), SH_PFC_PIN_GROUP(rpc_data), SH_PFC_PIN_GROUP(rpc_reset), @@ -1853,16 +1791,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 12), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 12), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -2496,8 +2434,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; @@ -2656,7 +2593,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ } }; -static const struct sh_pfc_soc_operations pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77970_pfc_ops = { .pin_to_pocctrl = r8a77970_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -2664,7 +2601,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = { const struct sh_pfc_soc_info r8a77970_pinmux_info = { .name = "r8a77970_pfc", - .ops = &pinmux_ops, + .ops = &r8a77970_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index c4825b01449e..c229a5d8fa57 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -1365,30 +1365,14 @@ static const unsigned int intc_ex_irq5_mux[] = { }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* MMC_D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* MMC_D[0:3] */ - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* MMC_D[0:7] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -1687,22 +1671,6 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), - RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), -}; -static const unsigned int qspi0_data4_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, - QSPI0_IO2_MARK, QSPI0_IO3_MARK -}; /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { @@ -1712,36 +1680,14 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), - RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), -}; -static const unsigned int qspi1_data4_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, - QSPI1_IO2_MARK, QSPI1_IO3_MARK -}; /* - RPC -------------------------------------------------------------------- */ -static const unsigned int rpc_clk1_pins[] = { +static const unsigned int rpc_clk_pins[] = { /* Octal-SPI flash: C/SCLK */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int rpc_clk1_mux[] = { - QSPI0_SPCLK_MARK, -}; -static const unsigned int rpc_clk2_pins[] = { /* HyperFlash: CK, CK# */ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), }; -static const unsigned int rpc_clk2_mux[] = { +static const unsigned int rpc_clk_mux[] = { QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, }; static const unsigned int rpc_ctrl_pins[] = { @@ -1963,37 +1909,33 @@ static const unsigned int tpu_to3_mux[] = { }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), - RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), - RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), - RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), - RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), - RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), - RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), - }, +static const unsigned int vin0_data_pins[] = { + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), }; -static const union vin_data vin0_data_mux = { - .data24 = { - VI0_DATA0_MARK, VI0_DATA1_MARK, - VI0_DATA2_MARK, VI0_DATA3_MARK, - VI0_DATA4_MARK, VI0_DATA5_MARK, - VI0_DATA6_MARK, VI0_DATA7_MARK, - VI0_DATA8_MARK, VI0_DATA9_MARK, - VI0_DATA10_MARK, VI0_DATA11_MARK, - VI0_DATA12_MARK, VI0_DATA13_MARK, - VI0_DATA14_MARK, VI0_DATA15_MARK, - VI0_DATA16_MARK, VI0_DATA17_MARK, - VI0_DATA18_MARK, VI0_DATA19_MARK, - VI0_DATA20_MARK, VI0_DATA21_MARK, - VI0_DATA22_MARK, VI0_DATA23_MARK, - }, +static const unsigned int vin0_data_mux[] = { + VI0_DATA0_MARK, VI0_DATA1_MARK, + VI0_DATA2_MARK, VI0_DATA3_MARK, + VI0_DATA4_MARK, VI0_DATA5_MARK, + VI0_DATA6_MARK, VI0_DATA7_MARK, + VI0_DATA8_MARK, VI0_DATA9_MARK, + VI0_DATA10_MARK, VI0_DATA11_MARK, + VI0_DATA12_MARK, VI0_DATA13_MARK, + VI0_DATA14_MARK, VI0_DATA15_MARK, + VI0_DATA16_MARK, VI0_DATA17_MARK, + VI0_DATA18_MARK, VI0_DATA19_MARK, + VI0_DATA20_MARK, VI0_DATA21_MARK, + VI0_DATA22_MARK, VI0_DATA23_MARK, }; static const unsigned int vin0_data18_pins[] = { RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), @@ -2047,25 +1989,21 @@ static const unsigned int vin0_clk_mux[] = { }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data12 vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), - RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), - RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), }; -static const union vin_data12 vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { /* VI1_VSYNC#, VI1_HSYNC# */ @@ -2156,9 +2094,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), @@ -2198,13 +2136,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), - SH_PFC_PIN_GROUP(rpc_clk1), - SH_PFC_PIN_GROUP(rpc_clk2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), SH_PFC_PIN_GROUP(rpc_ctrl), SH_PFC_PIN_GROUP(rpc_data), SH_PFC_PIN_GROUP(rpc_reset), @@ -2233,20 +2171,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 16), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 20), - VIN_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 12), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -2940,8 +2878,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; @@ -3139,7 +3076,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ } }; -static const struct sh_pfc_soc_operations pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77980_pfc_ops = { .pin_to_pocctrl = r8a77980_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -3147,7 +3084,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = { const struct sh_pfc_soc_info r8a77980_pinmux_info = { .name = "r8a77980_pfc", - .ops = &pinmux_ops, + .ops = &r8a77980_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index f44c7da3ec16..6c4ba9e16058 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -2339,6 +2339,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2817,20 +2827,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), /* QSPI0_IO2, QSPI0_IO3 */ RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -2842,20 +2845,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), /* QSPI1_IO2, QSPI1_IO3 */ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3138,22 +3134,13 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; - -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; - -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3186,22 +3173,13 @@ static const unsigned int sdhi0_wp_mux[] = { }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; - -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; - -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3234,27 +3212,7 @@ static const unsigned int sdhi1_wp_mux[] = { }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; - -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; - -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; - -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; - -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), @@ -3262,7 +3220,7 @@ static const unsigned int sdhi3_data8_pins[] = { RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -3604,38 +3562,34 @@ static const unsigned int vin4_data18_a_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_data18_b_pins[] = { @@ -3662,52 +3616,34 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), - RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), - RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), - RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), - }, -}; - -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; - -static const unsigned int vin4_g8_pins[] = { +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), }; -static const unsigned int vin4_g8_mux[] = { - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { @@ -3744,30 +3680,26 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_a_pins = { - .data16 = { - RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), - RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - }, +static const unsigned int vin5_data_a_pins[] = { + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), }; -static const union vin_data16 vin5_data_a_mux = { - .data16 = { - VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, - VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, - VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, - VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, - VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, - VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, - VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, - VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, - }, +static const unsigned int vin5_data_a_mux[] = { + VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, + VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, + VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, + VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, + VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, + VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, + VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, }; static const unsigned int vin5_data8_b_pins[] = { @@ -3784,20 +3716,6 @@ static const unsigned int vin5_data8_b_mux[] = { VI5_DATA6_B_MARK, VI5_DATA7_B_MARK, }; -static const unsigned int vin5_high8_pins[] = { - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), -}; - -static const unsigned int vin5_high8_mux[] = { - VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, - VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, - VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, - VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, -}; - static const unsigned int vin5_sync_a_pins[] = { /* HSYNC_N, VSYNC_N */ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), @@ -3842,7 +3760,7 @@ static const unsigned int vin5_clk_b_mux[] = { static const struct { struct sh_pfc_pin_group common[255]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 - struct sh_pfc_pin_group automotive[21]; + struct sh_pfc_pin_group automotive[22]; #endif } pinmux_groups = { .common = { @@ -3989,11 +3907,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_ctrl_a), @@ -4024,19 +3942,19 @@ static const struct { SH_PFC_PIN_GROUP(scif5_data_c), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4071,31 +3989,31 @@ static const struct { SH_PFC_PIN_GROUP(usb0_id), SH_PFC_PIN_GROUP(usb30), SH_PFC_PIN_GROUP(usb30_id), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), - SH_PFC_PIN_GROUP(vin4_g8), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8, _a), - VIN_DATA_PIN_GROUP(vin5_data, 10, _a), - VIN_DATA_PIN_GROUP(vin5_data, 12, _a), - VIN_DATA_PIN_GROUP(vin5_data, 16, _a), + BUS_DATA_PIN_GROUP(vin5_data, 8, _a), + BUS_DATA_PIN_GROUP(vin5_data, 10, _a), + BUS_DATA_PIN_GROUP(vin5_data, 12, _a), + BUS_DATA_PIN_GROUP(vin5_data, 16, _a), SH_PFC_PIN_GROUP(vin5_data8_b), - SH_PFC_PIN_GROUP(vin5_high8), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data_a, 8, 8), SH_PFC_PIN_GROUP(vin5_sync_a), SH_PFC_PIN_GROUP(vin5_field_a), SH_PFC_PIN_GROUP(vin5_clkenb_a), @@ -4125,6 +4043,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; @@ -4315,6 +4234,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4569,7 +4494,7 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[49]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 - struct sh_pfc_function automotive[4]; + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -4629,6 +4554,7 @@ static const struct { SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; @@ -5115,8 +5041,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -5339,7 +5264,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77990_pfc_ops = { .pin_to_pocctrl = r8a77990_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -5348,7 +5273,7 @@ static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { #ifdef CONFIG_PINCTRL_PFC_R8A774C0 const struct sh_pfc_soc_info r8a774c0_pinmux_info = { .name = "r8a774c0_pfc", - .ops = &r8a77990_pinmux_ops, + .ops = &r8a77990_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -5372,7 +5297,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77990 const struct sh_pfc_soc_info r8a77990_pinmux_info = { .name = "r8a77990_pfc", - .ops = &r8a77990_pinmux_ops, + .ops = &r8a77990_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index c56e1e4c13b3..445c903a121a 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -1257,31 +1257,23 @@ static const unsigned int i2c3_b_mux[] = { SCL3_B_MARK, SDA3_B_MARK, }; +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; + /* - MMC ------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -1950,37 +1942,33 @@ static const unsigned int vin4_data18_mux[] = { VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_pins = { - .data24 = { - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), - RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), - RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), - RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), - RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), - RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), - RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), - RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), - RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), - RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), - RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), - }, +static const unsigned int vin4_data_pins[] = { + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), }; -static const union vin_data vin4_data_mux = { - .data24 = { - VI4_DATA0_MARK, VI4_DATA1_MARK, - VI4_DATA2_MARK, VI4_DATA3_MARK, - VI4_DATA4_MARK, VI4_DATA5_MARK, - VI4_DATA6_MARK, VI4_DATA7_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_mux[] = { + VI4_DATA0_MARK, VI4_DATA1_MARK, + VI4_DATA2_MARK, VI4_DATA3_MARK, + VI4_DATA4_MARK, VI4_DATA5_MARK, + VI4_DATA6_MARK, VI4_DATA7_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -2049,9 +2037,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c2_b), SH_PFC_PIN_GROUP(i2c3_a), SH_PFC_PIN_GROUP(i2c3_b), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mlb_3pin), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -2128,13 +2117,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi4_ctrl_b), SH_PFC_PIN_GROUP(ssi4_data_b), SH_PFC_PIN_GROUP(usb0), - VIN_DATA_PIN_GROUP(vin4_data, 8), - VIN_DATA_PIN_GROUP(vin4_data, 10), - VIN_DATA_PIN_GROUP(vin4_data, 12), - VIN_DATA_PIN_GROUP(vin4_data, 16), + BUS_DATA_PIN_GROUP(vin4_data, 8), + BUS_DATA_PIN_GROUP(vin4_data, 10), + BUS_DATA_PIN_GROUP(vin4_data, 12), + BUS_DATA_PIN_GROUP(vin4_data, 16), SH_PFC_PIN_GROUP(vin4_data18), - VIN_DATA_PIN_GROUP(vin4_data, 20), - VIN_DATA_PIN_GROUP(vin4_data, 24), + BUS_DATA_PIN_GROUP(vin4_data, 20), + BUS_DATA_PIN_GROUP(vin4_data, 24), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), @@ -2210,6 +2199,10 @@ static const char * const i2c3_groups[] = { "i2c3_b", }; +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; + static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -2217,6 +2210,49 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync_a", + "msiof2_sync_b", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk_a", + "msiof3_sync_a", + "msiof3_ss1_a", + "msiof3_ss2_a", + "msiof3_txd_a", + "msiof3_rxd_a", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_ss1_b", + "msiof3_ss2_b", + "msiof3_txd_b", + "msiof3_rxd_b", +}; + static const char * const pwm0_groups[] = { "pwm0_a", "pwm0_b", @@ -2314,49 +2350,6 @@ static const char * const vin4_groups[] = { "vin4_clk", }; -static const char * const msiof0_groups[] = { - "msiof0_clk", - "msiof0_sync", - "msiof0_ss1", - "msiof0_ss2", - "msiof0_txd", - "msiof0_rxd", -}; - -static const char * const msiof1_groups[] = { - "msiof1_clk", - "msiof1_sync", - "msiof1_ss1", - "msiof1_ss2", - "msiof1_txd", - "msiof1_rxd", -}; - -static const char * const msiof2_groups[] = { - "msiof2_clk", - "msiof2_sync_a", - "msiof2_sync_b", - "msiof2_ss1", - "msiof2_ss2", - "msiof2_txd", - "msiof2_rxd", -}; - -static const char * const msiof3_groups[] = { - "msiof3_clk_a", - "msiof3_sync_a", - "msiof3_ss1_a", - "msiof3_ss2_a", - "msiof3_txd_a", - "msiof3_rxd_a", - "msiof3_clk_b", - "msiof3_sync_b", - "msiof3_ss1_b", - "msiof3_ss2_b", - "msiof3_txd_b", - "msiof3_rxd_b", -}; - static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb0), @@ -2370,6 +2363,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(mlb_3pin), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -2842,7 +2836,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -3078,7 +3072,7 @@ r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, const struct pinmux_bias_reg *reg; unsigned int bit; - reg = rcar_pin_to_bias_reg(pfc, pin, &bit); + reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); if (!reg) return reg; @@ -3144,7 +3138,7 @@ static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, sh_pfc_write(pfc, reg->puen, enable); } -static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77995_pfc_ops = { .pin_to_pocctrl = r8a77995_pin_to_pocctrl, .get_bias = r8a77995_pinmux_get_bias, .set_bias = r8a77995_pinmux_set_bias, @@ -3152,7 +3146,7 @@ static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { const struct sh_pfc_soc_info r8a77995_pinmux_info = { .name = "r8a77995_pfc", - .ops = &r8a77995_pinmux_ops, + .ops = &r8a77995_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index 83580385c3ca..4a668a04b7ca 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -576,23 +576,23 @@ FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2 FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ -#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) -#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) -#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) -#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) -#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) -#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) -#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) +#define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) +#define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) +#define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) +#define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) +#define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) +#define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) +#define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) #define PINMUX_MOD_SELS \ \ -MOD_SEL2_14_15 \ -MOD_SEL2_12_13 \ -MOD_SEL2_10_11 \ -MOD_SEL2_8_9 \ -MOD_SEL2_6_7 \ -MOD_SEL2_4_5 \ -MOD_SEL2_2_3 +MOD_SEL2_15_14 \ +MOD_SEL2_13_12 \ +MOD_SEL2_11_10 \ +MOD_SEL2_9_8 \ +MOD_SEL2_7_6 \ +MOD_SEL2_5_4 \ +MOD_SEL2_3_2 #define PINMUX_PHYS \ FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ @@ -2009,30 +2009,14 @@ static const unsigned int intc_ex_irq5_mux[] = { }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* MMC_SD_D0 */ - RCAR_GP_PIN(0, 19), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_SD_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* MMC_SD_D[0:3] */ - RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), - RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_SD_D0_MARK, MMC_SD_D1_MARK, - MMC_SD_D2_MARK, MMC_SD_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* MMC_SD_D[0:3], MMC_D[4:7] */ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_SD_D0_MARK, MMC_SD_D1_MARK, MMC_SD_D2_MARK, MMC_SD_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -2384,19 +2368,12 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK }; @@ -2409,19 +2386,12 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK }; @@ -2715,9 +2685,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), @@ -2767,11 +2737,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm4), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), @@ -3696,13 +3666,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* RESERVED 19, 18, 17, 16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_14_15 - MOD_SEL2_12_13 - MOD_SEL2_10_11 - MOD_SEL2_8_9 - MOD_SEL2_6_7 - MOD_SEL2_4_5 - MOD_SEL2_2_3 + MOD_SEL2_15_14 + MOD_SEL2_13_12 + MOD_SEL2_11_10 + MOD_SEL2_9_8 + MOD_SEL2_7_6 + MOD_SEL2_5_4 + MOD_SEL2_3_2 0, 0, 0, 0, )) }, @@ -4041,8 +4011,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; @@ -4429,7 +4398,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations pinmux_ops = { +static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = { .pin_to_pocctrl = r8a779a0_pin_to_pocctrl, .get_bias = rcar_pinmux_get_bias, .set_bias = rcar_pinmux_set_bias, @@ -4437,7 +4406,7 @@ static const struct sh_pfc_soc_operations pinmux_ops = { const struct sh_pfc_soc_info r8a779a0_pinmux_info = { .name = "r8a779a0_pfc", - .ops = &pinmux_ops, + .ops = &r8a779a0_pfc_ops, .unlock_reg = 0x1ff, /* PMMRn mask */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c new file mode 100644 index 000000000000..91860608242c --- /dev/null +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c @@ -0,0 +1,2126 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * R8A779F0 processor support - PFC hardware block. + * + * Copyright (C) 2021 Renesas Electronics Corp. + * + * This file is based on the drivers/pinctrl/renesas/pfc-r8a779a0.c + */ + +#include +#include +#include + +#include "sh_pfc.h" + +#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_GP(fn, sfx) \ + PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS), \ + PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +/* + * F_() : just information + * FM() : macro for FN_xxx / xxx_MARK + */ + +/* GPSR0 */ +#define GPSR0_20 F_(IRQ3, IP2SR0_19_16) +#define GPSR0_19 F_(IRQ2, IP2SR0_15_12) +#define GPSR0_18 F_(IRQ1, IP2SR0_11_8) +#define GPSR0_17 F_(IRQ0, IP2SR0_7_4) +#define GPSR0_16 F_(MSIOF0_SS2, IP2SR0_3_0) +#define GPSR0_15 F_(MSIOF0_SS1, IP1SR0_31_28) +#define GPSR0_14 F_(MSIOF0_SCK, IP1SR0_27_24) +#define GPSR0_13 F_(MSIOF0_TXD, IP1SR0_23_20) +#define GPSR0_12 F_(MSIOF0_RXD, IP1SR0_19_16) +#define GPSR0_11 F_(MSIOF0_SYNC, IP1SR0_15_12) +#define GPSR0_10 F_(CTS0_N, IP1SR0_11_8) +#define GPSR0_9 F_(RTS0_N, IP1SR0_7_4) +#define GPSR0_8 F_(SCK0, IP1SR0_3_0) +#define GPSR0_7 F_(TX0, IP0SR0_31_28) +#define GPSR0_6 F_(RX0, IP0SR0_27_24) +#define GPSR0_5 F_(HRTS0_N, IP0SR0_23_20) +#define GPSR0_4 F_(HCTS0_N, IP0SR0_19_16) +#define GPSR0_3 F_(HTX0, IP0SR0_15_12) +#define GPSR0_2 F_(HRX0, IP0SR0_11_8) +#define GPSR0_1 F_(HSCK0, IP0SR0_7_4) +#define GPSR0_0 F_(SCIF_CLK, IP0SR0_3_0) + +/* GPSR1 */ +#define GPSR1_24 FM(SD_WP) +#define GPSR1_23 FM(SD_CD) +#define GPSR1_22 FM(MMC_SD_CMD) +#define GPSR1_21 FM(MMC_D7) +#define GPSR1_20 FM(MMC_DS) +#define GPSR1_19 FM(MMC_D6) +#define GPSR1_18 FM(MMC_D4) +#define GPSR1_17 FM(MMC_D5) +#define GPSR1_16 FM(MMC_SD_D3) +#define GPSR1_15 FM(MMC_SD_D2) +#define GPSR1_14 FM(MMC_SD_D1) +#define GPSR1_13 FM(MMC_SD_D0) +#define GPSR1_12 FM(MMC_SD_CLK) +#define GPSR1_11 FM(GP1_11) +#define GPSR1_10 FM(GP1_10) +#define GPSR1_9 FM(GP1_09) +#define GPSR1_8 FM(GP1_08) +#define GPSR1_7 F_(GP1_07, IP0SR1_31_28) +#define GPSR1_6 F_(GP1_06, IP0SR1_27_24) +#define GPSR1_5 F_(GP1_05, IP0SR1_23_20) +#define GPSR1_4 F_(GP1_04, IP0SR1_19_16) +#define GPSR1_3 F_(GP1_03, IP0SR1_15_12) +#define GPSR1_2 F_(GP1_02, IP0SR1_11_8) +#define GPSR1_1 F_(GP1_01, IP0SR1_7_4) +#define GPSR1_0 F_(GP1_00, IP0SR1_3_0) + +/* GPSR2 */ +#define GPSR2_16 FM(PCIE1_CLKREQ_N) +#define GPSR2_15 FM(PCIE0_CLKREQ_N) +#define GPSR2_14 FM(QSPI0_IO3) +#define GPSR2_13 FM(QSPI0_SSL) +#define GPSR2_12 FM(QSPI0_MISO_IO1) +#define GPSR2_11 FM(QSPI0_IO2) +#define GPSR2_10 FM(QSPI0_SPCLK) +#define GPSR2_9 FM(QSPI0_MOSI_IO0) +#define GPSR2_8 FM(QSPI1_SPCLK) +#define GPSR2_7 FM(QSPI1_MOSI_IO0) +#define GPSR2_6 FM(QSPI1_IO2) +#define GPSR2_5 FM(QSPI1_MISO_IO1) +#define GPSR2_4 FM(QSPI1_IO3) +#define GPSR2_3 FM(QSPI1_SSL) +#define GPSR2_2 FM(RPC_RESET_N) +#define GPSR2_1 FM(RPC_WP_N) +#define GPSR2_0 FM(RPC_INT_N) + +/* GPSR3 */ +#define GPSR3_18 FM(TSN0_AVTP_CAPTURE_B) +#define GPSR3_17 FM(TSN0_AVTP_MATCH_B) +#define GPSR3_16 FM(TSN0_AVTP_PPS) +#define GPSR3_15 FM(TSN1_AVTP_CAPTURE_B) +#define GPSR3_14 FM(TSN1_AVTP_MATCH_B) +#define GPSR3_13 FM(TSN1_AVTP_PPS) +#define GPSR3_12 FM(TSN0_MAGIC_B) +#define GPSR3_11 FM(TSN1_PHY_INT_B) +#define GPSR3_10 FM(TSN0_PHY_INT_B) +#define GPSR3_9 FM(TSN2_PHY_INT_B) +#define GPSR3_8 FM(TSN0_LINK_B) +#define GPSR3_7 FM(TSN2_LINK_B) +#define GPSR3_6 FM(TSN1_LINK_B) +#define GPSR3_5 FM(TSN1_MDC_B) +#define GPSR3_4 FM(TSN0_MDC_B) +#define GPSR3_3 FM(TSN2_MDC_B) +#define GPSR3_2 FM(TSN0_MDIO_B) +#define GPSR3_1 FM(TSN2_MDIO_B) +#define GPSR3_0 FM(TSN1_MDIO_B) + +/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ +#define IP0SR0_3_0 FM(SCIF_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_7_4 FM(HSCK0) FM(SCK3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_11_8 FM(HRX0) FM(RX3) FM(MSIOF3_RXD) F_(0, 0) F_(0, 0) FM(TSN0_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_15_12 FM(HTX0) FM(TX3) FM(MSIOF3_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_19_16 FM(HCTS0_N) FM(CTS3_N) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) FM(TSN0_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_23_20 FM(HRTS0_N) FM(RTS3_N) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) FM(TSN0_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_27_24 FM(RX0) FM(HRX1) F_(0, 0) FM(MSIOF1_RXD) F_(0, 0) FM(TSN1_AVTP_MATCH_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR0_31_28 FM(TX0) FM(HTX1) F_(0, 0) FM(MSIOF1_TXD) F_(0, 0) FM(TSN1_AVTP_CAPTURE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP1SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ +#define IP1SR0_3_0 FM(SCK0) FM(HSCK1) F_(0, 0) FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_7_4 FM(RTS0_N) FM(HRTS1_N) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) FM(TSN1_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_11_8 FM(CTS0_N) FM(HCTS1_N) F_(0, 0) FM(MSIOF1_SYNC) F_(0, 0) FM(TSN1_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_15_12 FM(MSIOF0_SYNC) FM(HCTS3_N) FM(CTS1_N) FM(IRQ4) F_(0, 0) FM(TSN0_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_19_16 FM(MSIOF0_RXD) FM(HRX3) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_23_20 FM(MSIOF0_TXD) FM(HTX3) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_27_24 FM(MSIOF0_SCK) FM(HSCK3) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1SR0_31_28 FM(MSIOF0_SS1) FM(HRTS3_N) FM(RTS1_N) FM(IRQ5) F_(0, 0) FM(TSN1_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +/* IP2SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ +#define IP2SR0_3_0 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_LINK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_7_4 FM(IRQ0) F_(0, 0) F_(0, 0) FM(MSIOF1_SS1) F_(0, 0) FM(TSN0_MAGIC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_11_8 FM(IRQ1) F_(0, 0) F_(0, 0) FM(MSIOF1_SS2) F_(0, 0) FM(TSN0_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_15_12 FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN1_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_19_16 FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TSN2_PHY_INT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP2SR0_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 - F */ +#define IP0SR1_3_0 FM(GP1_00) FM(TCLK1) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_7_4 FM(GP1_01) FM(TCLK4) FM(HRX2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_11_8 FM(GP1_02) F_(0, 0) FM(HTX2) FM(MSIOF2_SS1) F_(0, 0) FM(TSN2_MDC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_15_12 FM(GP1_03) FM(TCLK2) FM(HCTS2_N) FM(MSIOF2_SS2) FM(CTS4_N) FM(TSN2_MDIO_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_19_16 FM(GP1_04) FM(TCLK3) FM(HRTS2_N) FM(MSIOF2_SYNC) FM(RTS4_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_23_20 FM(GP1_05) FM(MSIOF2_SCK) FM(SCK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_27_24 FM(GP1_06) FM(MSIOF2_RXD) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP0SR1_31_28 FM(GP1_07) FM(MSIOF2_TXD) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) + +#define PINMUX_GPSR \ + GPSR1_24 \ + GPSR1_23 \ + GPSR1_22 \ + GPSR1_21 \ +GPSR0_20 GPSR1_20 \ +GPSR0_19 GPSR1_19 \ +GPSR0_18 GPSR1_18 GPSR3_18 \ +GPSR0_17 GPSR1_17 GPSR3_17 \ +GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \ +GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \ +GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 \ +GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 \ +GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 \ +GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 \ +GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 \ +GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 \ +GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 \ +GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 \ +GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 \ +GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 \ +GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 \ +GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 \ +GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 \ +GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 \ +GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 + +#define PINMUX_IPSR \ +\ +FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \ +FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \ +FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \ +FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 FM(IP2SR0_15_12) IP2SR0_15_12 \ +FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 FM(IP2SR0_19_16) IP2SR0_19_16 \ +FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 FM(IP2SR0_23_20) IP2SR0_23_20 \ +FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 FM(IP2SR0_27_24) IP2SR0_27_24 \ +FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 FM(IP2SR0_31_28) IP2SR0_31_28 \ +\ +FM(IP0SR1_3_0) IP0SR1_3_0 \ +FM(IP0SR1_7_4) IP0SR1_7_4 \ +FM(IP0SR1_11_8) IP0SR1_11_8 \ +FM(IP0SR1_15_12) IP0SR1_15_12 \ +FM(IP0SR1_19_16) IP0SR1_19_16 \ +FM(IP0SR1_23_20) IP0SR1_23_20 \ +FM(IP0SR1_27_24) IP0SR1_27_24 \ +FM(IP0SR1_31_28) IP0SR1_31_28 + +/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ +#define MOD_SEL1_11_10 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) +#define MOD_SEL1_9_8 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) +#define MOD_SEL1_7_6 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) +#define MOD_SEL1_5_4 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) +#define MOD_SEL1_3_2 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) +#define MOD_SEL1_1_0 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) + +#define PINMUX_MOD_SELS \ +\ +MOD_SEL1_11_10 \ +MOD_SEL1_9_8 \ +MOD_SEL1_7_6 \ +MOD_SEL1_5_4 \ +MOD_SEL1_3_2 \ +MOD_SEL1_1_0 + +#define PINMUX_PHYS \ + FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ + FM(SCL4) FM(SDA4) FM(SCL5) FM(SDA5) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + +#define F_(x, y) +#define FM(x) FN_##x, + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_FUNCTION_END, +#undef F_ +#undef FM + +#define F_(x, y) +#define FM(x) x##_MARK, + PINMUX_MARK_BEGIN, + PINMUX_GPSR + PINMUX_IPSR + PINMUX_MOD_SELS + PINMUX_PHYS + PINMUX_MARK_END, +#undef F_ +#undef FM +}; + +static const u16 pinmux_data[] = { + PINMUX_DATA_GP_ALL(), + + PINMUX_SINGLE(SD_WP), + PINMUX_SINGLE(SD_CD), + PINMUX_SINGLE(MMC_SD_CMD), + PINMUX_SINGLE(MMC_D7), + PINMUX_SINGLE(MMC_DS), + PINMUX_SINGLE(MMC_D6), + PINMUX_SINGLE(MMC_D4), + PINMUX_SINGLE(MMC_D5), + PINMUX_SINGLE(MMC_SD_D3), + PINMUX_SINGLE(MMC_SD_D2), + PINMUX_SINGLE(MMC_SD_D1), + PINMUX_SINGLE(MMC_SD_D0), + PINMUX_SINGLE(MMC_SD_CLK), + PINMUX_SINGLE(PCIE1_CLKREQ_N), + PINMUX_SINGLE(PCIE0_CLKREQ_N), + PINMUX_SINGLE(QSPI0_IO3), + PINMUX_SINGLE(QSPI0_SSL), + PINMUX_SINGLE(QSPI0_MISO_IO1), + PINMUX_SINGLE(QSPI0_IO2), + PINMUX_SINGLE(QSPI0_SPCLK), + PINMUX_SINGLE(QSPI0_MOSI_IO0), + PINMUX_SINGLE(QSPI1_SPCLK), + PINMUX_SINGLE(QSPI1_MOSI_IO0), + PINMUX_SINGLE(QSPI1_IO2), + PINMUX_SINGLE(QSPI1_MISO_IO1), + PINMUX_SINGLE(QSPI1_IO3), + PINMUX_SINGLE(QSPI1_SSL), + PINMUX_SINGLE(RPC_RESET_N), + PINMUX_SINGLE(RPC_WP_N), + PINMUX_SINGLE(RPC_INT_N), + + PINMUX_SINGLE(TSN0_AVTP_CAPTURE_B), + PINMUX_SINGLE(TSN0_AVTP_MATCH_B), + PINMUX_SINGLE(TSN0_AVTP_PPS), + PINMUX_SINGLE(TSN1_AVTP_CAPTURE_B), + PINMUX_SINGLE(TSN1_AVTP_MATCH_B), + PINMUX_SINGLE(TSN1_AVTP_PPS), + PINMUX_SINGLE(TSN0_MAGIC_B), + PINMUX_SINGLE(TSN1_PHY_INT_B), + PINMUX_SINGLE(TSN0_PHY_INT_B), + PINMUX_SINGLE(TSN2_PHY_INT_B), + PINMUX_SINGLE(TSN0_LINK_B), + PINMUX_SINGLE(TSN2_LINK_B), + PINMUX_SINGLE(TSN1_LINK_B), + PINMUX_SINGLE(TSN1_MDC_B), + PINMUX_SINGLE(TSN0_MDC_B), + PINMUX_SINGLE(TSN2_MDC_B), + PINMUX_SINGLE(TSN0_MDIO_B), + PINMUX_SINGLE(TSN2_MDIO_B), + PINMUX_SINGLE(TSN1_MDIO_B), + + /* IP0SR0 */ + PINMUX_IPSR_GPSR(IP0SR0_3_0, SCIF_CLK), + + PINMUX_IPSR_GPSR(IP0SR0_7_4, HSCK0), + PINMUX_IPSR_GPSR(IP0SR0_7_4, SCK3), + PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SCK), + PINMUX_IPSR_GPSR(IP0SR0_7_4, TSN0_AVTP_CAPTURE_A), + + PINMUX_IPSR_GPSR(IP0SR0_11_8, HRX0), + PINMUX_IPSR_GPSR(IP0SR0_11_8, RX3), + PINMUX_IPSR_GPSR(IP0SR0_11_8, MSIOF3_RXD), + PINMUX_IPSR_GPSR(IP0SR0_11_8, TSN0_AVTP_MATCH_A), + + PINMUX_IPSR_GPSR(IP0SR0_15_12, HTX0), + PINMUX_IPSR_GPSR(IP0SR0_15_12, TX3), + PINMUX_IPSR_GPSR(IP0SR0_15_12, MSIOF3_TXD), + + PINMUX_IPSR_GPSR(IP0SR0_19_16, HCTS0_N), + PINMUX_IPSR_GPSR(IP0SR0_19_16, CTS3_N), + PINMUX_IPSR_GPSR(IP0SR0_19_16, MSIOF3_SS1), + PINMUX_IPSR_GPSR(IP0SR0_19_16, TSN0_MDC_A), + + PINMUX_IPSR_GPSR(IP0SR0_23_20, HRTS0_N), + PINMUX_IPSR_GPSR(IP0SR0_23_20, RTS3_N), + PINMUX_IPSR_GPSR(IP0SR0_23_20, MSIOF3_SS2), + PINMUX_IPSR_GPSR(IP0SR0_23_20, TSN0_MDIO_A), + + PINMUX_IPSR_GPSR(IP0SR0_27_24, RX0), + PINMUX_IPSR_GPSR(IP0SR0_27_24, HRX1), + PINMUX_IPSR_GPSR(IP0SR0_27_24, MSIOF1_RXD), + PINMUX_IPSR_GPSR(IP0SR0_27_24, TSN1_AVTP_MATCH_A), + + PINMUX_IPSR_GPSR(IP0SR0_31_28, TX0), + PINMUX_IPSR_GPSR(IP0SR0_31_28, HTX1), + PINMUX_IPSR_GPSR(IP0SR0_31_28, MSIOF1_TXD), + PINMUX_IPSR_GPSR(IP0SR0_31_28, TSN1_AVTP_CAPTURE_A), + + /* IP1SR0 */ + PINMUX_IPSR_GPSR(IP1SR0_3_0, SCK0), + PINMUX_IPSR_GPSR(IP1SR0_3_0, HSCK1), + PINMUX_IPSR_GPSR(IP1SR0_3_0, MSIOF1_SCK), + + PINMUX_IPSR_GPSR(IP1SR0_7_4, RTS0_N), + PINMUX_IPSR_GPSR(IP1SR0_7_4, HRTS1_N), + PINMUX_IPSR_GPSR(IP1SR0_7_4, MSIOF3_SYNC), + PINMUX_IPSR_GPSR(IP1SR0_7_4, TSN1_MDIO_A), + + PINMUX_IPSR_GPSR(IP1SR0_11_8, CTS0_N), + PINMUX_IPSR_GPSR(IP1SR0_11_8, HCTS1_N), + PINMUX_IPSR_GPSR(IP1SR0_11_8, MSIOF1_SYNC), + PINMUX_IPSR_GPSR(IP1SR0_11_8, TSN1_MDC_A), + + PINMUX_IPSR_GPSR(IP1SR0_15_12, MSIOF0_SYNC), + PINMUX_IPSR_GPSR(IP1SR0_15_12, HCTS3_N), + PINMUX_IPSR_GPSR(IP1SR0_15_12, CTS1_N), + PINMUX_IPSR_GPSR(IP1SR0_15_12, IRQ4), + PINMUX_IPSR_GPSR(IP1SR0_15_12, TSN0_LINK_A), + + PINMUX_IPSR_GPSR(IP1SR0_19_16, MSIOF0_RXD), + PINMUX_IPSR_GPSR(IP1SR0_19_16, HRX3), + PINMUX_IPSR_GPSR(IP1SR0_19_16, RX1), + + PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF0_TXD), + PINMUX_IPSR_GPSR(IP1SR0_23_20, HTX3), + PINMUX_IPSR_GPSR(IP1SR0_23_20, TX1), + + PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF0_SCK), + PINMUX_IPSR_GPSR(IP1SR0_27_24, HSCK3), + PINMUX_IPSR_GPSR(IP1SR0_27_24, SCK1), + + PINMUX_IPSR_GPSR(IP1SR0_31_28, MSIOF0_SS1), + PINMUX_IPSR_GPSR(IP1SR0_31_28, HRTS3_N), + PINMUX_IPSR_GPSR(IP1SR0_31_28, RTS1_N), + PINMUX_IPSR_GPSR(IP1SR0_31_28, IRQ5), + PINMUX_IPSR_GPSR(IP1SR0_31_28, TSN1_LINK_A), + + /* IP2SR0 */ + PINMUX_IPSR_GPSR(IP2SR0_3_0, MSIOF0_SS2), + PINMUX_IPSR_GPSR(IP2SR0_3_0, TSN2_LINK_A), + + PINMUX_IPSR_GPSR(IP2SR0_7_4, IRQ0), + PINMUX_IPSR_GPSR(IP2SR0_7_4, MSIOF1_SS1), + PINMUX_IPSR_GPSR(IP2SR0_7_4, TSN0_MAGIC_A), + + PINMUX_IPSR_GPSR(IP2SR0_11_8, IRQ1), + PINMUX_IPSR_GPSR(IP2SR0_11_8, MSIOF1_SS2), + PINMUX_IPSR_GPSR(IP2SR0_11_8, TSN0_PHY_INT_A), + + PINMUX_IPSR_GPSR(IP2SR0_15_12, IRQ2), + PINMUX_IPSR_GPSR(IP2SR0_15_12, TSN1_PHY_INT_A), + + PINMUX_IPSR_GPSR(IP2SR0_19_16, IRQ3), + PINMUX_IPSR_GPSR(IP2SR0_19_16, TSN2_PHY_INT_A), + + /* IP0SR1 */ + /* GP1_00 = SCL0 */ + PINMUX_IPSR_MSEL(IP0SR1_3_0, GP1_00, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR1_3_0, TCLK1, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR1_3_0, HSCK2, SEL_I2C0_0), + PINMUX_IPSR_PHYS(IP0SR1_3_0, SCL0, SEL_I2C0_3), + + /* GP1_01 = SDA0 */ + PINMUX_IPSR_MSEL(IP0SR1_7_4, GP1_01, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR1_7_4, TCLK4, SEL_I2C0_0), + PINMUX_IPSR_MSEL(IP0SR1_7_4, HRX2, SEL_I2C0_0), + PINMUX_IPSR_PHYS(IP0SR1_7_4, SDA0, SEL_I2C0_3), + + /* GP1_02 = SCL1 */ + PINMUX_IPSR_MSEL(IP0SR1_11_8, GP1_02, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_11_8, HTX2, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_11_8, MSIOF2_SS1, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_11_8, TSN2_MDC_A, SEL_I2C1_0), + PINMUX_IPSR_PHYS(IP0SR1_11_8, SCL1, SEL_I2C1_3), + + /* GP1_03 = SDA1 */ + PINMUX_IPSR_MSEL(IP0SR1_15_12, GP1_03, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, TCLK2, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, HCTS2_N, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, MSIOF2_SS2, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, CTS4_N, SEL_I2C1_0), + PINMUX_IPSR_MSEL(IP0SR1_15_12, TSN2_MDIO_A, SEL_I2C1_0), + PINMUX_IPSR_PHYS(IP0SR1_15_12, SDA1, SEL_I2C1_3), + + /* GP1_04 = SCL2 */ + PINMUX_IPSR_MSEL(IP0SR1_19_16, GP1_04, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_19_16, TCLK3, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_19_16, HRTS2_N, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_19_16, MSIOF2_SYNC, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_19_16, RTS4_N, SEL_I2C2_0), + PINMUX_IPSR_PHYS(IP0SR1_19_16, SCL2, SEL_I2C2_3), + + /* GP1_05 = SDA2 */ + PINMUX_IPSR_MSEL(IP0SR1_23_20, GP1_05, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_23_20, MSIOF2_SCK, SEL_I2C2_0), + PINMUX_IPSR_MSEL(IP0SR1_23_20, SCK4, SEL_I2C2_0), + PINMUX_IPSR_PHYS(IP0SR1_23_20, SDA2, SEL_I2C2_3), + + /* GP1_06 = SCL3 */ + PINMUX_IPSR_MSEL(IP0SR1_27_24, GP1_06, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP0SR1_27_24, MSIOF2_RXD, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP0SR1_27_24, RX4, SEL_I2C3_0), + PINMUX_IPSR_PHYS(IP0SR1_27_24, SCL3, SEL_I2C3_3), + + /* GP1_07 = SDA3 */ + PINMUX_IPSR_MSEL(IP0SR1_31_28, GP1_07, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP0SR1_31_28, MSIOF2_TXD, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP0SR1_31_28, TX4, SEL_I2C3_0), + PINMUX_IPSR_PHYS(IP0SR1_31_28, SDA3, SEL_I2C3_3), + + /* GP1_08 = SCL4 */ + PINMUX_IPSR_NOGM(0, GP1_08, SEL_I2C4_0), + PINMUX_IPSR_NOFN(GP1_08, SCL4, SEL_I2C4_3), + + /* GP1_09 = SDA4 */ + PINMUX_IPSR_NOGM(0, GP1_09, SEL_I2C4_0), + PINMUX_IPSR_NOFN(GP1_09, SDA4, SEL_I2C4_3), + + /* GP1_10 = SCL5 */ + PINMUX_IPSR_NOGM(0, GP1_10, SEL_I2C5_0), + PINMUX_IPSR_NOFN(GP1_10, SCL5, SEL_I2C5_3), + + /* GP1_11 = SDA5 */ + PINMUX_IPSR_NOGM(0, GP1_11, SEL_I2C5_0), + PINMUX_IPSR_NOFN(GP1_11, SDA5, SEL_I2C5_3), +}; + +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + +static const struct sh_pfc_pin pinmux_pins[] = { + PINMUX_GPIO_GP_ALL(), +}; + +/* - HSCIF0 ----------------------------------------------------------------- */ +static const unsigned int hscif0_data_pins[] = { + /* HRX0, HTX0 */ + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), +}; +static const unsigned int hscif0_data_mux[] = { + HRX0_MARK, HTX0_MARK, +}; +static const unsigned int hscif0_clk_pins[] = { + /* HSCK0 */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int hscif0_clk_mux[] = { + HSCK0_MARK, +}; +static const unsigned int hscif0_ctrl_pins[] = { + /* HRTS0#, HCTS0# */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), +}; +static const unsigned int hscif0_ctrl_mux[] = { + HRTS0_N_MARK, HCTS0_N_MARK, +}; + +/* - HSCIF1 ----------------------------------------------------------------- */ +static const unsigned int hscif1_data_pins[] = { + /* HRX1, HTX1 */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int hscif1_data_mux[] = { + HRX1_MARK, HTX1_MARK, +}; +static const unsigned int hscif1_clk_pins[] = { + /* HSCK1 */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int hscif1_clk_mux[] = { + HSCK1_MARK, +}; +static const unsigned int hscif1_ctrl_pins[] = { + /* HRTS1#, HCTS1# */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int hscif1_ctrl_mux[] = { + HRTS1_N_MARK, HCTS1_N_MARK, +}; + +/* - HSCIF2 ----------------------------------------------------------------- */ +static const unsigned int hscif2_data_pins[] = { + /* HRX2, HTX2 */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), +}; +static const unsigned int hscif2_data_mux[] = { + HRX2_MARK, HTX2_MARK, +}; +static const unsigned int hscif2_clk_pins[] = { + /* HSCK2 */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int hscif2_clk_mux[] = { + HSCK2_MARK, +}; +static const unsigned int hscif2_ctrl_pins[] = { + /* HRTS2#, HCTS2# */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), +}; +static const unsigned int hscif2_ctrl_mux[] = { + HRTS2_N_MARK, HCTS2_N_MARK, +}; + +/* - HSCIF3 ----------------------------------------------------------------- */ +static const unsigned int hscif3_data_pins[] = { + /* HRX3, HTX3 */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; +static const unsigned int hscif3_data_mux[] = { + HRX3_MARK, HTX3_MARK, +}; +static const unsigned int hscif3_clk_pins[] = { + /* HSCK3 */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int hscif3_clk_mux[] = { + HSCK3_MARK, +}; +static const unsigned int hscif3_ctrl_pins[] = { + /* HRTS3#, HCTS3# */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), +}; +static const unsigned int hscif3_ctrl_mux[] = { + HRTS3_N_MARK, HCTS3_N_MARK, +}; + +/* - I2C0 ------------------------------------------------------------------- */ +static const unsigned int i2c0_pins[] = { + /* SDA0, SCL0 */ + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), +}; +static const unsigned int i2c0_mux[] = { + SDA0_MARK, SCL0_MARK, +}; + +/* - I2C1 ------------------------------------------------------------------- */ +static const unsigned int i2c1_pins[] = { + /* SDA1, SCL1 */ + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), +}; +static const unsigned int i2c1_mux[] = { + SDA1_MARK, SCL1_MARK, +}; + +/* - I2C2 ------------------------------------------------------------------- */ +static const unsigned int i2c2_pins[] = { + /* SDA2, SCL2 */ + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), +}; +static const unsigned int i2c2_mux[] = { + SDA2_MARK, SCL2_MARK, +}; + +/* - I2C3 ------------------------------------------------------------------- */ +static const unsigned int i2c3_pins[] = { + /* SDA3, SCL3 */ + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), +}; +static const unsigned int i2c3_mux[] = { + SDA3_MARK, SCL3_MARK, +}; + +/* - I2C4 ------------------------------------------------------------------- */ +static const unsigned int i2c4_pins[] = { + /* SDA4, SCL4 */ + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), +}; +static const unsigned int i2c4_mux[] = { + SDA4_MARK, SCL4_MARK, +}; + +/* - I2C5 ------------------------------------------------------------------- */ +static const unsigned int i2c5_pins[] = { + /* SDA5, SCL5 */ + RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), +}; +static const unsigned int i2c5_mux[] = { + SDA5_MARK, SCL5_MARK, +}; + + +/* - INTC-EX ---------------------------------------------------------------- */ +static const unsigned int intc_ex_irq0_pins[] = { + /* IRQ0 */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int intc_ex_irq0_mux[] = { + IRQ0_MARK, +}; +static const unsigned int intc_ex_irq1_pins[] = { + /* IRQ1 */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int intc_ex_irq1_mux[] = { + IRQ1_MARK, +}; +static const unsigned int intc_ex_irq2_pins[] = { + /* IRQ2 */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int intc_ex_irq2_mux[] = { + IRQ2_MARK, +}; +static const unsigned int intc_ex_irq3_pins[] = { + /* IRQ3 */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int intc_ex_irq3_mux[] = { + IRQ3_MARK, +}; +static const unsigned int intc_ex_irq4_pins[] = { + /* IRQ4 */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int intc_ex_irq4_mux[] = { + IRQ4_MARK, +}; +static const unsigned int intc_ex_irq5_pins[] = { + /* IRQ5 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int intc_ex_irq5_mux[] = { + IRQ5_MARK, +}; + +/* - MMC -------------------------------------------------------------------- */ +static const unsigned int mmc_data_pins[] = { + /* MMC_SD_D[0:3], MMC_D[4:7] */ + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21), +}; +static const unsigned int mmc_data_mux[] = { + MMC_SD_D0_MARK, MMC_SD_D1_MARK, + MMC_SD_D2_MARK, MMC_SD_D3_MARK, + MMC_D4_MARK, MMC_D5_MARK, + MMC_D6_MARK, MMC_D7_MARK, +}; +static const unsigned int mmc_ctrl_pins[] = { + /* MMC_SD_CLK, MMC_SD_CMD */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22), +}; +static const unsigned int mmc_ctrl_mux[] = { + MMC_SD_CLK_MARK, MMC_SD_CMD_MARK, +}; +static const unsigned int mmc_cd_pins[] = { + /* SD_CD */ + RCAR_GP_PIN(1, 23), +}; +static const unsigned int mmc_cd_mux[] = { + SD_CD_MARK, +}; +static const unsigned int mmc_wp_pins[] = { + /* SD_WP */ + RCAR_GP_PIN(1, 24), +}; +static const unsigned int mmc_wp_mux[] = { + SD_WP_MARK, +}; +static const unsigned int mmc_ds_pins[] = { + /* MMC_DS */ + RCAR_GP_PIN(1, 20), +}; +static const unsigned int mmc_ds_mux[] = { + MMC_DS_MARK, +}; + +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* MSIOF0_SCK */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* MSIOF0_SYNC */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_ss1_pins[] = { + /* MSIOF0_SS1 */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int msiof0_ss1_mux[] = { + MSIOF0_SS1_MARK, +}; +static const unsigned int msiof0_ss2_pins[] = { + /* MSIOF0_SS2 */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int msiof0_ss2_mux[] = { + MSIOF0_SS2_MARK, +}; +static const unsigned int msiof0_txd_pins[] = { + /* MSIOF0_TXD */ + RCAR_GP_PIN(0, 13), +}; +static const unsigned int msiof0_txd_mux[] = { + MSIOF0_TXD_MARK, +}; +static const unsigned int msiof0_rxd_pins[] = { + /* MSIOF0_RXD */ + RCAR_GP_PIN(0, 12), +}; +static const unsigned int msiof0_rxd_mux[] = { + MSIOF0_RXD_MARK, +}; + +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* MSIOF1_SCK */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* MSIOF1_SYNC */ + RCAR_GP_PIN(0, 10), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_ss1_pins[] = { + /* MSIOF1_SS1 */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int msiof1_ss1_mux[] = { + MSIOF1_SS1_MARK, +}; +static const unsigned int msiof1_ss2_pins[] = { + /* MSIOF1_SS2 */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int msiof1_ss2_mux[] = { + MSIOF1_SS2_MARK, +}; +static const unsigned int msiof1_txd_pins[] = { + /* MSIOF1_TXD */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int msiof1_txd_mux[] = { + MSIOF1_TXD_MARK, +}; +static const unsigned int msiof1_rxd_pins[] = { + /* MSIOF1_RXD */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int msiof1_rxd_mux[] = { + MSIOF1_RXD_MARK, +}; + +/* - MSIOF2 ----------------------------------------------------------------- */ +static const unsigned int msiof2_clk_pins[] = { + /* MSIOF2_SCK */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int msiof2_clk_mux[] = { + MSIOF2_SCK_MARK, +}; +static const unsigned int msiof2_sync_pins[] = { + /* MSIOF2_SYNC */ + RCAR_GP_PIN(1, 4), +}; +static const unsigned int msiof2_sync_mux[] = { + MSIOF2_SYNC_MARK, +}; +static const unsigned int msiof2_ss1_pins[] = { + /* MSIOF2_SS1 */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int msiof2_ss1_mux[] = { + MSIOF2_SS1_MARK, +}; +static const unsigned int msiof2_ss2_pins[] = { + /* MSIOF2_SS2 */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int msiof2_ss2_mux[] = { + MSIOF2_SS2_MARK, +}; +static const unsigned int msiof2_txd_pins[] = { + /* MSIOF2_TXD */ + RCAR_GP_PIN(1, 7), +}; +static const unsigned int msiof2_txd_mux[] = { + MSIOF2_TXD_MARK, +}; +static const unsigned int msiof2_rxd_pins[] = { + /* MSIOF2_RXD */ + RCAR_GP_PIN(1, 6), +}; +static const unsigned int msiof2_rxd_mux[] = { + MSIOF2_RXD_MARK, +}; + +/* - MSIOF3 ----------------------------------------------------------------- */ +static const unsigned int msiof3_clk_pins[] = { + /* MSIOF3_SCK */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int msiof3_clk_mux[] = { + MSIOF3_SCK_MARK, +}; +static const unsigned int msiof3_sync_pins[] = { + /* MSIOF3_SYNC */ + RCAR_GP_PIN(0, 9), +}; +static const unsigned int msiof3_sync_mux[] = { + MSIOF3_SYNC_MARK, +}; +static const unsigned int msiof3_ss1_pins[] = { + /* MSIOF3_SS1 */ + RCAR_GP_PIN(0, 4), +}; +static const unsigned int msiof3_ss1_mux[] = { + MSIOF3_SS1_MARK, +}; +static const unsigned int msiof3_ss2_pins[] = { + /* MSIOF3_SS2 */ + RCAR_GP_PIN(0, 5), +}; +static const unsigned int msiof3_ss2_mux[] = { + MSIOF3_SS2_MARK, +}; +static const unsigned int msiof3_txd_pins[] = { + /* MSIOF3_TXD */ + RCAR_GP_PIN(0, 3), +}; +static const unsigned int msiof3_txd_mux[] = { + MSIOF3_TXD_MARK, +}; +static const unsigned int msiof3_rxd_pins[] = { + /* MSIOF3_RXD */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int msiof3_rxd_mux[] = { + MSIOF3_RXD_MARK, +}; + +/* - PCIE ------------------------------------------------------------------- */ +static const unsigned int pcie0_clkreq_n_pins[] = { + /* PCIE0_CLKREQ# */ + RCAR_GP_PIN(2, 15), +}; + +static const unsigned int pcie0_clkreq_n_mux[] = { + PCIE0_CLKREQ_N_MARK, +}; + +static const unsigned int pcie1_clkreq_n_pins[] = { + /* PCIE1_CLKREQ# */ + RCAR_GP_PIN(2, 16), +}; + +static const unsigned int pcie1_clkreq_n_mux[] = { + PCIE1_CLKREQ_N_MARK, +}; + +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14), +}; +static const unsigned int qspi0_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK +}; + +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4), +}; +static const unsigned int qspi1_data_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK +}; + +/* - SCIF0 ------------------------------------------------------------------ */ +static const unsigned int scif0_data_pins[] = { + /* RX0, TX0 */ + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; +static const unsigned int scif0_data_mux[] = { + RX0_MARK, TX0_MARK, +}; +static const unsigned int scif0_clk_pins[] = { + /* SCK0 */ + RCAR_GP_PIN(0, 8), +}; +static const unsigned int scif0_clk_mux[] = { + SCK0_MARK, +}; +static const unsigned int scif0_ctrl_pins[] = { + /* RTS0#, CTS0# */ + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), +}; +static const unsigned int scif0_ctrl_mux[] = { + RTS0_N_MARK, CTS0_N_MARK, +}; + +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RX1, TX1 */ + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), +}; +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK1 */ + RCAR_GP_PIN(0, 14), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS1#, CTS1# */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_MARK, CTS1_N_MARK, +}; + +/* - SCIF3 ------------------------------------------------------------------ */ +static const unsigned int scif3_data_pins[] = { + /* RX3, TX3 */ + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), +}; +static const unsigned int scif3_data_mux[] = { + RX3_MARK, TX3_MARK, +}; +static const unsigned int scif3_clk_pins[] = { + /* SCK3 */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int scif3_clk_mux[] = { + SCK3_MARK, +}; +static const unsigned int scif3_ctrl_pins[] = { + /* RTS3#, CTS3# */ + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), +}; +static const unsigned int scif3_ctrl_mux[] = { + RTS3_N_MARK, CTS3_N_MARK, +}; + +/* - SCIF4 ------------------------------------------------------------------ */ +static const unsigned int scif4_data_pins[] = { + /* RX4, TX4 */ + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), +}; +static const unsigned int scif4_data_mux[] = { + RX4_MARK, TX4_MARK, +}; +static const unsigned int scif4_clk_pins[] = { + /* SCK4 */ + RCAR_GP_PIN(1, 5), +}; +static const unsigned int scif4_clk_mux[] = { + SCK4_MARK, +}; +static const unsigned int scif4_ctrl_pins[] = { + /* RTS4#, CTS4# */ + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), +}; +static const unsigned int scif4_ctrl_mux[] = { + RTS4_N_MARK, CTS4_N_MARK, +}; + +/* - SCIF Clock ------------------------------------------------------------- */ +static const unsigned int scif_clk_pins[] = { + /* SCIF_CLK */ + RCAR_GP_PIN(0, 0), +}; +static const unsigned int scif_clk_mux[] = { + SCIF_CLK_MARK, +}; + +/* - TSN0 ------------------------------------------------ */ +static const unsigned int tsn0_link_a_pins[] = { + /* TSN0_LINK_A */ + RCAR_GP_PIN(0, 11), +}; +static const unsigned int tsn0_link_a_mux[] = { + TSN0_LINK_A_MARK, +}; +static const unsigned int tsn0_magic_a_pins[] = { + /* TSN0_MAGIC_A */ + RCAR_GP_PIN(0, 17), +}; +static const unsigned int tsn0_magic_a_mux[] = { + TSN0_MAGIC_A_MARK, +}; +static const unsigned int tsn0_phy_int_a_pins[] = { + /* TSN0_PHY_INT_A */ + RCAR_GP_PIN(0, 18), +}; +static const unsigned int tsn0_phy_int_a_mux[] = { + TSN0_PHY_INT_A_MARK, +}; +static const unsigned int tsn0_mdio_a_pins[] = { + /* TSN0_MDC_A, TSN0_MDIO_A */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), +}; +static const unsigned int tsn0_mdio_a_mux[] = { + TSN0_MDC_A_MARK, TSN0_MDIO_A_MARK, +}; +static const unsigned int tsn0_link_b_pins[] = { + /* TSN0_LINK_B */ + RCAR_GP_PIN(3, 8), +}; +static const unsigned int tsn0_link_b_mux[] = { + TSN0_LINK_B_MARK, +}; +static const unsigned int tsn0_magic_b_pins[] = { + /* TSN0_MAGIC_B */ + RCAR_GP_PIN(3, 12), +}; +static const unsigned int tsn0_magic_b_mux[] = { + TSN0_MAGIC_B_MARK, +}; +static const unsigned int tsn0_phy_int_b_pins[] = { + /* TSN0_PHY_INT_B */ + RCAR_GP_PIN(3, 10), +}; +static const unsigned int tsn0_phy_int_b_mux[] = { + TSN0_PHY_INT_B_MARK, +}; +static const unsigned int tsn0_mdio_b_pins[] = { + /* TSN0_MDC_B, TSN0_MDIO_B */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2), +}; +static const unsigned int tsn0_mdio_b_mux[] = { + TSN0_MDC_B_MARK, TSN0_MDIO_B_MARK, +}; +static const unsigned int tsn0_avtp_pps_pins[] = { + /* TSN0_AVTP_PPS */ + RCAR_GP_PIN(3, 16), +}; +static const unsigned int tsn0_avtp_pps_mux[] = { + TSN0_AVTP_PPS_MARK, +}; +static const unsigned int tsn0_avtp_capture_a_pins[] = { + /* TSN0_AVTP_CAPTURE_A */ + RCAR_GP_PIN(0, 1), +}; +static const unsigned int tsn0_avtp_capture_a_mux[] = { + TSN0_AVTP_CAPTURE_A_MARK, +}; +static const unsigned int tsn0_avtp_match_a_pins[] = { + /* TSN0_AVTP_MATCH_A */ + RCAR_GP_PIN(0, 2), +}; +static const unsigned int tsn0_avtp_match_a_mux[] = { + TSN0_AVTP_MATCH_A_MARK, +}; +static const unsigned int tsn0_avtp_capture_b_pins[] = { + /* TSN0_AVTP_CAPTURE_B */ + RCAR_GP_PIN(3, 18), +}; +static const unsigned int tsn0_avtp_capture_b_mux[] = { + TSN0_AVTP_CAPTURE_B_MARK, +}; +static const unsigned int tsn0_avtp_match_b_pins[] = { + /* TSN0_AVTP_MATCH_B */ + RCAR_GP_PIN(3, 17), +}; +static const unsigned int tsn0_avtp_match_b_mux[] = { + TSN0_AVTP_MATCH_B_MARK, +}; + +/* - TSN1 ------------------------------------------------ */ +static const unsigned int tsn1_link_a_pins[] = { + /* TSN1_LINK_A */ + RCAR_GP_PIN(0, 15), +}; +static const unsigned int tsn1_link_a_mux[] = { + TSN1_LINK_A_MARK, +}; +static const unsigned int tsn1_phy_int_a_pins[] = { + /* TSN1_PHY_INT_A */ + RCAR_GP_PIN(0, 19), +}; +static const unsigned int tsn1_phy_int_a_mux[] = { + TSN1_PHY_INT_A_MARK, +}; +static const unsigned int tsn1_mdio_a_pins[] = { + /* TSN1_MDC_A, TSN1_MDIO_A */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), +}; +static const unsigned int tsn1_mdio_a_mux[] = { + TSN1_MDC_A_MARK, TSN1_MDIO_A_MARK, +}; +static const unsigned int tsn1_link_b_pins[] = { + /* TSN1_LINK_B */ + RCAR_GP_PIN(3, 6), +}; +static const unsigned int tsn1_link_b_mux[] = { + TSN1_LINK_B_MARK, +}; +static const unsigned int tsn1_phy_int_b_pins[] = { + /* TSN1_PHY_INT_B */ + RCAR_GP_PIN(3, 11), +}; +static const unsigned int tsn1_phy_int_b_mux[] = { + TSN1_PHY_INT_B_MARK, +}; +static const unsigned int tsn1_mdio_b_pins[] = { + /* TSN1_MDC_B, TSN1_MDIO_B */ + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0), +}; +static const unsigned int tsn1_mdio_b_mux[] = { + TSN1_MDC_B_MARK, TSN1_MDIO_B_MARK, +}; +static const unsigned int tsn1_avtp_pps_pins[] = { + /* TSN1_AVTP_PPS */ + RCAR_GP_PIN(3, 13), +}; +static const unsigned int tsn1_avtp_pps_mux[] = { + TSN0_AVTP_PPS_MARK, +}; +static const unsigned int tsn1_avtp_capture_a_pins[] = { + /* TSN1_AVTP_CAPTURE_A */ + RCAR_GP_PIN(0, 7), +}; +static const unsigned int tsn1_avtp_capture_a_mux[] = { + TSN1_AVTP_CAPTURE_A_MARK, +}; +static const unsigned int tsn1_avtp_match_a_pins[] = { + /* TSN1_AVTP_MATCH_A */ + RCAR_GP_PIN(0, 6), +}; +static const unsigned int tsn1_avtp_match_a_mux[] = { + TSN1_AVTP_MATCH_A_MARK, +}; +static const unsigned int tsn1_avtp_capture_b_pins[] = { + /* TSN1_AVTP_CAPTURE_B */ + RCAR_GP_PIN(3, 15), +}; +static const unsigned int tsn1_avtp_capture_b_mux[] = { + TSN1_AVTP_CAPTURE_B_MARK, +}; +static const unsigned int tsn1_avtp_match_b_pins[] = { + /* TSN1_AVTP_MATCH_B */ + RCAR_GP_PIN(3, 14), +}; +static const unsigned int tsn1_avtp_match_b_mux[] = { + TSN1_AVTP_MATCH_B_MARK, +}; + +/* - TSN2 ------------------------------------------------ */ +static const unsigned int tsn2_link_a_pins[] = { + /* TSN2_LINK_A */ + RCAR_GP_PIN(0, 16), +}; +static const unsigned int tsn2_link_a_mux[] = { + TSN2_LINK_A_MARK, +}; +static const unsigned int tsn2_phy_int_a_pins[] = { + /* TSN2_PHY_INT_A */ + RCAR_GP_PIN(0, 20), +}; +static const unsigned int tsn2_phy_int_a_mux[] = { + TSN2_PHY_INT_A_MARK, +}; +static const unsigned int tsn2_mdio_a_pins[] = { + /* TSN2_MDC_A, TSN2_MDIO_A */ + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), +}; +static const unsigned int tsn2_mdio_a_mux[] = { + TSN2_MDC_A_MARK, TSN2_MDIO_A_MARK, +}; +static const unsigned int tsn2_link_b_pins[] = { + /* TSN2_LINK_B */ + RCAR_GP_PIN(3, 7), +}; +static const unsigned int tsn2_link_b_mux[] = { + TSN2_LINK_B_MARK, +}; +static const unsigned int tsn2_phy_int_b_pins[] = { + /* TSN2_PHY_INT_B */ + RCAR_GP_PIN(3, 9), +}; +static const unsigned int tsn2_phy_int_b_mux[] = { + TSN2_PHY_INT_B_MARK, +}; +static const unsigned int tsn2_mdio_b_pins[] = { + /* TSN2_MDC_B, TSN2_MDIO_B */ + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1), +}; +static const unsigned int tsn2_mdio_b_mux[] = { + TSN2_MDC_B_MARK, TSN2_MDIO_B_MARK, +}; + +static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(hscif3_data), + SH_PFC_PIN_GROUP(hscif3_clk), + SH_PFC_PIN_GROUP(hscif3_ctrl), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c5), + SH_PFC_PIN_GROUP(intc_ex_irq0), + SH_PFC_PIN_GROUP(intc_ex_irq1), + SH_PFC_PIN_GROUP(intc_ex_irq2), + SH_PFC_PIN_GROUP(intc_ex_irq3), + SH_PFC_PIN_GROUP(intc_ex_irq4), + SH_PFC_PIN_GROUP(intc_ex_irq5), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(mmc_cd), + SH_PFC_PIN_GROUP(mmc_wp), + SH_PFC_PIN_GROUP(mmc_ds), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_txd), + SH_PFC_PIN_GROUP(msiof0_rxd), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_txd), + SH_PFC_PIN_GROUP(msiof1_rxd), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_txd), + SH_PFC_PIN_GROUP(msiof2_rxd), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_txd), + SH_PFC_PIN_GROUP(msiof3_rxd), + SH_PFC_PIN_GROUP(pcie0_clkreq_n), + SH_PFC_PIN_GROUP(pcie1_clkreq_n), + SH_PFC_PIN_GROUP(qspi0_ctrl), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_ctrl), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_clk), + SH_PFC_PIN_GROUP(scif4_ctrl), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(tsn0_link_a), + SH_PFC_PIN_GROUP(tsn0_magic_a), + SH_PFC_PIN_GROUP(tsn0_phy_int_a), + SH_PFC_PIN_GROUP(tsn0_mdio_a), + SH_PFC_PIN_GROUP(tsn0_link_b), + SH_PFC_PIN_GROUP(tsn0_magic_b), + SH_PFC_PIN_GROUP(tsn0_phy_int_b), + SH_PFC_PIN_GROUP(tsn0_mdio_b), + SH_PFC_PIN_GROUP(tsn0_avtp_pps), + SH_PFC_PIN_GROUP(tsn0_avtp_capture_a), + SH_PFC_PIN_GROUP(tsn0_avtp_match_a), + SH_PFC_PIN_GROUP(tsn0_avtp_capture_b), + SH_PFC_PIN_GROUP(tsn0_avtp_match_b), + SH_PFC_PIN_GROUP(tsn1_link_a), + SH_PFC_PIN_GROUP(tsn1_phy_int_a), + SH_PFC_PIN_GROUP(tsn1_mdio_a), + SH_PFC_PIN_GROUP(tsn1_link_b), + SH_PFC_PIN_GROUP(tsn1_phy_int_b), + SH_PFC_PIN_GROUP(tsn1_mdio_b), + SH_PFC_PIN_GROUP(tsn1_avtp_pps), + SH_PFC_PIN_GROUP(tsn1_avtp_capture_a), + SH_PFC_PIN_GROUP(tsn1_avtp_match_a), + SH_PFC_PIN_GROUP(tsn1_avtp_capture_b), + SH_PFC_PIN_GROUP(tsn1_avtp_match_b), + SH_PFC_PIN_GROUP(tsn2_link_a), + SH_PFC_PIN_GROUP(tsn2_phy_int_a), + SH_PFC_PIN_GROUP(tsn2_mdio_a), + SH_PFC_PIN_GROUP(tsn2_link_b), + SH_PFC_PIN_GROUP(tsn2_phy_int_b), + SH_PFC_PIN_GROUP(tsn2_mdio_b), +}; + +static const char * const hscif0_groups[] = { + "hscif0_data", + "hscif0_clk", + "hscif0_ctrl", +}; + +static const char * const hscif1_groups[] = { + "hscif1_data", + "hscif1_clk", + "hscif1_ctrl", +}; + +static const char * const hscif2_groups[] = { + "hscif2_data", + "hscif2_clk", + "hscif2_ctrl", +}; + +static const char * const hscif3_groups[] = { + "hscif3_data", + "hscif3_clk", + "hscif3_ctrl", +}; + +static const char * const i2c0_groups[] = { + "i2c0", +}; + +static const char * const i2c1_groups[] = { + "i2c1", +}; + +static const char * const i2c2_groups[] = { + "i2c2", +}; + +static const char * const i2c3_groups[] = { + "i2c3", +}; + +static const char * const i2c4_groups[] = { + "i2c4", +}; + +static const char * const i2c5_groups[] = { + "i2c5", +}; + +static const char * const intc_ex_groups[] = { + "intc_ex_irq0", + "intc_ex_irq1", + "intc_ex_irq2", + "intc_ex_irq3", + "intc_ex_irq4", + "intc_ex_irq5", +}; + +static const char * const mmc_groups[] = { + "mmc_data1", + "mmc_data4", + "mmc_data8", + "mmc_ctrl", + "mmc_cd", + "mmc_wp", + "mmc_ds", +}; + +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk", + "msiof3_sync", + "msiof3_ss1", + "msiof3_ss2", + "msiof3_txd", + "msiof3_rxd", +}; + +static const char * const pcie_groups[] = { + "pcie0_clkreq_n", + "pcie1_clkreq_n", +}; + +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + +static const char * const scif0_groups[] = { + "scif0_data", + "scif0_clk", + "scif0_ctrl", +}; + +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_ctrl", +}; + +static const char * const scif3_groups[] = { + "scif3_data", + "scif3_clk", + "scif3_ctrl", +}; + +static const char * const scif4_groups[] = { + "scif4_data", + "scif4_clk", + "scif4_ctrl", +}; + +static const char * const scif_clk_groups[] = { + "scif_clk", +}; + +static const char * const tsn0_groups[] = { + "tsn0_link_a", + "tsn0_magic_a", + "tsn0_phy_int_a", + "tsn0_mdio_a", + "tsn0_link_b", + "tsn0_magic_b", + "tsn0_phy_int_b", + "tsn0_mdio_b", + "tsn0_avtp_pps", + "tsn0_avtp_capture_a", + "tsn0_avtp_match_a", + "tsn0_avtp_capture_b", + "tsn0_avtp_match_b", +}; + +static const char * const tsn1_groups[] = { + "tsn1_link_a", + "tsn1_phy_int_a", + "tsn1_mdio_a", + "tsn1_link_b", + "tsn1_phy_int_b", + "tsn1_mdio_b", + "tsn1_avtp_pps", + "tsn1_avtp_capture_a", + "tsn1_avtp_match_a", + "tsn1_avtp_capture_b", + "tsn1_avtp_match_b", +}; + +static const char * const tsn2_groups[] = { + "tsn2_link_a", + "tsn2_phy_int_a", + "tsn2_mdio_a", + "tsn2_link_b", + "tsn2_phy_int_b", + "tsn2_mdio_b", +}; + +static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(hscif3), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c5), + SH_PFC_FUNCTION(intc_ex), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pcie), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(tsn0), + SH_PFC_FUNCTION(tsn1), + SH_PFC_FUNCTION(tsn2), +}; + +static const struct pinmux_cfg_reg pinmux_config_regs[] = { +#define F_(x, y) FN_##y +#define FM(x) FN_##x + { PINMUX_CFG_REG("GPSR0", 0xe6050040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_20_FN, GPSR0_20, + GP_0_19_FN, GPSR0_19, + GP_0_18_FN, GPSR0_18, + GP_0_17_FN, GPSR0_17, + GP_0_16_FN, GPSR0_16, + GP_0_15_FN, GPSR0_15, + GP_0_14_FN, GPSR0_14, + GP_0_13_FN, GPSR0_13, + GP_0_12_FN, GPSR0_12, + GP_0_11_FN, GPSR0_11, + GP_0_10_FN, GPSR0_10, + GP_0_9_FN, GPSR0_9, + GP_0_8_FN, GPSR0_8, + GP_0_7_FN, GPSR0_7, + GP_0_6_FN, GPSR0_6, + GP_0_5_FN, GPSR0_5, + GP_0_4_FN, GPSR0_4, + GP_0_3_FN, GPSR0_3, + GP_0_2_FN, GPSR0_2, + GP_0_1_FN, GPSR0_1, + GP_0_0_FN, GPSR0_0, )) + }, + { PINMUX_CFG_REG("GPSR1", 0xe6050840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_24_FN, GPSR1_24, + GP_1_23_FN, GPSR1_23, + GP_1_22_FN, GPSR1_22, + GP_1_21_FN, GPSR1_21, + GP_1_20_FN, GPSR1_20, + GP_1_19_FN, GPSR1_19, + GP_1_18_FN, GPSR1_18, + GP_1_17_FN, GPSR1_17, + GP_1_16_FN, GPSR1_16, + GP_1_15_FN, GPSR1_15, + GP_1_14_FN, GPSR1_14, + GP_1_13_FN, GPSR1_13, + GP_1_12_FN, GPSR1_12, + GP_1_11_FN, GPSR1_11, + GP_1_10_FN, GPSR1_10, + GP_1_9_FN, GPSR1_9, + GP_1_8_FN, GPSR1_8, + GP_1_7_FN, GPSR1_7, + GP_1_6_FN, GPSR1_6, + GP_1_5_FN, GPSR1_5, + GP_1_4_FN, GPSR1_4, + GP_1_3_FN, GPSR1_3, + GP_1_2_FN, GPSR1_2, + GP_1_1_FN, GPSR1_1, + GP_1_0_FN, GPSR1_0, )) + }, + { PINMUX_CFG_REG("GPSR2", 0xe6051040, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_2_16_FN, GPSR2_16, + GP_2_15_FN, GPSR2_15, + GP_2_14_FN, GPSR2_14, + GP_2_13_FN, GPSR2_13, + GP_2_12_FN, GPSR2_12, + GP_2_11_FN, GPSR2_11, + GP_2_10_FN, GPSR2_10, + GP_2_9_FN, GPSR2_9, + GP_2_8_FN, GPSR2_8, + GP_2_7_FN, GPSR2_7, + GP_2_6_FN, GPSR2_6, + GP_2_5_FN, GPSR2_5, + GP_2_4_FN, GPSR2_4, + GP_2_3_FN, GPSR2_3, + GP_2_2_FN, GPSR2_2, + GP_2_1_FN, GPSR2_1, + GP_2_0_FN, GPSR2_0, )) + }, + { PINMUX_CFG_REG("GPSR3", 0xe6051840, 32, 1, GROUP( + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_18_FN, GPSR3_18, + GP_3_17_FN, GPSR3_17, + GP_3_16_FN, GPSR3_16, + GP_3_15_FN, GPSR3_15, + GP_3_14_FN, GPSR3_14, + GP_3_13_FN, GPSR3_13, + GP_3_12_FN, GPSR3_12, + GP_3_11_FN, GPSR3_11, + GP_3_10_FN, GPSR3_10, + GP_3_9_FN, GPSR3_9, + GP_3_8_FN, GPSR3_8, + GP_3_7_FN, GPSR3_7, + GP_3_6_FN, GPSR3_6, + GP_3_5_FN, GPSR3_5, + GP_3_4_FN, GPSR3_4, + GP_3_3_FN, GPSR3_3, + GP_3_2_FN, GPSR3_2, + GP_3_1_FN, GPSR3_1, + GP_3_0_FN, GPSR3_0, )) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG("IP0SR0", 0xe6050060, 32, 4, GROUP( + IP0SR0_31_28 + IP0SR0_27_24 + IP0SR0_23_20 + IP0SR0_19_16 + IP0SR0_15_12 + IP0SR0_11_8 + IP0SR0_7_4 + IP0SR0_3_0)) + }, + { PINMUX_CFG_REG("IP1SR0", 0xe6050064, 32, 4, GROUP( + IP1SR0_31_28 + IP1SR0_27_24 + IP1SR0_23_20 + IP1SR0_19_16 + IP1SR0_15_12 + IP1SR0_11_8 + IP1SR0_7_4 + IP1SR0_3_0)) + }, + { PINMUX_CFG_REG("IP2SR0", 0xe6050068, 32, 4, GROUP( + IP2SR0_31_28 + IP2SR0_27_24 + IP2SR0_23_20 + IP2SR0_19_16 + IP2SR0_15_12 + IP2SR0_11_8 + IP2SR0_7_4 + IP2SR0_3_0)) + }, + { PINMUX_CFG_REG("IP0SR1", 0xe6050860, 32, 4, GROUP( + IP0SR1_31_28 + IP0SR1_27_24 + IP0SR1_23_20 + IP0SR1_19_16 + IP0SR1_15_12 + IP0SR1_11_8 + IP0SR1_7_4 + IP0SR1_3_0)) + }, +#undef F_ +#undef FM + +#define F_(x, y) x, +#define FM(x) FN_##x, + { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6050900, 32, + GROUP(4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2), + GROUP( + /* RESERVED 31, 30, 29, 28 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 27, 26, 25, 24 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 23, 22, 21, 20 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 19, 18, 17, 16 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 15, 14, 13, 12 */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + MOD_SEL1_11_10 + MOD_SEL1_9_8 + MOD_SEL1_7_6 + MOD_SEL1_5_4 + MOD_SEL1_3_2 + MOD_SEL1_1_0)) + }, + { /* sentinel */ }, +}; + +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRV0CTRL0", 0xe6050080) { + { RCAR_GP_PIN(0, 7), 28, 3 }, /* TX0 */ + { RCAR_GP_PIN(0, 6), 24, 3 }, /* RX0 */ + { RCAR_GP_PIN(0, 5), 20, 3 }, /* HRTS0_N */ + { RCAR_GP_PIN(0, 4), 16, 3 }, /* HCTS0_N */ + { RCAR_GP_PIN(0, 3), 12, 3 }, /* HTX0 */ + { RCAR_GP_PIN(0, 2), 8, 3 }, /* HRX0 */ + { RCAR_GP_PIN(0, 1), 4, 3 }, /* HSCK0 */ + { RCAR_GP_PIN(0, 0), 0, 3 }, /* SCIF_CLK */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL0", 0xe6050084) { + { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF0_SS1 */ + { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF0_SCK */ + { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF0_TXD */ + { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF0_RXD */ + { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF0_SYNC */ + { RCAR_GP_PIN(0, 10), 8, 3 }, /* CTS0_N */ + { RCAR_GP_PIN(0, 9), 4, 3 }, /* RTS0_N */ + { RCAR_GP_PIN(0, 8), 0, 3 }, /* SCK0 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL0", 0xe6050088) { + { RCAR_GP_PIN(0, 20), 16, 3 }, /* IRQ3 */ + { RCAR_GP_PIN(0, 19), 12, 3 }, /* IRQ2 */ + { RCAR_GP_PIN(0, 18), 8, 3 }, /* IRQ1 */ + { RCAR_GP_PIN(0, 17), 4, 3 }, /* IRQ0 */ + { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF0_SS2 */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL1", 0xe6050880) { + { RCAR_GP_PIN(1, 7), 28, 3 }, /* GP1_07 */ + { RCAR_GP_PIN(1, 6), 24, 3 }, /* GP1_06 */ + { RCAR_GP_PIN(1, 5), 20, 3 }, /* GP1_05 */ + { RCAR_GP_PIN(1, 4), 16, 3 }, /* GP1_04 */ + { RCAR_GP_PIN(1, 3), 12, 3 }, /* GP1_03 */ + { RCAR_GP_PIN(1, 2), 8, 3 }, /* GP1_02 */ + { RCAR_GP_PIN(1, 1), 4, 3 }, /* GP1_01 */ + { RCAR_GP_PIN(1, 0), 0, 3 }, /* GP1_00 */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL1", 0xe6050884) { + { RCAR_GP_PIN(1, 15), 28, 3 }, /* MMC_SD_D2 */ + { RCAR_GP_PIN(1, 14), 24, 3 }, /* MMC_SD_D1 */ + { RCAR_GP_PIN(1, 13), 20, 3 }, /* MMC_SD_D0 */ + { RCAR_GP_PIN(1, 12), 16, 3 }, /* MMC_SD_CLK */ + { RCAR_GP_PIN(1, 11), 12, 3 }, /* GP1_11 */ + { RCAR_GP_PIN(1, 10), 8, 3 }, /* GP1_10 */ + { RCAR_GP_PIN(1, 9), 4, 3 }, /* GP1_09 */ + { RCAR_GP_PIN(1, 8), 0, 3 }, /* GP1_08 */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL1", 0xe6050888) { + { RCAR_GP_PIN(1, 23), 28, 3 }, /* SD_CD */ + { RCAR_GP_PIN(1, 22), 24, 3 }, /* MMC_SD_CMD */ + { RCAR_GP_PIN(1, 21), 20, 3 }, /* MMC_D7 */ + { RCAR_GP_PIN(1, 20), 16, 3 }, /* MMC_DS */ + { RCAR_GP_PIN(1, 19), 12, 3 }, /* MMC_D6 */ + { RCAR_GP_PIN(1, 18), 8, 3 }, /* MMC_D4 */ + { RCAR_GP_PIN(1, 17), 4, 3 }, /* MMC_D5 */ + { RCAR_GP_PIN(1, 16), 0, 3 }, /* MMC_SD_D3 */ + } }, + { PINMUX_DRIVE_REG("DRV3CTRL1", 0xe605088c) { + { RCAR_GP_PIN(1, 24), 0, 3 }, /* SD_WP */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL2", 0xe6051080) { + { RCAR_GP_PIN(2, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */ + { RCAR_GP_PIN(2, 6), 24, 2 }, /* QSPI1_IO2 */ + { RCAR_GP_PIN(2, 5), 20, 2 }, /* QSPI1_MISO_IO1 */ + { RCAR_GP_PIN(2, 4), 16, 2 }, /* QSPI1_IO3 */ + { RCAR_GP_PIN(2, 3), 12, 2 }, /* QSPI1_SSL */ + { RCAR_GP_PIN(2, 2), 8, 2 }, /* RPC_RESET_N */ + { RCAR_GP_PIN(2, 1), 4, 2 }, /* RPC_WP_N */ + { RCAR_GP_PIN(2, 0), 0, 2 }, /* RPC_INT_N */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL2", 0xe6051084) { + { RCAR_GP_PIN(2, 15), 28, 3 }, /* PCIE0_CLKREQ_N */ + { RCAR_GP_PIN(2, 14), 24, 2 }, /* QSPI0_IO3 */ + { RCAR_GP_PIN(2, 13), 20, 2 }, /* QSPI0_SSL */ + { RCAR_GP_PIN(2, 12), 16, 2 }, /* QSPI0_MISO_IO1 */ + { RCAR_GP_PIN(2, 11), 12, 2 }, /* QSPI0_IO2 */ + { RCAR_GP_PIN(2, 10), 8, 2 }, /* QSPI0_SPCLK */ + { RCAR_GP_PIN(2, 9), 4, 2 }, /* QSPI0_MOSI_IO0 */ + { RCAR_GP_PIN(2, 8), 0, 2 }, /* QSPI1_SPCLK */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL2", 0xe6051088) { + { RCAR_GP_PIN(2, 16), 0, 3 }, /* PCIE1_CLKREQ_N */ + } }, + { PINMUX_DRIVE_REG("DRV0CTRL3", 0xe6051880) { + { RCAR_GP_PIN(3, 7), 28, 3 }, /* TSN2_LINK_B */ + { RCAR_GP_PIN(3, 6), 24, 3 }, /* TSN1_LINK_B */ + { RCAR_GP_PIN(3, 5), 20, 3 }, /* TSN1_MDC_B */ + { RCAR_GP_PIN(3, 4), 16, 3 }, /* TSN0_MDC_B */ + { RCAR_GP_PIN(3, 3), 12, 3 }, /* TSN2_MDC_B */ + { RCAR_GP_PIN(3, 2), 8, 3 }, /* TSN0_MDIO_B */ + { RCAR_GP_PIN(3, 1), 4, 3 }, /* TSN2_MDIO_B */ + { RCAR_GP_PIN(3, 0), 0, 3 }, /* TSN1_MDIO_B */ + } }, + { PINMUX_DRIVE_REG("DRV1CTRL3", 0xe6051884) { + { RCAR_GP_PIN(3, 15), 28, 3 }, /* TSN1_AVTP_CAPTURE_B */ + { RCAR_GP_PIN(3, 14), 24, 3 }, /* TSN1_AVTP_MATCH_B */ + { RCAR_GP_PIN(3, 13), 20, 3 }, /* TSN1_AVTP_PPS */ + { RCAR_GP_PIN(3, 12), 16, 3 }, /* TSN0_MAGIC_B */ + { RCAR_GP_PIN(3, 11), 12, 3 }, /* TSN1_PHY_INT_B */ + { RCAR_GP_PIN(3, 10), 8, 3 }, /* TSN0_PHY_INT_B */ + { RCAR_GP_PIN(3, 9), 4, 3 }, /* TSN2_PHY_INT_B */ + { RCAR_GP_PIN(3, 8), 0, 3 }, /* TSN0_LINK_B */ + } }, + { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6051888) { + { RCAR_GP_PIN(3, 18), 8, 3 }, /* TSN0_AVTP_CAPTURE_B */ + { RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */ + { RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */ + } }, + { /* sentinel */ }, +}; + +enum ioctrl_regs { + POC0, + POC1, + POC2, + POC3, + TD0SEL1, +}; + +static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { + [POC0] = { 0xe60500a0, }, + [POC1] = { 0xe60508a0, }, + [POC2] = { 0xe60510a0, }, + [POC3] = { 0xe60518a0, }, + [TD0SEL1] = { 0xe6050920, }, + { /* sentinel */ }, +}; + +static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) +{ + int bit = pin & 0x1f; + + *pocctrl = pinmux_ioctrl_regs[POC0].reg; + if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 20)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC1].reg; + if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 24)) + return bit; + + *pocctrl = pinmux_ioctrl_regs[POC3].reg; + if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 18)) + return bit; + + return -EINVAL; +} + +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe60500c0, "PUD0", 0xe60500e0) { + [ 0] = RCAR_GP_PIN(0, 0), /* SCIF_CLK */ + [ 1] = RCAR_GP_PIN(0, 1), /* HSCK0 */ + [ 2] = RCAR_GP_PIN(0, 2), /* HRX0 */ + [ 3] = RCAR_GP_PIN(0, 3), /* HTX0 */ + [ 4] = RCAR_GP_PIN(0, 4), /* HCTS0_N */ + [ 5] = RCAR_GP_PIN(0, 5), /* HRTS0_N */ + [ 6] = RCAR_GP_PIN(0, 6), /* RX0 */ + [ 7] = RCAR_GP_PIN(0, 7), /* TX0 */ + [ 8] = RCAR_GP_PIN(0, 8), /* SCK0 */ + [ 9] = RCAR_GP_PIN(0, 9), /* RTS0_N */ + [10] = RCAR_GP_PIN(0, 10), /* CTS0_N */ + [11] = RCAR_GP_PIN(0, 11), /* MSIOF0_SYNC */ + [12] = RCAR_GP_PIN(0, 12), /* MSIOF0_RXD */ + [13] = RCAR_GP_PIN(0, 13), /* MSIOF0_TXD */ + [14] = RCAR_GP_PIN(0, 14), /* MSIOF0_SCK */ + [15] = RCAR_GP_PIN(0, 15), /* MSIOF0_SS1 */ + [16] = RCAR_GP_PIN(0, 16), /* MSIOF0_SS2 */ + [17] = RCAR_GP_PIN(0, 17), /* IRQ0 */ + [18] = RCAR_GP_PIN(0, 18), /* IRQ1 */ + [19] = RCAR_GP_PIN(0, 19), /* IRQ2 */ + [20] = RCAR_GP_PIN(0, 20), /* IRQ3 */ + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe60508c0, "PUD1", 0xe60508e0) { + [ 0] = RCAR_GP_PIN(1, 0), /* GP1_00 */ + [ 1] = RCAR_GP_PIN(1, 1), /* GP1_01 */ + [ 2] = RCAR_GP_PIN(1, 2), /* GP1_02 */ + [ 3] = RCAR_GP_PIN(1, 3), /* GP1_03 */ + [ 4] = RCAR_GP_PIN(1, 4), /* GP1_04 */ + [ 5] = RCAR_GP_PIN(1, 5), /* GP1_05 */ + [ 6] = RCAR_GP_PIN(1, 6), /* GP1_06 */ + [ 7] = RCAR_GP_PIN(1, 7), /* GP1_07 */ + [ 8] = RCAR_GP_PIN(1, 8), /* GP1_08 */ + [ 9] = RCAR_GP_PIN(1, 9), /* GP1_09 */ + [10] = RCAR_GP_PIN(1, 10), /* GP1_10 */ + [11] = RCAR_GP_PIN(1, 11), /* GP1_11 */ + [12] = RCAR_GP_PIN(1, 12), /* MMC_SD_CLK */ + [13] = RCAR_GP_PIN(1, 13), /* MMC_SD_D0 */ + [14] = RCAR_GP_PIN(1, 14), /* MMC_SD_D1 */ + [15] = RCAR_GP_PIN(1, 15), /* MMC_SD_D2 */ + [16] = RCAR_GP_PIN(1, 16), /* MMC_SD_D3 */ + [17] = RCAR_GP_PIN(1, 17), /* MMC_D5 */ + [18] = RCAR_GP_PIN(1, 18), /* MMC_D4 */ + [19] = RCAR_GP_PIN(1, 19), /* MMC_D6 */ + [20] = RCAR_GP_PIN(1, 20), /* MMC_DS */ + [21] = RCAR_GP_PIN(1, 21), /* MMC_D7 */ + [22] = RCAR_GP_PIN(1, 22), /* MMC_SD_CMD */ + [23] = RCAR_GP_PIN(1, 23), /* SD_CD */ + [24] = RCAR_GP_PIN(1, 24), /* SD_WP */ + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe60510c0, "PUD2", 0xe60510e0) { + [ 0] = RCAR_GP_PIN(2, 0), /* RPC_INT_N */ + [ 1] = RCAR_GP_PIN(2, 1), /* RPC_WP_N */ + [ 2] = RCAR_GP_PIN(2, 2), /* RPC_RESET_N */ + [ 3] = RCAR_GP_PIN(2, 3), /* QSPI1_SSL */ + [ 4] = RCAR_GP_PIN(2, 4), /* QSPI1_IO3 */ + [ 5] = RCAR_GP_PIN(2, 5), /* QSPI1_MISO_IO1 */ + [ 6] = RCAR_GP_PIN(2, 6), /* QSPI1_IO2 */ + [ 7] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI_IO0 */ + [ 8] = RCAR_GP_PIN(2, 8), /* QSPI1_SPCLK */ + [ 9] = RCAR_GP_PIN(2, 9), /* QSPI0_MOSI_IO0 */ + [10] = RCAR_GP_PIN(2, 10), /* QSPI0_SPCLK */ + [11] = RCAR_GP_PIN(2, 11), /* QSPI0_IO2 */ + [12] = RCAR_GP_PIN(2, 12), /* QSPI0_MISO_IO1 */ + [13] = RCAR_GP_PIN(2, 13), /* QSPI0_SSL */ + [14] = RCAR_GP_PIN(2, 14), /* QSPI0_IO3 */ + [15] = RCAR_GP_PIN(2, 15), /* PCIE0_CLKREQ_N */ + [16] = RCAR_GP_PIN(2, 16), /* PCIE1_CLKREQ_N */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe60518c0, "PUD3", 0xe60518e0) { + [ 0] = RCAR_GP_PIN(3, 0), /* TSN1_MDIO_B */ + [ 1] = RCAR_GP_PIN(3, 1), /* TSN2_MDIO_B */ + [ 2] = RCAR_GP_PIN(3, 2), /* TSN0_MDIO_B */ + [ 3] = RCAR_GP_PIN(3, 3), /* TSN2_MDC_B */ + [ 4] = RCAR_GP_PIN(3, 4), /* TSN0_MDC_B */ + [ 5] = RCAR_GP_PIN(3, 5), /* TSN1_MDC_B */ + [ 6] = RCAR_GP_PIN(3, 6), /* TSN1_LINK_B */ + [ 7] = RCAR_GP_PIN(3, 7), /* TSN2_LINK_B */ + [ 8] = RCAR_GP_PIN(3, 8), /* TSN0_LINK_B */ + [ 9] = RCAR_GP_PIN(3, 9), /* TSN2_PHY_INT_B */ + [10] = RCAR_GP_PIN(3, 10), /* TSN0_PHY_INT_B */ + [11] = RCAR_GP_PIN(3, 11), /* TSN1_PHY_INT_B */ + [12] = RCAR_GP_PIN(3, 12), /* TSN0_MAGIC_B */ + [13] = RCAR_GP_PIN(3, 13), /* TSN1_AVTP_PPS */ + [14] = RCAR_GP_PIN(3, 14), /* TSN1_AVTP_MATCH_B */ + [15] = RCAR_GP_PIN(3, 15), /* TSN1_AVTP_CAPTURE_B */ + [16] = RCAR_GP_PIN(3, 16), /* TSN0_AVTP_PPS */ + [17] = RCAR_GP_PIN(3, 17), /* TSN0_AVTP_MATCH_B */ + [18] = RCAR_GP_PIN(3, 18), /* TSN0_AVTP_CAPTURE_B */ + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ }, +}; + +static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = { + .pin_to_pocctrl = r8a779f0_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, +}; + +const struct sh_pfc_soc_info r8a779f0_pinmux_info = { + .name = "r8a779f0_pfc", + .ops = &r8a779f0_pfc_ops, + .unlock_reg = 0x1ff, /* PMMRn mask */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; diff --git a/drivers/pinctrl/renesas/pfc-sh7203.c b/drivers/pinctrl/renesas/pfc-sh7203.c index 811a6f2cb1fc..3986802b448a 100644 --- a/drivers/pinctrl/renesas/pfc-sh7203.c +++ b/drivers/pinctrl/renesas/pfc-sh7203.c @@ -6,7 +6,6 @@ */ #include -#include #include #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pfc-sh7264.c b/drivers/pinctrl/renesas/pfc-sh7264.c index 908837ea487b..7476b982101d 100644 --- a/drivers/pinctrl/renesas/pfc-sh7264.c +++ b/drivers/pinctrl/renesas/pfc-sh7264.c @@ -6,7 +6,6 @@ */ #include -#include #include #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pfc-sh7269.c b/drivers/pinctrl/renesas/pfc-sh7269.c index e2916aaa8304..733a2c114ca2 100644 --- a/drivers/pinctrl/renesas/pfc-sh7269.c +++ b/drivers/pinctrl/renesas/pfc-sh7269.c @@ -7,7 +7,6 @@ */ #include -#include #include #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pfc-sh73a0.c b/drivers/pinctrl/renesas/pfc-sh73a0.c index ed6db809e80d..5d8a0179fd60 100644 --- a/drivers/pinctrl/renesas/pfc-sh73a0.c +++ b/drivers/pinctrl/renesas/pfc-sh73a0.c @@ -1777,35 +1777,11 @@ static const unsigned int irda_1_mux[] = { PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK, }; /* - KEYSC ------------------------------------------------------------------ */ -static const unsigned int keysc_in5_pins[] = { - /* KEYIN[0:4] */ - 66, 67, 68, 69, 70, -}; -static const unsigned int keysc_in5_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, -}; -static const unsigned int keysc_in6_pins[] = { - /* KEYIN[0:5] */ - 66, 67, 68, 69, 70, 71, -}; -static const unsigned int keysc_in6_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, KEYIN5_MARK, -}; -static const unsigned int keysc_in7_pins[] = { - /* KEYIN[0:6] */ - 66, 67, 68, 69, 70, 71, 72, -}; -static const unsigned int keysc_in7_mux[] = { - KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, - KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, -}; -static const unsigned int keysc_in8_pins[] = { +static const unsigned int keysc_in_pins[] = { /* KEYIN[0:7] */ 66, 67, 68, 69, 70, 71, 72, 73, }; -static const unsigned int keysc_in8_mux[] = { +static const unsigned int keysc_in_mux[] = { KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, }; @@ -1936,65 +1912,13 @@ static const unsigned int keysc_out11_1_mux[] = { PORT143_KEYOUT11_MARK, }; /* - LCD -------------------------------------------------------------------- */ -static const unsigned int lcd_data8_pins[] = { - /* D[0:7] */ - 192, 193, 194, 195, 196, 197, 198, 199, -}; -static const unsigned int lcd_data8_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, -}; -static const unsigned int lcd_data9_pins[] = { - /* D[0:8] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, -}; -static const unsigned int lcd_data9_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, -}; -static const unsigned int lcd_data12_pins[] = { - /* D[0:11] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, -}; -static const unsigned int lcd_data12_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, -}; -static const unsigned int lcd_data16_pins[] = { - /* D[0:15] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, 204, 205, 206, 207, -}; -static const unsigned int lcd_data16_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, -}; -static const unsigned int lcd_data18_pins[] = { - /* D[0:17] */ - 192, 193, 194, 195, 196, 197, 198, 199, - 200, 201, 202, 203, 204, 205, 206, 207, - 208, 209, -}; -static const unsigned int lcd_data18_mux[] = { - LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, - LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, - LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, - LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK, - LCDD16_MARK, LCDD17_MARK, -}; -static const unsigned int lcd_data24_pins[] = { +static const unsigned int lcd_data_pins[] = { /* D[0:23] */ 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215 }; -static const unsigned int lcd_data24_mux[] = { +static const unsigned int lcd_data_mux[] = { LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK, LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK, LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK, @@ -2031,65 +1955,13 @@ static const unsigned int lcd_sys_mux[] = { LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK, }; /* - LCD2 ------------------------------------------------------------------- */ -static const unsigned int lcd2_data8_pins[] = { - /* D[0:7] */ - 128, 129, 142, 143, 144, 145, 138, 139, -}; -static const unsigned int lcd2_data8_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, -}; -static const unsigned int lcd2_data9_pins[] = { - /* D[0:8] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, -}; -static const unsigned int lcd2_data9_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, -}; -static const unsigned int lcd2_data12_pins[] = { - /* D[0:11] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, -}; -static const unsigned int lcd2_data12_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, -}; -static const unsigned int lcd2_data16_pins[] = { - /* D[0:15] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, 132, 133, 134, 135, -}; -static const unsigned int lcd2_data16_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, - LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, -}; -static const unsigned int lcd2_data18_pins[] = { - /* D[0:17] */ - 128, 129, 142, 143, 144, 145, 138, 139, - 140, 141, 130, 131, 132, 133, 134, 135, - 136, 137, -}; -static const unsigned int lcd2_data18_mux[] = { - LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, - LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, - LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, - LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK, - LCD2D16_MARK, LCD2D17_MARK, -}; -static const unsigned int lcd2_data24_pins[] = { +static const unsigned int lcd2_data_pins[] = { /* D[0:23] */ 128, 129, 142, 143, 144, 145, 138, 139, 140, 141, 130, 131, 132, 133, 134, 135, 136, 137, 146, 147, 234, 235, 238, 239 }; -static const unsigned int lcd2_data24_mux[] = { +static const unsigned int lcd2_data_mux[] = { LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK, LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK, LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK, @@ -2130,25 +2002,11 @@ static const unsigned int lcd2_sys_1_mux[] = { LCD2RD__MARK, PORT217_LCD2RS_MARK, }; /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc0_data1_0_pins[] = { - /* D[0] */ - 271, -}; -static const unsigned int mmc0_data1_0_mux[] = { - MMCD0_0_MARK, -}; -static const unsigned int mmc0_data4_0_pins[] = { - /* D[0:3] */ - 271, 272, 273, 274, -}; -static const unsigned int mmc0_data4_0_mux[] = { - MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, -}; -static const unsigned int mmc0_data8_0_pins[] = { +static const unsigned int mmc0_data_0_pins[] = { /* D[0:7] */ 271, 272, 273, 274, 275, 276, 277, 278, }; -static const unsigned int mmc0_data8_0_mux[] = { +static const unsigned int mmc0_data_0_mux[] = { MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK, MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK, }; @@ -2160,25 +2018,11 @@ static const unsigned int mmc0_ctrl_0_mux[] = { MMCCMD0_MARK, MMCCLK0_MARK, }; -static const unsigned int mmc0_data1_1_pins[] = { - /* D[0] */ - 305, -}; -static const unsigned int mmc0_data1_1_mux[] = { - MMCD1_0_MARK, -}; -static const unsigned int mmc0_data4_1_pins[] = { - /* D[0:3] */ - 305, 304, 303, 302, -}; -static const unsigned int mmc0_data4_1_mux[] = { - MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, -}; -static const unsigned int mmc0_data8_1_pins[] = { +static const unsigned int mmc0_data_1_pins[] = { /* D[0:7] */ 305, 304, 303, 302, 301, 300, 299, 298, }; -static const unsigned int mmc0_data8_1_mux[] = { +static const unsigned int mmc0_data_1_mux[] = { MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK, MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK, }; @@ -2851,18 +2695,11 @@ static const unsigned int scifb_ctrl_1_mux[] = { PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - 252, -}; -static const unsigned int sdhi0_data1_mux[] = { - SDHID0_0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ 252, 253, 254, 255, }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -2887,18 +2724,11 @@ static const unsigned int sdhi0_wp_mux[] = { SDHIWP0_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - 259, -}; -static const unsigned int sdhi1_data1_mux[] = { - SDHID1_0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ 259, 260, 261, 262, }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -2909,18 +2739,11 @@ static const unsigned int sdhi1_ctrl_mux[] = { SDHICMD1_MARK, SDHICLK1_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - 265, -}; -static const unsigned int sdhi2_data1_mux[] = { - SDHID2_0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ 265, 266, 267, 268, }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -3138,10 +2961,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c3_2), SH_PFC_PIN_GROUP(irda_0), SH_PFC_PIN_GROUP(irda_1), - SH_PFC_PIN_GROUP(keysc_in5), - SH_PFC_PIN_GROUP(keysc_in6), - SH_PFC_PIN_GROUP(keysc_in7), - SH_PFC_PIN_GROUP(keysc_in8), + BUS_DATA_PIN_GROUP(keysc_in, 5), + BUS_DATA_PIN_GROUP(keysc_in, 6), + BUS_DATA_PIN_GROUP(keysc_in, 7), + BUS_DATA_PIN_GROUP(keysc_in, 8), SH_PFC_PIN_GROUP(keysc_out04), SH_PFC_PIN_GROUP(keysc_out5), SH_PFC_PIN_GROUP(keysc_out6_0), @@ -3160,33 +2983,33 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(keysc_out10_1), SH_PFC_PIN_GROUP(keysc_out11_0), SH_PFC_PIN_GROUP(keysc_out11_1), - SH_PFC_PIN_GROUP(lcd_data8), - SH_PFC_PIN_GROUP(lcd_data9), - SH_PFC_PIN_GROUP(lcd_data12), - SH_PFC_PIN_GROUP(lcd_data16), - SH_PFC_PIN_GROUP(lcd_data18), - SH_PFC_PIN_GROUP(lcd_data24), + BUS_DATA_PIN_GROUP(lcd_data, 8), + BUS_DATA_PIN_GROUP(lcd_data, 9), + BUS_DATA_PIN_GROUP(lcd_data, 12), + BUS_DATA_PIN_GROUP(lcd_data, 16), + BUS_DATA_PIN_GROUP(lcd_data, 18), + BUS_DATA_PIN_GROUP(lcd_data, 24), SH_PFC_PIN_GROUP(lcd_display), SH_PFC_PIN_GROUP(lcd_lclk), SH_PFC_PIN_GROUP(lcd_sync), SH_PFC_PIN_GROUP(lcd_sys), - SH_PFC_PIN_GROUP(lcd2_data8), - SH_PFC_PIN_GROUP(lcd2_data9), - SH_PFC_PIN_GROUP(lcd2_data12), - SH_PFC_PIN_GROUP(lcd2_data16), - SH_PFC_PIN_GROUP(lcd2_data18), - SH_PFC_PIN_GROUP(lcd2_data24), + BUS_DATA_PIN_GROUP(lcd2_data, 8), + BUS_DATA_PIN_GROUP(lcd2_data, 9), + BUS_DATA_PIN_GROUP(lcd2_data, 12), + BUS_DATA_PIN_GROUP(lcd2_data, 16), + BUS_DATA_PIN_GROUP(lcd2_data, 18), + BUS_DATA_PIN_GROUP(lcd2_data, 24), SH_PFC_PIN_GROUP(lcd2_sync_0), SH_PFC_PIN_GROUP(lcd2_sync_1), SH_PFC_PIN_GROUP(lcd2_sys_0), SH_PFC_PIN_GROUP(lcd2_sys_1), - SH_PFC_PIN_GROUP(mmc0_data1_0), - SH_PFC_PIN_GROUP(mmc0_data4_0), - SH_PFC_PIN_GROUP(mmc0_data8_0), + BUS_DATA_PIN_GROUP(mmc0_data, 1, _0), + BUS_DATA_PIN_GROUP(mmc0_data, 4, _0), + BUS_DATA_PIN_GROUP(mmc0_data, 8, _0), SH_PFC_PIN_GROUP(mmc0_ctrl_0), - SH_PFC_PIN_GROUP(mmc0_data1_1), - SH_PFC_PIN_GROUP(mmc0_data4_1), - SH_PFC_PIN_GROUP(mmc0_data8_1), + BUS_DATA_PIN_GROUP(mmc0_data, 1, _1), + BUS_DATA_PIN_GROUP(mmc0_data, 4, _1), + BUS_DATA_PIN_GROUP(mmc0_data, 8, _1), SH_PFC_PIN_GROUP(mmc0_ctrl_1), SH_PFC_PIN_GROUP(msiof0_rsck), SH_PFC_PIN_GROUP(msiof0_tsck), @@ -3280,16 +3103,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb_data_1), SH_PFC_PIN_GROUP(scifb_clk_1), SH_PFC_PIN_GROUP(scifb_ctrl_1), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(tpu0_to0), SH_PFC_PIN_GROUP(tpu0_to1), @@ -4314,9 +4137,9 @@ static const unsigned int sh73a0_portcr_offsets[] = { 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000, }; -static void __iomem *sh73a0_pin_to_portcr(struct sh_pfc *pfc, unsigned int pin) +static int sh73a0_pin_to_portcr(unsigned int pin) { - return pfc->windows->virt + sh73a0_portcr_offsets[pin >> 5] + pin; + return sh73a0_portcr_offsets[pin >> 5] + pin; } /* ----------------------------------------------------------------------------- diff --git a/drivers/pinctrl/renesas/pfc-sh7720.c b/drivers/pinctrl/renesas/pfc-sh7720.c index 37bcae6b3208..7071ef52449d 100644 --- a/drivers/pinctrl/renesas/pfc-sh7720.c +++ b/drivers/pinctrl/renesas/pfc-sh7720.c @@ -6,7 +6,6 @@ */ #include -#include #include #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pfc-sh7722.c b/drivers/pinctrl/renesas/pfc-sh7722.c index 95295be4e703..13d9967dce59 100644 --- a/drivers/pinctrl/renesas/pfc-sh7722.c +++ b/drivers/pinctrl/renesas/pfc-sh7722.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 #include #include -#include #include #include "sh_pfc.h" diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index ccee9c9e2e22..cb805502fb0f 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1090,12 +1090,12 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) } if (of_args.args[0] != 0 || of_args.args[1] != 0 || - of_args.args[2] != ARRAY_SIZE(rzg2l_gpio_names)) { + of_args.args[2] != pctrl->data->n_port_pins) { dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); return -EINVAL; } - chip->names = rzg2l_gpio_names; + chip->names = pctrl->data->port_pins; chip->request = rzg2l_gpio_request; chip->free = rzg2l_gpio_free; chip->get_direction = rzg2l_gpio_get_direction; diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c index 96b9de974246..4c37aebc75b8 100644 --- a/drivers/pinctrl/renesas/pinctrl.c +++ b/drivers/pinctrl/renesas/pinctrl.c @@ -397,7 +397,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); - if (!pfc->gpio) { + if (!pfc->gpio && !cfg->mux_mark) { /* If GPIOs are handled externally the pin mux type needs to be * set to GPIO here. */ @@ -639,7 +639,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) return -ENOTSUPP; - bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl); + bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); if (WARN(bit < 0, "invalid pin %#x", _pin)) return bit; @@ -711,7 +711,7 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) return -ENOTSUPP; - bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl); + bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl); if (WARN(bit < 0, "invalid pin %#x", _pin)) return bit; @@ -835,16 +835,16 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc) } const struct pinmux_bias_reg * -rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, +rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, unsigned int *bit) { unsigned int i, j; - for (i = 0; pfc->info->bias_regs[i].puen || pfc->info->bias_regs[i].pud; i++) { - for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { - if (pfc->info->bias_regs[i].pins[j] == pin) { + for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) { + for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) { + if (info->bias_regs[i].pins[j] == pin) { *bit = j; - return &pfc->info->bias_regs[i]; + return &info->bias_regs[i]; } } } @@ -859,7 +859,7 @@ unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) const struct pinmux_bias_reg *reg; unsigned int bit; - reg = rcar_pin_to_bias_reg(pfc, pin, &bit); + reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); if (!reg) return PIN_CONFIG_BIAS_DISABLE; @@ -885,7 +885,7 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, u32 enable, updown; unsigned int bit; - reg = rcar_pin_to_bias_reg(pfc, pin, &bit); + reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); if (!reg) return; @@ -919,7 +919,8 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) { - void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin); + void __iomem *reg = pfc->windows->virt + + pfc->info->ops->pin_to_portcr(pin); u32 value = ioread8(reg) & PORTnCR_PULMD_MASK; switch (value) { @@ -936,7 +937,8 @@ unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, unsigned int bias) { - void __iomem *reg = pfc->info->ops->pin_to_portcr(pfc, pin); + void __iomem *reg = pfc->windows->virt + + pfc->info->ops->pin_to_portcr(pin); u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK; switch (bias) { diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 2479b4fb9cf9..6b5836ea47de 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -49,15 +49,34 @@ struct sh_pfc_pin { u16 enum_id; }; -#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ - { \ - .name = #alias, \ - .pins = n##_pins, \ - .mux = n##_mux, \ - .nr_pins = ARRAY_SIZE(n##_pins) + \ - BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ - } -#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) +#define SH_PFC_PIN_GROUP_ALIAS(alias, _name) { \ + .name = #alias, \ + .pins = _name##_pins, \ + .mux = _name##_mux, \ + .nr_pins = ARRAY_SIZE(_name##_pins) + \ + BUILD_BUG_ON_ZERO(sizeof(_name##_pins) != sizeof(_name##_mux)), \ +} +#define SH_PFC_PIN_GROUP(name) SH_PFC_PIN_GROUP_ALIAS(name, name) + +/* + * Define a pin group referring to a subset of an array of pins. + */ +#define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) { \ + .name = #_name, \ + .pins = data##_pins + first, \ + .mux = data##_mux + first, \ + .nr_pins = n + \ + BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_pins)) + \ + BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_mux)), \ +} + +/* + * Define a pin group for the data pins of a resizable bus. + * An optional 'suffix' argument is accepted, to be used when the same group + * can appear on a different set of pins. + */ +#define BUS_DATA_PIN_GROUP(base, n, ...) \ + SH_PFC_PIN_GROUP_SUBSET(base##n##__VA_ARGS__, base##__VA_ARGS__, 0, n) struct sh_pfc_pin_group { const char *name; @@ -66,49 +85,11 @@ struct sh_pfc_pin_group { unsigned int nr_pins; }; -/* - * Using union vin_data{,12,16} saves memory occupied by the VIN data pins. - * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups - * in this case. It accepts an optional 'version' argument used when the - * same group can appear on a different set of pins. - */ -#define VIN_DATA_PIN_GROUP(n, s, ...) \ - { \ - .name = #n#s#__VA_ARGS__, \ - .pins = n##__VA_ARGS__##_pins.data##s, \ - .mux = n##__VA_ARGS__##_mux.data##s, \ - .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \ - } - -union vin_data12 { - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; -}; - -union vin_data16 { - unsigned int data16[16]; - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; -}; - -union vin_data { - unsigned int data24[24]; - unsigned int data20[20]; - unsigned int data16[16]; - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; - unsigned int data4[4]; -}; - -#define SH_PFC_FUNCTION(n) \ - { \ - .name = #n, \ - .groups = n##_groups, \ - .nr_groups = ARRAY_SIZE(n##_groups), \ - } +#define SH_PFC_FUNCTION(n) { \ + .name = #n, \ + .groups = n##_groups, \ + .nr_groups = ARRAY_SIZE(n##_groups), \ +} struct sh_pfc_function { const char *name; @@ -231,8 +212,9 @@ struct pinmux_irq { * Describe the mapping from GPIOs to a single IRQ * - ids...: List of GPIOs that are mapped to the same IRQ */ -#define PINMUX_IRQ(ids...) \ - { .gpios = (const short []) { ids, -1 } } +#define PINMUX_IRQ(ids...) { \ + .gpios = (const short []) { ids, -1 } \ +} struct pinmux_range { u16 begin; @@ -272,8 +254,8 @@ struct sh_pfc_soc_operations { unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); - int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); - void __iomem * (*pin_to_portcr)(struct sh_pfc *pfc, unsigned int pin); + int (*pin_to_pocctrl)(unsigned int pin, u32 *pocctrl); + int (*pin_to_portcr)(unsigned int pin); }; struct sh_pfc_soc_info { @@ -342,6 +324,7 @@ extern const struct sh_pfc_soc_info r8a77980_pinmux_info; extern const struct sh_pfc_soc_info r8a77990_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; +extern const struct sh_pfc_soc_info r8a779f0_pinmux_info; extern const struct sh_pfc_soc_info sh7203_pinmux_info; extern const struct sh_pfc_soc_info sh7264_pinmux_info; extern const struct sh_pfc_soc_info sh7269_pinmux_info; @@ -535,9 +518,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) -#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_19(bank, fn, sfx, cfg) \ PORT_GP_CFG_18(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 18, fn, sfx, cfg) +#define PORT_GP_19(bank, fn, sfx) PORT_GP_CFG_19(bank, fn, sfx, 0) + +#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ + PORT_GP_CFG_19(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) @@ -624,13 +611,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str) /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ -#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ - { \ - .pin = (bank * 32) + _pin, \ - .name = __stringify(_name), \ - .enum_id = _name##_DATA, \ - .configs = cfg, \ - } +#define _GP_GPIO(bank, _pin, _name, sfx, cfg) { \ + .pin = (bank * 32) + _pin, \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + .configs = cfg, \ +} #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused) /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ @@ -688,13 +674,12 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; } /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ -#define SH_PFC_PIN_CFG(_pin, cfgs) \ - { \ - .pin = _pin, \ - .name = __stringify(PORT##_pin), \ - .enum_id = PORT##_pin##_DATA, \ - .configs = cfgs, \ - } +#define SH_PFC_PIN_CFG(_pin, cfgs) { \ + .pin = _pin, \ + .name = __stringify(PORT##_pin), \ + .enum_id = PORT##_pin##_DATA, \ + .configs = cfgs, \ +} /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, * PORT_name_OUT, PORT_name_IN marks @@ -743,35 +728,32 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; #define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL) /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ -#define _NOGP_PINMUX(_pin, _name, cfg) \ - { \ - .pin = PIN_##_pin, \ - .name = "PIN_" _name, \ - .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ - } +#define _NOGP_PINMUX(_pin, _name, cfg) { \ + .pin = PIN_##_pin, \ + .name = "PIN_" _name, \ + .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ +} #define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX) /* * PORTnCR helper macro for SH-Mobile/R-Mobile */ -#define PORTCR(nr, reg) \ - { \ - PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ - GROUP(2, 2, 1, 3), \ - GROUP( \ - /* PULMD[1:0], handled by .set_bias() */ \ - 0, 0, 0, 0, \ - /* IE and OE */ \ - 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ - /* SEC, not supported */ \ - 0, 0, \ - /* PTMD[2:0] */ \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 \ - )) \ - } +#define PORTCR(nr, reg) { \ + PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(2, 2, 1, 3), \ + GROUP( \ + /* PULMD[1:0], handled by .set_bias() */ \ + 0, 0, 0, 0, \ + /* IE and OE */ \ + 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ + /* SEC, not supported */ \ + 0, 0, \ + /* PTMD[2:0] */ \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 \ + )) \ +} /* * GPIO number helper macro for R-Car @@ -782,7 +764,7 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; * Bias helpers */ const struct pinmux_bias_reg * -rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, +rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, unsigned int *bit); unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index 4102ce955bd7..d291819c2f77 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -725,3 +725,74 @@ const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = { .ctrl = exynosautov9_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynosautov9_pin_ctrl), }; + +/* + * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three + * gpio/pin-mux/pinconfig controllers. + */ + +/* pin banks of FSD pin-controller 0 (FSYS) */ +static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04), + EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08), + EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c), + EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10), +}; + +/* pin banks of FSD pin-controller 1 (PERIC) */ +static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = { + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00), + EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04), + EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08), + EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14), + EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18), + EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c), + EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20), + EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24), + EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28), + EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30), + EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34), + EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38), + EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c), + EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), + EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44), + EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48), + EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c), + EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50), +}; + +/* pin banks of FSD pin-controller 2 (PMU) */ +static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = { + EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"), +}; + +const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 FSYS0 data */ + .pin_banks = fsd_pin_banks0, + .nr_banks = ARRAY_SIZE(fsd_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 PERIC data */ + .pin_banks = fsd_pin_banks1, + .nr_banks = ARRAY_SIZE(fsd_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 PMU data */ + .pin_banks = fsd_pin_banks2, + .nr_banks = ARRAY_SIZE(fsd_pin_banks2), + }, +}; + +const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { + .ctrl = fsd_pin_ctrl, + .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index a158d587814e..c1c4ffbae6e2 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -344,7 +344,8 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); - pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); + pr_info("wake %s for irq %u (%s-%lu)\n", on ? "enabled" : "disabled", + irqd->irq, bank->name, irqd->hwirq); if (!on) *our_chip->eint_wake_mask_value |= bit; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 568b6e65dfed..f610beab23a0 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1320,6 +1320,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos850_of_data }, { .compatible = "samsung,exynosautov9-pinctrl", .data = &exynosautov9_of_data }, + { .compatible = "tesla,fsd-pinctrl", + .data = &fsd_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 1f8d30ba05af..5b32d3f30fcd 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -342,6 +342,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; +extern const struct samsung_pinctrl_of_match_data fsd_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; diff --git a/drivers/pinctrl/sunplus/Kconfig b/drivers/pinctrl/sunplus/Kconfig new file mode 100644 index 000000000000..4b5c47c193d9 --- /dev/null +++ b/drivers/pinctrl/sunplus/Kconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Sunplus Pin control driver configuration +# + +config PINCTRL_SPPCTL + tristate "Sunplus SP7021 PinMux and GPIO driver" + depends on SOC_SP7021 + depends on OF && HAS_IOMEM + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + select PINCONF + select PINMUX + select GPIOLIB + select OF_GPIO + help + Say Y here to support Sunplus SP7021 pinmux controller. + This driver requires the pinctrl framework. + GPIO is provided by the same driver. + To compile this driver as a module, choose M here. + The module will be called sppinctrl. diff --git a/drivers/pinctrl/sunplus/Makefile b/drivers/pinctrl/sunplus/Makefile new file mode 100644 index 000000000000..a26952c5286a --- /dev/null +++ b/drivers/pinctrl/sunplus/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the Sunplus Pin control drivers. +# +obj-$(CONFIG_PINCTRL_SPPCTL) += sppinctrl.o +sppinctrl-objs := sppctl.o sppctl_sp7021.o diff --git a/drivers/pinctrl/sunplus/sppctl.c b/drivers/pinctrl/sunplus/sppctl.c new file mode 100644 index 000000000000..3ba47040ac42 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl.c @@ -0,0 +1,1118 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "../core.h" +#include "../pinctrl-utils.h" + +#include "sppctl.h" + +struct sppctl_gpio_chip { + void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */ + void __iomem *first_base; /* GPIO_FIRST */ + + struct gpio_chip chip; + spinlock_t lock; /* lock for accessing OE register */ +}; + +static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); +} + +static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off); +} + +static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); +} + +static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, + u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off); +} + +static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); +} + +static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off); +} + +static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off); +} + +static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off); +} + +static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); +} + +static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, + u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off); +} + +static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); +} + +static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, + u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off); +} + +static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off) +{ + return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); +} + +static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off) +{ + writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off); +} + +static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off) +{ + u32 bit_off; + + /* Each register has 32 bits. */ + *reg_off = (offset / 32) * 4; + bit_off = offset % 32; + + return bit_off; +} + +static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off) +{ + u32 bit_off; + + /* + * Each MOON register has 32 bits. Upper 16-bit word are mask-fields. + * The lower 16-bit word are the control-fields. The corresponding + * bits in mask-field should be set then you can write something to + * control-field. + */ + *reg_off = (offset / 16) * 4; + bit_off = offset % 16; + + return bit_off; +} + +static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val) +{ + u32 bit_off; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off); + if (val) + return SPPCTL_SET_MOON_REG_BIT(bit_off); + else + return SPPCTL_CLR_MOON_REG_BIT(bit_off); +} + +/** + * sppctl_func_set() - Set pin of fully-pinmux function. + * + * Mask-fields and control-fields of fully-pinmux function of SP7021 are + * arranged as shown below: + * + * func# | register | mask-field | control-field + * -------+----------+--------------+--------------- + * 0 | base[0] | (22 : 16) | ( 6 : 0) + * 1 | base[0] | (30 : 24) | (14 : 8) + * 2 | base[1] | (22 : 16) | ( 6 : 0) + * 3 | baeg[1] | (30 : 24) | (14 : 8) + * : | : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + * + * Control-fields are used to set where the function pin is going to + * be routed to. + * + * Note that mask-fields and control-fields of even number of 'func' + * are located at bits (22:16) and (6:0), while odd number of 'func's + * are located at bits (30:24) and (14:8). + */ +static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val) +{ + u32 reg, offset; + + /* + * Note that upper 16-bit word are mask-fields and lower 16-bit + * word are the control-fields. Set corresponding bits in mask- + * field before write to a control-field. + */ + reg = SPPCTL_FULLY_PINMUX_MASK_MASK | val; + + /* + * MUXF_L2SW_CLK_OUT is the first fully-pinmux pin + * and its register offset is 0. + */ + func -= MUXF_L2SW_CLK_OUT; + + /* + * Check if 'func' is an odd number or not. Mask and control- + * fields of odd number 'func' is located at upper portion of + * a register. Extra shift is needed. + */ + if (func & BIT(0)) + reg <<= SPPCTL_FULLY_PINMUX_UPPER_SHIFT; + + /* Convert func# to register offset w.r.t. base register. */ + offset = func * 2; + offset &= GENMASK(31, 2); + + writel(reg, pctl->moon2_base + offset); +} + +/** + * sppctl_gmx_set() - Set pin of group-pinmux. + * + * Mask-fields and control-fields of group-pinmux function of SP7021 are + * arranged as shown below: + * + * register | mask-fields | control-fields + * ----------+--------------+---------------- + * base[0] | (31 : 16) | (15 : 0) + * base[1] | (31 : 24) | (15 : 0) + * base[2] | (31 : 24) | (15 : 0) + * : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + * + * Control-fields are used to set where the function pin is going to + * be routed to. A control-field consists of one or more bits. + */ +static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz, + u8 val) +{ + u32 mask, reg; + + /* + * Note that upper 16-bit word are mask-fields and lower 16-bit + * word are the control-fields. Set corresponding bits in mask- + * field before write to a control-field. + */ + mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT; + reg = (mask | val) << bit_off; + + writel(reg, pctl->moon1_base + reg_off * 4); +} + +/** + * sppctl_first_get() - get bit of FIRST register. + * + * There are 4 FIRST registers. Each has 32 control-bits. + * Totally, there are 4 * 32 = 128 control-bits. + * Control-bits are arranged as shown below: + * + * registers | control-bits + * -----------+-------------- + * first[0] | (31 : 0) + * first[1] | (63 : 32) + * first[2] | (95 : 64) + * first[3] | (127 : 96) + * + * Each control-bit sets type of a GPIO pin. + * 0: a fully-pinmux pin + * 1: a GPIO or IOP pin + */ +static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); + reg = sppctl_first_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +/** + * sppctl_master_get() - get bit of MASTER register. + * + * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits. + * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are + * control-bits. Totally, there are 128 mask-bits and 128 control-bits. + * They are arranged as shown below: + * + * register | mask-bits | control-bits + * -----------+-------------+-------------- + * master[0] | (15 : 0) | (15 : 0) + * master[1] | (31 : 16) | (31 : 16) + * master[2] | (47 : 32) | (47 : 32) + * : | : | : + * master[7] | (127 : 112) | (127 : 112) + * + * where mask-bits are used to protect control-bits from write-in + * accidentally. Set the corresponding mask-bit before you write + * a value into a control-bit. + * + * Each control-bit sets type of a GPIO pin when FIRST bit is 1. + * 0: a IOP pin + * 1: a GPIO pin + */ +static int sppctl_master_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_master_readl(spp_gchip, reg_off); + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static void sppctl_first_master_set(struct gpio_chip *chip, unsigned int offset, + enum mux_first_reg first, enum mux_master_reg master) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + enum mux_first_reg val; + + /* FIRST register */ + if (first != mux_f_keep) { + bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); + reg = sppctl_first_readl(spp_gchip, reg_off); + val = (reg & BIT(bit_off)) ? mux_f_gpio : mux_f_mux; + + if (first != val) + switch (first) { + case mux_f_gpio: + reg |= BIT(bit_off); + sppctl_first_writel(spp_gchip, reg, reg_off); + break; + + case mux_f_mux: + reg &= ~BIT(bit_off); + sppctl_first_writel(spp_gchip, reg, reg_off); + break; + + case mux_f_keep: + break; + } + } + + /* MASTER register */ + if (master != mux_m_keep) { + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, (master == mux_m_gpio)); + sppctl_gpio_master_writel(spp_gchip, reg, reg_off); + } +} + +static void sppctl_gpio_input_inv_set(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + sppctl_gpio_iinv_writel(spp_gchip, reg, reg_off); +} + +static void sppctl_gpio_output_inv_set(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + sppctl_gpio_oinv_writel(spp_gchip, reg, reg_off); +} + +static int sppctl_gpio_output_od_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_od_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static void sppctl_gpio_output_od_set(struct gpio_chip *chip, unsigned int offset, + unsigned int val) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); + sppctl_gpio_od_writel(spp_gchip, reg, reg_off); +} + +static int sppctl_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_oe_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 0 : 1; +} + +static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + unsigned long flags; + + bit_off = sppctl_get_moon_reg_and_bit_offset(offset, ®_off); + + spin_lock_irqsave(&spp_gchip->lock, flags); + + if (sppctl_gpio_get_direction(chip, offset)) + reg = sppctl_gpio_iinv_readl(spp_gchip, reg_off); + else + reg = sppctl_gpio_oinv_readl(spp_gchip, reg_off); + + spin_unlock_irqrestore(&spp_gchip->lock, flags); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static int sppctl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + unsigned long flags; + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 0); + + spin_lock_irqsave(&spp_gchip->lock, flags); + + sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); + + spin_unlock_irqrestore(&spp_gchip->lock, flags); + return 0; +} + +static int sppctl_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + unsigned long flags; + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + + spin_lock_irqsave(&spp_gchip->lock, flags); + + sppctl_gpio_oe_writel(spp_gchip, reg, reg_off); + + if (val < 0) { + spin_unlock_irqrestore(&spp_gchip->lock, flags); + return 0; + } + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); + sppctl_gpio_out_writel(spp_gchip, reg, reg_off); + + spin_unlock_irqrestore(&spp_gchip->lock, flags); + return 0; +} + +static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, bit_off, reg; + + bit_off = sppctl_get_reg_and_bit_offset(offset, ®_off); + reg = sppctl_gpio_in_readl(spp_gchip, reg_off); + + return (reg & BIT(bit_off)) ? 1 : 0; +} + +static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) +{ + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, val); + sppctl_gpio_out_writel(spp_gchip, reg, reg_off); +} + +static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset, + unsigned long config) +{ + enum pin_config_param param = pinconf_to_config_param(config); + struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip); + u32 reg_off, reg; + + switch (param) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + reg = sppctl_prep_moon_reg_and_offset(offset, ®_off, 1); + sppctl_gpio_od_writel(spp_gchip, reg, reg_off); + break; + + case PIN_CONFIG_INPUT_ENABLE: + break; + + case PIN_CONFIG_OUTPUT: + return sppctl_gpio_direction_output(chip, offset, 0); + + case PIN_CONFIG_PERSIST_STATE: + return -ENOTSUPP; + + default: + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void sppctl_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + const char *label; + int i; + + for (i = 0; i < chip->ngpio; i++) { + label = gpiochip_is_requested(chip, i); + if (!label) + label = ""; + + seq_printf(s, " gpio-%03d (%-16.16s | %-16.16s)", i + chip->base, + chip->names[i], label); + seq_printf(s, " %c", sppctl_gpio_get_direction(chip, i) ? 'I' : 'O'); + seq_printf(s, ":%d", sppctl_gpio_get(chip, i)); + seq_printf(s, " %s", sppctl_first_get(chip, i) ? "gpi" : "mux"); + seq_printf(s, " %s", sppctl_master_get(chip, i) ? "gpi" : "iop"); + seq_printf(s, " %s", sppctl_gpio_inv_get(chip, i) ? "inv" : " "); + seq_printf(s, " %s", sppctl_gpio_output_od_get(chip, i) ? "oDr" : ""); + seq_puts(s, "\n"); + } +} +#endif + +static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pctl) +{ + struct sppctl_gpio_chip *spp_gchip; + struct gpio_chip *gchip; + int err; + + spp_gchip = devm_kzalloc(&pdev->dev, sizeof(*spp_gchip), GFP_KERNEL); + if (!spp_gchip) + return -ENOMEM; + pctl->spp_gchip = spp_gchip; + + spp_gchip->gpioxt_base = pctl->gpioxt_base; + spp_gchip->first_base = pctl->first_base; + spin_lock_init(&spp_gchip->lock); + + gchip = &spp_gchip->chip; + gchip->label = SPPCTL_MODULE_NAME; + gchip->parent = &pdev->dev; + gchip->owner = THIS_MODULE; + gchip->request = gpiochip_generic_request; + gchip->free = gpiochip_generic_free; + gchip->get_direction = sppctl_gpio_get_direction; + gchip->direction_input = sppctl_gpio_direction_input; + gchip->direction_output = sppctl_gpio_direction_output; + gchip->get = sppctl_gpio_get; + gchip->set = sppctl_gpio_set; + gchip->set_config = sppctl_gpio_set_config; +#ifdef CONFIG_DEBUG_FS + gchip->dbg_show = sppctl_gpio_dbg_show; +#endif + gchip->base = -1; + gchip->ngpio = sppctl_gpio_list_sz; + gchip->names = sppctl_gpio_list_s; + gchip->of_gpio_n_cells = 2; + + pctl->pctl_grange.npins = gchip->ngpio; + pctl->pctl_grange.name = gchip->label; + pctl->pctl_grange.gc = gchip; + + err = devm_gpiochip_add_data(&pdev->dev, gchip, spp_gchip); + if (err) + return dev_err_probe(&pdev->dev, err, "Failed to add gpiochip!\n"); + + return 0; +} + +static int sppctl_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + unsigned int param = pinconf_to_config_param(*config); + unsigned int arg; + + switch (param) { + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!sppctl_gpio_output_od_get(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + arg = 0; + break; + + case PIN_CONFIG_OUTPUT: + if (!sppctl_first_get(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + if (!sppctl_master_get(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + if (sppctl_gpio_get_direction(&pctl->spp_gchip->chip, pin)) + return -EINVAL; + arg = sppctl_gpio_get(&pctl->spp_gchip->chip, pin); + break; + + default: + return -EOPNOTSUPP; + } + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int sppctl_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + int i; + + /* Special handling for IOP pins */ + if (configs[0] == SPPCTL_IOP_CONFIGS) { + sppctl_first_master_set(&pctl->spp_gchip->chip, pin, mux_f_gpio, mux_m_iop); + return 0; + } + + for (i = 0; i < num_configs; i++) { + if (configs[i] & SPPCTL_PCTL_L_OUT) + sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 0); + if (configs[i] & SPPCTL_PCTL_L_OU1) + sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 1); + if (configs[i] & SPPCTL_PCTL_L_INV) + sppctl_gpio_input_inv_set(&pctl->spp_gchip->chip, pin); + if (configs[i] & SPPCTL_PCTL_L_ONV) + sppctl_gpio_output_inv_set(&pctl->spp_gchip->chip, pin); + if (configs[i] & SPPCTL_PCTL_L_ODR) + sppctl_gpio_output_od_set(&pctl->spp_gchip->chip, pin, 1); + } + + return 0; +} + +static const struct pinconf_ops sppctl_pconf_ops = { + .is_generic = true, + .pin_config_get = sppctl_pin_config_get, + .pin_config_set = sppctl_pin_config_set, +}; + +static int sppctl_get_functions_count(struct pinctrl_dev *pctldev) +{ + return sppctl_list_funcs_sz; +} + +static const char *sppctl_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return sppctl_list_funcs[selector].name; +} + +static int sppctl_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, unsigned int *num_groups) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct sppctl_func *f = &sppctl_list_funcs[selector]; + int i; + + *num_groups = 0; + switch (f->type) { + case pinmux_type_fpmx: + *num_groups = sppctl_pmux_list_sz; + *groups = sppctl_pmux_list_s; + break; + + case pinmux_type_grp: + if (!f->grps) + break; + + *num_groups = f->gnum; + for (i = 0; i < pctl->unq_grps_sz; i++) + if (pctl->g2fp_maps[i].f_idx == selector) + break; + *groups = &pctl->unq_grps[i]; + break; + + default: + dev_err(pctldev->dev, "Unknown pinmux (selector: %d, type: %d)\n", + selector, f->type); + break; + } + + return 0; +} + +/** + * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting + * + * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by + * settings its control-field. Refer to following table: + * + * control-field | GPIO + * --------------+-------- + * 0 | No map + * 1 | 8 + * 2 | 9 + * 3 | 10 + * : | : + * 65 | 71 + */ +static inline int sppctl_fully_pinmux_conv(unsigned int offset) +{ + return (offset < 8) ? 0 : offset - 7; +} + +static int sppctl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, + unsigned int group_selector) +{ + const struct sppctl_func *f = &sppctl_list_funcs[func_selector]; + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + struct grp2fp_map g2fpm = pctl->g2fp_maps[group_selector]; + int i; + + switch (f->type) { + case pinmux_type_fpmx: + sppctl_first_master_set(&pctl->spp_gchip->chip, group_selector, + mux_f_mux, mux_m_keep); + sppctl_func_set(pctl, func_selector, sppctl_fully_pinmux_conv(group_selector)); + break; + + case pinmux_type_grp: + for (i = 0; i < f->grps[g2fpm.g_idx].pnum; i++) + sppctl_first_master_set(&pctl->spp_gchip->chip, + f->grps[g2fpm.g_idx].pins[i], + mux_f_mux, mux_m_keep); + sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, f->grps[g2fpm.g_idx].gval); + break; + + default: + dev_err(pctldev->dev, "Unknown pinmux type (func_selector: %d, type: %d)\n", + func_selector, f->type); + break; + } + + return 0; +} + +static int sppctl_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, unsigned int offset) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + int g_f, g_m; + + g_f = sppctl_first_get(&pctl->spp_gchip->chip, offset); + g_m = sppctl_master_get(&pctl->spp_gchip->chip, offset); + if (g_f == mux_f_gpio && g_m == mux_m_gpio) + return 0; + + sppctl_first_master_set(&pctl->spp_gchip->chip, offset, mux_f_gpio, mux_m_gpio); + return 0; +} + +static const struct pinmux_ops sppctl_pinmux_ops = { + .get_functions_count = sppctl_get_functions_count, + .get_function_name = sppctl_get_function_name, + .get_function_groups = sppctl_get_function_groups, + .set_mux = sppctl_set_mux, + .gpio_request_enable = sppctl_gpio_request_enable, + .strict = true, +}; + +static int sppctl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->unq_grps_sz; +} + +static const char *sppctl_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->unq_grps[selector]; +} + +static int sppctl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + struct grp2fp_map g2fpm = pctl->g2fp_maps[selector]; + const struct sppctl_func *f; + + f = &sppctl_list_funcs[g2fpm.f_idx]; + *num_pins = 0; + + /* Except group-pinmux, each group has 1 pin. */ + if (f->type != pinmux_type_grp) { + *num_pins = 1; + *pins = &sppctl_pins_gpio[selector]; + return 0; + } + + /* Group-pinmux may have more than one pin. */ + if (!f->grps) + return 0; + + if (f->gnum < 1) + return 0; + + *num_pins = f->grps[g2fpm.g_idx].pnum; + *pins = f->grps[g2fpm.g_idx].pins; + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +static void sppctl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, + unsigned int offset) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + const char *pin_type; + u8 first, master; + + first = sppctl_first_get(&pctl->spp_gchip->chip, offset); + master = sppctl_master_get(&pctl->spp_gchip->chip, offset); + if (first) + if (master) + pin_type = "GPIO"; + else + pin_type = " IOP"; + else + pin_type = " MUX"; + seq_printf(s, " %s", pin_type); +} +#endif + +static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config, + struct pinctrl_map **map, unsigned int *num_maps) +{ + struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev); + int nmG = of_property_count_strings(np_config, "groups"); + const struct sppctl_func *f = NULL; + u8 pin_num, pin_type, pin_func; + struct device_node *parent; + unsigned long *configs; + struct property *prop; + const char *s_f, *s_g; + + const __be32 *list; + u32 dt_pin, dt_fun; + int i, size = 0; + + list = of_get_property(np_config, "sunplus,pins", &size); + + if (nmG <= 0) + nmG = 0; + + parent = of_get_parent(np_config); + *num_maps = size / sizeof(*list); + + /* + * Process property: + * sunplus,pins = < u32 u32 u32 ... >; + * + * Each 32-bit integer defines a individual pin in which: + * + * Bit 32~24: defines GPIO pin number. Its range is 0 ~ 98. + * Bit 23~16: defines types: (1) fully-pinmux pins + * (2) IO processor pins + * (3) digital GPIO pins + * Bit 15~8: defines pins of peripherals (which are defined in + * 'include/dt-binging/pinctrl/sppctl.h'). + * Bit 7~0: defines types or initial-state of digital GPIO pins. + */ + for (i = 0; i < (*num_maps); i++) { + dt_pin = be32_to_cpu(list[i]); + pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); + + if (pin_num >= sppctl_pins_all_sz) { + dev_err(pctldev->dev, "Invalid pin property at index %d (0x%08x)\n", + i, dt_pin); + return -EINVAL; + } + } + + *map = kcalloc(*num_maps + nmG, sizeof(**map), GFP_KERNEL); + for (i = 0; i < (*num_maps); i++) { + dt_pin = be32_to_cpu(list[i]); + pin_num = FIELD_GET(GENMASK(31, 24), dt_pin); + pin_type = FIELD_GET(GENMASK(23, 16), dt_pin); + pin_func = FIELD_GET(GENMASK(15, 8), dt_pin); + (*map)[i].name = parent->name; + + if (pin_type == SPPCTL_PCTL_G_GPIO) { + /* A digital GPIO pin */ + (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[i].data.configs.num_configs = 1; + (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); + configs = kmalloc(sizeof(*configs), GFP_KERNEL); + *configs = FIELD_GET(GENMASK(7, 0), dt_pin); + (*map)[i].data.configs.configs = configs; + + dev_dbg(pctldev->dev, "%s: GPIO (%s)\n", + (*map)[i].data.configs.group_or_pin, + (*configs & (SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_OU1)) ? + "OUT" : "IN"); + } else if (pin_type == SPPCTL_PCTL_G_IOPP) { + /* A IO Processor (IOP) pin */ + (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN; + (*map)[i].data.configs.num_configs = 1; + (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num); + configs = kmalloc(sizeof(*configs), GFP_KERNEL); + *configs = SPPCTL_IOP_CONFIGS; + (*map)[i].data.configs.configs = configs; + + dev_dbg(pctldev->dev, "%s: IOP\n", + (*map)[i].data.configs.group_or_pin); + } else { + /* A fully-pinmux pin */ + (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[i].data.mux.function = sppctl_list_funcs[pin_func].name; + (*map)[i].data.mux.group = pin_get_name(pctldev, pin_num); + + dev_dbg(pctldev->dev, "%s: %s\n", (*map)[i].data.mux.group, + (*map)[i].data.mux.function); + } + } + + /* + * Process properties: + * function = "xxx"; + * groups = "yyy"; + */ + if (nmG > 0 && of_property_read_string(np_config, "function", &s_f) == 0) { + of_property_for_each_string(np_config, "groups", prop, s_g) { + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.function = s_f; + (*map)[*num_maps].data.mux.group = s_g; + (*num_maps)++; + + dev_dbg(pctldev->dev, "%s: %s\n", s_f, s_g); + } + } + + /* + * Process property: + * sunplus,zerofunc = < u32 u32 u32 ...> + */ + list = of_get_property(np_config, "sunplus,zerofunc", &size); + if (list) { + for (i = 0; i < (size / sizeof(*list)); i++) { + dt_fun = be32_to_cpu(list[i]); + if (dt_fun >= sppctl_list_funcs_sz) { + dev_err(pctldev->dev, "Zero-func %d out of range!\n", + dt_fun); + continue; + } + + f = &sppctl_list_funcs[dt_fun]; + switch (f->type) { + case pinmux_type_fpmx: + sppctl_func_set(pctl, dt_fun, 0); + dev_dbg(pctldev->dev, "%s: No map\n", f->name); + break; + + case pinmux_type_grp: + sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, 0); + dev_dbg(pctldev->dev, "%s: No map\n", f->name); + break; + + default: + dev_err(pctldev->dev, "Wrong zero-group: %d (%s)\n", + dt_fun, f->name); + break; + } + } + } + + of_node_put(parent); + dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps); + return 0; +} + +static const struct pinctrl_ops sppctl_pctl_ops = { + .get_groups_count = sppctl_get_groups_count, + .get_group_name = sppctl_get_group_name, + .get_group_pins = sppctl_get_group_pins, +#ifdef CONFIG_DEBUG_FS + .pin_dbg_show = sppctl_pin_dbg_show, +#endif + .dt_node_to_map = sppctl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int sppctl_group_groups(struct platform_device *pdev) +{ + struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); + int i, k, j; + + /* Calculate number of total group (GPIO + group-pinmux group). */ + sppctl->unq_grps_sz = sppctl_gpio_list_sz; + for (i = 0; i < sppctl_list_funcs_sz; i++) + if (sppctl_list_funcs[i].type == pinmux_type_grp) + sppctl->unq_grps_sz += sppctl_list_funcs[i].gnum; + + sppctl->unq_grps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, + sizeof(*sppctl->unq_grps), GFP_KERNEL); + if (!sppctl->unq_grps) + return -ENOMEM; + + sppctl->g2fp_maps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1, + sizeof(*sppctl->g2fp_maps), GFP_KERNEL); + if (!sppctl->g2fp_maps) + return -ENOMEM; + + /* Add GPIO pins. */ + for (i = 0; i < sppctl_gpio_list_sz; i++) { + sppctl->unq_grps[i] = sppctl_gpio_list_s[i]; + sppctl->g2fp_maps[i].f_idx = 0; + sppctl->g2fp_maps[i].g_idx = i; + } + + /* Add group-pinmux to end of GPIO pins. */ + j = sppctl_gpio_list_sz; + for (i = 0; i < sppctl_list_funcs_sz; i++) { + if (sppctl_list_funcs[i].type != pinmux_type_grp) + continue; + + for (k = 0; k < sppctl_list_funcs[i].gnum; k++) { + sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name; + sppctl->g2fp_maps[j].f_idx = i; + sppctl->g2fp_maps[j].g_idx = k; + j++; + } + } + + return 0; +} + +static int sppctl_pinctrl_init(struct platform_device *pdev) +{ + struct sppctl_pdata *sppctl = platform_get_drvdata(pdev); + int err; + + sppctl->pctl_desc.owner = THIS_MODULE; + sppctl->pctl_desc.name = dev_name(&pdev->dev); + sppctl->pctl_desc.pins = sppctl_pins_all; + sppctl->pctl_desc.npins = sppctl_pins_all_sz; + sppctl->pctl_desc.pctlops = &sppctl_pctl_ops; + sppctl->pctl_desc.confops = &sppctl_pconf_ops; + sppctl->pctl_desc.pmxops = &sppctl_pinmux_ops; + + err = sppctl_group_groups(pdev); + if (err) + return err; + + err = devm_pinctrl_register_and_init(&pdev->dev, &sppctl->pctl_desc, + sppctl, &sppctl->pctl_dev); + if (err) + return dev_err_probe(&pdev->dev, err, "Failed to register pinctrl!\n"); + + pinctrl_enable(sppctl->pctl_dev); + return 0; +} + +static int sppctl_resource_map(struct platform_device *pdev, struct sppctl_pdata *sppctl) +{ + sppctl->moon2_base = devm_platform_ioremap_resource_byname(pdev, "moon2"); + if (IS_ERR(sppctl->moon2_base)) + return PTR_ERR(sppctl->moon2_base); + + sppctl->gpioxt_base = devm_platform_ioremap_resource_byname(pdev, "gpioxt"); + if (IS_ERR(sppctl->gpioxt_base)) + return PTR_ERR(sppctl->gpioxt_base); + + sppctl->first_base = devm_platform_ioremap_resource_byname(pdev, "first"); + if (IS_ERR(sppctl->first_base)) + return PTR_ERR(sppctl->first_base); + + sppctl->moon1_base = devm_platform_ioremap_resource_byname(pdev, "moon1"); + if (IS_ERR(sppctl->moon1_base)) + return PTR_ERR(sppctl->moon1_base); + + return 0; +} + +static int sppctl_probe(struct platform_device *pdev) +{ + struct sppctl_pdata *sppctl; + int ret; + + sppctl = devm_kzalloc(&pdev->dev, sizeof(*sppctl), GFP_KERNEL); + if (!sppctl) + return -ENOMEM; + platform_set_drvdata(pdev, sppctl); + + ret = sppctl_resource_map(pdev, sppctl); + if (ret) + return ret; + + ret = sppctl_gpio_new(pdev, sppctl); + if (ret) + return ret; + + ret = sppctl_pinctrl_init(pdev); + if (ret) + return ret; + + pinctrl_add_gpio_range(sppctl->pctl_dev, &sppctl->pctl_grange); + + return 0; +} + +static const struct of_device_id sppctl_match_table[] = { + { .compatible = "sunplus,sp7021-pctl" }, + { /* sentinel */ } +}; + +static struct platform_driver sppctl_pinctrl_driver = { + .driver = { + .name = SPPCTL_MODULE_NAME, + .of_match_table = sppctl_match_table, + }, + .probe = sppctl_probe, +}; +builtin_platform_driver(sppctl_pinctrl_driver) + +MODULE_AUTHOR("Dvorkin Dmitry "); +MODULE_AUTHOR("Wells Lu "); +MODULE_DESCRIPTION("Sunplus SP7021 Pin Control and GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/sunplus/sppctl.h b/drivers/pinctrl/sunplus/sppctl.h new file mode 100644 index 000000000000..6210f2200586 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#ifndef __SPPCTL_H__ +#define __SPPCTL_H__ + +#include +#include +#include +#include +#include +#include + +#define SPPCTL_MODULE_NAME "sppctl_sp7021" + +#define SPPCTL_GPIO_OFF_FIRST 0x00 +#define SPPCTL_GPIO_OFF_MASTER 0x00 +#define SPPCTL_GPIO_OFF_OE 0x20 +#define SPPCTL_GPIO_OFF_OUT 0x40 +#define SPPCTL_GPIO_OFF_IN 0x60 +#define SPPCTL_GPIO_OFF_IINV 0x80 +#define SPPCTL_GPIO_OFF_OINV 0xa0 +#define SPPCTL_GPIO_OFF_OD 0xc0 + +#define SPPCTL_FULLY_PINMUX_MASK_MASK GENMASK(22, 16) +#define SPPCTL_FULLY_PINMUX_SEL_MASK GENMASK(6, 0) +#define SPPCTL_FULLY_PINMUX_UPPER_SHIFT 8 + +/* + * Mask-fields and control-fields of MOON registers of SP7021 are + * arranged as shown below: + * + * register | mask-fields | control-fields + * ----------+--------------+---------------- + * base[0] | (31 : 16) | (15 : 0) + * base[1] | (31 : 24) | (15 : 0) + * base[2] | (31 : 24) | (15 : 0) + * : | : | : + * + * where mask-fields are used to protect control-fields from write-in + * accidentally. Set the corresponding bits in the mask-field before + * you write a value into a control-field. + */ +#define SPPCTL_MOON_REG_MASK_SHIFT 16 +#define SPPCTL_SET_MOON_REG_BIT(bit) (BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) | BIT(bit)) +#define SPPCTL_CLR_MOON_REG_BIT(bit) BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) + +#define SPPCTL_IOP_CONFIGS 0xff + +#define FNCE(n, r, o, bo, bl, g) { \ + .name = n, \ + .type = r, \ + .roff = o, \ + .boff = bo, \ + .blen = bl, \ + .grps = (g), \ + .gnum = ARRAY_SIZE(g), \ +} + +#define FNCN(n, r, o, bo, bl) { \ + .name = n, \ + .type = r, \ + .roff = o, \ + .boff = bo, \ + .blen = bl, \ + .grps = NULL, \ + .gnum = 0, \ +} + +#define EGRP(n, v, p) { \ + .name = n, \ + .gval = (v), \ + .pins = (p), \ + .pnum = ARRAY_SIZE(p), \ +} + +/** + * enum mux_first_reg - Define modes of access of FIRST register + * @mux_f_mux: Set the corresponding pin to a fully-pinmux pin + * @mux_f_gpio: Set the corresponding pin to a GPIO or IOP pin + * @mux_f_keep: Don't change (keep intact) + */ +enum mux_first_reg { + mux_f_mux = 0, + mux_f_gpio = 1, + mux_f_keep = 2, +}; + +/** + * enum mux_master_reg - Define modes of access of MASTER register + * @mux_m_iop: Set the corresponding pin to an IO processor (IOP) pin + * @mux_m_gpio: Set the corresponding pin to a digital GPIO pin + * @mux_m_keep: Don't change (keep intact) + */ +enum mux_master_reg { + mux_m_iop = 0, + mux_m_gpio = 1, + mux_m_keep = 2, +}; + +/** + * enum pinmux_type - Define types of pinmux pins + * @pinmux_type_fpmx: A fully-pinmux pin + * @pinmux_type_grp: A group-pinmux pin + */ +enum pinmux_type { + pinmux_type_fpmx, + pinmux_type_grp, +}; + +/** + * struct grp2fp_map - A map storing indexes + * @f_idx: an index to function table + * @g_idx: an index to group table + */ +struct grp2fp_map { + u16 f_idx; + u16 g_idx; +}; + +struct sppctl_gpio_chip; + +struct sppctl_pdata { + void __iomem *moon2_base; /* MOON2 */ + void __iomem *gpioxt_base; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */ + void __iomem *first_base; /* FIRST */ + void __iomem *moon1_base; /* MOON1 */ + + struct pinctrl_desc pctl_desc; + struct pinctrl_dev *pctl_dev; + struct pinctrl_gpio_range pctl_grange; + struct sppctl_gpio_chip *spp_gchip; + + char const **unq_grps; + size_t unq_grps_sz; + struct grp2fp_map *g2fp_maps; +}; + +struct sppctl_grp { + const char * const name; + const u8 gval; /* group number */ + const unsigned * const pins; /* list of pins */ + const unsigned int pnum; /* number of pins */ +}; + +struct sppctl_func { + const char * const name; + const enum pinmux_type type; /* function type */ + const u8 roff; /* register offset */ + const u8 boff; /* bit offset */ + const u8 blen; /* bit length */ + const struct sppctl_grp * const grps; /* list of groups */ + const unsigned int gnum; /* number of groups */ +}; + +extern const struct sppctl_func sppctl_list_funcs[]; +extern const char * const sppctl_pmux_list_s[]; +extern const char * const sppctl_gpio_list_s[]; +extern const struct pinctrl_pin_desc sppctl_pins_all[]; +extern const unsigned int sppctl_pins_gpio[]; + +extern const size_t sppctl_list_funcs_sz; +extern const size_t sppctl_pmux_list_sz; +extern const size_t sppctl_gpio_list_sz; +extern const size_t sppctl_pins_all_sz; + +#endif diff --git a/drivers/pinctrl/sunplus/sppctl_sp7021.c b/drivers/pinctrl/sunplus/sppctl_sp7021.c new file mode 100644 index 000000000000..9748345b9298 --- /dev/null +++ b/drivers/pinctrl/sunplus/sppctl_sp7021.c @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SP7021 Pin Controller Driver. + * Copyright (C) Sunplus Tech / Tibbo Tech. + */ + +#include +#include +#include + +#include "sppctl.h" + +#define D_PIS(x, y) "P" __stringify(x) "_0" __stringify(y) +#define D(x, y) ((x) * 8 + (y)) +#define P(x, y) PINCTRL_PIN(D(x, y), D_PIS(x, y)) + +const char * const sppctl_gpio_list_s[] = { + D_PIS(0, 0), D_PIS(0, 1), D_PIS(0, 2), D_PIS(0, 3), + D_PIS(0, 4), D_PIS(0, 5), D_PIS(0, 6), D_PIS(0, 7), + D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), + D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), + D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), + D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), + D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), + D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), + D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), + D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), + D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), + D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), + D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), + D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), + D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), + D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), + D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), + D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), + D_PIS(9, 0), D_PIS(9, 1), D_PIS(9, 2), D_PIS(9, 3), + D_PIS(9, 4), D_PIS(9, 5), D_PIS(9, 6), D_PIS(9, 7), + D_PIS(10, 0), D_PIS(10, 1), D_PIS(10, 2), D_PIS(10, 3), + D_PIS(10, 4), D_PIS(10, 5), D_PIS(10, 6), D_PIS(10, 7), + D_PIS(11, 0), D_PIS(11, 1), D_PIS(11, 2), D_PIS(11, 3), + D_PIS(11, 4), D_PIS(11, 5), D_PIS(11, 6), D_PIS(11, 7), + D_PIS(12, 0), D_PIS(12, 1), D_PIS(12, 2), +}; + +const size_t sppctl_gpio_list_sz = ARRAY_SIZE(sppctl_gpio_list_s); + +const unsigned int sppctl_pins_gpio[] = { + D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), + D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), + D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), + D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), + D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), + D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), + D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), + D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), + D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), + D(11, 0), D(11, 1), D(11, 2), D(11, 3), D(11, 4), D(11, 5), D(11, 6), D(11, 7), + D(12, 0), D(12, 1), D(12, 2), +}; + +const struct pinctrl_pin_desc sppctl_pins_all[] = { + /* gpio and iop only */ + P(0, 0), P(0, 1), P(0, 2), P(0, 3), P(0, 4), P(0, 5), P(0, 6), P(0, 7), + /* gpio, iop, muxable */ + P(1, 0), P(1, 1), P(1, 2), P(1, 3), P(1, 4), P(1, 5), P(1, 6), P(1, 7), + P(2, 0), P(2, 1), P(2, 2), P(2, 3), P(2, 4), P(2, 5), P(2, 6), P(2, 7), + P(3, 0), P(3, 1), P(3, 2), P(3, 3), P(3, 4), P(3, 5), P(3, 6), P(3, 7), + P(4, 0), P(4, 1), P(4, 2), P(4, 3), P(4, 4), P(4, 5), P(4, 6), P(4, 7), + P(5, 0), P(5, 1), P(5, 2), P(5, 3), P(5, 4), P(5, 5), P(5, 6), P(5, 7), + P(6, 0), P(6, 1), P(6, 2), P(6, 3), P(6, 4), P(6, 5), P(6, 6), P(6, 7), + P(7, 0), P(7, 1), P(7, 2), P(7, 3), P(7, 4), P(7, 5), P(7, 6), P(7, 7), + P(8, 0), P(8, 1), P(8, 2), P(8, 3), P(8, 4), P(8, 5), P(8, 6), P(8, 7), + /* gpio and iop only */ + P(9, 0), P(9, 1), P(9, 2), P(9, 3), P(9, 4), P(9, 5), P(9, 6), P(9, 7), + P(10, 0), P(10, 1), P(10, 2), P(10, 3), P(10, 4), P(10, 5), P(10, 6), P(10, 7), + P(11, 0), P(11, 1), P(11, 2), P(11, 3), P(11, 4), P(11, 5), P(11, 6), P(11, 7), + P(12, 0), P(12, 1), P(12, 2), +}; + +const size_t sppctl_pins_all_sz = ARRAY_SIZE(sppctl_pins_all); + +const char * const sppctl_pmux_list_s[] = { + D_PIS(0, 0), + D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3), + D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7), + D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3), + D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7), + D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3), + D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7), + D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3), + D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7), + D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3), + D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7), + D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3), + D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7), + D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3), + D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7), + D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3), + D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7), +}; + +const size_t sppctl_pmux_list_sz = ARRAY_SIZE(sppctl_pmux_list_s); + +static const unsigned int pins_spif1[] = { + D(10, 3), D(10, 4), D(10, 6), D(10, 7), +}; + +static const unsigned int pins_spif2[] = { + D(9, 4), D(9, 6), D(9, 7), D(10, 1), +}; + +static const struct sppctl_grp sp7021grps_spif[] = { + EGRP("SPI_FLASH1", 1, pins_spif1), + EGRP("SPI_FLASH2", 2, pins_spif2), +}; + +static const unsigned int pins_spi41[] = { + D(10, 2), D(10, 5), +}; + +static const unsigned int pins_spi42[] = { + D(9, 5), D(9, 8), +}; + +static const struct sppctl_grp sp7021grps_spi4[] = { + EGRP("SPI_FLASH_4BIT1", 1, pins_spi41), + EGRP("SPI_FLASH_4BIT2", 2, pins_spi42), +}; + +static const unsigned int pins_snan[] = { + D(9, 4), D(9, 5), D(9, 6), D(9, 7), D(10, 0), D(10, 1), +}; + +static const struct sppctl_grp sp7021grps_snan[] = { + EGRP("SPI_NAND", 1, pins_snan), +}; + +static const unsigned int pins_emmc[] = { + D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), + D(9, 6), D(9, 7), D(10, 0), D(10, 1), +}; + +static const struct sppctl_grp sp7021grps_emmc[] = { + EGRP("CARD0_EMMC", 1, pins_emmc), +}; + +static const unsigned int pins_sdsd[] = { + D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), +}; + +static const struct sppctl_grp sp7021grps_sdsd[] = { + EGRP("SD_CARD", 1, pins_sdsd), +}; + +static const unsigned int pins_uar0[] = { + D(11, 0), D(11, 1), +}; + +static const struct sppctl_grp sp7021grps_uar0[] = { + EGRP("UA0", 1, pins_uar0), +}; + +static const unsigned int pins_adbg1[] = { + D(10, 2), D(10, 3), +}; + +static const unsigned int pins_adbg2[] = { + D(7, 1), D(7, 2), +}; + +static const struct sppctl_grp sp7021grps_adbg[] = { + EGRP("ACHIP_DEBUG1", 1, pins_adbg1), + EGRP("ACHIP_DEBUG2", 2, pins_adbg2), +}; + +static const unsigned int pins_aua2axi1[] = { + D(2, 0), D(2, 1), D(2, 2), +}; + +static const unsigned int pins_aua2axi2[] = { + D(1, 0), D(1, 1), D(1, 2), +}; + +static const struct sppctl_grp sp7021grps_au2x[] = { + EGRP("ACHIP_UA2AXI1", 1, pins_aua2axi1), + EGRP("ACHIP_UA2AXI2", 2, pins_aua2axi2), +}; + +static const unsigned int pins_fpga[] = { + D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), + D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), + D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), + D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), + D(4, 6), D(4, 7), D(5, 0), D(5, 1), D(5, 2), +}; + +static const struct sppctl_grp sp7021grps_fpga[] = { + EGRP("FPGA_IFX", 1, pins_fpga), +}; + +static const unsigned int pins_hdmi1[] = { + D(10, 6), D(12, 2), D(12, 1), +}; + +static const unsigned int pins_hdmi2[] = { + D(8, 3), D(8, 5), D(8, 6), +}; + +static const unsigned int pins_hdmi3[] = { + D(7, 4), D(7, 6), D(7, 7), +}; + +static const struct sppctl_grp sp7021grps_hdmi[] = { + EGRP("HDMI_TX1", 1, pins_hdmi1), + EGRP("HDMI_TX2", 2, pins_hdmi2), + EGRP("HDMI_TX3", 3, pins_hdmi3), +}; + +static const unsigned int pins_eadc[] = { + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), +}; + +static const struct sppctl_grp sp7021grps_eadc[] = { + EGRP("AUD_EXT_ADC_IFX0", 1, pins_eadc), +}; + +static const unsigned int pins_edac[] = { + D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 4), +}; + +static const struct sppctl_grp sp7021grps_edac[] = { + EGRP("AUD_EXT_DAC_IFX0", 1, pins_edac), +}; + +static const unsigned int pins_spdi[] = { + D(2, 4), +}; + +static const struct sppctl_grp sp7021grps_spdi[] = { + EGRP("AUD_IEC_RX0", 1, pins_spdi), +}; + +static const unsigned int pins_spdo[] = { + D(3, 6), +}; + +static const struct sppctl_grp sp7021grps_spdo[] = { + EGRP("AUD_IEC_TX0", 1, pins_spdo), +}; + +static const unsigned int pins_tdmt[] = { + D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), +}; + +static const struct sppctl_grp sp7021grps_tdmt[] = { + EGRP("TDMTX_IFX0", 1, pins_tdmt), +}; + +static const unsigned int pins_tdmr[] = { + D(1, 7), D(2, 0), D(2, 1), D(2, 2), +}; + +static const struct sppctl_grp sp7021grps_tdmr[] = { + EGRP("TDMRX_IFX0", 1, pins_tdmr), +}; + +static const unsigned int pins_pdmr[] = { + D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), +}; + +static const struct sppctl_grp sp7021grps_pdmr[] = { + EGRP("PDMRX_IFX0", 1, pins_pdmr), +}; + +static const unsigned int pins_pcmt[] = { + D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), +}; + +static const struct sppctl_grp sp7021grps_pcmt[] = { + EGRP("PCM_IEC_TX", 1, pins_pcmt), +}; + +static const unsigned int pins_lcdi[] = { + D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3), + D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 3), + D(3, 4), D(3, 5), D(3, 6), D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), + D(4, 4), D(4, 5), D(4, 6), D(4, 7), +}; + +static const struct sppctl_grp sp7021grps_lcdi[] = { + EGRP("LCDIF", 1, pins_lcdi), +}; + +static const unsigned int pins_dvdd[] = { + D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), + D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), +}; + +static const struct sppctl_grp sp7021grps_dvdd[] = { + EGRP("DVD_DSP_DEBUG", 1, pins_dvdd), +}; + +static const unsigned int pins_i2cd[] = { + D(1, 0), D(1, 1), +}; + +static const struct sppctl_grp sp7021grps_i2cd[] = { + EGRP("I2C_DEBUG", 1, pins_i2cd), +}; + +static const unsigned int pins_i2cs[] = { + D(0, 0), D(0, 1), +}; + +static const struct sppctl_grp sp7021grps_i2cs[] = { + EGRP("I2C_SLAVE", 1, pins_i2cs), +}; + +static const unsigned int pins_wakp[] = { + D(10, 5), +}; + +static const struct sppctl_grp sp7021grps_wakp[] = { + EGRP("WAKEUP", 1, pins_wakp), +}; + +static const unsigned int pins_u2ax[] = { + D(2, 0), D(2, 1), D(3, 0), D(3, 1), +}; + +static const struct sppctl_grp sp7021grps_u2ax[] = { + EGRP("UART2AXI", 1, pins_u2ax), +}; + +static const unsigned int pins_u0ic[] = { + D(0, 0), D(0, 1), D(0, 4), D(0, 5), D(1, 0), D(1, 1), +}; + +static const struct sppctl_grp sp7021grps_u0ic[] = { + EGRP("USB0_I2C", 1, pins_u0ic), +}; + +static const unsigned int pins_u1ic[] = { + D(0, 2), D(0, 3), D(0, 6), D(0, 7), D(1, 2), D(1, 3), +}; + +static const struct sppctl_grp sp7021grps_u1ic[] = { + EGRP("USB1_I2C", 1, pins_u1ic), +}; + +static const unsigned int pins_u0ot[] = { + D(11, 2), +}; + +static const struct sppctl_grp sp7021grps_u0ot[] = { + EGRP("USB0_OTG", 1, pins_u0ot), +}; + +static const unsigned int pins_u1ot[] = { + D(11, 3), +}; + +static const struct sppctl_grp sp7021grps_u1ot[] = { + EGRP("USB1_OTG", 1, pins_u1ot), +}; + +static const unsigned int pins_uphd[] = { + D(0, 1), D(0, 2), D(0, 3), D(7, 4), D(7, 5), D(7, 6), + D(7, 7), D(8, 0), D(8, 1), D(8, 2), D(8, 3), + D(9, 7), D(10, 2), D(10, 3), D(10, 4), +}; + +static const struct sppctl_grp sp7021grps_up0d[] = { + EGRP("UPHY0_DEBUG", 1, pins_uphd), +}; + +static const struct sppctl_grp sp7021grps_up1d[] = { + EGRP("UPHY1_DEBUG", 1, pins_uphd), +}; + +static const unsigned int pins_upex[] = { + D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), + D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), + D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), + D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), + D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7), + D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7), + D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7), + D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7), + D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7), +}; + +static const struct sppctl_grp sp7021grps_upex[] = { + EGRP("UPHY0_EXT", 1, pins_upex), +}; + +static const unsigned int pins_prp1[] = { + D(0, 6), D(0, 7), + D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7), + D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7), + D(3, 0), D(3, 1), D(3, 2), +}; + +static const unsigned int pins_prp2[] = { + D(3, 4), D(3, 6), D(3, 7), + D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7), + D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7), + D(6, 4), +}; + +static const struct sppctl_grp sp7021grps_prbp[] = { + EGRP("PROBE_PORT1", 1, pins_prp1), + EGRP("PROBE_PORT2", 2, pins_prp2), +}; + +const struct sppctl_func sppctl_list_funcs[] = { + FNCN("L2SW_CLK_OUT", pinmux_type_fpmx, 0x00, 0, 7), + FNCN("L2SW_MAC_SMI_MDC", pinmux_type_fpmx, 0x00, 8, 7), + FNCN("L2SW_LED_FLASH0", pinmux_type_fpmx, 0x01, 0, 7), + FNCN("L2SW_LED_FLASH1", pinmux_type_fpmx, 0x01, 8, 7), + FNCN("L2SW_LED_ON0", pinmux_type_fpmx, 0x02, 0, 7), + FNCN("L2SW_LED_ON1", pinmux_type_fpmx, 0x02, 8, 7), + FNCN("L2SW_MAC_SMI_MDIO", pinmux_type_fpmx, 0x03, 0, 7), + FNCN("L2SW_P0_MAC_RMII_TXEN", pinmux_type_fpmx, 0x03, 8, 7), + FNCN("L2SW_P0_MAC_RMII_TXD0", pinmux_type_fpmx, 0x04, 0, 7), + FNCN("L2SW_P0_MAC_RMII_TXD1", pinmux_type_fpmx, 0x04, 8, 7), + FNCN("L2SW_P0_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x05, 0, 7), + FNCN("L2SW_P0_MAC_RMII_RXD0", pinmux_type_fpmx, 0x05, 8, 7), + FNCN("L2SW_P0_MAC_RMII_RXD1", pinmux_type_fpmx, 0x06, 0, 7), + FNCN("L2SW_P0_MAC_RMII_RXER", pinmux_type_fpmx, 0x06, 8, 7), + FNCN("L2SW_P1_MAC_RMII_TXEN", pinmux_type_fpmx, 0x07, 0, 7), + FNCN("L2SW_P1_MAC_RMII_TXD0", pinmux_type_fpmx, 0x07, 8, 7), + FNCN("L2SW_P1_MAC_RMII_TXD1", pinmux_type_fpmx, 0x08, 0, 7), + FNCN("L2SW_P1_MAC_RMII_CRSDV", pinmux_type_fpmx, 0x08, 8, 7), + FNCN("L2SW_P1_MAC_RMII_RXD0", pinmux_type_fpmx, 0x09, 0, 7), + FNCN("L2SW_P1_MAC_RMII_RXD1", pinmux_type_fpmx, 0x09, 8, 7), + FNCN("L2SW_P1_MAC_RMII_RXER", pinmux_type_fpmx, 0x0A, 0, 7), + FNCN("DAISY_MODE", pinmux_type_fpmx, 0x0A, 8, 7), + FNCN("SDIO_CLK", pinmux_type_fpmx, 0x0B, 0, 7), /* 1x SDIO */ + FNCN("SDIO_CMD", pinmux_type_fpmx, 0x0B, 8, 7), + FNCN("SDIO_D0", pinmux_type_fpmx, 0x0C, 0, 7), + FNCN("SDIO_D1", pinmux_type_fpmx, 0x0C, 8, 7), + FNCN("SDIO_D2", pinmux_type_fpmx, 0x0D, 0, 7), + FNCN("SDIO_D3", pinmux_type_fpmx, 0x0D, 8, 7), + FNCN("PWM0", pinmux_type_fpmx, 0x0E, 0, 7), /* 8x PWM */ + FNCN("PWM1", pinmux_type_fpmx, 0x0E, 8, 7), + FNCN("PWM2", pinmux_type_fpmx, 0x0F, 0, 7), + FNCN("PWM3", pinmux_type_fpmx, 0x0F, 8, 7), + + FNCN("PWM4", pinmux_type_fpmx, 0x10, 0, 7), + FNCN("PWM5", pinmux_type_fpmx, 0x10, 8, 7), + FNCN("PWM6", pinmux_type_fpmx, 0x11, 0, 7), + FNCN("PWM7", pinmux_type_fpmx, 0x11, 8, 7), + FNCN("ICM0_D", pinmux_type_fpmx, 0x12, 0, 7), /* 4x Input captures */ + FNCN("ICM1_D", pinmux_type_fpmx, 0x12, 8, 7), + FNCN("ICM2_D", pinmux_type_fpmx, 0x13, 0, 7), + FNCN("ICM3_D", pinmux_type_fpmx, 0x13, 8, 7), + FNCN("ICM0_CLK", pinmux_type_fpmx, 0x14, 0, 7), + FNCN("ICM1_CLK", pinmux_type_fpmx, 0x14, 8, 7), + FNCN("ICM2_CLK", pinmux_type_fpmx, 0x15, 0, 7), + FNCN("ICM3_CLK", pinmux_type_fpmx, 0x15, 8, 7), + FNCN("SPIM0_INT", pinmux_type_fpmx, 0x16, 0, 7), /* 4x SPI masters */ + FNCN("SPIM0_CLK", pinmux_type_fpmx, 0x16, 8, 7), + FNCN("SPIM0_EN", pinmux_type_fpmx, 0x17, 0, 7), + FNCN("SPIM0_DO", pinmux_type_fpmx, 0x17, 8, 7), + FNCN("SPIM0_DI", pinmux_type_fpmx, 0x18, 0, 7), + FNCN("SPIM1_INT", pinmux_type_fpmx, 0x18, 8, 7), + FNCN("SPIM1_CLK", pinmux_type_fpmx, 0x19, 0, 7), + FNCN("SPIM1_EN", pinmux_type_fpmx, 0x19, 8, 7), + FNCN("SPIM1_DO", pinmux_type_fpmx, 0x1A, 0, 7), + FNCN("SPIM1_DI", pinmux_type_fpmx, 0x1A, 8, 7), + FNCN("SPIM2_INT", pinmux_type_fpmx, 0x1B, 0, 7), + FNCN("SPIM2_CLK", pinmux_type_fpmx, 0x1B, 8, 7), + FNCN("SPIM2_EN", pinmux_type_fpmx, 0x1C, 0, 7), + FNCN("SPIM2_DO", pinmux_type_fpmx, 0x1C, 8, 7), + FNCN("SPIM2_DI", pinmux_type_fpmx, 0x1D, 0, 7), + FNCN("SPIM3_INT", pinmux_type_fpmx, 0x1D, 8, 7), + FNCN("SPIM3_CLK", pinmux_type_fpmx, 0x1E, 0, 7), + FNCN("SPIM3_EN", pinmux_type_fpmx, 0x1E, 8, 7), + FNCN("SPIM3_DO", pinmux_type_fpmx, 0x1F, 0, 7), + FNCN("SPIM3_DI", pinmux_type_fpmx, 0x1F, 8, 7), + + FNCN("SPI0S_INT", pinmux_type_fpmx, 0x20, 0, 7), /* 4x SPI slaves */ + FNCN("SPI0S_CLK", pinmux_type_fpmx, 0x20, 8, 7), + FNCN("SPI0S_EN", pinmux_type_fpmx, 0x21, 0, 7), + FNCN("SPI0S_DO", pinmux_type_fpmx, 0x21, 8, 7), + FNCN("SPI0S_DI", pinmux_type_fpmx, 0x22, 0, 7), + FNCN("SPI1S_INT", pinmux_type_fpmx, 0x22, 8, 7), + FNCN("SPI1S_CLK", pinmux_type_fpmx, 0x23, 0, 7), + FNCN("SPI1S_EN", pinmux_type_fpmx, 0x23, 8, 7), + FNCN("SPI1S_DO", pinmux_type_fpmx, 0x24, 0, 7), + FNCN("SPI1S_DI", pinmux_type_fpmx, 0x24, 8, 7), + FNCN("SPI2S_INT", pinmux_type_fpmx, 0x25, 0, 7), + FNCN("SPI2S_CLK", pinmux_type_fpmx, 0x25, 8, 7), + FNCN("SPI2S_EN", pinmux_type_fpmx, 0x26, 0, 7), + FNCN("SPI2S_DO", pinmux_type_fpmx, 0x26, 8, 7), + FNCN("SPI2S_DI", pinmux_type_fpmx, 0x27, 0, 7), + FNCN("SPI3S_INT", pinmux_type_fpmx, 0x27, 8, 7), + FNCN("SPI3S_CLK", pinmux_type_fpmx, 0x28, 0, 7), + FNCN("SPI3S_EN", pinmux_type_fpmx, 0x28, 8, 7), + FNCN("SPI3S_DO", pinmux_type_fpmx, 0x29, 0, 7), + FNCN("SPI3S_DI", pinmux_type_fpmx, 0x29, 8, 7), + FNCN("I2CM0_CLK", pinmux_type_fpmx, 0x2A, 0, 7), /* 4x I2C masters */ + FNCN("I2CM0_DAT", pinmux_type_fpmx, 0x2A, 8, 7), + FNCN("I2CM1_CLK", pinmux_type_fpmx, 0x2B, 0, 7), + FNCN("I2CM1_DAT", pinmux_type_fpmx, 0x2B, 8, 7), + FNCN("I2CM2_CLK", pinmux_type_fpmx, 0x2C, 0, 7), + FNCN("I2CM2_DAT", pinmux_type_fpmx, 0x2C, 8, 7), + FNCN("I2CM3_CLK", pinmux_type_fpmx, 0x2D, 0, 7), + FNCN("I2CM3_DAT", pinmux_type_fpmx, 0x2D, 8, 7), + FNCN("UA1_TX", pinmux_type_fpmx, 0x2E, 0, 7), /* 4x UARTS */ + FNCN("UA1_RX", pinmux_type_fpmx, 0x2E, 8, 7), + FNCN("UA1_CTS", pinmux_type_fpmx, 0x2F, 0, 7), + FNCN("UA1_RTS", pinmux_type_fpmx, 0x2F, 8, 7), + + FNCN("UA2_TX", pinmux_type_fpmx, 0x30, 0, 7), + FNCN("UA2_RX", pinmux_type_fpmx, 0x30, 8, 7), + FNCN("UA2_CTS", pinmux_type_fpmx, 0x31, 0, 7), + FNCN("UA2_RTS", pinmux_type_fpmx, 0x31, 8, 7), + FNCN("UA3_TX", pinmux_type_fpmx, 0x32, 0, 7), + FNCN("UA3_RX", pinmux_type_fpmx, 0x32, 8, 7), + FNCN("UA3_CTS", pinmux_type_fpmx, 0x33, 0, 7), + FNCN("UA3_RTS", pinmux_type_fpmx, 0x33, 8, 7), + FNCN("UA4_TX", pinmux_type_fpmx, 0x34, 0, 7), + FNCN("UA4_RX", pinmux_type_fpmx, 0x34, 8, 7), + FNCN("UA4_CTS", pinmux_type_fpmx, 0x35, 0, 7), + FNCN("UA4_RTS", pinmux_type_fpmx, 0x35, 8, 7), + FNCN("TIMER0_INT", pinmux_type_fpmx, 0x36, 0, 7), /* 4x timer int. */ + FNCN("TIMER1_INT", pinmux_type_fpmx, 0x36, 8, 7), + FNCN("TIMER2_INT", pinmux_type_fpmx, 0x37, 0, 7), + FNCN("TIMER3_INT", pinmux_type_fpmx, 0x37, 8, 7), + FNCN("GPIO_INT0", pinmux_type_fpmx, 0x38, 0, 7), /* 8x GPIO int. */ + FNCN("GPIO_INT1", pinmux_type_fpmx, 0x38, 8, 7), + FNCN("GPIO_INT2", pinmux_type_fpmx, 0x39, 0, 7), + FNCN("GPIO_INT3", pinmux_type_fpmx, 0x39, 8, 7), + FNCN("GPIO_INT4", pinmux_type_fpmx, 0x3A, 0, 7), + FNCN("GPIO_INT5", pinmux_type_fpmx, 0x3A, 8, 7), + FNCN("GPIO_INT6", pinmux_type_fpmx, 0x3B, 0, 7), + FNCN("GPIO_INT7", pinmux_type_fpmx, 0x3B, 8, 7), + + /* MOON1 register */ + FNCE("SPI_FLASH", pinmux_type_grp, 0x01, 0, 2, sp7021grps_spif), + FNCE("SPI_FLASH_4BIT", pinmux_type_grp, 0x01, 2, 2, sp7021grps_spi4), + FNCE("SPI_NAND", pinmux_type_grp, 0x01, 4, 1, sp7021grps_snan), + FNCE("CARD0_EMMC", pinmux_type_grp, 0x01, 5, 1, sp7021grps_emmc), + FNCE("SD_CARD", pinmux_type_grp, 0x01, 6, 1, sp7021grps_sdsd), + FNCE("UA0", pinmux_type_grp, 0x01, 7, 1, sp7021grps_uar0), + FNCE("ACHIP_DEBUG", pinmux_type_grp, 0x01, 8, 2, sp7021grps_adbg), + FNCE("ACHIP_UA2AXI", pinmux_type_grp, 0x01, 10, 2, sp7021grps_au2x), + FNCE("FPGA_IFX", pinmux_type_grp, 0x01, 12, 1, sp7021grps_fpga), + FNCE("HDMI_TX", pinmux_type_grp, 0x01, 13, 2, sp7021grps_hdmi), + + FNCE("AUD_EXT_ADC_IFX0", pinmux_type_grp, 0x01, 15, 1, sp7021grps_eadc), + FNCE("AUD_EXT_DAC_IFX0", pinmux_type_grp, 0x02, 0, 1, sp7021grps_edac), + FNCE("SPDIF_RX", pinmux_type_grp, 0x02, 2, 1, sp7021grps_spdi), + FNCE("SPDIF_TX", pinmux_type_grp, 0x02, 3, 1, sp7021grps_spdo), + FNCE("TDMTX_IFX0", pinmux_type_grp, 0x02, 4, 1, sp7021grps_tdmt), + FNCE("TDMRX_IFX0", pinmux_type_grp, 0x02, 5, 1, sp7021grps_tdmr), + FNCE("PDMRX_IFX0", pinmux_type_grp, 0x02, 6, 1, sp7021grps_pdmr), + FNCE("PCM_IEC_TX", pinmux_type_grp, 0x02, 7, 1, sp7021grps_pcmt), + FNCE("LCDIF", pinmux_type_grp, 0x04, 6, 1, sp7021grps_lcdi), + FNCE("DVD_DSP_DEBUG", pinmux_type_grp, 0x02, 8, 1, sp7021grps_dvdd), + FNCE("I2C_DEBUG", pinmux_type_grp, 0x02, 9, 1, sp7021grps_i2cd), + FNCE("I2C_SLAVE", pinmux_type_grp, 0x02, 10, 1, sp7021grps_i2cs), + FNCE("WAKEUP", pinmux_type_grp, 0x02, 11, 1, sp7021grps_wakp), + FNCE("UART2AXI", pinmux_type_grp, 0x02, 12, 2, sp7021grps_u2ax), + FNCE("USB0_I2C", pinmux_type_grp, 0x02, 14, 2, sp7021grps_u0ic), + FNCE("USB1_I2C", pinmux_type_grp, 0x03, 0, 2, sp7021grps_u1ic), + FNCE("USB0_OTG", pinmux_type_grp, 0x03, 2, 1, sp7021grps_u0ot), + FNCE("USB1_OTG", pinmux_type_grp, 0x03, 3, 1, sp7021grps_u1ot), + FNCE("UPHY0_DEBUG", pinmux_type_grp, 0x03, 4, 1, sp7021grps_up0d), + FNCE("UPHY1_DEBUG", pinmux_type_grp, 0x03, 5, 1, sp7021grps_up1d), + FNCE("UPHY0_EXT", pinmux_type_grp, 0x03, 6, 1, sp7021grps_upex), + FNCE("PROBE_PORT", pinmux_type_grp, 0x03, 7, 2, sp7021grps_prbp), +}; + +const size_t sppctl_list_funcs_sz = ARRAY_SIZE(sppctl_list_funcs); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 1f401377ff60..d9327d7d56ee 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -784,11 +784,10 @@ static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank); reg = regulator_get(pctl->dev, supply); - if (IS_ERR(reg)) { - dev_err(pctl->dev, "Couldn't get bank P%c regulator\n", - 'A' + bank); - return PTR_ERR(reg); - } + if (IS_ERR(reg)) + return dev_err_probe(pctl->dev, PTR_ERR(reg), + "Couldn't get bank P%c regulator\n", + 'A' + bank); ret = regulator_enable(reg); if (ret) { diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index a4fa8e3af607..65ed20bc1fa2 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -461,10 +461,18 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = { 166, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned ain1_pins[] = {151, 152, 153, 154, 155, 156, 157}; -static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4}; -static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142}; -static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0}; +static const unsigned ain1_pins[] = {151, 152, 153, 154}; +static const int ain1_muxvals[] = {4, 4, 4, 4}; +static const unsigned ain1_dat2_pins[] = {155}; +static const int ain1_dat2_muxvals[] = {4}; +static const unsigned ain1_dat4_pins[] = {156, 157}; +static const int ain1_dat4_muxvals[] = {4, 4}; +static const unsigned aout1_pins[] = {137, 138, 139, 140}; +static const int aout1_muxvals[] = {0, 0, 0, 0}; +static const unsigned aout1_dat2_pins[] = {141}; +static const int aout1_dat2_muxvals[] = {0}; +static const unsigned aout1_dat4_pins[] = {142, 143}; +static const int aout1_dat4_muxvals[] = {0, 3}; static const unsigned ainiec1_pins[] = {150}; static const int ainiec1_muxvals[] = {4}; static const unsigned ainiec1b_pins[] = {141}; @@ -582,7 +590,11 @@ static const unsigned int gpio_range5_pins[] = { static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(ainiec1), UNIPHIER_PINCTRL_GROUP(ainiec1b), UNIPHIER_PINCTRL_GROUP(aoutiec1), @@ -626,8 +638,10 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range5), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const aout1_groups[] = {"aout1"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4"}; static const char * const ainiec1_groups[] = {"ainiec1", "ainiec1b"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; static const char * const aoutiec2_groups[] = {"aoutiec2"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 850736998206..a68b21fbd0c7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -542,18 +542,38 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = { 175, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned ain1_pins[] = {150, 151, 152, 153, 154, 155, 156}; -static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4}; -static const unsigned ain2_pins[] = {116, 117, 118, 119, 120, 121, 122}; -static const int ain2_muxvals[] = {26, 26, 26, 26, 26, 26, 26}; +static const unsigned ain1_pins[] = {150, 151, 152, 153}; +static const int ain1_muxvals[] = {4, 4, 4, 4}; +static const unsigned ain1_dat2_pins[] = {154}; +static const int ain1_dat2_muxvals[] = {4}; +static const unsigned ain1_dat4_pins[] = {155, 156}; +static const int ain1_dat4_muxvals[] = {4, 4}; +static const unsigned ain2_pins[] = {116, 117, 118, 119}; +static const int ain2_muxvals[] = {26, 26, 26, 26}; +static const unsigned ain2_dat2_pins[] = {120}; +static const int ain2_dat2_muxvals[] = {26}; +static const unsigned ain2_dat4_pins[] = {121, 122}; +static const int ain2_dat4_muxvals[] = {26, 26}; static const unsigned ain3_pins[] = {116, 117, 118, 119}; static const int ain3_muxvals[] = {27, 27, 27, 27}; -static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142}; -static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0}; -static const unsigned aout1b_pins[] = {150, 151, 152, 153, 154, 155, 156}; -static const int aout1b_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; -static const unsigned aout2_pins[] = {165, 157, 162, 158, 159, 160, 161}; -static const int aout2_muxvals[] = {2, 2, 2, 1, 1, 1, 1}; +static const unsigned aout1_pins[] = {137, 138, 139, 140}; +static const int aout1_muxvals[] = {0, 0, 0, 0}; +static const unsigned aout1_dat2_pins[] = {141}; +static const int aout1_dat2_muxvals[] = {0}; +static const unsigned aout1_dat4_pins[] = {142, 156}; +static const int aout1_dat4_muxvals[] = {0, 1}; +static const unsigned aout1b_pins[] = {150, 151, 152, 153}; +static const int aout1b_muxvals[] = {1, 1, 1, 1}; +static const unsigned aout1b_dat2_pins[] = {154}; +static const int aout1b_dat2_muxvals[] = {1}; +static const unsigned aout1b_dat4_pins[] = {155, 156}; +static const int aout1b_dat4_muxvals[] = {1, 1}; +static const unsigned aout2_pins[] = {165, 157, 162, 158}; +static const int aout2_muxvals[] = {2, 2, 2, 1}; +static const unsigned aout2_dat2_pins[] = {159}; +static const int aout2_dat2_muxvals[] = {1}; +static const unsigned aout2_dat4_pins[] = {160, 161}; +static const int aout2_dat4_muxvals[] = {1, 1}; static const unsigned aout3_pins[] = {166, 167, 168, 163}; static const int aout3_muxvals[] = {2, 2, 2, 1}; static const unsigned aout4_pins[] = {169, 170, 171, 164}; @@ -682,11 +702,21 @@ static const unsigned int gpio_range2_pins[] = { static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(ain2), + UNIPHIER_PINCTRL_GROUP(ain2_dat2), + UNIPHIER_PINCTRL_GROUP(ain2_dat4), UNIPHIER_PINCTRL_GROUP(ain3), UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(aout1b), + UNIPHIER_PINCTRL_GROUP(aout1b_dat2), + UNIPHIER_PINCTRL_GROUP(aout1b_dat4), UNIPHIER_PINCTRL_GROUP(aout2), + UNIPHIER_PINCTRL_GROUP(aout2_dat2), + UNIPHIER_PINCTRL_GROUP(aout2_dat4), UNIPHIER_PINCTRL_GROUP(aout3), UNIPHIER_PINCTRL_GROUP(aout4), UNIPHIER_PINCTRL_GROUP(aoutiec1), @@ -734,11 +764,17 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const ain2_groups[] = {"ain2"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const ain2_groups[] = {"ain2", "ain2_dat2", + "ain2_dat4"}; static const char * const ain3_groups[] = {"ain3"}; -static const char * const aout1_groups[] = {"aout1", "aout1b"}; -static const char * const aout2_groups[] = {"aout2"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4", + "aout1b", "aout1b_dat2", + "aout1b_dat4"}; +static const char * const aout2_groups[] = {"aout2", "aout2_dat2", + "aout2_dat4"}; static const char * const aout3_groups[] = {"aout3"}; static const char * const aout4_groups[] = {"aout4"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index e52e65a24048..2a9dbf969f0b 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -721,12 +721,32 @@ static const struct pinctrl_pin_desc uniphier_pxs2_pins[] = { static const unsigned ain1_pins[] = {161, 162, 173, 174}; static const int ain1_muxvals[] = {8, 8, 8, 8}; -static const unsigned ain2_pins[] = {98, 99, 100, 101, 102, 103, 104}; -static const int ain2_muxvals[] = {8, 8, 8, 8, 8, 8, 8}; +static const unsigned ain1_dat2_pins[] = {127}; +static const int ain1_dat2_muxvals[] = {3}; +static const unsigned ain1_dat4_pins[] = {128, 129}; +static const int ain1_dat4_muxvals[] = {3, 3}; +static const unsigned ain2_pins[] = {98, 99, 100, 101}; +static const int ain2_muxvals[] = {8, 8, 8, 8}; +static const unsigned ain2_dat2_pins[] = {102}; +static const int ain2_dat2_muxvals[] = {8}; +static const unsigned ain2_dat4_pins[] = {103, 104}; +static const int ain2_dat4_muxvals[] = {8, 8}; +static const unsigned ain3_pins[] = {132, 133, 134, 131}; +static const int ain3_muxvals[] = {5, 5, 5, 5}; static const unsigned ainiec1_pins[] = {91}; static const int ainiec1_muxvals[] = {11}; -static const unsigned aout2_pins[] = {175, 176, 177, 178, 183, 184, 185}; -static const int aout2_muxvals[] = {8, 8, 8, 8, 9, 9, 9}; +static const unsigned aout1_pins[] = {87, 88, 89, 90}; +static const int aout1_muxvals[] = {11, 11, 11, 11}; +static const unsigned aout1_dat2_pins[] = {92}; +static const int aout1_dat2_muxvals[] = {11}; +static const unsigned aout1_dat4_pins[] = {93, 94}; +static const int aout1_dat4_muxvals[] = {11, 11}; +static const unsigned aout2_pins[] = {177, 178, 175, 176}; +static const int aout2_muxvals[] = {8, 8, 8, 8}; +static const unsigned aout2_dat2_pins[] = {183}; +static const int aout2_dat2_muxvals[] = {9}; +static const unsigned aout2_dat4_pins[] = {184, 185}; +static const int aout2_dat4_muxvals[] = {9, 9}; static const unsigned aout3_pins[] = {105, 106, 107, 108}; static const int aout3_muxvals[] = {8, 8, 8, 8}; static const unsigned aoutiec1_pins[] = {95}; @@ -797,8 +817,12 @@ static const unsigned uart3b_pins[] = {181, 182}; static const int uart3b_muxvals[] = {10, 10}; static const unsigned usb0_pins[] = {56, 57}; static const int usb0_muxvals[] = {8, 8}; +static const unsigned usb0_device_pins[] = {213}; +static const int usb0_device_muxvals[] = {9}; static const unsigned usb1_pins[] = {58, 59}; static const int usb1_muxvals[] = {8, 8}; +static const unsigned usb1_device_pins[] = {214}; +static const int usb1_device_muxvals[] = {9}; static const unsigned usb2_pins[] = {60, 61}; static const int usb2_muxvals[] = {8, 8}; static const unsigned usb3_pins[] = {62, 63}; @@ -838,9 +862,19 @@ static const unsigned int gpio_range1_pins[] = { static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(ain2), + UNIPHIER_PINCTRL_GROUP(ain2_dat2), + UNIPHIER_PINCTRL_GROUP(ain2_dat4), + UNIPHIER_PINCTRL_GROUP(ain3), UNIPHIER_PINCTRL_GROUP(ainiec1), + UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(aout2), + UNIPHIER_PINCTRL_GROUP(aout2_dat2), + UNIPHIER_PINCTRL_GROUP(aout2_dat4), UNIPHIER_PINCTRL_GROUP(aout3), UNIPHIER_PINCTRL_GROUP(aoutiec1), UNIPHIER_PINCTRL_GROUP(aoutiec2), @@ -871,17 +905,25 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(uart3b), UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb0_device), UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb1_device), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const ain2_groups[] = {"ain2"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const ain2_groups[] = {"ain2", "ain2_dat2", + "ain2_dat4"}; +static const char * const ain3_groups[] = {"ain3"}; static const char * const ainiec1_groups[] = {"ainiec1"}; -static const char * const aout2_groups[] = {"aout2"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4"}; +static const char * const aout2_groups[] = {"aout2", "aout2_dat2", + "aout2_dat4"}; static const char * const aout3_groups[] = {"aout3"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; static const char * const aoutiec2_groups[] = {"aoutiec2"}; @@ -906,15 +948,17 @@ static const char * const uart0_groups[] = {"uart0", "uart0b", static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3", "uart3b"}; -static const char * const usb0_groups[] = {"usb0"}; -static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb0_groups[] = {"usb0", "usb0_device"}; +static const char * const usb1_groups[] = {"usb1", "usb1_device"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; static const struct uniphier_pinmux_function uniphier_pxs2_functions[] = { UNIPHIER_PINMUX_FUNCTION(ain1), UNIPHIER_PINMUX_FUNCTION(ain2), + UNIPHIER_PINMUX_FUNCTION(ain3), UNIPHIER_PINMUX_FUNCTION(ainiec1), + UNIPHIER_PINMUX_FUNCTION(aout1), UNIPHIER_PINMUX_FUNCTION(aout2), UNIPHIER_PINMUX_FUNCTION(aout3), UNIPHIER_PINMUX_FUNCTION(aoutiec1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 4810db6c0ee8..ab3bd2d9c6c7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -767,14 +767,30 @@ static const struct pinctrl_pin_desc uniphier_pxs3_pins[] = { 250, UNIPHIER_PIN_PULL_DOWN), }; -static const unsigned ain1_pins[] = {186, 187, 188, 189, 237, 238, 239}; -static const int ain1_muxvals[] = {0, 0, 0, 0, 1, 1, 1}; -static const unsigned ain2_pins[] = {243, 244, 245, 246, 247, 248, 249}; -static const int ain2_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; -static const unsigned aout1_pins[] = {226, 227, 228, 229, 230, 231, 232}; -static const int aout1_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; -static const unsigned aout2_pins[] = {192, 193, 194, 195, 196, 197, 198}; -static const int aout2_muxvals[] = {0, 0, 0, 0, 0, 0, 0}; +static const unsigned ain1_pins[] = {186, 187, 188, 189}; +static const int ain1_muxvals[] = {0, 0, 0, 0}; +static const unsigned ain1_dat2_pins[] = {237}; +static const int ain1_dat2_muxvals[] = {1}; +static const unsigned ain1_dat4_pins[] = {238, 239}; +static const int ain1_dat4_muxvals[] = {1, 1}; +static const unsigned ain2_pins[] = {243, 244, 245, 246}; +static const int ain2_muxvals[] = {1, 1, 1, 1}; +static const unsigned ain2_dat2_pins[] = {247}; +static const int ain2_dat2_muxvals[] = {1}; +static const unsigned ain2_dat4_pins[] = {248, 249}; +static const int ain2_dat4_muxvals[] = {1, 1}; +static const unsigned aout1_pins[] = {226, 227, 228, 229}; +static const int aout1_muxvals[] = {1, 1, 1, 1}; +static const unsigned aout1_dat2_pins[] = {230}; +static const int aout1_dat2_muxvals[] = {1}; +static const unsigned aout1_dat4_pins[] = {231, 232}; +static const int aout1_dat4_muxvals[] = {1, 1}; +static const unsigned aout2_pins[] = {192, 193, 194, 195}; +static const int aout2_muxvals[] = {0, 0, 0, 0}; +static const unsigned aout2_dat2_pins[] = {196}; +static const int aout2_dat2_muxvals[] = {0}; +static const unsigned aout2_dat4_pins[] = {197, 198}; +static const int aout2_dat4_muxvals[] = {0, 0}; static const unsigned aout3_pins[] = {199, 200, 201, 202}; static const int aout3_muxvals[] = {0, 0, 0, 0}; static const unsigned ainiec1_pins[] = {240}; @@ -839,8 +855,12 @@ static const unsigned int uart3_pins[] = {98, 99}; static const int uart3_muxvals[] = {0, 0}; static const unsigned int usb0_pins[] = {84, 85}; static const int usb0_muxvals[] = {0, 0}; +static const unsigned int usb0_device_pins[] = {110}; +static const int usb0_device_muxvals[] = {2}; static const unsigned int usb1_pins[] = {86, 87}; static const int usb1_muxvals[] = {0, 0}; +static const unsigned int usb1_device_pins[] = {111}; +static const int usb1_device_muxvals[] = {2}; static const unsigned int usb2_pins[] = {88, 89}; static const int usb2_muxvals[] = {0, 0}; static const unsigned int usb3_pins[] = {90, 91}; @@ -888,9 +908,17 @@ static const unsigned int gpio_range2_pins[] = { static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP(ain1), + UNIPHIER_PINCTRL_GROUP(ain1_dat2), + UNIPHIER_PINCTRL_GROUP(ain1_dat4), UNIPHIER_PINCTRL_GROUP(ain2), + UNIPHIER_PINCTRL_GROUP(ain2_dat2), + UNIPHIER_PINCTRL_GROUP(ain2_dat4), UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1_dat2), + UNIPHIER_PINCTRL_GROUP(aout1_dat4), UNIPHIER_PINCTRL_GROUP(aout2), + UNIPHIER_PINCTRL_GROUP(aout2_dat2), + UNIPHIER_PINCTRL_GROUP(aout2_dat4), UNIPHIER_PINCTRL_GROUP(aout3), UNIPHIER_PINCTRL_GROUP(ainiec1), UNIPHIER_PINCTRL_GROUP(aoutiec1), @@ -918,7 +946,9 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(usb0), + UNIPHIER_PINCTRL_GROUP(usb0_device), UNIPHIER_PINCTRL_GROUP(usb1), + UNIPHIER_PINCTRL_GROUP(usb1_device), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0), @@ -926,10 +956,14 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), }; -static const char * const ain1_groups[] = {"ain1"}; -static const char * const ain2_groups[] = {"ain2"}; -static const char * const aout1_groups[] = {"aout1"}; -static const char * const aout2_groups[] = {"aout2"}; +static const char * const ain1_groups[] = {"ain1", "ain1_dat2", + "ain1_dat4"}; +static const char * const ain2_groups[] = {"ain2", "ain2_dat2", + "ain1_dat4"}; +static const char * const aout1_groups[] = {"aout1", "aout1_dat2", + "aout1_dat4"}; +static const char * const aout2_groups[] = {"aout2", "aout2_dat2", + "aout2_dat4"}; static const char * const aout3_groups[] = {"aout3"}; static const char * const ainiec1_groups[] = {"ainiec1"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; @@ -954,8 +988,8 @@ static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3"}; -static const char * const usb0_groups[] = {"usb0"}; -static const char * const usb1_groups[] = {"usb1"}; +static const char * const usb0_groups[] = {"usb0", "usb0_device"}; +static const char * const usb1_groups[] = {"usb1", "usb1_device"}; static const char * const usb2_groups[] = {"usb2"}; static const char * const usb3_groups[] = {"usb3"}; diff --git a/drivers/thunderbolt/acpi.c b/drivers/thunderbolt/acpi.c index 79b5abf9d042..c89daac0ad8c 100644 --- a/drivers/thunderbolt/acpi.c +++ b/drivers/thunderbolt/acpi.c @@ -14,15 +14,15 @@ static acpi_status tb_acpi_add_link(acpi_handle handle, u32 level, void *data, void **return_value) { + struct acpi_device *adev = acpi_fetch_acpi_dev(handle); struct fwnode_reference_args args; struct fwnode_handle *fwnode; struct tb_nhi *nhi = data; - struct acpi_device *adev; struct pci_dev *pdev; struct device *dev; int ret; - if (acpi_bus_get_device(handle, &adev)) + if (!adev) return AE_OK; fwnode = acpi_fwnode_handle(adev); diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c index 470885e6f1c8..c90d22f56d4e 100644 --- a/drivers/thunderbolt/eeprom.c +++ b/drivers/thunderbolt/eeprom.c @@ -17,7 +17,7 @@ */ static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) { - return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); + return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1); } /* @@ -25,7 +25,7 @@ static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) */ static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl) { - return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1); + return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + ROUTER_CS_4, 1); } enum tb_eeprom_transfer { @@ -46,18 +46,18 @@ static int tb_eeprom_active(struct tb_switch *sw, bool enable) if (res) return res; if (enable) { - ctl.access_high = 1; + ctl.bit_banging_enable = 1; res = tb_eeprom_ctl_write(sw, &ctl); if (res) return res; - ctl.access_low = 0; + ctl.fl_cs = 0; return tb_eeprom_ctl_write(sw, &ctl); } else { - ctl.access_low = 1; + ctl.fl_cs = 1; res = tb_eeprom_ctl_write(sw, &ctl); if (res) return res; - ctl.access_high = 0; + ctl.bit_banging_enable = 0; return tb_eeprom_ctl_write(sw, &ctl); } } @@ -65,8 +65,8 @@ static int tb_eeprom_active(struct tb_switch *sw, bool enable) /* * tb_eeprom_transfer - transfer one bit * - * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in. - * If TB_EEPROM_OUT is passed, then ctl->data_out will be written. + * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->fl_do. + * If TB_EEPROM_OUT is passed, then ctl->fl_di will be written. */ static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, enum tb_eeprom_transfer direction) @@ -77,7 +77,7 @@ static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, if (res) return res; } - ctl->clock = 1; + ctl->fl_sk = 1; res = tb_eeprom_ctl_write(sw, ctl); if (res) return res; @@ -86,7 +86,7 @@ static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, if (res) return res; } - ctl->clock = 0; + ctl->fl_sk = 0; return tb_eeprom_ctl_write(sw, ctl); } @@ -101,7 +101,7 @@ static int tb_eeprom_out(struct tb_switch *sw, u8 val) if (res) return res; for (i = 0; i < 8; i++) { - ctl.data_out = val & 0x80; + ctl.fl_di = val & 0x80; res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT); if (res) return res; @@ -126,7 +126,7 @@ static int tb_eeprom_in(struct tb_switch *sw, u8 *val) res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN); if (res) return res; - *val |= ctl.data_in; + *val |= ctl.fl_do; } return 0; } @@ -553,9 +553,9 @@ static int tb_drom_parse(struct tb_switch *sw) crc = tb_crc8((u8 *) &header->uid, 8); if (crc != header->uid_crc8) { tb_sw_warn(sw, - "DROM UID CRC8 mismatch (expected: %#x, got: %#x), aborting\n", + "DROM UID CRC8 mismatch (expected: %#x, got: %#x)\n", header->uid_crc8, crc); - return -EINVAL; + return -EILSEQ; } if (!sw->uid) sw->uid = header->uid; @@ -654,6 +654,7 @@ int tb_drom_read(struct tb_switch *sw) sw->drom = kzalloc(size, GFP_KERNEL); if (!sw->drom) return -ENOMEM; +read: res = tb_drom_read_n(sw, 0, sw->drom, size); if (res) goto err; @@ -662,7 +663,11 @@ parse: header = (void *) sw->drom; if (header->data_len + TB_DROM_DATA_START != size) { - tb_sw_warn(sw, "drom size mismatch, aborting\n"); + tb_sw_warn(sw, "drom size mismatch\n"); + if (retries--) { + msleep(100); + goto read; + } goto err; } @@ -683,11 +688,9 @@ parse: /* If the DROM parsing fails, wait a moment and retry once */ if (res == -EILSEQ && retries--) { - tb_sw_warn(sw, "parsing DROM failed, retrying\n"); + tb_sw_warn(sw, "parsing DROM failed\n"); msleep(100); - res = tb_drom_read_n(sw, 0, sw->drom, size); - if (!res) - goto parse; + goto read; } if (!res) diff --git a/drivers/thunderbolt/lc.c b/drivers/thunderbolt/lc.c index 53495a38b4eb..633970fbe9b0 100644 --- a/drivers/thunderbolt/lc.c +++ b/drivers/thunderbolt/lc.c @@ -217,6 +217,116 @@ bool tb_lc_is_clx_supported(struct tb_port *port) return !!(val & TB_LC_LINK_ATTR_CPS); } +/** + * tb_lc_is_usb_plugged() - Is there USB device connected to port + * @port: Device router lane 0 adapter + * + * Returns true if the @port has USB type-C device connected. + */ +bool tb_lc_is_usb_plugged(struct tb_port *port) +{ + struct tb_switch *sw = port->sw; + int cap, ret; + u32 val; + + if (sw->generation != 3) + return false; + + cap = find_port_lc_cap(port); + if (cap < 0) + return false; + + ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_CS_42, 1); + if (ret) + return false; + + return !!(val & TB_LC_CS_42_USB_PLUGGED); +} + +/** + * tb_lc_is_xhci_connected() - Is the internal xHCI connected + * @port: Device router lane 0 adapter + * + * Returns true if the internal xHCI has been connected to @port. + */ +bool tb_lc_is_xhci_connected(struct tb_port *port) +{ + struct tb_switch *sw = port->sw; + int cap, ret; + u32 val; + + if (sw->generation != 3) + return false; + + cap = find_port_lc_cap(port); + if (cap < 0) + return false; + + ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_REQ, 1); + if (ret) + return false; + + return !!(val & TB_LC_LINK_REQ_XHCI_CONNECT); +} + +static int __tb_lc_xhci_connect(struct tb_port *port, bool connect) +{ + struct tb_switch *sw = port->sw; + int cap, ret; + u32 val; + + if (sw->generation != 3) + return -EINVAL; + + cap = find_port_lc_cap(port); + if (cap < 0) + return cap; + + ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_REQ, 1); + if (ret) + return ret; + + if (connect) + val |= TB_LC_LINK_REQ_XHCI_CONNECT; + else + val &= ~TB_LC_LINK_REQ_XHCI_CONNECT; + + return tb_sw_write(sw, &val, TB_CFG_SWITCH, cap + TB_LC_LINK_REQ, 1); +} + +/** + * tb_lc_xhci_connect() - Connect internal xHCI + * @port: Device router lane 0 adapter + * + * Tells LC to connect the internal xHCI to @port. Returns %0 on success + * and negative errno in case of failure. Can be called for Thunderbolt 3 + * routers only. + */ +int tb_lc_xhci_connect(struct tb_port *port) +{ + int ret; + + ret = __tb_lc_xhci_connect(port, true); + if (ret) + return ret; + + tb_port_dbg(port, "xHCI connected\n"); + return 0; +} + +/** + * tb_lc_xhci_disconnect() - Disconnect internal xHCI + * @port: Device router lane 0 adapter + * + * Tells LC to disconnect the internal xHCI from @port. Can be called + * for Thunderbolt 3 routers only. + */ +void tb_lc_xhci_disconnect(struct tb_port *port) +{ + __tb_lc_xhci_connect(port, false); + tb_port_dbg(port, "xHCI disconnected\n"); +} + static int tb_lc_set_wake_one(struct tb_switch *sw, unsigned int offset, unsigned int flags) { diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index c73da0532be4..4a582183f675 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -1229,8 +1230,6 @@ static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id) spin_lock_init(&nhi->lock); res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); - if (res) - res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); if (res) { dev_err(&pdev->dev, "failed to set DMA mask\n"); return res; diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c index d026e305fe5d..ac87e8b50e52 100644 --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c @@ -1528,7 +1528,13 @@ static int tb_plug_events_active(struct tb_switch *sw, bool active) case PCI_DEVICE_ID_INTEL_PORT_RIDGE: break; default: - data |= 4; + /* + * Skip Alpine Ridge, it needs to have vendor + * specific USB hotplug event enabled for the + * internal xHCI to work. + */ + if (!tb_switch_is_alpine_ridge(sw)) + data |= TB_PLUG_EVENTS_USB_DISABLE; } } else { data = data | 0x7c; @@ -2778,10 +2784,8 @@ int tb_switch_add(struct tb_switch *sw) /* read drom */ ret = tb_drom_read(sw); - if (ret) { - dev_err(&sw->dev, "reading DROM failed\n"); - return ret; - } + if (ret) + dev_warn(&sw->dev, "reading DROM failed: %d\n", ret); tb_sw_dbg(sw, "uid: %#llx\n", sw->uid); tb_check_quirks(sw); @@ -2974,6 +2978,10 @@ int tb_switch_resume(struct tb_switch *sw) return err; } + /* We don't have any way to confirm this was the same device */ + if (!sw->uid) + return -ENODEV; + if (tb_switch_is_usb4(sw)) err = usb4_switch_read_uid(sw, &uid); else @@ -3689,3 +3697,66 @@ int tb_switch_pcie_l1_enable(struct tb_switch *sw) /* Write to Upstream PCIe bridge #0 aka Up0 */ return tb_switch_pcie_bridge_write(sw, 0, 0x143, 0x0c5806b1); } + +/** + * tb_switch_xhci_connect() - Connect internal xHCI + * @sw: Router whose xHCI to connect + * + * Can be called to any router. For Alpine Ridge and Titan Ridge + * performs special flows that bring the xHCI functional for any device + * connected to the type-C port. Call only after PCIe tunnel has been + * established. The function only does the connect if not done already + * so can be called several times for the same router. + */ +int tb_switch_xhci_connect(struct tb_switch *sw) +{ + bool usb_port1, usb_port3, xhci_port1, xhci_port3; + struct tb_port *port1, *port3; + int ret; + + port1 = &sw->ports[1]; + port3 = &sw->ports[3]; + + if (tb_switch_is_alpine_ridge(sw)) { + usb_port1 = tb_lc_is_usb_plugged(port1); + usb_port3 = tb_lc_is_usb_plugged(port3); + xhci_port1 = tb_lc_is_xhci_connected(port1); + xhci_port3 = tb_lc_is_xhci_connected(port3); + + /* Figure out correct USB port to connect */ + if (usb_port1 && !xhci_port1) { + ret = tb_lc_xhci_connect(port1); + if (ret) + return ret; + } + if (usb_port3 && !xhci_port3) + return tb_lc_xhci_connect(port3); + } else if (tb_switch_is_titan_ridge(sw)) { + ret = tb_lc_xhci_connect(port1); + if (ret) + return ret; + return tb_lc_xhci_connect(port3); + } + + return 0; +} + +/** + * tb_switch_xhci_disconnect() - Disconnect internal xHCI + * @sw: Router whose xHCI to disconnect + * + * The opposite of tb_switch_xhci_connect(). Disconnects xHCI on both + * ports. + */ +void tb_switch_xhci_disconnect(struct tb_switch *sw) +{ + if (sw->generation == 3) { + struct tb_port *port1 = &sw->ports[1]; + struct tb_port *port3 = &sw->ports[3]; + + tb_lc_xhci_disconnect(port1); + tb_port_dbg(port1, "disconnected xHCI\n"); + tb_lc_xhci_disconnect(port3); + tb_port_dbg(port3, "disconnected xHCI\n"); + } +} diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c index cbd0ad85ffb1..9beb47b31c75 100644 --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c @@ -1054,6 +1054,8 @@ static int tb_disconnect_pci(struct tb *tb, struct tb_switch *sw) if (WARN_ON(!tunnel)) return -ENODEV; + tb_switch_xhci_disconnect(sw); + tb_tunnel_deactivate(tunnel); list_del(&tunnel->list); tb_tunnel_free(tunnel); @@ -1099,6 +1101,9 @@ static int tb_tunnel_pci(struct tb *tb, struct tb_switch *sw) if (tb_switch_pcie_l1_enable(sw)) tb_sw_warn(sw, "failed to enable PCIe L1 for Titan Ridge\n"); + if (tb_switch_xhci_connect(sw)) + tb_sw_warn(sw, "failed to connect xHCI\n"); + list_add_tail(&tunnel->list, &tcm->tunnel_list); return 0; } @@ -1256,12 +1261,18 @@ static void tb_handle_hotplug(struct work_struct *work) tb_port_unconfigure_xdomain(port); } else if (tb_port_is_dpout(port) || tb_port_is_dpin(port)) { tb_dp_resource_unavailable(tb, port); + } else if (!port->port) { + tb_sw_dbg(sw, "xHCI disconnect request\n"); + tb_switch_xhci_disconnect(sw); } else { tb_port_dbg(port, "got unplug event for disconnected port, ignoring\n"); } } else if (port->remote) { tb_port_dbg(port, "got plug event for connected port, ignoring\n"); + } else if (!port->port && sw->authorized) { + tb_sw_dbg(sw, "xHCI connect request\n"); + tb_switch_xhci_connect(sw); } else { if (tb_port_is_null(port)) { tb_port_dbg(port, "hotplug: scanning\n"); diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h index 74d3b14f004e..b6fcd8d45324 100644 --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h @@ -855,6 +855,7 @@ static inline bool tb_switch_is_alpine_ridge(const struct tb_switch *sw) if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) { switch (sw->config.device_id) { case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE: + case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE: case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE: case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE: case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE: @@ -987,6 +988,9 @@ int tb_switch_mask_clx_objections(struct tb_switch *sw); int tb_switch_pcie_l1_enable(struct tb_switch *sw); +int tb_switch_xhci_connect(struct tb_switch *sw); +void tb_switch_xhci_disconnect(struct tb_switch *sw); + int tb_wait_for_port(struct tb_port *port, bool wait_if_unplugged); int tb_port_add_nfc_credits(struct tb_port *port, int credits); int tb_port_clear_counter(struct tb_port *port, int counter); @@ -1081,6 +1085,10 @@ int tb_lc_configure_xdomain(struct tb_port *port); void tb_lc_unconfigure_xdomain(struct tb_port *port); int tb_lc_start_lane_initialization(struct tb_port *port); bool tb_lc_is_clx_supported(struct tb_port *port); +bool tb_lc_is_usb_plugged(struct tb_port *port); +bool tb_lc_is_xhci_connected(struct tb_port *port); +int tb_lc_xhci_connect(struct tb_port *port); +void tb_lc_xhci_disconnect(struct tb_port *port); int tb_lc_set_wake(struct tb_switch *sw, unsigned int flags); int tb_lc_set_sleep(struct tb_switch *sw); bool tb_lc_lane_bonding_possible(struct tb_switch *sw); diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h index a74f4878d3e7..b301eeb0c89b 100644 --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h @@ -133,11 +133,11 @@ struct tb_cap_phy { } __packed; struct tb_eeprom_ctl { - bool clock:1; /* send pulse to transfer one bit */ - bool access_low:1; /* set to 0 before access */ - bool data_out:1; /* to eeprom */ - bool data_in:1; /* from eeprom */ - bool access_high:1; /* set to 1 before access */ + bool fl_sk:1; /* send pulse to transfer one bit */ + bool fl_cs:1; /* set to 0 before access */ + bool fl_di:1; /* to eeprom */ + bool fl_do:1; /* from eeprom */ + bool bit_banging_enable:1; /* set to 1 before access */ bool not_present:1; /* should be 0 */ bool unknown1:1; bool present:1; /* should be 1 */ @@ -146,14 +146,14 @@ struct tb_eeprom_ctl { struct tb_cap_plug_events { struct tb_cap_extended_short cap_header; - u32 __unknown1:2; - u32 plug_events:5; - u32 __unknown2:25; - u32 __unknown3; - u32 __unknown4; + u32 __unknown1:2; /* VSC_CS_1 */ + u32 plug_events:5; /* VSC_CS_1 */ + u32 __unknown2:25; /* VSC_CS_1 */ + u32 vsc_cs_2; + u32 vsc_cs_3; struct tb_eeprom_ctl eeprom_ctl; - u32 __unknown5[7]; - u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */ + u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */ + u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */ } __packed; /* device headers */ @@ -389,6 +389,7 @@ struct tb_regs_port_header { #define DP_COMMON_CAP_1_LANE 0x0 #define DP_COMMON_CAP_2_LANES 0x1 #define DP_COMMON_CAP_4_LANES 0x2 +#define DP_COMMON_CAP_LTTPR_NS BIT(27) #define DP_COMMON_CAP_DPRX_DONE BIT(31) /* PCIe adapter registers */ @@ -462,6 +463,12 @@ struct tb_regs_hop { #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 BIT(3) /* Plug Events registers */ +#define TB_PLUG_EVENTS_USB_DISABLE BIT(2) +#define TB_PLUG_EVENTS_CS_1_LANE_DISABLE BIT(3) +#define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE BIT(4) +#define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE BIT(5) +#define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE BIT(6) + #define TB_PLUG_EVENTS_PCIE_WR_DATA 0x1b #define TB_PLUG_EVENTS_PCIE_CMD 0x1c #define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK GENMASK(9, 0) @@ -501,6 +508,9 @@ struct tb_regs_hop { #define TB_LC_POWER 0x740 /* Link controller registers */ +#define TB_LC_CS_42 0x2a +#define TB_LC_CS_42_USB_PLUGGED BIT(31) + #define TB_LC_PORT_ATTR 0x8d #define TB_LC_PORT_ATTR_BE BIT(12) @@ -521,4 +531,7 @@ struct tb_regs_hop { #define TB_LC_LINK_ATTR 0x97 #define TB_LC_LINK_ATTR_CPS BIT(18) +#define TB_LC_LINK_REQ 0xad +#define TB_LC_LINK_REQ_XHCI_CONNECT BIT(31) + #endif diff --git a/drivers/thunderbolt/tunnel.c b/drivers/thunderbolt/tunnel.c index a473cc7d9a8d..118742ec93ed 100644 --- a/drivers/thunderbolt/tunnel.c +++ b/drivers/thunderbolt/tunnel.c @@ -580,6 +580,16 @@ static int tb_dp_xchg_caps(struct tb_tunnel *tunnel) out_dp_cap = tb_dp_cap_set_lanes(out_dp_cap, new_lanes); } + /* + * Titan Ridge does not disable AUX timers when it gets + * SET_CONFIG with SET_LTTPR_MODE set. This causes problems with + * DP tunneling. + */ + if (tb_route(out->sw) && tb_switch_is_titan_ridge(out->sw)) { + out_dp_cap |= DP_COMMON_CAP_LTTPR_NS; + tb_port_dbg(out, "disabling LTTPR\n"); + } + return tb_port_write(in, &out_dp_cap, TB_CFG_PORT, in->cap_adap + DP_REMOTE_CAP, 1); } diff --git a/drivers/usb/cdns3/cdnsp-debug.h b/drivers/usb/cdns3/cdnsp-debug.h index a8776df2d4e0..f0ca865cce2a 100644 --- a/drivers/usb/cdns3/cdnsp-debug.h +++ b/drivers/usb/cdns3/cdnsp-debug.h @@ -182,208 +182,211 @@ static inline const char *cdnsp_decode_trb(char *str, size_t size, u32 field0, int ep_id = TRB_TO_EP_INDEX(field3) - 1; int type = TRB_FIELD_TO_TYPE(field3); unsigned int ep_num; - int ret = 0; + int ret; u32 temp; ep_num = DIV_ROUND_UP(ep_id, 2); switch (type) { case TRB_LINK: - ret += snprintf(str, size, - "LINK %08x%08x intr %ld type '%s' flags %c:%c:%c:%c", - field1, field0, GET_INTR_TARGET(field2), - cdnsp_trb_type_string(type), - field3 & TRB_IOC ? 'I' : 'i', - field3 & TRB_CHAIN ? 'C' : 'c', - field3 & TRB_TC ? 'T' : 't', - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "LINK %08x%08x intr %ld type '%s' flags %c:%c:%c:%c", + field1, field0, GET_INTR_TARGET(field2), + cdnsp_trb_type_string(type), + field3 & TRB_IOC ? 'I' : 'i', + field3 & TRB_CHAIN ? 'C' : 'c', + field3 & TRB_TC ? 'T' : 't', + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_TRANSFER: case TRB_COMPLETION: case TRB_PORT_STATUS: case TRB_HC_EVENT: - ret += snprintf(str, size, - "ep%d%s(%d) type '%s' TRB %08x%08x status '%s'" - " len %ld slot %ld flags %c:%c", - ep_num, ep_id % 2 ? "out" : "in", - TRB_TO_EP_INDEX(field3), - cdnsp_trb_type_string(type), field1, field0, - cdnsp_trb_comp_code_string(GET_COMP_CODE(field2)), - EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), - field3 & EVENT_DATA ? 'E' : 'e', - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "ep%d%s(%d) type '%s' TRB %08x%08x status '%s'" + " len %ld slot %ld flags %c:%c", + ep_num, ep_id % 2 ? "out" : "in", + TRB_TO_EP_INDEX(field3), + cdnsp_trb_type_string(type), field1, field0, + cdnsp_trb_comp_code_string(GET_COMP_CODE(field2)), + EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), + field3 & EVENT_DATA ? 'E' : 'e', + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_MFINDEX_WRAP: - ret += snprintf(str, size, "%s: flags %c", - cdnsp_trb_type_string(type), - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, "%s: flags %c", + cdnsp_trb_type_string(type), + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_SETUP: - ret += snprintf(str, size, - "type '%s' bRequestType %02x bRequest %02x " - "wValue %02x%02x wIndex %02x%02x wLength %d " - "length %ld TD size %ld intr %ld Setup ID %ld " - "flags %c:%c:%c", - cdnsp_trb_type_string(type), - field0 & 0xff, - (field0 & 0xff00) >> 8, - (field0 & 0xff000000) >> 24, - (field0 & 0xff0000) >> 16, - (field1 & 0xff00) >> 8, - field1 & 0xff, - (field1 & 0xff000000) >> 16 | - (field1 & 0xff0000) >> 16, - TRB_LEN(field2), GET_TD_SIZE(field2), - GET_INTR_TARGET(field2), - TRB_SETUPID_TO_TYPE(field3), - field3 & TRB_IDT ? 'D' : 'd', - field3 & TRB_IOC ? 'I' : 'i', - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "type '%s' bRequestType %02x bRequest %02x " + "wValue %02x%02x wIndex %02x%02x wLength %d " + "length %ld TD size %ld intr %ld Setup ID %ld " + "flags %c:%c:%c", + cdnsp_trb_type_string(type), + field0 & 0xff, + (field0 & 0xff00) >> 8, + (field0 & 0xff000000) >> 24, + (field0 & 0xff0000) >> 16, + (field1 & 0xff00) >> 8, + field1 & 0xff, + (field1 & 0xff000000) >> 16 | + (field1 & 0xff0000) >> 16, + TRB_LEN(field2), GET_TD_SIZE(field2), + GET_INTR_TARGET(field2), + TRB_SETUPID_TO_TYPE(field3), + field3 & TRB_IDT ? 'D' : 'd', + field3 & TRB_IOC ? 'I' : 'i', + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_DATA: - ret += snprintf(str, size, - "type '%s' Buffer %08x%08x length %ld TD size %ld " - "intr %ld flags %c:%c:%c:%c:%c:%c:%c", - cdnsp_trb_type_string(type), - field1, field0, TRB_LEN(field2), - GET_TD_SIZE(field2), - GET_INTR_TARGET(field2), - field3 & TRB_IDT ? 'D' : 'i', - field3 & TRB_IOC ? 'I' : 'i', - field3 & TRB_CHAIN ? 'C' : 'c', - field3 & TRB_NO_SNOOP ? 'S' : 's', - field3 & TRB_ISP ? 'I' : 'i', - field3 & TRB_ENT ? 'E' : 'e', - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "type '%s' Buffer %08x%08x length %ld TD size %ld " + "intr %ld flags %c:%c:%c:%c:%c:%c:%c", + cdnsp_trb_type_string(type), + field1, field0, TRB_LEN(field2), + GET_TD_SIZE(field2), + GET_INTR_TARGET(field2), + field3 & TRB_IDT ? 'D' : 'i', + field3 & TRB_IOC ? 'I' : 'i', + field3 & TRB_CHAIN ? 'C' : 'c', + field3 & TRB_NO_SNOOP ? 'S' : 's', + field3 & TRB_ISP ? 'I' : 'i', + field3 & TRB_ENT ? 'E' : 'e', + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_STATUS: - ret += snprintf(str, size, - "Buffer %08x%08x length %ld TD size %ld intr" - "%ld type '%s' flags %c:%c:%c:%c", - field1, field0, TRB_LEN(field2), - GET_TD_SIZE(field2), - GET_INTR_TARGET(field2), - cdnsp_trb_type_string(type), - field3 & TRB_IOC ? 'I' : 'i', - field3 & TRB_CHAIN ? 'C' : 'c', - field3 & TRB_ENT ? 'E' : 'e', - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "Buffer %08x%08x length %ld TD size %ld intr" + "%ld type '%s' flags %c:%c:%c:%c", + field1, field0, TRB_LEN(field2), + GET_TD_SIZE(field2), + GET_INTR_TARGET(field2), + cdnsp_trb_type_string(type), + field3 & TRB_IOC ? 'I' : 'i', + field3 & TRB_CHAIN ? 'C' : 'c', + field3 & TRB_ENT ? 'E' : 'e', + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_NORMAL: case TRB_ISOC: case TRB_EVENT_DATA: case TRB_TR_NOOP: - ret += snprintf(str, size, - "type '%s' Buffer %08x%08x length %ld " - "TD size %ld intr %ld " - "flags %c:%c:%c:%c:%c:%c:%c:%c:%c", - cdnsp_trb_type_string(type), - field1, field0, TRB_LEN(field2), - GET_TD_SIZE(field2), - GET_INTR_TARGET(field2), - field3 & TRB_BEI ? 'B' : 'b', - field3 & TRB_IDT ? 'T' : 't', - field3 & TRB_IOC ? 'I' : 'i', - field3 & TRB_CHAIN ? 'C' : 'c', - field3 & TRB_NO_SNOOP ? 'S' : 's', - field3 & TRB_ISP ? 'I' : 'i', - field3 & TRB_ENT ? 'E' : 'e', - field3 & TRB_CYCLE ? 'C' : 'c', - !(field3 & TRB_EVENT_INVALIDATE) ? 'V' : 'v'); + ret = snprintf(str, size, + "type '%s' Buffer %08x%08x length %ld " + "TD size %ld intr %ld " + "flags %c:%c:%c:%c:%c:%c:%c:%c:%c", + cdnsp_trb_type_string(type), + field1, field0, TRB_LEN(field2), + GET_TD_SIZE(field2), + GET_INTR_TARGET(field2), + field3 & TRB_BEI ? 'B' : 'b', + field3 & TRB_IDT ? 'T' : 't', + field3 & TRB_IOC ? 'I' : 'i', + field3 & TRB_CHAIN ? 'C' : 'c', + field3 & TRB_NO_SNOOP ? 'S' : 's', + field3 & TRB_ISP ? 'I' : 'i', + field3 & TRB_ENT ? 'E' : 'e', + field3 & TRB_CYCLE ? 'C' : 'c', + !(field3 & TRB_EVENT_INVALIDATE) ? 'V' : 'v'); break; case TRB_CMD_NOOP: case TRB_ENABLE_SLOT: - ret += snprintf(str, size, "%s: flags %c", - cdnsp_trb_type_string(type), - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, "%s: flags %c", + cdnsp_trb_type_string(type), + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_DISABLE_SLOT: - ret += snprintf(str, size, "%s: slot %ld flags %c", - cdnsp_trb_type_string(type), - TRB_TO_SLOT_ID(field3), - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, "%s: slot %ld flags %c", + cdnsp_trb_type_string(type), + TRB_TO_SLOT_ID(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_ADDR_DEV: - ret += snprintf(str, size, - "%s: ctx %08x%08x slot %ld flags %c:%c", - cdnsp_trb_type_string(type), field1, field0, - TRB_TO_SLOT_ID(field3), - field3 & TRB_BSR ? 'B' : 'b', - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "%s: ctx %08x%08x slot %ld flags %c:%c", + cdnsp_trb_type_string(type), field1, field0, + TRB_TO_SLOT_ID(field3), + field3 & TRB_BSR ? 'B' : 'b', + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_CONFIG_EP: - ret += snprintf(str, size, - "%s: ctx %08x%08x slot %ld flags %c:%c", - cdnsp_trb_type_string(type), field1, field0, - TRB_TO_SLOT_ID(field3), - field3 & TRB_DC ? 'D' : 'd', - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "%s: ctx %08x%08x slot %ld flags %c:%c", + cdnsp_trb_type_string(type), field1, field0, + TRB_TO_SLOT_ID(field3), + field3 & TRB_DC ? 'D' : 'd', + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_EVAL_CONTEXT: - ret += snprintf(str, size, - "%s: ctx %08x%08x slot %ld flags %c", - cdnsp_trb_type_string(type), field1, field0, - TRB_TO_SLOT_ID(field3), - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "%s: ctx %08x%08x slot %ld flags %c", + cdnsp_trb_type_string(type), field1, field0, + TRB_TO_SLOT_ID(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_RESET_EP: case TRB_HALT_ENDPOINT: case TRB_FLUSH_ENDPOINT: - ret += snprintf(str, size, - "%s: ep%d%s(%d) ctx %08x%08x slot %ld flags %c", - cdnsp_trb_type_string(type), - ep_num, ep_id % 2 ? "out" : "in", - TRB_TO_EP_INDEX(field3), field1, field0, - TRB_TO_SLOT_ID(field3), - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "%s: ep%d%s(%d) ctx %08x%08x slot %ld flags %c", + cdnsp_trb_type_string(type), + ep_num, ep_id % 2 ? "out" : "in", + TRB_TO_EP_INDEX(field3), field1, field0, + TRB_TO_SLOT_ID(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_STOP_RING: - ret += snprintf(str, size, - "%s: ep%d%s(%d) slot %ld sp %d flags %c", - cdnsp_trb_type_string(type), - ep_num, ep_id % 2 ? "out" : "in", - TRB_TO_EP_INDEX(field3), - TRB_TO_SLOT_ID(field3), - TRB_TO_SUSPEND_PORT(field3), - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "%s: ep%d%s(%d) slot %ld sp %d flags %c", + cdnsp_trb_type_string(type), + ep_num, ep_id % 2 ? "out" : "in", + TRB_TO_EP_INDEX(field3), + TRB_TO_SLOT_ID(field3), + TRB_TO_SUSPEND_PORT(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_SET_DEQ: - ret += snprintf(str, size, - "%s: ep%d%s(%d) deq %08x%08x stream %ld slot %ld flags %c", - cdnsp_trb_type_string(type), - ep_num, ep_id % 2 ? "out" : "in", - TRB_TO_EP_INDEX(field3), field1, field0, - TRB_TO_STREAM_ID(field2), - TRB_TO_SLOT_ID(field3), - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "%s: ep%d%s(%d) deq %08x%08x stream %ld slot %ld flags %c", + cdnsp_trb_type_string(type), + ep_num, ep_id % 2 ? "out" : "in", + TRB_TO_EP_INDEX(field3), field1, field0, + TRB_TO_STREAM_ID(field2), + TRB_TO_SLOT_ID(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_RESET_DEV: - ret += snprintf(str, size, "%s: slot %ld flags %c", - cdnsp_trb_type_string(type), - TRB_TO_SLOT_ID(field3), - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, "%s: slot %ld flags %c", + cdnsp_trb_type_string(type), + TRB_TO_SLOT_ID(field3), + field3 & TRB_CYCLE ? 'C' : 'c'); break; case TRB_ENDPOINT_NRDY: - temp = TRB_TO_HOST_STREAM(field2); + temp = TRB_TO_HOST_STREAM(field2); - ret += snprintf(str, size, - "%s: ep%d%s(%d) H_SID %x%s%s D_SID %lx flags %c:%c", - cdnsp_trb_type_string(type), - ep_num, ep_id % 2 ? "out" : "in", - TRB_TO_EP_INDEX(field3), temp, - temp == STREAM_PRIME_ACK ? "(PRIME)" : "", - temp == STREAM_REJECTED ? "(REJECTED)" : "", - TRB_TO_DEV_STREAM(field0), - field3 & TRB_STAT ? 'S' : 's', - field3 & TRB_CYCLE ? 'C' : 'c'); + ret = snprintf(str, size, + "%s: ep%d%s(%d) H_SID %x%s%s D_SID %lx flags %c:%c", + cdnsp_trb_type_string(type), + ep_num, ep_id % 2 ? "out" : "in", + TRB_TO_EP_INDEX(field3), temp, + temp == STREAM_PRIME_ACK ? "(PRIME)" : "", + temp == STREAM_REJECTED ? "(REJECTED)" : "", + TRB_TO_DEV_STREAM(field0), + field3 & TRB_STAT ? 'S' : 's', + field3 & TRB_CYCLE ? 'C' : 'c'); break; default: - ret += snprintf(str, size, - "type '%s' -> raw %08x %08x %08x %08x", - cdnsp_trb_type_string(type), - field0, field1, field2, field3); + ret = snprintf(str, size, + "type '%s' -> raw %08x %08x %08x %08x", + cdnsp_trb_type_string(type), + field0, field1, field2, field3); } + if (ret >= size) + pr_info("CDNSP: buffer overflowed.\n"); + return str; } diff --git a/drivers/usb/cdns3/cdnsp-gadget.c b/drivers/usb/cdns3/cdnsp-gadget.c index 5c9d07cc5410..c67715f6f756 100644 --- a/drivers/usb/cdns3/cdnsp-gadget.c +++ b/drivers/usb/cdns3/cdnsp-gadget.c @@ -1243,12 +1243,9 @@ static int cdnsp_run(struct cdnsp_device *pdev, enum usb_device_speed speed) { u32 fs_speed = 0; - u64 temp_64; u32 temp; int ret; - temp_64 = cdnsp_read_64(&pdev->ir_set->erst_dequeue); - temp_64 &= ~ERST_PTR_MASK; temp = readl(&pdev->ir_set->irq_control); temp &= ~IMOD_INTERVAL_MASK; temp |= ((IMOD_DEFAULT_INTERVAL / 250) & IMOD_INTERVAL_MASK); diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c index f9ca5010f65b..dc6c96e04bcf 100644 --- a/drivers/usb/chipidea/udc.c +++ b/drivers/usb/chipidea/udc.c @@ -2152,7 +2152,7 @@ static void udc_id_switch_for_host(struct ci_hdrc *ci) { /* * host doesn't care B_SESSION_VALID event - * so clear and disbale BSV irq + * so clear and disable BSV irq */ if (ci->is_otg) hw_write_otgsc(ci, OTGSC_BSVIE | OTGSC_BSVIS, OTGSC_BSVIS); diff --git a/drivers/usb/common/ulpi.c b/drivers/usb/common/ulpi.c index 5509d3847af4..0a4f441aff8f 100644 --- a/drivers/usb/common/ulpi.c +++ b/drivers/usb/common/ulpi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -232,9 +233,64 @@ err: return 0; } +static int ulpi_regs_read(struct seq_file *seq, void *data) +{ + struct ulpi *ulpi = seq->private; + +#define ulpi_print(name, reg) do { \ + int ret = ulpi_read(ulpi, reg); \ + if (ret < 0) \ + return ret; \ + seq_printf(seq, name " %.02x\n", ret); \ +} while (0) + + ulpi_print("Vendor ID Low ", ULPI_VENDOR_ID_LOW); + ulpi_print("Vendor ID High ", ULPI_VENDOR_ID_HIGH); + ulpi_print("Product ID Low ", ULPI_PRODUCT_ID_LOW); + ulpi_print("Product ID High ", ULPI_PRODUCT_ID_HIGH); + ulpi_print("Function Control ", ULPI_FUNC_CTRL); + ulpi_print("Interface Control ", ULPI_IFC_CTRL); + ulpi_print("OTG Control ", ULPI_OTG_CTRL); + ulpi_print("USB Interrupt Enable Rising ", ULPI_USB_INT_EN_RISE); + ulpi_print("USB Interrupt Enable Falling", ULPI_USB_INT_EN_FALL); + ulpi_print("USB Interrupt Status ", ULPI_USB_INT_STS); + ulpi_print("USB Interrupt Latch ", ULPI_USB_INT_LATCH); + ulpi_print("Debug ", ULPI_DEBUG); + ulpi_print("Scratch Register ", ULPI_SCRATCH); + ulpi_print("Carkit Control ", ULPI_CARKIT_CTRL); + ulpi_print("Carkit Interrupt Delay ", ULPI_CARKIT_INT_DELAY); + ulpi_print("Carkit Interrupt Enable ", ULPI_CARKIT_INT_EN); + ulpi_print("Carkit Interrupt Status ", ULPI_CARKIT_INT_STS); + ulpi_print("Carkit Interrupt Latch ", ULPI_CARKIT_INT_LATCH); + ulpi_print("Carkit Pulse Control ", ULPI_CARKIT_PLS_CTRL); + ulpi_print("Transmit Positive Width ", ULPI_TX_POS_WIDTH); + ulpi_print("Transmit Negative Width ", ULPI_TX_NEG_WIDTH); + ulpi_print("Receive Polarity Recovery ", ULPI_POLARITY_RECOVERY); + + return 0; +} + +static int ulpi_regs_open(struct inode *inode, struct file *f) +{ + struct ulpi *ulpi = inode->i_private; + + return single_open(f, ulpi_regs_read, ulpi); +} + +static const struct file_operations ulpi_regs_ops = { + .owner = THIS_MODULE, + .open = ulpi_regs_open, + .release = single_release, + .read = seq_read, + .llseek = seq_lseek +}; + +#define ULPI_ROOT debugfs_lookup(KBUILD_MODNAME, NULL) + static int ulpi_register(struct device *dev, struct ulpi *ulpi) { int ret; + struct dentry *root; ulpi->dev.parent = dev; /* needed early for ops */ ulpi->dev.bus = &ulpi_bus; @@ -259,6 +315,9 @@ static int ulpi_register(struct device *dev, struct ulpi *ulpi) return ret; } + root = debugfs_create_dir(dev_name(dev), ULPI_ROOT); + debugfs_create_file("regs", 0444, root, ulpi, &ulpi_regs_ops); + dev_dbg(&ulpi->dev, "registered ULPI PHY: vendor %04x, product %04x\n", ulpi->id.vendor, ulpi->id.product); @@ -304,6 +363,8 @@ EXPORT_SYMBOL_GPL(ulpi_register_interface); */ void ulpi_unregister_interface(struct ulpi *ulpi) { + debugfs_remove_recursive(debugfs_lookup(dev_name(&ulpi->dev), + ULPI_ROOT)); device_unregister(&ulpi->dev); } EXPORT_SYMBOL_GPL(ulpi_unregister_interface); @@ -312,13 +373,21 @@ EXPORT_SYMBOL_GPL(ulpi_unregister_interface); static int __init ulpi_init(void) { - return bus_register(&ulpi_bus); + int ret; + struct dentry *root; + + root = debugfs_create_dir(KBUILD_MODNAME, NULL); + ret = bus_register(&ulpi_bus); + if (ret) + debugfs_remove(root); + return ret; } subsys_initcall(ulpi_init); static void __exit ulpi_exit(void) { bus_unregister(&ulpi_bus); + debugfs_remove_recursive(ULPI_ROOT); } module_exit(ulpi_exit); diff --git a/drivers/usb/common/usb-conn-gpio.c b/drivers/usb/common/usb-conn-gpio.c index 0158148cb054..395f9bbe3056 100644 --- a/drivers/usb/common/usb-conn-gpio.c +++ b/drivers/usb/common/usb-conn-gpio.c @@ -175,7 +175,6 @@ static int usb_conn_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct usb_conn_info *info; - bool need_vbus = true; int ret = 0; info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); @@ -205,22 +204,9 @@ static int usb_conn_probe(struct platform_device *pdev) INIT_DELAYED_WORK(&info->dw_det, usb_conn_detect_cable); - /* - * If the USB connector is a child of a USB port and that port already provides the VBUS - * supply, there's no need for the USB connector to provide it again. - */ - if (dev->parent && dev->parent->of_node) { - if (of_find_property(dev->parent->of_node, "vbus-supply", NULL)) - need_vbus = false; - } - - if (!need_vbus) { - info->vbus = devm_regulator_get_optional(dev, "vbus"); - if (PTR_ERR(info->vbus) == -ENODEV) - info->vbus = NULL; - } else { - info->vbus = devm_regulator_get(dev, "vbus"); - } + info->vbus = devm_regulator_get_optional(dev, "vbus"); + if (PTR_ERR(info->vbus) == -ENODEV) + info->vbus = NULL; if (IS_ERR(info->vbus)) { ret = PTR_ERR(info->vbus); diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c index fa66e6e58792..6abb7294e919 100644 --- a/drivers/usb/core/devio.c +++ b/drivers/usb/core/devio.c @@ -139,30 +139,42 @@ MODULE_PARM_DESC(usbfs_memory_mb, /* Hard limit, necessary to avoid arithmetic overflow */ #define USBFS_XFER_MAX (UINT_MAX / 2 - 1000000) -static atomic64_t usbfs_memory_usage; /* Total memory currently allocated */ +static DEFINE_SPINLOCK(usbfs_memory_usage_lock); +static u64 usbfs_memory_usage; /* Total memory currently allocated */ /* Check whether it's okay to allocate more memory for a transfer */ static int usbfs_increase_memory_usage(u64 amount) { - u64 lim; + u64 lim, total_mem; + unsigned long flags; + int ret; lim = READ_ONCE(usbfs_memory_mb); lim <<= 20; - atomic64_add(amount, &usbfs_memory_usage); + ret = 0; + spin_lock_irqsave(&usbfs_memory_usage_lock, flags); + total_mem = usbfs_memory_usage + amount; + if (lim > 0 && total_mem > lim) + ret = -ENOMEM; + else + usbfs_memory_usage = total_mem; + spin_unlock_irqrestore(&usbfs_memory_usage_lock, flags); - if (lim > 0 && atomic64_read(&usbfs_memory_usage) > lim) { - atomic64_sub(amount, &usbfs_memory_usage); - return -ENOMEM; - } - - return 0; + return ret; } /* Memory for a transfer is being deallocated */ static void usbfs_decrease_memory_usage(u64 amount) { - atomic64_sub(amount, &usbfs_memory_usage); + unsigned long flags; + + spin_lock_irqsave(&usbfs_memory_usage_lock, flags); + if (amount > usbfs_memory_usage) + usbfs_memory_usage = 0; + else + usbfs_memory_usage -= amount; + spin_unlock_irqrestore(&usbfs_memory_usage_lock, flags); } static int connected(struct usb_dev_state *ps) diff --git a/drivers/usb/core/hcd-pci.c b/drivers/usb/core/hcd-pci.c index dd44e37a454a..8176bc81a635 100644 --- a/drivers/usb/core/hcd-pci.c +++ b/drivers/usb/core/hcd-pci.c @@ -248,7 +248,7 @@ int usb_hcd_pci_probe(struct pci_dev *dev, const struct pci_device_id *id, hcd->rsrc_len, driver->description)) break; } - if (region == PCI_ROM_RESOURCE) { + if (region == PCI_STD_NUM_BARS) { dev_dbg(&dev->dev, "no i/o regions available\n"); retval = -EBUSY; goto put_hcd; diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 47a1c8bddf86..1460857026e0 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -2983,8 +2983,12 @@ static int hub_port_reset(struct usb_hub *hub, int port1, status); } - /* Check for disconnect or reset */ - if (status == 0 || status == -ENOTCONN || status == -ENODEV) { + /* + * Check for disconnect or reset, and bail out after several + * reset attempts to avoid warm reset loop. + */ + if (status == 0 || status == -ENOTCONN || status == -ENODEV || + (status == -EBUSY && i == PORT_RESET_TRIES - 1)) { usb_clear_port_feature(hub->hdev, port1, USB_PORT_FEAT_C_RESET); @@ -5005,6 +5009,7 @@ hub_port_init(struct usb_hub *hub, struct usb_device *udev, int port1, retval = usb_get_bos_descriptor(udev); if (!retval) { udev->lpm_capable = usb_device_supports_lpm(udev); + udev->lpm_disable_count = 1; usb_set_lpm_parameters(udev); } } @@ -5928,16 +5933,6 @@ static int usb_reset_and_verify_device(struct usb_device *udev) */ usb_disable_usb2_hardware_lpm(udev); - /* Disable LPM while we reset the device and reinstall the alt settings. - * Device-initiated LPM, and system exit latency settings are cleared - * when the device is reset, so we have to set them up again. - */ - ret = usb_unlocked_disable_lpm(udev); - if (ret) { - dev_err(&udev->dev, "%s Failed to disable LPM\n", __func__); - goto re_enumerate_no_bos; - } - bos = udev->bos; udev->bos = NULL; @@ -6042,8 +6037,6 @@ done: re_enumerate: usb_release_bos_descriptor(udev); udev->bos = bos; -re_enumerate_no_bos: - /* LPM state doesn't matter when we're about to destroy the device. */ hub_port_logical_disconnect(parent_hub, port1); return -ENODEV; } diff --git a/drivers/usb/core/usb-acpi.c b/drivers/usb/core/usb-acpi.c index 50b2fc7fcc0e..bb1da35eb891 100644 --- a/drivers/usb/core/usb-acpi.c +++ b/drivers/usb/core/usb-acpi.c @@ -166,7 +166,7 @@ usb_acpi_get_companion_for_port(struct usb_port *port_dev) if (!parent_handle) return NULL; - acpi_bus_get_device(parent_handle, &adev); + adev = acpi_fetch_acpi_dev(parent_handle); port1 = port_dev->portnum; } diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c index 2ce3667ec6fa..2f71636af6e1 100644 --- a/drivers/usb/core/usb.c +++ b/drivers/usb/core/usb.c @@ -688,6 +688,10 @@ EXPORT_SYMBOL_GPL(usb_alloc_dev); * Drivers for USB interfaces should normally record such references in * their probe() methods, when they bind to an interface, and release * them by calling usb_put_dev(), in their disconnect() methods. + * However, if a driver does not access the usb_device structure after + * its disconnect() method returns then refcounting is not necessary, + * because the USB core guarantees that a usb_device will not be + * deallocated until after all of its interface drivers have been unbound. * * Return: A pointer to the device with the incremented reference counter. */ @@ -722,6 +726,10 @@ EXPORT_SYMBOL_GPL(usb_put_dev); * Drivers for USB interfaces should normally record such references in * their probe() methods, when they bind to an interface, and release * them by calling usb_put_intf(), in their disconnect() methods. + * However, if a driver does not access the usb_interface structure after + * its disconnect() method returns then refcounting is not necessary, + * because the USB core guarantees that a usb_interface will not be + * deallocated until after its driver has been unbound. * * Return: A pointer to the interface with the incremented reference counter. */ diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c index d300ae3d9274..1306f4ec788d 100644 --- a/drivers/usb/dwc2/params.c +++ b/drivers/usb/dwc2/params.c @@ -82,6 +82,14 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) p->phy_utmi_width = 8; } +static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg) +{ + struct dwc2_core_params *p = &hsotg->params; + + p->power_down = DWC2_POWER_DOWN_PARAM_NONE; + p->no_clock_gating = true; +} + static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) { struct dwc2_core_params *p = &hsotg->params; @@ -239,6 +247,8 @@ const struct of_device_id dwc2_of_match_table[] = { .data = dwc2_set_stm32mp15_fsotg_params }, { .compatible = "st,stm32mp15-hsotg", .data = dwc2_set_stm32mp15_hsotg_params }, + { .compatible = "intel,socfpga-agilex-hsotg", + .data = dwc2_set_socfpga_agilex_params }, {}, }; MODULE_DEVICE_TABLE(of, dwc2_of_match_table); diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f4c09951b517..1170b800acdc 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -115,8 +115,6 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) dwc->current_dr_role = mode; } -static int dwc3_core_soft_reset(struct dwc3 *dwc); - static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc = work_to_dwc(work); @@ -261,7 +259,7 @@ u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) * dwc3_core_soft_reset - Issues core soft reset and PHY reset * @dwc: pointer to our context structure */ -static int dwc3_core_soft_reset(struct dwc3 *dwc) +int dwc3_core_soft_reset(struct dwc3 *dwc) { u32 reg; int retries = 1000; @@ -347,17 +345,64 @@ static void dwc3_frame_length_adjustment(struct dwc3 *dwc) */ static void dwc3_ref_clk_period(struct dwc3 *dwc) { + unsigned long period; + unsigned long fladj; + unsigned long decr; + unsigned long rate; u32 reg; - if (dwc->ref_clk_per == 0) + if (dwc->ref_clk) { + rate = clk_get_rate(dwc->ref_clk); + if (!rate) + return; + period = NSEC_PER_SEC / rate; + } else if (dwc->ref_clk_per) { + period = dwc->ref_clk_per; + rate = NSEC_PER_SEC / period; + } else { return; + } reg = dwc3_readl(dwc->regs, DWC3_GUCTL); reg &= ~DWC3_GUCTL_REFCLKPER_MASK; - reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, dwc->ref_clk_per); + reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); dwc3_writel(dwc->regs, DWC3_GUCTL, reg); -} + if (DWC3_VER_IS_PRIOR(DWC3, 250A)) + return; + + /* + * The calculation below is + * + * 125000 * (NSEC_PER_SEC / (rate * period) - 1) + * + * but rearranged for fixed-point arithmetic. The division must be + * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and + * neither does rate * period). + * + * Note that rate * period ~= NSEC_PER_SECOND, minus the number of + * nanoseconds of error caused by the truncation which happened during + * the division when calculating rate or period (whichever one was + * derived from the other). We first calculate the relative error, then + * scale it to units of 8 ppm. + */ + fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); + fladj -= 125000; + + /* + * The documented 240MHz constant is scaled by 2 to get PLS1 as well. + */ + decr = 480000000 / rate; + + reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); + reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK + & ~DWC3_GFLADJ_240MHZDECR + & ~DWC3_GFLADJ_240MHZDECR_PLS1; + reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) + | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) + | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); + dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); +} /** * dwc3_free_one_event_buffer - Frees one event buffer @@ -745,6 +790,38 @@ static int dwc3_phy_setup(struct dwc3 *dwc) return 0; } +static int dwc3_clk_enable(struct dwc3 *dwc) +{ + int ret; + + ret = clk_prepare_enable(dwc->bus_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(dwc->ref_clk); + if (ret) + goto disable_bus_clk; + + ret = clk_prepare_enable(dwc->susp_clk); + if (ret) + goto disable_ref_clk; + + return 0; + +disable_ref_clk: + clk_disable_unprepare(dwc->ref_clk); +disable_bus_clk: + clk_disable_unprepare(dwc->bus_clk); + return ret; +} + +static void dwc3_clk_disable(struct dwc3 *dwc) +{ + clk_disable_unprepare(dwc->susp_clk); + clk_disable_unprepare(dwc->ref_clk); + clk_disable_unprepare(dwc->bus_clk); +} + static void dwc3_core_exit(struct dwc3 *dwc) { dwc3_event_buffers_cleanup(dwc); @@ -758,7 +835,7 @@ static void dwc3_core_exit(struct dwc3 *dwc) usb_phy_set_suspend(dwc->usb3_phy, 1); phy_power_off(dwc->usb2_generic_phy); phy_power_off(dwc->usb3_generic_phy); - clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); + dwc3_clk_disable(dwc); reset_control_assert(dwc->reset); } @@ -1088,6 +1165,11 @@ static int dwc3_core_init(struct dwc3 *dwc) if (dwc->parkmode_disable_ss_quirk) reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; + if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && + (dwc->maximum_speed == USB_SPEED_HIGH || + dwc->maximum_speed == USB_SPEED_FULL)) + reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); } @@ -1605,25 +1687,31 @@ static int dwc3_probe(struct platform_device *pdev) return PTR_ERR(dwc->reset); if (dev->of_node) { - ret = devm_clk_bulk_get_all(dev, &dwc->clks); - if (ret == -EPROBE_DEFER) - return ret; /* * Clocks are optional, but new DT platforms should support all * clocks as required by the DT-binding. */ - if (ret < 0) - dwc->num_clks = 0; - else - dwc->num_clks = ret; + dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); + if (IS_ERR(dwc->bus_clk)) + return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), + "could not get bus clock\n"); + dwc->ref_clk = devm_clk_get_optional(dev, "ref"); + if (IS_ERR(dwc->ref_clk)) + return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), + "could not get ref clock\n"); + + dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); + if (IS_ERR(dwc->susp_clk)) + return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), + "could not get suspend clock\n"); } ret = reset_control_deassert(dwc->reset); if (ret) return ret; - ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); + ret = dwc3_clk_enable(dwc); if (ret) goto assert_reset; @@ -1711,7 +1799,7 @@ err1: pm_runtime_disable(&pdev->dev); disable_clks: - clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); + dwc3_clk_disable(dwc); assert_reset: reset_control_assert(dwc->reset); @@ -1755,7 +1843,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc) if (ret) return ret; - ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); + ret = dwc3_clk_enable(dwc); if (ret) goto assert_reset; @@ -1766,7 +1854,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc) return 0; disable_clks: - clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); + dwc3_clk_disable(dwc); assert_reset: reset_control_assert(dwc->reset); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index e1cc3f7398fb..5c9d467195a6 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -259,6 +259,7 @@ /* Global User Control 1 Register */ #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31) #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) @@ -388,6 +389,9 @@ /* Global Frame Length Adjustment Register */ #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) #define DWC3_GFLADJ_30MHZ_MASK 0x3f +#define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8) +#define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24) +#define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31) /* Global User Control Register*/ #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 @@ -733,6 +737,7 @@ struct dwc3_ep { #define DWC3_EP_FIRST_STREAM_PRIMED BIT(10) #define DWC3_EP_PENDING_CLEAR_STALL BIT(11) #define DWC3_EP_TXFIFO_RESIZED BIT(12) +#define DWC3_EP_DELAY_STOP BIT(13) /* This last one is specific to EP0 */ #define DWC3_EP0_DIR_IN BIT(31) @@ -978,8 +983,9 @@ struct dwc3_scratchpad_array { * @eps: endpoint array * @gadget: device side representation of the peripheral controller * @gadget_driver: pointer to the gadget driver - * @clks: array of clocks - * @num_clks: number of clocks + * @bus_clk: clock for accessing the registers + * @ref_clk: reference clock + * @susp_clk: clock used when the SS phy is in low power (S3) state * @reset: reset control * @regs: base address for our registers * @regs_size: address space size @@ -1134,8 +1140,9 @@ struct dwc3 { struct usb_gadget *gadget; struct usb_gadget_driver *gadget_driver; - struct clk_bulk_data *clks; - int num_clks; + struct clk *bus_clk; + struct clk *ref_clk; + struct clk *susp_clk; struct reset_control *reset; @@ -1525,6 +1532,8 @@ bool dwc3_has_imod(struct dwc3 *dwc); int dwc3_event_buffers_setup(struct dwc3 *dwc); void dwc3_event_buffers_cleanup(struct dwc3 *dwc); +int dwc3_core_soft_reset(struct dwc3 *dwc); + #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE) int dwc3_host_init(struct dwc3 *dwc); void dwc3_host_exit(struct dwc3 *dwc); diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index d7f76835137f..b60b5f7b6dff 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -559,6 +560,18 @@ static int dwc3_setup_role_switch(struct dwc3 *dwc) if (IS_ERR(dwc->role_sw)) return PTR_ERR(dwc->role_sw); + if (dwc->dev->of_node) { + /* populate connector entry */ + int ret = devm_of_platform_populate(dwc->dev); + + if (ret) { + usb_role_switch_unregister(dwc->role_sw); + dwc->role_sw = NULL; + dev_err(dwc->dev, "DWC3 platform devices creation failed: %i\n", ret); + return ret; + } + } + dwc3_set_mode(dwc, mode); return 0; } diff --git a/drivers/usb/dwc3/dwc3-imx8mp.c b/drivers/usb/dwc3/dwc3-imx8mp.c index d328d20abfbc..174f07614318 100644 --- a/drivers/usb/dwc3/dwc3-imx8mp.c +++ b/drivers/usb/dwc3/dwc3-imx8mp.c @@ -36,9 +36,21 @@ #define USB_WAKEUP_EN_MASK GENMASK(5, 0) +/* USB glue registers */ +#define USB_CTRL0 0x00 +#define USB_CTRL1 0x04 + +#define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */ +#define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */ +#define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */ + +#define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */ +#define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */ + struct dwc3_imx8mp { struct device *dev; struct platform_device *dwc3; + void __iomem *hsio_blk_base; void __iomem *glue_base; struct clk *hsio_clk; struct clk *suspend_clk; @@ -47,6 +59,42 @@ struct dwc3_imx8mp { bool wakeup_pending; }; +static void imx8mp_configure_glue(struct dwc3_imx8mp *dwc3_imx) +{ + struct device *dev = dwc3_imx->dev; + u32 value; + + if (!dwc3_imx->glue_base) + return; + + value = readl(dwc3_imx->glue_base + USB_CTRL0); + + if (device_property_read_bool(dev, "fsl,permanently-attached")) + value |= (USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED); + else + value &= ~(USB_CTRL0_USB2_FIXED | USB_CTRL0_USB3_FIXED); + + if (device_property_read_bool(dev, "fsl,disable-port-power-control")) + value &= ~(USB_CTRL0_PORTPWR_EN); + else + value |= USB_CTRL0_PORTPWR_EN; + + writel(value, dwc3_imx->glue_base + USB_CTRL0); + + value = readl(dwc3_imx->glue_base + USB_CTRL1); + if (device_property_read_bool(dev, "fsl,over-current-active-low")) + value |= USB_CTRL1_OC_POLARITY; + else + value &= ~USB_CTRL1_OC_POLARITY; + + if (device_property_read_bool(dev, "fsl,power-active-low")) + value |= USB_CTRL1_PWR_POLARITY; + else + value &= ~USB_CTRL1_PWR_POLARITY; + + writel(value, dwc3_imx->glue_base + USB_CTRL1); +} + static void dwc3_imx8mp_wakeup_enable(struct dwc3_imx8mp *dwc3_imx) { struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3); @@ -55,7 +103,7 @@ static void dwc3_imx8mp_wakeup_enable(struct dwc3_imx8mp *dwc3_imx) if (!dwc3) return; - val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL); + val = readl(dwc3_imx->hsio_blk_base + USB_WAKEUP_CTRL); if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci) val |= USB_WAKEUP_EN | USB_WAKEUP_SS_CONN | @@ -64,16 +112,16 @@ static void dwc3_imx8mp_wakeup_enable(struct dwc3_imx8mp *dwc3_imx) val |= USB_WAKEUP_EN | USB_WAKEUP_VBUS_EN | USB_WAKEUP_VBUS_SRC_SESS_VAL; - writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL); + writel(val, dwc3_imx->hsio_blk_base + USB_WAKEUP_CTRL); } static void dwc3_imx8mp_wakeup_disable(struct dwc3_imx8mp *dwc3_imx) { u32 val; - val = readl(dwc3_imx->glue_base + USB_WAKEUP_CTRL); + val = readl(dwc3_imx->hsio_blk_base + USB_WAKEUP_CTRL); val &= ~(USB_WAKEUP_EN | USB_WAKEUP_EN_MASK); - writel(val, dwc3_imx->glue_base + USB_WAKEUP_CTRL); + writel(val, dwc3_imx->hsio_blk_base + USB_WAKEUP_CTRL); } static irqreturn_t dwc3_imx8mp_interrupt(int irq, void *_dwc3_imx) @@ -100,6 +148,7 @@ static int dwc3_imx8mp_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct device_node *dwc3_np, *node = dev->of_node; struct dwc3_imx8mp *dwc3_imx; + struct resource *res; int err, irq; if (!node) { @@ -115,9 +164,18 @@ static int dwc3_imx8mp_probe(struct platform_device *pdev) dwc3_imx->dev = dev; - dwc3_imx->glue_base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(dwc3_imx->glue_base)) - return PTR_ERR(dwc3_imx->glue_base); + dwc3_imx->hsio_blk_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dwc3_imx->hsio_blk_base)) + return PTR_ERR(dwc3_imx->hsio_blk_base); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_warn(dev, "Base address for glue layer missing. Continuing without, some features are missing though."); + } else { + dwc3_imx->glue_base = devm_ioremap_resource(dev, res); + if (IS_ERR(dwc3_imx->glue_base)) + return PTR_ERR(dwc3_imx->glue_base); + } dwc3_imx->hsio_clk = devm_clk_get(dev, "hsio"); if (IS_ERR(dwc3_imx->hsio_clk)) { @@ -152,6 +210,8 @@ static int dwc3_imx8mp_probe(struct platform_device *pdev) } dwc3_imx->irq = irq; + imx8mp_configure_glue(dwc3_imx); + pm_runtime_set_active(dev); pm_runtime_enable(dev); err = pm_runtime_get_sync(dev); @@ -252,6 +312,9 @@ static int __maybe_unused dwc3_imx8mp_resume(struct dwc3_imx8mp *dwc3_imx, dwc3_imx8mp_wakeup_disable(dwc3_imx); dwc3_imx->pm_suspended = false; + /* Upon power loss any previous configuration is lost, restore it */ + imx8mp_configure_glue(dwc3_imx); + if (dwc3_imx->wakeup_pending) { dwc3_imx->wakeup_pending = false; if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_DEVICE) { diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index bd814df3bf8b..b282ad0e69c6 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -188,7 +188,7 @@ static int dwc3_meson_gxl_usb_post_init(struct dwc3_meson_g12a *priv); * reset to recover usage of the port. */ -static struct dwc3_meson_g12a_drvdata gxl_drvdata = { +static const struct dwc3_meson_g12a_drvdata gxl_drvdata = { .otg_switch_supported = true, .otg_phy_host_port_disable = true, .clks = meson_gxl_clocks, @@ -202,7 +202,7 @@ static struct dwc3_meson_g12a_drvdata gxl_drvdata = { .usb_post_init = dwc3_meson_gxl_usb_post_init, }; -static struct dwc3_meson_g12a_drvdata gxm_drvdata = { +static const struct dwc3_meson_g12a_drvdata gxm_drvdata = { .otg_switch_supported = true, .otg_phy_host_port_disable = true, .clks = meson_gxl_clocks, @@ -216,7 +216,7 @@ static struct dwc3_meson_g12a_drvdata gxm_drvdata = { .usb_post_init = dwc3_meson_gxl_usb_post_init, }; -static struct dwc3_meson_g12a_drvdata axg_drvdata = { +static const struct dwc3_meson_g12a_drvdata axg_drvdata = { .otg_switch_supported = true, .clks = meson_gxl_clocks, .num_clks = ARRAY_SIZE(meson_gxl_clocks), @@ -229,7 +229,7 @@ static struct dwc3_meson_g12a_drvdata axg_drvdata = { .usb_post_init = dwc3_meson_gxl_usb_post_init, }; -static struct dwc3_meson_g12a_drvdata g12a_drvdata = { +static const struct dwc3_meson_g12a_drvdata g12a_drvdata = { .otg_switch_supported = true, .clks = meson_g12a_clocks, .num_clks = ARRAY_SIZE(meson_g12a_clocks), @@ -241,7 +241,7 @@ static struct dwc3_meson_g12a_drvdata g12a_drvdata = { .usb_init = dwc3_meson_g12a_usb_init, }; -static struct dwc3_meson_g12a_drvdata a1_drvdata = { +static const struct dwc3_meson_g12a_drvdata a1_drvdata = { .otg_switch_supported = false, .clks = meson_a1_clocks, .num_clks = ARRAY_SIZE(meson_a1_clocks), diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c index e196673f5c64..efaf0db595f4 100644 --- a/drivers/usb/dwc3/dwc3-omap.c +++ b/drivers/usb/dwc3/dwc3-omap.c @@ -242,7 +242,7 @@ static void dwc3_omap_set_mailbox(struct dwc3_omap *omap, break; case OMAP_DWC3_ID_FLOAT: - if (omap->vbus_reg) + if (omap->vbus_reg && regulator_is_enabled(omap->vbus_reg)) regulator_disable(omap->vbus_reg); val = dwc3_omap_read_utmi_ctrl(omap); val |= USBOTGSS_UTMI_OTG_CTRL_IDDIG; diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index 06d0e88ec8af..33f657d83246 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -40,6 +40,7 @@ #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee #define PCI_DEVICE_ID_INTEL_TGPH 0x43ee #define PCI_DEVICE_ID_INTEL_JSP 0x4dee +#define PCI_DEVICE_ID_INTEL_ADL 0x465e #define PCI_DEVICE_ID_INTEL_ADLP 0x51ee #define PCI_DEVICE_ID_INTEL_ADLM 0x54ee #define PCI_DEVICE_ID_INTEL_ADLS 0x7ae1 @@ -120,6 +121,13 @@ static const struct property_entry dwc3_pci_intel_properties[] = { {} }; +static const struct property_entry dwc3_pci_intel_phy_charger_detect_properties[] = { + PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), + PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), + PROPERTY_ENTRY_BOOL("linux,phy_charger_detect"), + {} +}; + static const struct property_entry dwc3_pci_intel_byt_properties[] = { PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), @@ -169,6 +177,10 @@ static const struct software_node dwc3_pci_intel_swnode = { .properties = dwc3_pci_intel_properties, }; +static const struct software_node dwc3_pci_intel_phy_charger_detect_swnode = { + .properties = dwc3_pci_intel_phy_charger_detect_properties, +}; + static const struct software_node dwc3_pci_intel_byt_swnode = { .properties = dwc3_pci_intel_byt_properties, }; @@ -185,7 +197,8 @@ static const struct software_node dwc3_pci_amd_mr_swnode = { .properties = dwc3_pci_mr_properties, }; -static int dwc3_pci_quirks(struct dwc3_pci *dwc) +static int dwc3_pci_quirks(struct dwc3_pci *dwc, + const struct software_node *swnode) { struct pci_dev *pdev = dwc->pci; @@ -239,10 +252,30 @@ static int dwc3_pci_quirks(struct dwc3_pci *dwc) gpiod_put(gpio); usleep_range(10000, 11000); } + + /* + * Make the pdev name predictable (only 1 DWC3 on BYT) + * and patch the phy dev-name into the lookup table so + * that the phy-driver can get the GPIOs. + */ + dwc->dwc3->id = PLATFORM_DEVID_NONE; + platform_bytcr_gpios.dev_id = "dwc3.ulpi"; + + /* + * Some Android tablets with a Crystal Cove PMIC + * (INT33FD), rely on the TUSB1211 phy for charger + * detection. These can be identified by them _not_ + * using the standard ACPI battery and ac drivers. + */ + if (acpi_dev_present("INT33FD", "1", 2) && + acpi_quirk_skip_acpi_ac_and_battery()) { + dev_info(&pdev->dev, "Using TUSB1211 phy for charger detection\n"); + swnode = &dwc3_pci_intel_phy_charger_detect_swnode; + } } } - return 0; + return device_add_software_node(&dwc->dwc3->dev, swnode); } #ifdef CONFIG_PM @@ -307,11 +340,7 @@ static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) dwc->dwc3->dev.parent = dev; ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); - ret = device_add_software_node(&dwc->dwc3->dev, (void *)id->driver_data); - if (ret < 0) - goto err; - - ret = dwc3_pci_quirks(dwc); + ret = dwc3_pci_quirks(dwc, (void *)id->driver_data); if (ret) goto err; @@ -412,6 +441,9 @@ static const struct pci_device_id dwc3_pci_id_table[] = { { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_JSP), (kernel_ulong_t) &dwc3_pci_intel_swnode, }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL), + (kernel_ulong_t) &dwc3_pci_intel_swnode, }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADLP), (kernel_ulong_t) &dwc3_pci_intel_swnode, }, diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 658739410992..1064be5518f6 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -271,6 +271,7 @@ void dwc3_ep0_out_start(struct dwc3 *dwc) { struct dwc3_ep *dep; int ret; + int i; complete(&dwc->ep0_in_setup); @@ -279,6 +280,19 @@ void dwc3_ep0_out_start(struct dwc3 *dwc) DWC3_TRBCTL_CONTROL_SETUP, false); ret = dwc3_ep0_start_trans(dep); WARN_ON(ret < 0); + for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) { + struct dwc3_ep *dwc3_ep; + + dwc3_ep = dwc->eps[i]; + if (!dwc3_ep) + continue; + + if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP)) + continue; + + dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP; + dwc3_stop_active_transfer(dwc3_ep, true, true); + } } static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index a0c883f19a41..ab725d2262d6 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -654,9 +654,6 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); } -static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, - bool interrupt); - /** * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value * @dwc: pointer to the DWC3 context @@ -1673,6 +1670,40 @@ static int __dwc3_gadget_get_frame(struct dwc3 *dwc) return DWC3_DSTS_SOFFN(reg); } +/** + * __dwc3_stop_active_transfer - stop the current active transfer + * @dep: isoc endpoint + * @force: set forcerm bit in the command + * @interrupt: command complete interrupt after End Transfer command + * + * When setting force, the ForceRM bit will be set. In that case + * the controller won't update the TRB progress on command + * completion. It also won't clear the HWO bit in the TRB. + * The command will also not complete immediately in that case. + */ +static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt) +{ + struct dwc3_gadget_ep_cmd_params params; + u32 cmd; + int ret; + + cmd = DWC3_DEPCMD_ENDTRANSFER; + cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; + cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; + cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); + memset(¶ms, 0, sizeof(params)); + ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); + WARN_ON_ONCE(ret); + dep->resource_index = 0; + + if (!interrupt) + dep->flags &= ~DWC3_EP_TRANSFER_STARTED; + else if (!ret) + dep->flags |= DWC3_EP_END_TRANSFER_PENDING; + + return ret; +} + /** * dwc3_gadget_start_isoc_quirk - workaround invalid frame number * @dep: isoc endpoint @@ -1830,7 +1861,13 @@ static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) } for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) { - dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1); + int future_interval = i + 1; + + /* Give the controller at least 500us to schedule transfers */ + if (desc->bInterval < 3) + future_interval += 3 - desc->bInterval; + + dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval); ret = __dwc3_gadget_kick_transfer(dep); if (ret != -EAGAIN) @@ -1842,21 +1879,8 @@ static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) * status, issue END_TRANSFER command and retry on the next XferNotReady * event. */ - if (ret == -EAGAIN) { - struct dwc3_gadget_ep_cmd_params params; - u32 cmd; - - cmd = DWC3_DEPCMD_ENDTRANSFER | - DWC3_DEPCMD_CMDIOC | - DWC3_DEPCMD_PARAM(dep->resource_index); - - dep->resource_index = 0; - memset(¶ms, 0, sizeof(params)); - - ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); - if (!ret) - dep->flags |= DWC3_EP_END_TRANSFER_PENDING; - } + if (ret == -EAGAIN) + ret = __dwc3_stop_active_transfer(dep, false, true); return ret; } @@ -1899,6 +1923,7 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) */ if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) || (dep->flags & DWC3_EP_WEDGE) || + (dep->flags & DWC3_EP_DELAY_STOP) || (dep->flags & DWC3_EP_STALL)) { dep->flags |= DWC3_EP_DELAY_START; return 0; @@ -1913,13 +1938,11 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) * errors which will force us issue EndTransfer command. */ if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { - if (!(dep->flags & DWC3_EP_PENDING_REQUEST) && - !(dep->flags & DWC3_EP_TRANSFER_STARTED)) - return 0; - - if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { - if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) + if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) { + if ((dep->flags & DWC3_EP_PENDING_REQUEST)) return __dwc3_gadget_start_isoc(dep); + + return 0; } } @@ -2033,6 +2056,16 @@ static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, if (r == req) { struct dwc3_request *t; + /* + * If a Setup packet is received but yet to DMA out, the controller will + * not process the End Transfer command of any endpoint. Polling of its + * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a + * timeout. Delay issuing the End Transfer command until the Setup TRB is + * prepared. + */ + if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) + dep->flags |= DWC3_EP_DELAY_STOP; + /* wait until it is processed */ dwc3_stop_active_transfer(dep, true, true); @@ -2116,7 +2149,8 @@ int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) list_for_each_entry_safe(req, tmp, &dep->started_list, list) dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED); - if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) { + if (dep->flags & DWC3_EP_END_TRANSFER_PENDING || + (dep->flags & DWC3_EP_DELAY_STOP)) { dep->flags |= DWC3_EP_PENDING_CLEAR_STALL; return 0; } @@ -2544,6 +2578,17 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) dwc->ev_buf->length; } } else { + /* + * In the Synopsys DWC_usb31 1.90a programming guide section + * 4.1.9, it specifies that for a reconnect after a + * device-initiated disconnect requires a core soft reset + * (DCTL.CSftRst) before enabling the run/stop bit. + */ + spin_unlock_irqrestore(&dwc->lock, flags); + dwc3_core_soft_reset(dwc); + spin_lock_irqsave(&dwc->lock, flags); + + dwc3_event_buffers_setup(dwc); __dwc3_gadget_start(dwc); } @@ -3596,14 +3641,11 @@ static void dwc3_reset_gadget(struct dwc3 *dwc) } } -static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, +void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt) { - struct dwc3_gadget_ep_cmd_params params; - u32 cmd; - int ret; - if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) || + (dep->flags & DWC3_EP_DELAY_STOP) || (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) return; @@ -3634,19 +3676,7 @@ static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, * This mode is NOT available on the DWC_usb31 IP. */ - cmd = DWC3_DEPCMD_ENDTRANSFER; - cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; - cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; - cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); - memset(¶ms, 0, sizeof(params)); - ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); - WARN_ON_ONCE(ret); - dep->resource_index = 0; - - if (!interrupt) - dep->flags &= ~DWC3_EP_TRANSFER_STARTED; - else - dep->flags |= DWC3_EP_END_TRANSFER_PENDING; + __dwc3_stop_active_transfer(dep, force, interrupt); } static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h index 77df4b6d6c13..f763380e672e 100644 --- a/drivers/usb/dwc3/gadget.h +++ b/drivers/usb/dwc3/gadget.h @@ -116,6 +116,7 @@ int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, gfp_t gfp_flags); int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol); void dwc3_ep0_send_delayed_status(struct dwc3 *dwc); +void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt); /** * dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW diff --git a/drivers/usb/early/xhci-dbc.c b/drivers/usb/early/xhci-dbc.c index 4502108069cd..bfb7e2b85299 100644 --- a/drivers/usb/early/xhci-dbc.c +++ b/drivers/usb/early/xhci-dbc.c @@ -599,23 +599,26 @@ static int __init xdbc_early_setup(void) return 0; } -int __init early_xdbc_parse_parameter(char *s) +int __init early_xdbc_parse_parameter(char *s, int keep_early) { unsigned long dbgp_num = 0; u32 bus, dev, func, offset; + char *e; int ret; if (!early_pci_allowed()) return -EPERM; - if (strstr(s, "keep")) - early_console_keep = true; + early_console_keep = keep_early; if (xdbc.xdbc_reg) return 0; - if (*s && kstrtoul(s, 0, &dbgp_num)) - dbgp_num = 0; + if (*s) { + dbgp_num = simple_strtoul(s, &e, 10); + if (s == e) + dbgp_num = 0; + } pr_notice("dbgp_num: %lu\n", dbgp_num); diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 130dad7130b6..33f1ef91b046 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -4,7 +4,6 @@ # subdir-ccflags-$(CONFIG_USB_GADGET_DEBUG) := -DDEBUG subdir-ccflags-$(CONFIG_USB_GADGET_VERBOSE) += -DVERBOSE_DEBUG -ccflags-y += -I$(srctree)/drivers/usb/gadget/udc obj-$(CONFIG_USB_LIBCOMPOSITE) += libcomposite.o libcomposite-y := usbstring.o config.o epautoconf.o diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index 9315313108c9..2eaeaae96759 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -863,24 +863,25 @@ static int set_config(struct usb_composite_dev *cdev, const struct usb_ctrlrequest *ctrl, unsigned number) { struct usb_gadget *gadget = cdev->gadget; - struct usb_configuration *c = NULL; + struct usb_configuration *c = NULL, *iter; int result = -EINVAL; unsigned power = gadget_is_otg(gadget) ? 8 : 100; int tmp; if (number) { - list_for_each_entry(c, &cdev->configs, list) { - if (c->bConfigurationValue == number) { - /* - * We disable the FDs of the previous - * configuration only if the new configuration - * is a valid one - */ - if (cdev->config) - reset_config(cdev); - result = 0; - break; - } + list_for_each_entry(iter, &cdev->configs, list) { + if (iter->bConfigurationValue != number) + continue; + /* + * We disable the FDs of the previous + * configuration only if the new configuration + * is a valid one + */ + if (cdev->config) + reset_config(cdev); + c = iter; + result = 0; + break; } if (result < 0) goto done; @@ -1690,6 +1691,7 @@ composite_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) u16 w_value = le16_to_cpu(ctrl->wValue); u16 w_length = le16_to_cpu(ctrl->wLength); struct usb_function *f = NULL; + struct usb_function *iter; u8 endp; if (w_length > USB_COMP_EP0_BUFSIZ) { @@ -2046,12 +2048,12 @@ unknown: if (!cdev->config) break; endp = ((w_index & 0x80) >> 3) | (w_index & 0x0f); - list_for_each_entry(f, &cdev->config->functions, list) { - if (test_bit(endp, f->endpoints)) + list_for_each_entry(iter, &cdev->config->functions, list) { + if (test_bit(endp, iter->endpoints)) { + f = iter; break; + } } - if (&f->list == &cdev->config->functions) - f = NULL; break; } try_fun_setup: diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c index fd3966bedefe..f8cc026d019e 100644 --- a/drivers/usb/gadget/configfs.c +++ b/drivers/usb/gadget/configfs.c @@ -450,7 +450,7 @@ static int config_usb_cfg_link( struct usb_function_instance *fi = to_usb_function_instance(usb_func_ci); - struct usb_function_instance *a_fi; + struct usb_function_instance *a_fi = NULL, *iter; struct usb_function *f; int ret; @@ -460,11 +460,13 @@ static int config_usb_cfg_link( * from another gadget or a random directory. * Also a function instance can only be linked once. */ - list_for_each_entry(a_fi, &gi->available_func, cfs_list) { - if (a_fi == fi) - break; + list_for_each_entry(iter, &gi->available_func, cfs_list) { + if (iter != fi) + continue; + a_fi = iter; + break; } - if (a_fi != fi) { + if (!a_fi) { ret = -EINVAL; goto out; } @@ -914,15 +916,17 @@ static int os_desc_link(struct config_item *os_desc_ci, struct gadget_info *gi = os_desc_item_to_gadget_info(os_desc_ci); struct usb_composite_dev *cdev = &gi->cdev; struct config_usb_cfg *c_target = to_config_usb_cfg(usb_cfg_ci); - struct usb_configuration *c; + struct usb_configuration *c = NULL, *iter; int ret; mutex_lock(&gi->lock); - list_for_each_entry(c, &cdev->configs, list) { - if (c == &c_target->c) - break; + list_for_each_entry(iter, &cdev->configs, list) { + if (iter != &c_target->c) + continue; + c = iter; + break; } - if (c != &c_target->c) { + if (!c) { ret = -EINVAL; goto out; } diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index 1922fd02043c..4585ee3a444a 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -919,12 +919,12 @@ static ssize_t __ffs_epfile_read_data(struct ffs_epfile *epfile, data_len, ret); data_len -= ret; - buf = kmalloc(sizeof(*buf) + data_len, GFP_KERNEL); + buf = kmalloc(struct_size(buf, storage, data_len), GFP_KERNEL); if (!buf) return -ENOMEM; buf->length = data_len; buf->data = buf->storage; - memcpy(buf->storage, data + ret, data_len); + memcpy(buf->storage, data + ret, flex_array_size(buf, storage, data_len)); /* * At this point read_buffer is NULL or READ_BUFFER_DROP (if diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_storage.c index 7371c6e65b10..3a77bca0ebe1 100644 --- a/drivers/usb/gadget/function/f_mass_storage.c +++ b/drivers/usb/gadget/function/f_mass_storage.c @@ -1189,6 +1189,8 @@ static int do_read_toc(struct fsg_common *common, struct fsg_buffhd *bh) int msf = common->cmnd[1] & 0x02; int start_track = common->cmnd[6]; u8 *buf = (u8 *)bh->buf; + u8 format; + int i, len; if ((common->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */ start_track > 1) { @@ -1196,18 +1198,62 @@ static int do_read_toc(struct fsg_common *common, struct fsg_buffhd *bh) return -EINVAL; } - memset(buf, 0, 20); - buf[1] = (20-2); /* TOC data length */ - buf[2] = 1; /* First track number */ - buf[3] = 1; /* Last track number */ - buf[5] = 0x16; /* Data track, copying allowed */ - buf[6] = 0x01; /* Only track is number 1 */ - store_cdrom_address(&buf[8], msf, 0); + format = common->cmnd[2] & 0xf; + /* + * Check if CDB is old style SFF-8020i + * i.e. format is in 2 MSBs of byte 9 + * Mac OS-X host sends us this. + */ + if (format == 0) + format = (common->cmnd[9] >> 6) & 0x3; - buf[13] = 0x16; /* Lead-out track is data */ - buf[14] = 0xAA; /* Lead-out track number */ - store_cdrom_address(&buf[16], msf, curlun->num_sectors); - return 20; + switch (format) { + case 0: + /* Formatted TOC */ + len = 4 + 2*8; /* 4 byte header + 2 descriptors */ + memset(buf, 0, len); + buf[1] = len - 2; /* TOC Length excludes length field */ + buf[2] = 1; /* First track number */ + buf[3] = 1; /* Last track number */ + buf[5] = 0x16; /* Data track, copying allowed */ + buf[6] = 0x01; /* Only track is number 1 */ + store_cdrom_address(&buf[8], msf, 0); + + buf[13] = 0x16; /* Lead-out track is data */ + buf[14] = 0xAA; /* Lead-out track number */ + store_cdrom_address(&buf[16], msf, curlun->num_sectors); + return len; + + case 2: + /* Raw TOC */ + len = 4 + 3*11; /* 4 byte header + 3 descriptors */ + memset(buf, 0, len); /* Header + A0, A1 & A2 descriptors */ + buf[1] = len - 2; /* TOC Length excludes length field */ + buf[2] = 1; /* First complete session */ + buf[3] = 1; /* Last complete session */ + + buf += 4; + /* fill in A0, A1 and A2 points */ + for (i = 0; i < 3; i++) { + buf[0] = 1; /* Session number */ + buf[1] = 0x16; /* Data track, copying allowed */ + /* 2 - Track number 0 -> TOC */ + buf[3] = 0xA0 + i; /* A0, A1, A2 point */ + /* 4, 5, 6 - Min, sec, frame is zero */ + buf[8] = 1; /* Pmin: last track number */ + buf += 11; /* go to next track descriptor */ + } + buf -= 11; /* go back to A2 descriptor */ + + /* For A2, 7, 8, 9, 10 - zero, Pmin, Psec, Pframe of Lead out */ + store_cdrom_address(&buf[7], msf, curlun->num_sectors); + return len; + + default: + /* Multi-session, PMA, ATIP, CD-TEXT not supported/required */ + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } } static int do_mode_sense(struct fsg_common *common, struct fsg_buffhd *bh) @@ -1945,7 +1991,7 @@ static int do_scsi_command(struct fsg_common *common) common->data_size_from_cmnd = get_unaligned_be16(&common->cmnd[7]); reply = check_command(common, 10, DATA_DIR_TO_HOST, - (7<<6) | (1<<1), 1, + (0xf<<6) | (3<<1), 1, "READ TOC"); if (reply == 0) reply = do_read_toc(common, bh); diff --git a/drivers/usb/gadget/function/f_phonet.c b/drivers/usb/gadget/function/f_phonet.c index 068ed8417e5a..0bebbdf3f213 100644 --- a/drivers/usb/gadget/function/f_phonet.c +++ b/drivers/usb/gadget/function/f_phonet.c @@ -668,10 +668,8 @@ static struct usb_function *phonet_alloc(struct usb_function_instance *fi) { struct f_phonet *fp; struct f_phonet_opts *opts; - int size; - size = sizeof(*fp) + (phonet_rxq_size * sizeof(struct usb_request *)); - fp = kzalloc(size, GFP_KERNEL); + fp = kzalloc(struct_size(fp, out_reqv, phonet_rxq_size), GFP_KERNEL); if (!fp) return ERR_PTR(-ENOMEM); diff --git a/drivers/usb/gadget/function/f_serial.c b/drivers/usb/gadget/function/f_serial.c index 1ed8ff0ac2d3..a9480b9e312e 100644 --- a/drivers/usb/gadget/function/f_serial.c +++ b/drivers/usb/gadget/function/f_serial.c @@ -345,6 +345,10 @@ static void gser_free(struct usb_function *f) static void gser_unbind(struct usb_configuration *c, struct usb_function *f) { + struct f_gser *gser = func_to_gser(f); + + /* Ensure port is disconnected before unbinding */ + gserial_disconnect(&gser->port); usb_free_all_descriptors(f); } diff --git a/drivers/usb/gadget/function/f_uac1.c b/drivers/usb/gadget/function/f_uac1.c index 03f50643fbba..6f0e1d803dc2 100644 --- a/drivers/usb/gadget/function/f_uac1.c +++ b/drivers/usb/gadget/function/f_uac1.c @@ -3,6 +3,7 @@ * f_uac1.c -- USB Audio Class 1.0 Function (using u_audio API) * * Copyright (C) 2016 Ruslan Bilovol + * Copyright (C) 2021 Julian Scheel * * This driver doesn't expect any real Audio codec to be present * on the device - the audio streams are simply sinked to and @@ -42,6 +43,9 @@ struct f_uac1 { /* Interrupt IN endpoint of AC interface */ struct usb_ep *int_ep; atomic_t int_count; + int ctl_id; /* EP id */ + int c_srate; /* current capture srate */ + int p_srate; /* current playback prate */ }; static inline struct f_uac1 *func_to_uac1(struct usb_function *f) @@ -188,16 +192,18 @@ static struct uac1_as_header_descriptor as_in_header_desc = { .wFormatTag = cpu_to_le16(UAC_FORMAT_TYPE_I_PCM), }; -DECLARE_UAC_FORMAT_TYPE_I_DISCRETE_DESC(1); +DECLARE_UAC_FORMAT_TYPE_I_DISCRETE_DESC(UAC_MAX_RATES); +#define uac_format_type_i_discrete_descriptor \ + uac_format_type_i_discrete_descriptor_##UAC_MAX_RATES -static struct uac_format_type_i_discrete_descriptor_1 as_out_type_i_desc = { - .bLength = UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(1), +static struct uac_format_type_i_discrete_descriptor as_out_type_i_desc = { + .bLength = 0, /* filled on rate setup */ .bDescriptorType = USB_DT_CS_INTERFACE, .bDescriptorSubtype = UAC_FORMAT_TYPE, .bFormatType = UAC_FORMAT_TYPE_I, .bSubframeSize = 2, .bBitResolution = 16, - .bSamFreqType = 1, + .bSamFreqType = 0, /* filled on rate setup */ }; /* Standard ISO OUT Endpoint Descriptor */ @@ -221,14 +227,14 @@ static struct uac_iso_endpoint_descriptor as_iso_out_desc = { .wLockDelay = cpu_to_le16(1), }; -static struct uac_format_type_i_discrete_descriptor_1 as_in_type_i_desc = { - .bLength = UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(1), +static struct uac_format_type_i_discrete_descriptor as_in_type_i_desc = { + .bLength = 0, /* filled on rate setup */ .bDescriptorType = USB_DT_CS_INTERFACE, .bDescriptorSubtype = UAC_FORMAT_TYPE, .bFormatType = UAC_FORMAT_TYPE_I, .bSubframeSize = 2, .bBitResolution = 16, - .bSamFreqType = 1, + .bSamFreqType = 0, /* filled on rate setup */ }; /* Standard ISO OUT Endpoint Descriptor */ @@ -303,7 +309,7 @@ enum { }; static struct usb_string strings_uac1[] = { - [STR_AC_IF].s = "AC Interface", + /* [STR_AC_IF].s = DYNAMIC, */ [STR_USB_OUT_IT].s = "Playback Input terminal", [STR_USB_OUT_IT_CH_NAMES].s = "Playback Channels", [STR_IO_OUT_OT].s = "Playback Output terminal", @@ -333,6 +339,30 @@ static struct usb_gadget_strings *uac1_strings[] = { * This function is an ALSA sound card following USB Audio Class Spec 1.0. */ +static void uac_cs_attr_sample_rate(struct usb_ep *ep, struct usb_request *req) +{ + struct usb_function *fn = ep->driver_data; + struct usb_composite_dev *cdev = fn->config->cdev; + struct g_audio *agdev = func_to_g_audio(fn); + struct f_uac1 *uac1 = func_to_uac1(fn); + u8 *buf = (u8 *)req->buf; + u32 val = 0; + + if (req->actual != 3) { + WARN(cdev, "Invalid data size for UAC_EP_CS_ATTR_SAMPLE_RATE.\n"); + return; + } + + val = buf[0] | (buf[1] << 8) | (buf[2] << 16); + if (uac1->ctl_id == (USB_DIR_IN | 2)) { + uac1->p_srate = val; + u_audio_set_playback_srate(agdev, uac1->p_srate); + } else if (uac1->ctl_id == (USB_DIR_OUT | 1)) { + uac1->c_srate = val; + u_audio_set_capture_srate(agdev, uac1->c_srate); + } +} + static void audio_notify_complete(struct usb_ep *_ep, struct usb_request *req) { struct g_audio *audio = req->context; @@ -707,18 +737,27 @@ static int audio_set_endpoint_req(struct usb_function *f, const struct usb_ctrlrequest *ctrl) { struct usb_composite_dev *cdev = f->config->cdev; + struct usb_request *req = f->config->cdev->req; + struct f_uac1 *uac1 = func_to_uac1(f); int value = -EOPNOTSUPP; u16 ep = le16_to_cpu(ctrl->wIndex); u16 len = le16_to_cpu(ctrl->wLength); u16 w_value = le16_to_cpu(ctrl->wValue); + u8 cs = w_value >> 8; DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n", ctrl->bRequest, w_value, len, ep); switch (ctrl->bRequest) { - case UAC_SET_CUR: + case UAC_SET_CUR: { + if (cs == UAC_EP_CS_ATTR_SAMPLE_RATE) { + cdev->gadget->ep0->driver_data = f; + uac1->ctl_id = ep; + req->complete = uac_cs_attr_sample_rate; + } value = len; break; + } case UAC_SET_MIN: break; @@ -743,16 +782,33 @@ static int audio_get_endpoint_req(struct usb_function *f, const struct usb_ctrlrequest *ctrl) { struct usb_composite_dev *cdev = f->config->cdev; + struct usb_request *req = f->config->cdev->req; + struct f_uac1 *uac1 = func_to_uac1(f); + u8 *buf = (u8 *)req->buf; int value = -EOPNOTSUPP; - u8 ep = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF); + u8 ep = le16_to_cpu(ctrl->wIndex); u16 len = le16_to_cpu(ctrl->wLength); u16 w_value = le16_to_cpu(ctrl->wValue); + u8 cs = w_value >> 8; + u32 val = 0; DBG(cdev, "bRequest 0x%x, w_value 0x%04x, len %d, endpoint %d\n", ctrl->bRequest, w_value, len, ep); switch (ctrl->bRequest) { - case UAC_GET_CUR: + case UAC_GET_CUR: { + if (cs == UAC_EP_CS_ATTR_SAMPLE_RATE) { + if (ep == (USB_DIR_IN | 2)) + val = uac1->p_srate; + else if (ep == (USB_DIR_OUT | 1)) + val = uac1->c_srate; + buf[2] = (val >> 16) & 0xff; + buf[1] = (val >> 8) & 0xff; + buf[0] = val & 0xff; + } + value = len; + break; + } case UAC_GET_MIN: case UAC_GET_MAX: case UAC_GET_RES: @@ -905,6 +961,14 @@ static void f_audio_disable(struct usb_function *f) usb_ep_disable(uac1->int_ep); } +static void +f_audio_suspend(struct usb_function *f) +{ + struct f_uac1 *uac1 = func_to_uac1(f); + + u_audio_suspend(&uac1->g_audio); +} + /*-------------------------------------------------------------------------*/ static struct uac_feature_unit_descriptor *build_fu_desc(int chmask) { @@ -1074,10 +1138,10 @@ static int f_audio_validate_opts(struct g_audio *audio, struct device *dev) } else if ((opts->c_ssize < 1) || (opts->c_ssize > 4)) { dev_err(dev, "Error: incorrect capture sample size\n"); return -EINVAL; - } else if (!opts->p_srate) { + } else if (!opts->p_srates[0]) { dev_err(dev, "Error: incorrect playback sampling rate\n"); return -EINVAL; - } else if (!opts->c_srate) { + } else if (!opts->c_srates[0]) { dev_err(dev, "Error: incorrect capture sampling rate\n"); return -EINVAL; } @@ -1118,10 +1182,9 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f) struct f_uac1_opts *audio_opts; struct usb_ep *ep = NULL; struct usb_string *us; - u8 *sam_freq; - int rate; int ba_iface_id; int status; + int idx, i; status = f_audio_validate_opts(audio, dev); if (status) @@ -1129,6 +1192,8 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f) audio_opts = container_of(f->fi, struct f_uac1_opts, func_inst); + strings_uac1[STR_AC_IF].s = audio_opts->function_name; + us = usb_gstrings_attach(cdev, uac1_strings, ARRAY_SIZE(strings_uac1)); if (IS_ERR(us)) return PTR_ERR(us); @@ -1213,12 +1278,25 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f) } /* Set sample rates */ - rate = audio_opts->c_srate; - sam_freq = as_out_type_i_desc.tSamFreq[0]; - memcpy(sam_freq, &rate, 3); - rate = audio_opts->p_srate; - sam_freq = as_in_type_i_desc.tSamFreq[0]; - memcpy(sam_freq, &rate, 3); + for (i = 0, idx = 0; i < UAC_MAX_RATES; i++) { + if (audio_opts->c_srates[i] == 0) + break; + memcpy(as_out_type_i_desc.tSamFreq[idx++], + &audio_opts->c_srates[i], 3); + } + as_out_type_i_desc.bLength = UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(idx); + as_out_type_i_desc.bSamFreqType = idx; + + for (i = 0, idx = 0; i < UAC_MAX_RATES; i++) { + if (audio_opts->p_srates[i] == 0) + break; + memcpy(as_in_type_i_desc.tSamFreq[idx++], + &audio_opts->p_srates[i], 3); + } + as_in_type_i_desc.bLength = UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE(idx); + as_in_type_i_desc.bSamFreqType = idx; + uac1->p_srate = audio_opts->p_srates[0]; + uac1->c_srate = audio_opts->c_srates[0]; /* allocate instance-specific interface IDs, and patch descriptors */ status = usb_interface_id(c, f); @@ -1297,7 +1375,8 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f) audio->out_ep_maxpsize = le16_to_cpu(as_out_ep_desc.wMaxPacketSize); audio->in_ep_maxpsize = le16_to_cpu(as_in_ep_desc.wMaxPacketSize); audio->params.c_chmask = audio_opts->c_chmask; - audio->params.c_srate = audio_opts->c_srate; + memcpy(audio->params.c_srates, audio_opts->c_srates, + sizeof(audio->params.c_srates)); audio->params.c_ssize = audio_opts->c_ssize; if (FUIN_EN(audio_opts)) { audio->params.p_fu.id = USB_IN_FU_ID; @@ -1309,7 +1388,8 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f) audio->params.p_fu.volume_res = audio_opts->p_volume_res; } audio->params.p_chmask = audio_opts->p_chmask; - audio->params.p_srate = audio_opts->p_srate; + memcpy(audio->params.p_srates, audio_opts->p_srates, + sizeof(audio->params.p_srates)); audio->params.p_ssize = audio_opts->p_ssize; if (FUOUT_EN(audio_opts)) { audio->params.c_fu.id = USB_OUT_FU_ID; @@ -1414,11 +1494,106 @@ end: \ \ CONFIGFS_ATTR(f_uac1_opts_, name) +#define UAC1_RATE_ATTRIBUTE(name) \ +static ssize_t f_uac1_opts_##name##_show(struct config_item *item, \ + char *page) \ +{ \ + struct f_uac1_opts *opts = to_f_uac1_opts(item); \ + int result = 0; \ + int i; \ + \ + mutex_lock(&opts->lock); \ + page[0] = '\0'; \ + for (i = 0; i < UAC_MAX_RATES; i++) { \ + if (opts->name##s[i] == 0) \ + break; \ + result += sprintf(page + strlen(page), "%u,", \ + opts->name##s[i]); \ + } \ + if (strlen(page) > 0) \ + page[strlen(page) - 1] = '\n'; \ + mutex_unlock(&opts->lock); \ + \ + return result; \ +} \ + \ +static ssize_t f_uac1_opts_##name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + struct f_uac1_opts *opts = to_f_uac1_opts(item); \ + char *split_page = NULL; \ + int ret = -EINVAL; \ + char *token; \ + u32 num; \ + int i; \ + \ + mutex_lock(&opts->lock); \ + if (opts->refcnt) { \ + ret = -EBUSY; \ + goto end; \ + } \ + \ + i = 0; \ + memset(opts->name##s, 0x00, sizeof(opts->name##s)); \ + split_page = kstrdup(page, GFP_KERNEL); \ + while ((token = strsep(&split_page, ",")) != NULL) { \ + ret = kstrtou32(token, 0, &num); \ + if (ret) \ + goto end; \ + \ + opts->name##s[i++] = num; \ + ret = len; \ + }; \ + \ +end: \ + kfree(split_page); \ + mutex_unlock(&opts->lock); \ + return ret; \ +} \ + \ +CONFIGFS_ATTR(f_uac1_opts_, name) + +#define UAC1_ATTRIBUTE_STRING(name) \ +static ssize_t f_uac1_opts_##name##_show(struct config_item *item, \ + char *page) \ +{ \ + struct f_uac1_opts *opts = to_f_uac1_opts(item); \ + int result; \ + \ + mutex_lock(&opts->lock); \ + result = snprintf(page, sizeof(opts->name), "%s", opts->name); \ + mutex_unlock(&opts->lock); \ + \ + return result; \ +} \ + \ +static ssize_t f_uac1_opts_##name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + struct f_uac1_opts *opts = to_f_uac1_opts(item); \ + int ret = 0; \ + \ + mutex_lock(&opts->lock); \ + if (opts->refcnt) { \ + ret = -EBUSY; \ + goto end; \ + } \ + \ + ret = snprintf(opts->name, min(sizeof(opts->name), len), \ + "%s", page); \ + \ +end: \ + mutex_unlock(&opts->lock); \ + return ret; \ +} \ + \ +CONFIGFS_ATTR(f_uac1_opts_, name) + UAC1_ATTRIBUTE(u32, c_chmask); -UAC1_ATTRIBUTE(u32, c_srate); +UAC1_RATE_ATTRIBUTE(c_srate); UAC1_ATTRIBUTE(u32, c_ssize); UAC1_ATTRIBUTE(u32, p_chmask); -UAC1_ATTRIBUTE(u32, p_srate); +UAC1_RATE_ATTRIBUTE(p_srate); UAC1_ATTRIBUTE(u32, p_ssize); UAC1_ATTRIBUTE(u32, req_number); @@ -1433,6 +1608,7 @@ UAC1_ATTRIBUTE(bool, c_volume_present); UAC1_ATTRIBUTE(s16, c_volume_min); UAC1_ATTRIBUTE(s16, c_volume_max); UAC1_ATTRIBUTE(s16, c_volume_res); +UAC1_ATTRIBUTE_STRING(function_name); static struct configfs_attribute *f_uac1_attrs[] = { &f_uac1_opts_attr_c_chmask, @@ -1455,6 +1631,8 @@ static struct configfs_attribute *f_uac1_attrs[] = { &f_uac1_opts_attr_c_volume_max, &f_uac1_opts_attr_c_volume_res, + &f_uac1_opts_attr_function_name, + NULL, }; @@ -1487,10 +1665,10 @@ static struct usb_function_instance *f_audio_alloc_inst(void) &f_uac1_func_type); opts->c_chmask = UAC1_DEF_CCHMASK; - opts->c_srate = UAC1_DEF_CSRATE; + opts->c_srates[0] = UAC1_DEF_CSRATE; opts->c_ssize = UAC1_DEF_CSSIZE; opts->p_chmask = UAC1_DEF_PCHMASK; - opts->p_srate = UAC1_DEF_PSRATE; + opts->p_srates[0] = UAC1_DEF_PSRATE; opts->p_ssize = UAC1_DEF_PSSIZE; opts->p_mute_present = UAC1_DEF_MUTE_PRESENT; @@ -1506,6 +1684,9 @@ static struct usb_function_instance *f_audio_alloc_inst(void) opts->c_volume_res = UAC1_DEF_RES_DB; opts->req_number = UAC1_DEF_REQ_NUM; + + snprintf(opts->function_name, sizeof(opts->function_name), "AC Interface"); + return &opts->func_inst; } @@ -1562,6 +1743,7 @@ static struct usb_function *f_audio_alloc(struct usb_function_instance *fi) uac1->g_audio.func.get_alt = f_audio_get_alt; uac1->g_audio.func.setup = f_audio_setup; uac1->g_audio.func.disable = f_audio_disable; + uac1->g_audio.func.suspend = f_audio_suspend; uac1->g_audio.func.free_func = f_audio_free; return &uac1->g_audio.func; diff --git a/drivers/usb/gadget/function/f_uac2.c b/drivers/usb/gadget/function/f_uac2.c index 097a709549d6..1905a8d8e0c9 100644 --- a/drivers/usb/gadget/function/f_uac2.c +++ b/drivers/usb/gadget/function/f_uac2.c @@ -70,6 +70,8 @@ struct f_uac2 { /* Interrupt IN endpoint of AC interface */ struct usb_ep *int_ep; atomic_t int_count; + /* transient state, only valid during handling of a single control request */ + int clock_id; }; static inline struct f_uac2 *func_to_uac2(struct usb_function *f) @@ -104,14 +106,11 @@ enum { STR_AS_IN_ALT1, }; -static char clksrc_in[8]; -static char clksrc_out[8]; - static struct usb_string strings_fn[] = { - [STR_ASSOC].s = "Source/Sink", + /* [STR_ASSOC].s = DYNAMIC, */ [STR_IF_CTRL].s = "Topology Control", - [STR_CLKSRC_IN].s = clksrc_in, - [STR_CLKSRC_OUT].s = clksrc_out, + [STR_CLKSRC_IN].s = "Input Clock", + [STR_CLKSRC_OUT].s = "Output Clock", [STR_USB_IT].s = "USBH Out", [STR_IO_IT].s = "USBD Out", [STR_USB_OT].s = "USBH In", @@ -125,6 +124,16 @@ static struct usb_string strings_fn[] = { { }, }; +static const char *const speed_names[] = { + [USB_SPEED_UNKNOWN] = "UNKNOWN", + [USB_SPEED_LOW] = "LS", + [USB_SPEED_FULL] = "FS", + [USB_SPEED_HIGH] = "HS", + [USB_SPEED_WIRELESS] = "W", + [USB_SPEED_SUPER] = "SS", + [USB_SPEED_SUPER_PLUS] = "SS+", +}; + static struct usb_gadget_strings str_fn = { .language = 0x0409, /* en-us */ .strings = strings_fn, @@ -166,7 +175,7 @@ static struct uac_clock_source_descriptor in_clk_src_desc = { .bDescriptorSubtype = UAC2_CLOCK_SOURCE, /* .bClockID = DYNAMIC */ .bmAttributes = UAC_CLOCK_SOURCE_TYPE_INT_FIXED, - .bmControls = (CONTROL_RDONLY << CLK_FREQ_CTRL), + .bmControls = (CONTROL_RDWR << CLK_FREQ_CTRL), .bAssocTerminal = 0, }; @@ -178,7 +187,7 @@ static struct uac_clock_source_descriptor out_clk_src_desc = { .bDescriptorSubtype = UAC2_CLOCK_SOURCE, /* .bClockID = DYNAMIC */ .bmAttributes = UAC_CLOCK_SOURCE_TYPE_INT_FIXED, - .bmControls = (CONTROL_RDONLY << CLK_FREQ_CTRL), + .bmControls = (CONTROL_RDWR << CLK_FREQ_CTRL), .bAssocTerminal = 0, }; @@ -344,7 +353,7 @@ static struct usb_endpoint_descriptor hs_epout_desc = { /* .bmAttributes = DYNAMIC */ /* .wMaxPacketSize = DYNAMIC */ - .bInterval = 4, + /* .bInterval = DYNAMIC */ }; static struct usb_endpoint_descriptor ss_epout_desc = { @@ -354,7 +363,7 @@ static struct usb_endpoint_descriptor ss_epout_desc = { .bEndpointAddress = USB_DIR_OUT, /* .bmAttributes = DYNAMIC */ /* .wMaxPacketSize = DYNAMIC */ - .bInterval = 4, + /* .bInterval = DYNAMIC */ }; static struct usb_ss_ep_comp_descriptor ss_epout_desc_comp = { @@ -478,7 +487,7 @@ static struct usb_endpoint_descriptor hs_epin_desc = { .bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC, /* .wMaxPacketSize = DYNAMIC */ - .bInterval = 4, + /* .bInterval = DYNAMIC */ }; static struct usb_endpoint_descriptor ss_epin_desc = { @@ -488,7 +497,7 @@ static struct usb_endpoint_descriptor ss_epin_desc = { .bEndpointAddress = USB_DIR_IN, .bmAttributes = USB_ENDPOINT_XFER_ISOC | USB_ENDPOINT_SYNC_ASYNC, /* .wMaxPacketSize = DYNAMIC */ - .bInterval = 4, + /* .bInterval = DYNAMIC */ }; static struct usb_ss_ep_comp_descriptor ss_epin_desc_comp = { @@ -634,44 +643,50 @@ struct cntrl_cur_lay3 { __le32 dCUR; }; -struct cntrl_range_lay3 { - __le16 wNumSubRanges; +struct cntrl_subrange_lay3 { __le32 dMIN; __le32 dMAX; __le32 dRES; } __packed; -static int set_ep_max_packet_size(const struct f_uac2_opts *uac2_opts, - struct usb_endpoint_descriptor *ep_desc, - enum usb_device_speed speed, bool is_playback) +#define ranges_lay3_size(c) (sizeof(c.wNumSubRanges) \ + + le16_to_cpu(c.wNumSubRanges) \ + * sizeof(struct cntrl_subrange_lay3)) + +#define DECLARE_UAC2_CNTRL_RANGES_LAY3(k, n) \ + struct cntrl_ranges_lay3_##k { \ + __le16 wNumSubRanges; \ + struct cntrl_subrange_lay3 r[n]; \ +} __packed + +DECLARE_UAC2_CNTRL_RANGES_LAY3(srates, UAC_MAX_RATES); + +static int get_max_srate(const int *srates) +{ + int i, max_srate = 0; + + for (i = 0; i < UAC_MAX_RATES; i++) { + if (srates[i] == 0) + break; + if (srates[i] > max_srate) + max_srate = srates[i]; + } + return max_srate; +} + +static int get_max_bw_for_bint(const struct f_uac2_opts *uac2_opts, + u8 bint, unsigned int factor, bool is_playback) { int chmask, srate, ssize; - u16 max_size_bw, max_size_ep; - unsigned int factor; - - switch (speed) { - case USB_SPEED_FULL: - max_size_ep = 1023; - factor = 1000; - break; - - case USB_SPEED_HIGH: - case USB_SPEED_SUPER: - max_size_ep = 1024; - factor = 8000; - break; - - default: - return -EINVAL; - } + u16 max_size_bw; if (is_playback) { chmask = uac2_opts->p_chmask; - srate = uac2_opts->p_srate; + srate = get_max_srate(uac2_opts->p_srates); ssize = uac2_opts->p_ssize; } else { chmask = uac2_opts->c_chmask; - srate = uac2_opts->c_srate; + srate = get_max_srate(uac2_opts->c_srates); ssize = uac2_opts->c_ssize; } @@ -681,14 +696,76 @@ static int set_ep_max_packet_size(const struct f_uac2_opts *uac2_opts, srate = srate * (1000 + uac2_opts->fb_max) / 1000; // updated srate is always bigger, therefore DIV_ROUND_UP always yields +1 max_size_bw = num_channels(chmask) * ssize * - (DIV_ROUND_UP(srate, factor / (1 << (ep_desc->bInterval - 1)))); + (DIV_ROUND_UP(srate, factor / (1 << (bint - 1)))); } else { // adding 1 frame provision for Win10 max_size_bw = num_channels(chmask) * ssize * - (DIV_ROUND_UP(srate, factor / (1 << (ep_desc->bInterval - 1))) + 1); + (DIV_ROUND_UP(srate, factor / (1 << (bint - 1))) + 1); } - ep_desc->wMaxPacketSize = cpu_to_le16(min_t(u16, max_size_bw, - max_size_ep)); + return max_size_bw; +} + +static int set_ep_max_packet_size_bint(struct device *dev, const struct f_uac2_opts *uac2_opts, + struct usb_endpoint_descriptor *ep_desc, + enum usb_device_speed speed, bool is_playback) +{ + u16 max_size_bw, max_size_ep; + u8 bint, opts_bint; + char *dir; + + switch (speed) { + case USB_SPEED_FULL: + max_size_ep = 1023; + // fixed + bint = ep_desc->bInterval; + max_size_bw = get_max_bw_for_bint(uac2_opts, bint, 1000, is_playback); + break; + + case USB_SPEED_HIGH: + case USB_SPEED_SUPER: + max_size_ep = 1024; + if (is_playback) + opts_bint = uac2_opts->p_hs_bint; + else + opts_bint = uac2_opts->c_hs_bint; + + if (opts_bint > 0) { + /* fixed bint */ + bint = opts_bint; + max_size_bw = get_max_bw_for_bint(uac2_opts, bint, 8000, is_playback); + } else { + /* checking bInterval from 4 to 1 whether the required bandwidth fits */ + for (bint = 4; bint > 0; --bint) { + max_size_bw = get_max_bw_for_bint( + uac2_opts, bint, 8000, is_playback); + if (max_size_bw <= max_size_ep) + break; + } + } + break; + + default: + return -EINVAL; + } + + if (is_playback) + dir = "Playback"; + else + dir = "Capture"; + + if (max_size_bw <= max_size_ep) + dev_dbg(dev, + "%s %s: Would use wMaxPacketSize %d and bInterval %d\n", + speed_names[speed], dir, max_size_bw, bint); + else { + dev_warn(dev, + "%s %s: Req. wMaxPacketSize %d at bInterval %d > max ISOC %d, may drop data!\n", + speed_names[speed], dir, max_size_bw, bint, max_size_ep); + max_size_bw = max_size_ep; + } + + ep_desc->wMaxPacketSize = cpu_to_le16(max_size_bw); + ep_desc->bInterval = bint; return 0; } @@ -896,50 +973,45 @@ static void setup_descriptor(struct f_uac2_opts *opts) static int afunc_validate_opts(struct g_audio *agdev, struct device *dev) { struct f_uac2_opts *opts = g_audio_to_uac2_opts(agdev); + const char *msg = NULL; - if (!opts->p_chmask && !opts->c_chmask) { - dev_err(dev, "Error: no playback and capture channels\n"); - return -EINVAL; - } else if (opts->p_chmask & ~UAC2_CHANNEL_MASK) { - dev_err(dev, "Error: unsupported playback channels mask\n"); - return -EINVAL; - } else if (opts->c_chmask & ~UAC2_CHANNEL_MASK) { - dev_err(dev, "Error: unsupported capture channels mask\n"); - return -EINVAL; - } else if ((opts->p_ssize < 1) || (opts->p_ssize > 4)) { - dev_err(dev, "Error: incorrect playback sample size\n"); - return -EINVAL; - } else if ((opts->c_ssize < 1) || (opts->c_ssize > 4)) { - dev_err(dev, "Error: incorrect capture sample size\n"); - return -EINVAL; - } else if (!opts->p_srate) { - dev_err(dev, "Error: incorrect playback sampling rate\n"); - return -EINVAL; - } else if (!opts->c_srate) { - dev_err(dev, "Error: incorrect capture sampling rate\n"); - return -EINVAL; - } + if (!opts->p_chmask && !opts->c_chmask) + msg = "no playback and capture channels"; + else if (opts->p_chmask & ~UAC2_CHANNEL_MASK) + msg = "unsupported playback channels mask"; + else if (opts->c_chmask & ~UAC2_CHANNEL_MASK) + msg = "unsupported capture channels mask"; + else if ((opts->p_ssize < 1) || (opts->p_ssize > 4)) + msg = "incorrect playback sample size"; + else if ((opts->c_ssize < 1) || (opts->c_ssize > 4)) + msg = "incorrect capture sample size"; + else if (!opts->p_srates[0]) + msg = "incorrect playback sampling rate"; + else if (!opts->c_srates[0]) + msg = "incorrect capture sampling rate"; - if (opts->p_volume_max <= opts->p_volume_min) { - dev_err(dev, "Error: incorrect playback volume max/min\n"); - return -EINVAL; - } else if (opts->c_volume_max <= opts->c_volume_min) { - dev_err(dev, "Error: incorrect capture volume max/min\n"); - return -EINVAL; - } else if (opts->p_volume_res <= 0) { - dev_err(dev, "Error: negative/zero playback volume resolution\n"); - return -EINVAL; - } else if (opts->c_volume_res <= 0) { - dev_err(dev, "Error: negative/zero capture volume resolution\n"); - return -EINVAL; - } + else if (opts->p_volume_max <= opts->p_volume_min) + msg = "incorrect playback volume max/min"; + else if (opts->c_volume_max <= opts->c_volume_min) + msg = "incorrect capture volume max/min"; + else if (opts->p_volume_res <= 0) + msg = "negative/zero playback volume resolution"; + else if (opts->c_volume_res <= 0) + msg = "negative/zero capture volume resolution"; - if ((opts->p_volume_max - opts->p_volume_min) % opts->p_volume_res) { - dev_err(dev, "Error: incorrect playback volume resolution\n"); - return -EINVAL; - } else if ((opts->c_volume_max - opts->c_volume_min) % opts->c_volume_res) { - dev_err(dev, "Error: incorrect capture volume resolution\n"); - return -EINVAL; + else if ((opts->p_volume_max - opts->p_volume_min) % opts->p_volume_res) + msg = "incorrect playback volume resolution"; + else if ((opts->c_volume_max - opts->c_volume_min) % opts->c_volume_res) + msg = "incorrect capture volume resolution"; + + else if ((opts->p_hs_bint < 0) || (opts->p_hs_bint > 4)) + msg = "incorrect playback HS/SS bInterval (1-4: fixed, 0: auto)"; + else if ((opts->c_hs_bint < 0) || (opts->c_hs_bint > 4)) + msg = "incorrect capture HS/SS bInterval (1-4: fixed, 0: auto)"; + + if (msg) { + dev_err(dev, "Error: %s\n", msg); + return -EINVAL; } return 0; @@ -961,6 +1033,8 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn) if (ret) return ret; + strings_fn[STR_ASSOC].s = uac2_opts->function_name; + us = usb_gstrings_attach(cdev, fn_strings, ARRAY_SIZE(strings_fn)); if (IS_ERR(us)) return PTR_ERR(us); @@ -1037,9 +1111,6 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn) *bma = cpu_to_le32(control); } - snprintf(clksrc_in, sizeof(clksrc_in), "%uHz", uac2_opts->p_srate); - snprintf(clksrc_out, sizeof(clksrc_out), "%uHz", uac2_opts->c_srate); - ret = usb_interface_id(cfg, fn); if (ret < 0) { dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); @@ -1103,44 +1174,49 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn) std_ac_if_desc.bNumEndpoints = 1; } + hs_epin_desc.bInterval = uac2_opts->p_hs_bint; + ss_epin_desc.bInterval = uac2_opts->p_hs_bint; + hs_epout_desc.bInterval = uac2_opts->c_hs_bint; + ss_epout_desc.bInterval = uac2_opts->c_hs_bint; + /* Calculate wMaxPacketSize according to audio bandwidth */ - ret = set_ep_max_packet_size(uac2_opts, &fs_epin_desc, USB_SPEED_FULL, - true); + ret = set_ep_max_packet_size_bint(dev, uac2_opts, &fs_epin_desc, + USB_SPEED_FULL, true); if (ret < 0) { dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); return ret; } - ret = set_ep_max_packet_size(uac2_opts, &fs_epout_desc, USB_SPEED_FULL, - false); + ret = set_ep_max_packet_size_bint(dev, uac2_opts, &fs_epout_desc, + USB_SPEED_FULL, false); if (ret < 0) { dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); return ret; } - ret = set_ep_max_packet_size(uac2_opts, &hs_epin_desc, USB_SPEED_HIGH, - true); + ret = set_ep_max_packet_size_bint(dev, uac2_opts, &hs_epin_desc, + USB_SPEED_HIGH, true); if (ret < 0) { dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); return ret; } - ret = set_ep_max_packet_size(uac2_opts, &hs_epout_desc, USB_SPEED_HIGH, - false); + ret = set_ep_max_packet_size_bint(dev, uac2_opts, &hs_epout_desc, + USB_SPEED_HIGH, false); if (ret < 0) { dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); return ret; } - ret = set_ep_max_packet_size(uac2_opts, &ss_epin_desc, USB_SPEED_SUPER, - true); + ret = set_ep_max_packet_size_bint(dev, uac2_opts, &ss_epin_desc, + USB_SPEED_SUPER, true); if (ret < 0) { dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); return ret; } - ret = set_ep_max_packet_size(uac2_opts, &ss_epout_desc, USB_SPEED_SUPER, - false); + ret = set_ep_max_packet_size_bint(dev, uac2_opts, &ss_epout_desc, + USB_SPEED_SUPER, false); if (ret < 0) { dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); return ret; @@ -1209,7 +1285,8 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn) agdev->gadget = gadget; agdev->params.p_chmask = uac2_opts->p_chmask; - agdev->params.p_srate = uac2_opts->p_srate; + memcpy(agdev->params.p_srates, uac2_opts->p_srates, + sizeof(agdev->params.p_srates)); agdev->params.p_ssize = uac2_opts->p_ssize; if (FUIN_EN(uac2_opts)) { agdev->params.p_fu.id = USB_IN_FU_ID; @@ -1220,7 +1297,8 @@ afunc_bind(struct usb_configuration *cfg, struct usb_function *fn) agdev->params.p_fu.volume_res = uac2_opts->p_volume_res; } agdev->params.c_chmask = uac2_opts->c_chmask; - agdev->params.c_srate = uac2_opts->c_srate; + memcpy(agdev->params.c_srates, uac2_opts->c_srates, + sizeof(agdev->params.c_srates)); agdev->params.c_ssize = uac2_opts->c_ssize; if (FUOUT_EN(uac2_opts)) { agdev->params.c_fu.id = USB_OUT_FU_ID; @@ -1411,6 +1489,14 @@ afunc_disable(struct usb_function *fn) usb_ep_disable(uac2->int_ep); } +static void +afunc_suspend(struct usb_function *fn) +{ + struct f_uac2 *uac2 = func_to_uac2(fn); + + u_audio_suspend(&uac2->g_audio); +} + static int in_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr) { @@ -1423,10 +1509,10 @@ in_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr) u8 entity_id = (w_index >> 8) & 0xff; u8 control_selector = w_value >> 8; int value = -EOPNOTSUPP; - int p_srate, c_srate; + u32 p_srate, c_srate; - p_srate = opts->p_srate; - c_srate = opts->c_srate; + u_audio_get_playback_srate(agdev, &p_srate); + u_audio_get_capture_srate(agdev, &c_srate); if ((entity_id == USB_IN_CLK_ID) || (entity_id == USB_OUT_CLK_ID)) { if (control_selector == UAC2_CS_CONTROL_SAM_FREQ) { @@ -1500,28 +1586,39 @@ in_rq_range(struct usb_function *fn, const struct usb_ctrlrequest *cr) u8 entity_id = (w_index >> 8) & 0xff; u8 control_selector = w_value >> 8; int value = -EOPNOTSUPP; - int p_srate, c_srate; - - p_srate = opts->p_srate; - c_srate = opts->c_srate; if ((entity_id == USB_IN_CLK_ID) || (entity_id == USB_OUT_CLK_ID)) { if (control_selector == UAC2_CS_CONTROL_SAM_FREQ) { - struct cntrl_range_lay3 r; + struct cntrl_ranges_lay3_srates rs; + int i; + int wNumSubRanges = 0; + int srate; + int *srates; if (entity_id == USB_IN_CLK_ID) - r.dMIN = cpu_to_le32(p_srate); + srates = opts->p_srates; else if (entity_id == USB_OUT_CLK_ID) - r.dMIN = cpu_to_le32(c_srate); + srates = opts->c_srates; else return -EOPNOTSUPP; + for (i = 0; i < UAC_MAX_RATES; i++) { + srate = srates[i]; + if (srate == 0) + break; - r.dMAX = r.dMIN; - r.dRES = 0; - r.wNumSubRanges = cpu_to_le16(1); - - value = min_t(unsigned int, w_length, sizeof(r)); - memcpy(req->buf, &r, value); + rs.r[wNumSubRanges].dMIN = cpu_to_le32(srate); + rs.r[wNumSubRanges].dMAX = cpu_to_le32(srate); + rs.r[wNumSubRanges].dRES = 0; + wNumSubRanges++; + dev_dbg(&agdev->gadget->dev, + "%s(): clk %d: rate ID %d: %d\n", + __func__, entity_id, wNumSubRanges, srate); + } + rs.wNumSubRanges = cpu_to_le16(wNumSubRanges); + value = min_t(unsigned int, w_length, ranges_lay3_size(rs)); + dev_dbg(&agdev->gadget->dev, "%s(): sending %d rates, size %d\n", + __func__, rs.wNumSubRanges, value); + memcpy(req->buf, &rs, value); } else { dev_err(&agdev->gadget->dev, "%s:%d control_selector=%d TODO!\n", @@ -1580,6 +1677,25 @@ ac_rq_in(struct usb_function *fn, const struct usb_ctrlrequest *cr) return -EOPNOTSUPP; } +static void uac2_cs_control_sam_freq(struct usb_ep *ep, struct usb_request *req) +{ + struct usb_function *fn = ep->driver_data; + struct g_audio *agdev = func_to_g_audio(fn); + struct f_uac2 *uac2 = func_to_uac2(fn); + u32 val; + + if (req->actual != 4) + return; + + val = le32_to_cpu(*((__le32 *)req->buf)); + dev_dbg(&agdev->gadget->dev, "%s val: %d.\n", __func__, val); + if (uac2->clock_id == USB_IN_CLK_ID) { + u_audio_set_playback_srate(agdev, val); + } else if (uac2->clock_id == USB_OUT_CLK_ID) { + u_audio_set_capture_srate(agdev, val); + } +} + static void out_rq_cur_complete(struct usb_ep *ep, struct usb_request *req) { @@ -1631,6 +1747,7 @@ out_rq_cur_complete(struct usb_ep *ep, struct usb_request *req) static int out_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr) { + struct usb_composite_dev *cdev = fn->config->cdev; struct usb_request *req = fn->config->cdev->req; struct g_audio *agdev = func_to_g_audio(fn); struct f_uac2_opts *opts = g_audio_to_uac2_opts(agdev); @@ -1640,10 +1757,17 @@ out_rq_cur(struct usb_function *fn, const struct usb_ctrlrequest *cr) u16 w_value = le16_to_cpu(cr->wValue); u8 entity_id = (w_index >> 8) & 0xff; u8 control_selector = w_value >> 8; + u8 clock_id = w_index >> 8; if ((entity_id == USB_IN_CLK_ID) || (entity_id == USB_OUT_CLK_ID)) { - if (control_selector == UAC2_CS_CONTROL_SAM_FREQ) + if (control_selector == UAC2_CS_CONTROL_SAM_FREQ) { + dev_dbg(&agdev->gadget->dev, + "control_selector UAC2_CS_CONTROL_SAM_FREQ, clock: %d\n", clock_id); + cdev->gadget->ep0->driver_data = fn; + uac2->clock_id = clock_id; + req->complete = uac2_cs_control_sam_freq; return w_length; + } } else if ((FUIN_EN(opts) && (entity_id == USB_IN_FU_ID)) || (FUOUT_EN(opts) && (entity_id == USB_OUT_FU_ID))) { memcpy(&uac2->setup_cr, cr, sizeof(*cr)); @@ -1731,10 +1855,12 @@ static struct configfs_item_operations f_uac2_item_ops = { .release = f_uac2_attr_release, }; +#define uac2_kstrtou8 kstrtou8 #define uac2_kstrtou32 kstrtou32 #define uac2_kstrtos16 kstrtos16 #define uac2_kstrtobool(s, base, res) kstrtobool((s), (res)) +static const char *u8_fmt = "%u\n"; static const char *u32_fmt = "%u\n"; static const char *s16_fmt = "%hd\n"; static const char *bool_fmt = "%u\n"; @@ -1836,13 +1962,110 @@ end: \ \ CONFIGFS_ATTR(f_uac2_opts_, name) +#define UAC2_RATE_ATTRIBUTE(name) \ +static ssize_t f_uac2_opts_##name##_show(struct config_item *item, \ + char *page) \ +{ \ + struct f_uac2_opts *opts = to_f_uac2_opts(item); \ + int result = 0; \ + int i; \ + \ + mutex_lock(&opts->lock); \ + page[0] = '\0'; \ + for (i = 0; i < UAC_MAX_RATES; i++) { \ + if (opts->name##s[i] == 0) \ + break; \ + result += sprintf(page + strlen(page), "%u,", \ + opts->name##s[i]); \ + } \ + if (strlen(page) > 0) \ + page[strlen(page) - 1] = '\n'; \ + mutex_unlock(&opts->lock); \ + \ + return result; \ +} \ + \ +static ssize_t f_uac2_opts_##name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + struct f_uac2_opts *opts = to_f_uac2_opts(item); \ + char *split_page = NULL; \ + int ret = -EINVAL; \ + char *token; \ + u32 num; \ + int i; \ + \ + mutex_lock(&opts->lock); \ + if (opts->refcnt) { \ + ret = -EBUSY; \ + goto end; \ + } \ + \ + i = 0; \ + memset(opts->name##s, 0x00, sizeof(opts->name##s)); \ + split_page = kstrdup(page, GFP_KERNEL); \ + while ((token = strsep(&split_page, ",")) != NULL) { \ + ret = kstrtou32(token, 0, &num); \ + if (ret) \ + goto end; \ + \ + opts->name##s[i++] = num; \ + ret = len; \ + }; \ + \ +end: \ + kfree(split_page); \ + mutex_unlock(&opts->lock); \ + return ret; \ +} \ + \ +CONFIGFS_ATTR(f_uac2_opts_, name) + +#define UAC2_ATTRIBUTE_STRING(name) \ +static ssize_t f_uac2_opts_##name##_show(struct config_item *item, \ + char *page) \ +{ \ + struct f_uac2_opts *opts = to_f_uac2_opts(item); \ + int result; \ + \ + mutex_lock(&opts->lock); \ + result = snprintf(page, sizeof(opts->name), "%s", opts->name); \ + mutex_unlock(&opts->lock); \ + \ + return result; \ +} \ + \ +static ssize_t f_uac2_opts_##name##_store(struct config_item *item, \ + const char *page, size_t len) \ +{ \ + struct f_uac2_opts *opts = to_f_uac2_opts(item); \ + int ret = 0; \ + \ + mutex_lock(&opts->lock); \ + if (opts->refcnt) { \ + ret = -EBUSY; \ + goto end; \ + } \ + \ + ret = snprintf(opts->name, min(sizeof(opts->name), len), \ + "%s", page); \ + \ +end: \ + mutex_unlock(&opts->lock); \ + return ret; \ +} \ + \ +CONFIGFS_ATTR(f_uac2_opts_, name) + UAC2_ATTRIBUTE(u32, p_chmask); -UAC2_ATTRIBUTE(u32, p_srate); +UAC2_RATE_ATTRIBUTE(p_srate); UAC2_ATTRIBUTE(u32, p_ssize); +UAC2_ATTRIBUTE(u8, p_hs_bint); UAC2_ATTRIBUTE(u32, c_chmask); -UAC2_ATTRIBUTE(u32, c_srate); +UAC2_RATE_ATTRIBUTE(c_srate); UAC2_ATTRIBUTE_SYNC(c_sync); UAC2_ATTRIBUTE(u32, c_ssize); +UAC2_ATTRIBUTE(u8, c_hs_bint); UAC2_ATTRIBUTE(u32, req_number); UAC2_ATTRIBUTE(bool, p_mute_present); @@ -1857,14 +2080,17 @@ UAC2_ATTRIBUTE(s16, c_volume_min); UAC2_ATTRIBUTE(s16, c_volume_max); UAC2_ATTRIBUTE(s16, c_volume_res); UAC2_ATTRIBUTE(u32, fb_max); +UAC2_ATTRIBUTE_STRING(function_name); static struct configfs_attribute *f_uac2_attrs[] = { &f_uac2_opts_attr_p_chmask, &f_uac2_opts_attr_p_srate, &f_uac2_opts_attr_p_ssize, + &f_uac2_opts_attr_p_hs_bint, &f_uac2_opts_attr_c_chmask, &f_uac2_opts_attr_c_srate, &f_uac2_opts_attr_c_ssize, + &f_uac2_opts_attr_c_hs_bint, &f_uac2_opts_attr_c_sync, &f_uac2_opts_attr_req_number, &f_uac2_opts_attr_fb_max, @@ -1881,6 +2107,8 @@ static struct configfs_attribute *f_uac2_attrs[] = { &f_uac2_opts_attr_c_volume_max, &f_uac2_opts_attr_c_volume_res, + &f_uac2_opts_attr_function_name, + NULL, }; @@ -1913,11 +2141,13 @@ static struct usb_function_instance *afunc_alloc_inst(void) &f_uac2_func_type); opts->p_chmask = UAC2_DEF_PCHMASK; - opts->p_srate = UAC2_DEF_PSRATE; + opts->p_srates[0] = UAC2_DEF_PSRATE; opts->p_ssize = UAC2_DEF_PSSIZE; + opts->p_hs_bint = UAC2_DEF_PHSBINT; opts->c_chmask = UAC2_DEF_CCHMASK; - opts->c_srate = UAC2_DEF_CSRATE; + opts->c_srates[0] = UAC2_DEF_CSRATE; opts->c_ssize = UAC2_DEF_CSSIZE; + opts->c_hs_bint = UAC2_DEF_CHSBINT; opts->c_sync = UAC2_DEF_CSYNC; opts->p_mute_present = UAC2_DEF_MUTE_PRESENT; @@ -1934,6 +2164,9 @@ static struct usb_function_instance *afunc_alloc_inst(void) opts->req_number = UAC2_DEF_REQ_NUM; opts->fb_max = FBACK_FAST_MAX; + + snprintf(opts->function_name, sizeof(opts->function_name), "Source/Sink"); + return &opts->func_inst; } @@ -1985,6 +2218,7 @@ static struct usb_function *afunc_alloc(struct usb_function_instance *fi) uac2->g_audio.func.set_alt = afunc_set_alt; uac2->g_audio.func.get_alt = afunc_get_alt; uac2->g_audio.func.disable = afunc_disable; + uac2->g_audio.func.suspend = afunc_suspend; uac2->g_audio.func.setup = afunc_setup; uac2->g_audio.func.free_func = afunc_free; diff --git a/drivers/usb/gadget/function/u_audio.c b/drivers/usb/gadget/function/u_audio.c index 4561d7a183ff..2bb569895a90 100644 --- a/drivers/usb/gadget/function/u_audio.c +++ b/drivers/usb/gadget/function/u_audio.c @@ -32,6 +32,7 @@ enum { UAC_P_PITCH_CTRL, UAC_MUTE_CTRL, UAC_VOLUME_CTRL, + UAC_RATE_CTRL, }; /* Runtime data params for one stream */ @@ -62,6 +63,10 @@ struct uac_rtd_params { s16 volume; int mute; + struct snd_kcontrol *snd_kctl_rate; /* read-only current rate */ + int srate; /* selected samplerate */ + int active; /* playback/capture running */ + spinlock_t lock; /* lock for control transfers */ }; @@ -150,8 +155,6 @@ static void u_audio_iso_complete(struct usb_ep *ep, struct usb_request *req) struct snd_pcm_runtime *runtime; struct uac_rtd_params *prm = req->context; struct snd_uac_chip *uac = prm->uac; - struct g_audio *audio_dev = uac->audio_dev; - struct uac_params *params = &audio_dev->params; unsigned int frames, p_pktsize; unsigned long long pitched_rate_mil, p_pktsize_residue_mil, residue_frames_mil, div_result; @@ -196,15 +199,14 @@ static void u_audio_iso_complete(struct usb_ep *ep, struct usb_request *req) */ unsigned long long p_interval_mil = uac->p_interval * 1000000ULL; - pitched_rate_mil = (unsigned long long) - params->p_srate * prm->pitch; + pitched_rate_mil = (unsigned long long) prm->srate * prm->pitch; div_result = pitched_rate_mil; do_div(div_result, uac->p_interval); do_div(div_result, 1000000); frames = (unsigned int) div_result; pr_debug("p_srate %d, pitch %d, interval_mil %llu, frames %d\n", - params->p_srate, prm->pitch, p_interval_mil, frames); + prm->srate, prm->pitch, p_interval_mil, frames); p_pktsize = min_t(unsigned int, uac->p_framesize * frames, @@ -281,7 +283,6 @@ static void u_audio_iso_fback_complete(struct usb_ep *ep, struct uac_rtd_params *prm = req->context; struct snd_uac_chip *uac = prm->uac; struct g_audio *audio_dev = uac->audio_dev; - struct uac_params *params = &audio_dev->params; int status = req->status; /* i/f shutting down */ @@ -303,7 +304,7 @@ static void u_audio_iso_fback_complete(struct usb_ep *ep, __func__, status, req->actual, req->length); u_audio_set_fback_frequency(audio_dev->gadget->speed, audio_dev->out_ep, - params->c_srate, prm->pitch, + prm->srate, prm->pitch, req->buf); if (usb_ep_queue(ep, req, GFP_ATOMIC)) @@ -387,16 +388,14 @@ static int uac_pcm_open(struct snd_pcm_substream *substream) struct snd_pcm_runtime *runtime = substream->runtime; struct g_audio *audio_dev; struct uac_params *params; + struct uac_rtd_params *prm; int p_ssize, c_ssize; - int p_srate, c_srate; int p_chmask, c_chmask; audio_dev = uac->audio_dev; params = &audio_dev->params; p_ssize = params->p_ssize; c_ssize = params->c_ssize; - p_srate = params->p_srate; - c_srate = params->c_srate; p_chmask = params->p_chmask; c_chmask = params->c_chmask; uac->p_residue_mil = 0; @@ -404,19 +403,18 @@ static int uac_pcm_open(struct snd_pcm_substream *substream) runtime->hw = uac_pcm_hardware; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - runtime->hw.rate_min = p_srate; runtime->hw.formats = uac_ssize_to_fmt(p_ssize); runtime->hw.channels_min = num_channels(p_chmask); - runtime->hw.period_bytes_min = 2 * uac->p_prm.max_psize - / runtime->hw.periods_min; + prm = &uac->p_prm; } else { - runtime->hw.rate_min = c_srate; runtime->hw.formats = uac_ssize_to_fmt(c_ssize); runtime->hw.channels_min = num_channels(c_chmask); - runtime->hw.period_bytes_min = 2 * uac->c_prm.max_psize - / runtime->hw.periods_min; + prm = &uac->c_prm; } + runtime->hw.period_bytes_min = 2 * prm->max_psize + / runtime->hw.periods_min; + runtime->hw.rate_min = prm->srate; runtime->hw.rate_max = runtime->hw.rate_min; runtime->hw.channels_max = runtime->hw.channels_min; @@ -493,6 +491,99 @@ static inline void free_ep_fback(struct uac_rtd_params *prm, struct usb_ep *ep) dev_err(uac->card->dev, "%s:%d Error!\n", __func__, __LINE__); } +static void set_active(struct uac_rtd_params *prm, bool active) +{ + // notifying through the Rate ctrl + struct snd_kcontrol *kctl = prm->snd_kctl_rate; + unsigned long flags; + + spin_lock_irqsave(&prm->lock, flags); + if (prm->active != active) { + prm->active = active; + snd_ctl_notify(prm->uac->card, SNDRV_CTL_EVENT_MASK_VALUE, + &kctl->id); + } + spin_unlock_irqrestore(&prm->lock, flags); +} + +int u_audio_set_capture_srate(struct g_audio *audio_dev, int srate) +{ + struct uac_params *params = &audio_dev->params; + struct snd_uac_chip *uac = audio_dev->uac; + struct uac_rtd_params *prm; + int i; + unsigned long flags; + + dev_dbg(&audio_dev->gadget->dev, "%s: srate %d\n", __func__, srate); + prm = &uac->c_prm; + for (i = 0; i < UAC_MAX_RATES; i++) { + if (params->c_srates[i] == srate) { + spin_lock_irqsave(&prm->lock, flags); + prm->srate = srate; + spin_unlock_irqrestore(&prm->lock, flags); + return 0; + } + if (params->c_srates[i] == 0) + break; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(u_audio_set_capture_srate); + +int u_audio_get_capture_srate(struct g_audio *audio_dev, u32 *val) +{ + struct snd_uac_chip *uac = audio_dev->uac; + struct uac_rtd_params *prm; + unsigned long flags; + + prm = &uac->c_prm; + spin_lock_irqsave(&prm->lock, flags); + *val = prm->srate; + spin_unlock_irqrestore(&prm->lock, flags); + return 0; +} +EXPORT_SYMBOL_GPL(u_audio_get_capture_srate); + +int u_audio_set_playback_srate(struct g_audio *audio_dev, int srate) +{ + struct uac_params *params = &audio_dev->params; + struct snd_uac_chip *uac = audio_dev->uac; + struct uac_rtd_params *prm; + int i; + unsigned long flags; + + dev_dbg(&audio_dev->gadget->dev, "%s: srate %d\n", __func__, srate); + prm = &uac->p_prm; + for (i = 0; i < UAC_MAX_RATES; i++) { + if (params->p_srates[i] == srate) { + spin_lock_irqsave(&prm->lock, flags); + prm->srate = srate; + spin_unlock_irqrestore(&prm->lock, flags); + return 0; + } + if (params->p_srates[i] == 0) + break; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(u_audio_set_playback_srate); + +int u_audio_get_playback_srate(struct g_audio *audio_dev, u32 *val) +{ + struct snd_uac_chip *uac = audio_dev->uac; + struct uac_rtd_params *prm; + unsigned long flags; + + prm = &uac->p_prm; + spin_lock_irqsave(&prm->lock, flags); + *val = prm->srate; + spin_unlock_irqrestore(&prm->lock, flags); + return 0; +} +EXPORT_SYMBOL_GPL(u_audio_get_playback_srate); + int u_audio_start_capture(struct g_audio *audio_dev) { struct snd_uac_chip *uac = audio_dev->uac; @@ -504,8 +595,9 @@ int u_audio_start_capture(struct g_audio *audio_dev) struct uac_params *params = &audio_dev->params; int req_len, i; - ep = audio_dev->out_ep; prm = &uac->c_prm; + dev_dbg(dev, "start capture with rate %d\n", prm->srate); + ep = audio_dev->out_ep; config_ep_by_speed(gadget, &audio_dev->func, ep); req_len = ep->maxpacket; @@ -531,6 +623,8 @@ int u_audio_start_capture(struct g_audio *audio_dev) dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); } + set_active(&uac->c_prm, true); + ep_fback = audio_dev->in_ep_fback; if (!ep_fback) return 0; @@ -562,7 +656,7 @@ int u_audio_start_capture(struct g_audio *audio_dev) */ prm->pitch = 1000000; u_audio_set_fback_frequency(audio_dev->gadget->speed, ep, - params->c_srate, prm->pitch, + prm->srate, prm->pitch, req_fback->buf); if (usb_ep_queue(ep_fback, req_fback, GFP_ATOMIC)) @@ -576,6 +670,7 @@ void u_audio_stop_capture(struct g_audio *audio_dev) { struct snd_uac_chip *uac = audio_dev->uac; + set_active(&uac->c_prm, false); if (audio_dev->in_ep_fback) free_ep_fback(&uac->c_prm, audio_dev->in_ep_fback); free_ep(&uac->c_prm, audio_dev->out_ep); @@ -596,8 +691,9 @@ int u_audio_start_playback(struct g_audio *audio_dev) int req_len, i; unsigned int p_pktsize; - ep = audio_dev->in_ep; prm = &uac->p_prm; + dev_dbg(dev, "start playback with rate %d\n", prm->srate); + ep = audio_dev->in_ep; config_ep_by_speed(gadget, &audio_dev->func, ep); ep_desc = ep->desc; @@ -618,7 +714,7 @@ int u_audio_start_playback(struct g_audio *audio_dev) uac->p_interval = factor / (1 << (ep_desc->bInterval - 1)); p_pktsize = min_t(unsigned int, uac->p_framesize * - (params->p_srate / uac->p_interval), + (prm->srate / uac->p_interval), ep->maxpacket); req_len = p_pktsize; @@ -646,6 +742,8 @@ int u_audio_start_playback(struct g_audio *audio_dev) dev_err(dev, "%s:%d Error!\n", __func__, __LINE__); } + set_active(&uac->p_prm, true); + return 0; } EXPORT_SYMBOL_GPL(u_audio_start_playback); @@ -654,10 +752,20 @@ void u_audio_stop_playback(struct g_audio *audio_dev) { struct snd_uac_chip *uac = audio_dev->uac; + set_active(&uac->p_prm, false); free_ep(&uac->p_prm, audio_dev->in_ep); } EXPORT_SYMBOL_GPL(u_audio_stop_playback); +void u_audio_suspend(struct g_audio *audio_dev) +{ + struct snd_uac_chip *uac = audio_dev->uac; + + set_active(&uac->p_prm, false); + set_active(&uac->c_prm, false); +} +EXPORT_SYMBOL_GPL(u_audio_suspend); + int u_audio_get_volume(struct g_audio *audio_dev, int playback, s16 *val) { struct snd_uac_chip *uac = audio_dev->uac; @@ -943,6 +1051,68 @@ static int u_audio_volume_put(struct snd_kcontrol *kcontrol, return change; } +static int get_max_srate(const int *srates) +{ + int i, max_srate = 0; + + for (i = 0; i < UAC_MAX_RATES; i++) { + if (srates[i] == 0) + break; + if (srates[i] > max_srate) + max_srate = srates[i]; + } + return max_srate; +} + +static int get_min_srate(const int *srates) +{ + int i, min_srate = INT_MAX; + + for (i = 0; i < UAC_MAX_RATES; i++) { + if (srates[i] == 0) + break; + if (srates[i] < min_srate) + min_srate = srates[i]; + } + return min_srate; +} + +static int u_audio_rate_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + const int *srates; + struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol); + struct snd_uac_chip *uac = prm->uac; + struct g_audio *audio_dev = uac->audio_dev; + struct uac_params *params = &audio_dev->params; + + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + + if (prm == &uac->c_prm) + srates = params->c_srates; + else + srates = params->p_srates; + uinfo->value.integer.min = get_min_srate(srates); + uinfo->value.integer.max = get_max_srate(srates); + return 0; +} + +static int u_audio_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct uac_rtd_params *prm = snd_kcontrol_chip(kcontrol); + unsigned long flags; + + spin_lock_irqsave(&prm->lock, flags); + if (prm->active) + ucontrol->value.integer.value[0] = prm->srate; + else + /* not active: reporting zero rate */ + ucontrol->value.integer.value[0] = 0; + spin_unlock_irqrestore(&prm->lock, flags); + return 0; +} static struct snd_kcontrol_new u_audio_controls[] = { [UAC_FBACK_CTRL] { @@ -973,6 +1143,13 @@ static struct snd_kcontrol_new u_audio_controls[] = { .get = u_audio_volume_get, .put = u_audio_volume_put, }, + [UAC_RATE_CTRL] { + .iface = SNDRV_CTL_ELEM_IFACE_PCM, + .name = "", /* will be filled later */ + .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, + .info = u_audio_rate_info, + .get = u_audio_rate_get, + }, }; int g_audio_setup(struct g_audio *g_audio, const char *pcm_name, @@ -1005,6 +1182,7 @@ int g_audio_setup(struct g_audio *g_audio, const char *pcm_name, spin_lock_init(&prm->lock); uac->c_prm.uac = uac; prm->max_psize = g_audio->out_ep_maxpsize; + prm->srate = params->c_srates[0]; prm->reqs = kcalloc(params->req_number, sizeof(struct usb_request *), @@ -1029,6 +1207,7 @@ int g_audio_setup(struct g_audio *g_audio, const char *pcm_name, spin_lock_init(&prm->lock); uac->p_prm.uac = uac; prm->max_psize = g_audio->in_ep_maxpsize; + prm->srate = params->p_srates[0]; prm->reqs = kcalloc(params->req_number, sizeof(struct usb_request *), @@ -1186,6 +1365,25 @@ int g_audio_setup(struct g_audio *g_audio, const char *pcm_name, prm->volume_min = fu->volume_min; prm->volume_res = fu->volume_res; } + + /* Add rate control */ + snprintf(ctrl_name, sizeof(ctrl_name), + "%s Rate", direction); + u_audio_controls[UAC_RATE_CTRL].name = ctrl_name; + + kctl = snd_ctl_new1(&u_audio_controls[UAC_RATE_CTRL], prm); + if (!kctl) { + err = -ENOMEM; + goto snd_fail; + } + + kctl->id.device = pcm->device; + kctl->id.subdevice = 0; + + err = snd_ctl_add(card, kctl); + if (err < 0) + goto snd_fail; + prm->snd_kctl_rate = kctl; } strscpy(card->driver, card_name, sizeof(card->driver)); diff --git a/drivers/usb/gadget/function/u_audio.h b/drivers/usb/gadget/function/u_audio.h index 8dfdae1721cd..9512b8fccfaa 100644 --- a/drivers/usb/gadget/function/u_audio.h +++ b/drivers/usb/gadget/function/u_audio.h @@ -10,6 +10,7 @@ #define __U_AUDIO_H #include +#include "uac_common.h" /* * Same maximum frequency deviation on the slower side as in @@ -40,16 +41,18 @@ struct uac_fu_params { struct uac_params { /* playback */ int p_chmask; /* channel mask */ - int p_srate; /* rate in Hz */ + int p_srates[UAC_MAX_RATES]; /* available rates in Hz (0 terminated list) */ int p_ssize; /* sample size */ struct uac_fu_params p_fu; /* Feature Unit parameters */ /* capture */ int c_chmask; /* channel mask */ - int c_srate; /* rate in Hz */ + int c_srates[UAC_MAX_RATES]; /* available rates in Hz (0 terminated list) */ int c_ssize; /* sample size */ struct uac_fu_params c_fu; /* Feature Unit parameters */ + /* rates are dynamic, in uac_rtd_params */ + int req_number; /* number of preallocated requests */ int fb_max; /* upper frequency drift feedback limit per-mil */ }; @@ -117,9 +120,16 @@ void u_audio_stop_capture(struct g_audio *g_audio); int u_audio_start_playback(struct g_audio *g_audio); void u_audio_stop_playback(struct g_audio *g_audio); +int u_audio_get_capture_srate(struct g_audio *audio_dev, u32 *val); +int u_audio_set_capture_srate(struct g_audio *audio_dev, int srate); +int u_audio_get_playback_srate(struct g_audio *audio_dev, u32 *val); +int u_audio_set_playback_srate(struct g_audio *audio_dev, int srate); + int u_audio_get_volume(struct g_audio *g_audio, int playback, s16 *val); int u_audio_set_volume(struct g_audio *g_audio, int playback, s16 val); int u_audio_get_mute(struct g_audio *g_audio, int playback, int *val); int u_audio_set_mute(struct g_audio *g_audio, int playback, int val); +void u_audio_suspend(struct g_audio *g_audio); + #endif /* __U_AUDIO_H */ diff --git a/drivers/usb/gadget/function/u_uac1.h b/drivers/usb/gadget/function/u_uac1.h index 589fae861141..f7a616760e31 100644 --- a/drivers/usb/gadget/function/u_uac1.h +++ b/drivers/usb/gadget/function/u_uac1.h @@ -9,6 +9,7 @@ #define __U_UAC1_H #include +#include "uac_common.h" #define UAC1_OUT_EP_MAX_PACKET_SIZE 200 #define UAC1_DEF_CCHMASK 0x3 @@ -30,10 +31,10 @@ struct f_uac1_opts { struct usb_function_instance func_inst; int c_chmask; - int c_srate; + int c_srates[UAC_MAX_RATES]; int c_ssize; int p_chmask; - int p_srate; + int p_srates[UAC_MAX_RATES]; int p_ssize; bool p_mute_present; @@ -51,6 +52,8 @@ struct f_uac1_opts { int req_number; unsigned bound:1; + char function_name[32]; + struct mutex lock; int refcnt; }; diff --git a/drivers/usb/gadget/function/u_uac2.h b/drivers/usb/gadget/function/u_uac2.h index e0c8e3513bfd..0510c9bad58d 100644 --- a/drivers/usb/gadget/function/u_uac2.h +++ b/drivers/usb/gadget/function/u_uac2.h @@ -14,13 +14,16 @@ #define U_UAC2_H #include +#include "uac_common.h" #define UAC2_DEF_PCHMASK 0x3 #define UAC2_DEF_PSRATE 48000 #define UAC2_DEF_PSSIZE 2 +#define UAC2_DEF_PHSBINT 0 #define UAC2_DEF_CCHMASK 0x3 #define UAC2_DEF_CSRATE 64000 #define UAC2_DEF_CSSIZE 2 +#define UAC2_DEF_CHSBINT 0 #define UAC2_DEF_CSYNC USB_ENDPOINT_SYNC_ASYNC #define UAC2_DEF_MUTE_PRESENT 1 @@ -35,12 +38,14 @@ struct f_uac2_opts { struct usb_function_instance func_inst; int p_chmask; - int p_srate; + int p_srates[UAC_MAX_RATES]; int p_ssize; + u8 p_hs_bint; int c_chmask; - int c_srate; + int c_srates[UAC_MAX_RATES]; int c_ssize; int c_sync; + u8 c_hs_bint; bool p_mute_present; bool p_volume_present; @@ -58,6 +63,8 @@ struct f_uac2_opts { int fb_max; bool bound; + char function_name[32]; + struct mutex lock; int refcnt; }; diff --git a/drivers/usb/gadget/function/uac_common.h b/drivers/usb/gadget/function/uac_common.h new file mode 100644 index 000000000000..3ecf89d6e814 --- /dev/null +++ b/drivers/usb/gadget/function/uac_common.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + */ + +#ifndef UAC_COMMON_H +#define UAC_COMMON_H + +#define UAC_MAX_RATES 10 /* maximum number of rates configurable by f_uac1/2 */ +#endif diff --git a/drivers/usb/gadget/legacy/audio.c b/drivers/usb/gadget/legacy/audio.c index a748ed0842e8..76ea6decf7b6 100644 --- a/drivers/usb/gadget/legacy/audio.c +++ b/drivers/usb/gadget/legacy/audio.c @@ -22,91 +22,108 @@ USB_GADGET_COMPOSITE_OPTIONS(); /* Playback(USB-IN) Default Stereo - Fl/Fr */ static int p_chmask = UAC2_DEF_PCHMASK; -module_param(p_chmask, uint, S_IRUGO); +module_param(p_chmask, uint, 0444); MODULE_PARM_DESC(p_chmask, "Playback Channel Mask"); /* Playback Default 48 KHz */ -static int p_srate = UAC2_DEF_PSRATE; -module_param(p_srate, uint, S_IRUGO); -MODULE_PARM_DESC(p_srate, "Playback Sampling Rate"); +static int p_srates[UAC_MAX_RATES] = {UAC2_DEF_PSRATE}; +static int p_srates_cnt = 1; +module_param_array_named(p_srate, p_srates, uint, &p_srates_cnt, 0444); +MODULE_PARM_DESC(p_srate, "Playback Sampling Rates (array)"); /* Playback Default 16bits/sample */ static int p_ssize = UAC2_DEF_PSSIZE; -module_param(p_ssize, uint, S_IRUGO); +module_param(p_ssize, uint, 0444); MODULE_PARM_DESC(p_ssize, "Playback Sample Size(bytes)"); +/* Playback bInterval for HS/SS (1-4: fixed, 0: auto) */ +static u8 p_hs_bint = UAC2_DEF_PHSBINT; +module_param(p_hs_bint, byte, 0444); +MODULE_PARM_DESC(p_hs_bint, + "Playback bInterval for HS/SS (1-4: fixed, 0: auto)"); + /* Capture(USB-OUT) Default Stereo - Fl/Fr */ static int c_chmask = UAC2_DEF_CCHMASK; -module_param(c_chmask, uint, S_IRUGO); +module_param(c_chmask, uint, 0444); MODULE_PARM_DESC(c_chmask, "Capture Channel Mask"); /* Capture Default 64 KHz */ -static int c_srate = UAC2_DEF_CSRATE; -module_param(c_srate, uint, S_IRUGO); -MODULE_PARM_DESC(c_srate, "Capture Sampling Rate"); +static int c_srates[UAC_MAX_RATES] = {UAC2_DEF_CSRATE}; +static int c_srates_cnt = 1; +module_param_array_named(c_srate, c_srates, uint, &c_srates_cnt, 0444); +MODULE_PARM_DESC(c_srate, "Capture Sampling Rates (array)"); /* Capture Default 16bits/sample */ static int c_ssize = UAC2_DEF_CSSIZE; -module_param(c_ssize, uint, S_IRUGO); +module_param(c_ssize, uint, 0444); MODULE_PARM_DESC(c_ssize, "Capture Sample Size(bytes)"); + +/* capture bInterval for HS/SS (1-4: fixed, 0: auto) */ +static u8 c_hs_bint = UAC2_DEF_CHSBINT; +module_param(c_hs_bint, byte, 0444); +MODULE_PARM_DESC(c_hs_bint, + "Capture bInterval for HS/SS (1-4: fixed, 0: auto)"); + #else #ifndef CONFIG_GADGET_UAC1_LEGACY #include "u_uac1.h" /* Playback(USB-IN) Default Stereo - Fl/Fr */ static int p_chmask = UAC1_DEF_PCHMASK; -module_param(p_chmask, uint, S_IRUGO); +module_param(p_chmask, uint, 0444); MODULE_PARM_DESC(p_chmask, "Playback Channel Mask"); /* Playback Default 48 KHz */ -static int p_srate = UAC1_DEF_PSRATE; -module_param(p_srate, uint, S_IRUGO); -MODULE_PARM_DESC(p_srate, "Playback Sampling Rate"); +static int p_srates[UAC_MAX_RATES] = {UAC1_DEF_PSRATE}; +static int p_srates_cnt = 1; +module_param_array_named(p_srate, p_srates, uint, &p_srates_cnt, 0444); +MODULE_PARM_DESC(p_srate, "Playback Sampling Rates (array)"); /* Playback Default 16bits/sample */ static int p_ssize = UAC1_DEF_PSSIZE; -module_param(p_ssize, uint, S_IRUGO); +module_param(p_ssize, uint, 0444); MODULE_PARM_DESC(p_ssize, "Playback Sample Size(bytes)"); /* Capture(USB-OUT) Default Stereo - Fl/Fr */ static int c_chmask = UAC1_DEF_CCHMASK; -module_param(c_chmask, uint, S_IRUGO); +module_param(c_chmask, uint, 0444); MODULE_PARM_DESC(c_chmask, "Capture Channel Mask"); /* Capture Default 48 KHz */ -static int c_srate = UAC1_DEF_CSRATE; -module_param(c_srate, uint, S_IRUGO); -MODULE_PARM_DESC(c_srate, "Capture Sampling Rate"); +static int c_srates[UAC_MAX_RATES] = {UAC1_DEF_CSRATE}; +static int c_srates_cnt = 1; +module_param_array_named(c_srate, c_srates, uint, &c_srates_cnt, 0444); +MODULE_PARM_DESC(c_srate, "Capture Sampling Rates (array)"); /* Capture Default 16bits/sample */ static int c_ssize = UAC1_DEF_CSSIZE; -module_param(c_ssize, uint, S_IRUGO); +module_param(c_ssize, uint, 0444); MODULE_PARM_DESC(c_ssize, "Capture Sample Size(bytes)"); #else /* CONFIG_GADGET_UAC1_LEGACY */ #include "u_uac1_legacy.h" static char *fn_play = FILE_PCM_PLAYBACK; -module_param(fn_play, charp, S_IRUGO); +module_param(fn_play, charp, 0444); MODULE_PARM_DESC(fn_play, "Playback PCM device file name"); static char *fn_cap = FILE_PCM_CAPTURE; -module_param(fn_cap, charp, S_IRUGO); +module_param(fn_cap, charp, 0444); MODULE_PARM_DESC(fn_cap, "Capture PCM device file name"); static char *fn_cntl = FILE_CONTROL; -module_param(fn_cntl, charp, S_IRUGO); +module_param(fn_cntl, charp, 0444); MODULE_PARM_DESC(fn_cntl, "Control device file name"); static int req_buf_size = UAC1_OUT_EP_MAX_PACKET_SIZE; -module_param(req_buf_size, int, S_IRUGO); +module_param(req_buf_size, int, 0444); MODULE_PARM_DESC(req_buf_size, "ISO OUT endpoint request buffer size"); static int req_count = UAC1_REQ_COUNT; -module_param(req_count, int, S_IRUGO); +module_param(req_count, int, 0444); MODULE_PARM_DESC(req_count, "ISO OUT endpoint request count"); static int audio_buf_size = UAC1_AUDIO_BUF_SIZE; -module_param(audio_buf_size, int, S_IRUGO); +module_param(audio_buf_size, int, 0444); MODULE_PARM_DESC(audio_buf_size, "Audio buffer size"); #endif /* CONFIG_GADGET_UAC1_LEGACY */ #endif @@ -237,9 +254,11 @@ static int audio_bind(struct usb_composite_dev *cdev) { #ifndef CONFIG_GADGET_UAC1 struct f_uac2_opts *uac2_opts; + int i; #else #ifndef CONFIG_GADGET_UAC1_LEGACY struct f_uac1_opts *uac1_opts; + int i; #else struct f_uac1_legacy_opts *uac1_opts; #endif @@ -263,20 +282,34 @@ static int audio_bind(struct usb_composite_dev *cdev) #ifndef CONFIG_GADGET_UAC1 uac2_opts = container_of(fi_uac2, struct f_uac2_opts, func_inst); uac2_opts->p_chmask = p_chmask; - uac2_opts->p_srate = p_srate; + + for (i = 0; i < p_srates_cnt; ++i) + uac2_opts->p_srates[i] = p_srates[i]; + uac2_opts->p_ssize = p_ssize; + uac2_opts->p_hs_bint = p_hs_bint; uac2_opts->c_chmask = c_chmask; - uac2_opts->c_srate = c_srate; + + for (i = 0; i < c_srates_cnt; ++i) + uac2_opts->c_srates[i] = c_srates[i]; + uac2_opts->c_ssize = c_ssize; + uac2_opts->c_hs_bint = c_hs_bint; uac2_opts->req_number = UAC2_DEF_REQ_NUM; #else #ifndef CONFIG_GADGET_UAC1_LEGACY uac1_opts = container_of(fi_uac1, struct f_uac1_opts, func_inst); uac1_opts->p_chmask = p_chmask; - uac1_opts->p_srate = p_srate; + + for (i = 0; i < p_srates_cnt; ++i) + uac1_opts->p_srates[i] = p_srates[i]; + uac1_opts->p_ssize = p_ssize; uac1_opts->c_chmask = c_chmask; - uac1_opts->c_srate = c_srate; + + for (i = 0; i < c_srates_cnt; ++i) + uac1_opts->c_srates[i] = c_srates[i]; + uac1_opts->c_ssize = c_ssize; uac1_opts->req_number = UAC1_DEF_REQ_NUM; #else /* CONFIG_GADGET_UAC1_LEGACY */ diff --git a/drivers/usb/gadget/legacy/hid.c b/drivers/usb/gadget/legacy/hid.c index 3912cc805f3a..1187ee4f316a 100644 --- a/drivers/usb/gadget/legacy/hid.c +++ b/drivers/usb/gadget/legacy/hid.c @@ -134,7 +134,7 @@ static int hid_bind(struct usb_composite_dev *cdev) { struct usb_gadget *gadget = cdev->gadget; struct list_head *tmp; - struct hidg_func_node *n, *m; + struct hidg_func_node *n = NULL, *m, *iter_n; struct f_hid_opts *hid_opts; int status, funcs = 0; @@ -144,18 +144,19 @@ static int hid_bind(struct usb_composite_dev *cdev) if (!funcs) return -ENODEV; - list_for_each_entry(n, &hidg_func_list, node) { - n->fi = usb_get_function_instance("hid"); - if (IS_ERR(n->fi)) { - status = PTR_ERR(n->fi); + list_for_each_entry(iter_n, &hidg_func_list, node) { + iter_n->fi = usb_get_function_instance("hid"); + if (IS_ERR(iter_n->fi)) { + status = PTR_ERR(iter_n->fi); + n = iter_n; goto put; } - hid_opts = container_of(n->fi, struct f_hid_opts, func_inst); - hid_opts->subclass = n->func->subclass; - hid_opts->protocol = n->func->protocol; - hid_opts->report_length = n->func->report_length; - hid_opts->report_desc_length = n->func->report_desc_length; - hid_opts->report_desc = n->func->report_desc; + hid_opts = container_of(iter_n->fi, struct f_hid_opts, func_inst); + hid_opts->subclass = iter_n->func->subclass; + hid_opts->protocol = iter_n->func->protocol; + hid_opts->report_length = iter_n->func->report_length; + hid_opts->report_desc_length = iter_n->func->report_desc_length; + hid_opts->report_desc = iter_n->func->report_desc; } diff --git a/drivers/usb/gadget/legacy/inode.c b/drivers/usb/gadget/legacy/inode.c index 51f9d96827b1..0c01e749f9ea 100644 --- a/drivers/usb/gadget/legacy/inode.c +++ b/drivers/usb/gadget/legacy/inode.c @@ -2101,7 +2101,7 @@ MODULE_ALIAS_FS("gadgetfs"); /*----------------------------------------------------------------------*/ -static int __init init (void) +static int __init gadgetfs_init (void) { int status; @@ -2111,12 +2111,12 @@ static int __init init (void) shortname, driver_desc); return status; } -module_init (init); +module_init (gadgetfs_init); -static void __exit cleanup (void) +static void __exit gadgetfs_cleanup (void) { pr_debug ("unregister %s\n", shortname); unregister_filesystem (&gadgetfs_type); } -module_exit (cleanup); +module_exit (gadgetfs_cleanup); diff --git a/drivers/usb/gadget/legacy/raw_gadget.c b/drivers/usb/gadget/legacy/raw_gadget.c index d86c3a36441e..8d40a1f2ec57 100644 --- a/drivers/usb/gadget/legacy/raw_gadget.c +++ b/drivers/usb/gadget/legacy/raw_gadget.c @@ -758,6 +758,7 @@ static int raw_ioctl_ep_enable(struct raw_dev *dev, unsigned long value) unsigned long flags; struct usb_endpoint_descriptor *desc; struct raw_ep *ep; + bool ep_props_matched = false; desc = memdup_user((void __user *)value, sizeof(*desc)); if (IS_ERR(desc)) @@ -787,13 +788,14 @@ static int raw_ioctl_ep_enable(struct raw_dev *dev, unsigned long value) for (i = 0; i < dev->eps_num; i++) { ep = &dev->eps[i]; - if (ep->state != STATE_EP_DISABLED) - continue; if (ep->addr != usb_endpoint_num(desc) && ep->addr != USB_RAW_EP_ADDR_ANY) continue; if (!usb_gadget_ep_match_desc(dev->gadget, ep->ep, desc, NULL)) continue; + ep_props_matched = true; + if (ep->state != STATE_EP_DISABLED) + continue; ep->ep->desc = desc; ret = usb_ep_enable(ep->ep); if (ret < 0) { @@ -815,8 +817,13 @@ static int raw_ioctl_ep_enable(struct raw_dev *dev, unsigned long value) goto out_unlock; } - dev_dbg(&dev->gadget->dev, "fail, no gadget endpoints available\n"); - ret = -EBUSY; + if (!ep_props_matched) { + dev_dbg(&dev->gadget->dev, "fail, bad endpoint descriptor\n"); + ret = -EINVAL; + } else { + dev_dbg(&dev->gadget->dev, "fail, no endpoints available\n"); + ret = -EBUSY; + } out_free: kfree(desc); @@ -1157,7 +1164,7 @@ static int raw_ioctl_eps_info(struct raw_dev *dev, unsigned long value) struct usb_raw_eps_info *info; struct raw_ep *ep; - info = kmalloc(sizeof(*info), GFP_KERNEL); + info = kzalloc(sizeof(*info), GFP_KERNEL); if (!info) { ret = -ENOMEM; goto out; @@ -1177,7 +1184,6 @@ static int raw_ioctl_eps_info(struct raw_dev *dev, unsigned long value) goto out_free; } - memset(info, 0, sizeof(*info)); for (i = 0; i < dev->eps_num; i++) { ep = &dev->eps[i]; strscpy(&info->eps[i].name[0], ep->ep->name, diff --git a/drivers/usb/gadget/legacy/serial.c b/drivers/usb/gadget/legacy/serial.c index da44f89f5e73..dcd3a6603d90 100644 --- a/drivers/usb/gadget/legacy/serial.c +++ b/drivers/usb/gadget/legacy/serial.c @@ -273,7 +273,7 @@ static struct usb_composite_driver gserial_driver = { static int switch_gserial_enable(bool do_enable) { if (!serial_config_driver.label) - /* init() was not called, yet */ + /* gserial_init() was not called, yet */ return 0; if (do_enable) @@ -283,7 +283,7 @@ static int switch_gserial_enable(bool do_enable) return 0; } -static int __init init(void) +static int __init gserial_init(void) { /* We *could* export two configs; that'd be much cleaner... * but neither of these product IDs was defined that way. @@ -314,11 +314,11 @@ static int __init init(void) return usb_composite_probe(&gserial_driver); } -module_init(init); +module_init(gserial_init); -static void __exit cleanup(void) +static void __exit gserial_cleanup(void) { if (enable) usb_composite_unregister(&gserial_driver); } -module_exit(cleanup); +module_exit(gserial_cleanup); diff --git a/drivers/usb/gadget/udc/aspeed-vhub/epn.c b/drivers/usb/gadget/udc/aspeed-vhub/epn.c index 917892ca8753..b5252880b389 100644 --- a/drivers/usb/gadget/udc/aspeed-vhub/epn.c +++ b/drivers/usb/gadget/udc/aspeed-vhub/epn.c @@ -466,19 +466,21 @@ static int ast_vhub_epn_dequeue(struct usb_ep* u_ep, struct usb_request *u_req) { struct ast_vhub_ep *ep = to_ast_ep(u_ep); struct ast_vhub *vhub = ep->vhub; - struct ast_vhub_req *req; + struct ast_vhub_req *req = NULL, *iter; unsigned long flags; int rc = -EINVAL; spin_lock_irqsave(&vhub->lock, flags); /* Make sure it's actually queued on this endpoint */ - list_for_each_entry (req, &ep->queue, queue) { - if (&req->req == u_req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != u_req) + continue; + req = iter; + break; } - if (&req->req == u_req) { + if (req) { EPVDBG(ep, "dequeue req @%p active=%d\n", req, req->active); if (req->active) diff --git a/drivers/usb/gadget/udc/at91_udc.c b/drivers/usb/gadget/udc/at91_udc.c index 9040a0561466..728987280373 100644 --- a/drivers/usb/gadget/udc/at91_udc.c +++ b/drivers/usb/gadget/udc/at91_udc.c @@ -704,7 +704,7 @@ done: static int at91_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct at91_ep *ep; - struct at91_request *req; + struct at91_request *req = NULL, *iter; unsigned long flags; struct at91_udc *udc; @@ -717,11 +717,13 @@ static int at91_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&udc->lock, flags); /* make sure it's actually queued on this endpoint */ - list_for_each_entry (req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { spin_unlock_irqrestore(&udc->lock, flags); return -EINVAL; } diff --git a/drivers/usb/gadget/udc/atmel_usba_udc.c b/drivers/usb/gadget/udc/atmel_usba_udc.c index 2b893bceea45..ae2bfbac603e 100644 --- a/drivers/usb/gadget/udc/atmel_usba_udc.c +++ b/drivers/usb/gadget/udc/atmel_usba_udc.c @@ -860,7 +860,8 @@ static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct usba_ep *ep = to_usba_ep(_ep); struct usba_udc *udc = ep->udc; - struct usba_request *req; + struct usba_request *req = NULL; + struct usba_request *iter; unsigned long flags; u32 status; @@ -869,12 +870,14 @@ static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&udc->lock, flags); - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { spin_unlock_irqrestore(&udc->lock, flags); return -EINVAL; } diff --git a/drivers/usb/gadget/udc/bdc/bdc_ep.c b/drivers/usb/gadget/udc/bdc/bdc_ep.c index 8e2f20b12519..fa88f210ecd5 100644 --- a/drivers/usb/gadget/udc/bdc/bdc_ep.c +++ b/drivers/usb/gadget/udc/bdc/bdc_ep.c @@ -1757,6 +1757,7 @@ static int bdc_gadget_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct bdc_req *req; + struct bdc_req *iter; unsigned long flags; struct bdc_ep *ep; struct bdc *bdc; @@ -1771,12 +1772,16 @@ static int bdc_gadget_ep_dequeue(struct usb_ep *_ep, dev_dbg(bdc->dev, "%s ep:%s req:%p\n", __func__, ep->name, req); bdc_dbg_bd_list(bdc, ep); spin_lock_irqsave(&bdc->lock, flags); + + req = NULL; /* make sure it's still queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->usb_req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->usb_req != _req) + continue; + req = iter; + break; } - if (&req->usb_req != _req) { + if (!req) { spin_unlock_irqrestore(&bdc->lock, flags); dev_err(bdc->dev, "usb_req !=req n"); return -EINVAL; diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c index c109b069f511..85b194011a16 100644 --- a/drivers/usb/gadget/udc/core.c +++ b/drivers/usb/gadget/udc/core.c @@ -1525,7 +1525,7 @@ err1: int usb_gadget_probe_driver(struct usb_gadget_driver *driver) { - struct usb_udc *udc = NULL; + struct usb_udc *udc = NULL, *iter; int ret = -ENODEV; if (!driver || !driver->bind || !driver->setup) @@ -1533,10 +1533,12 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver) mutex_lock(&udc_lock); if (driver->udc_name) { - list_for_each_entry(udc, &udc_list, list) { - ret = strcmp(driver->udc_name, dev_name(&udc->dev)); - if (!ret) - break; + list_for_each_entry(iter, &udc_list, list) { + ret = strcmp(driver->udc_name, dev_name(&iter->dev)); + if (ret) + continue; + udc = iter; + break; } if (ret) ret = -ENODEV; @@ -1545,10 +1547,12 @@ int usb_gadget_probe_driver(struct usb_gadget_driver *driver) else goto found; } else { - list_for_each_entry(udc, &udc_list, list) { + list_for_each_entry(iter, &udc_list, list) { /* For now we take the first one */ - if (!udc->driver) - goto found; + if (iter->driver) + continue; + udc = iter; + goto found; } } diff --git a/drivers/usb/gadget/udc/dummy_hcd.c b/drivers/usb/gadget/udc/dummy_hcd.c index a2d956af42a2..899ac9f9c279 100644 --- a/drivers/usb/gadget/udc/dummy_hcd.c +++ b/drivers/usb/gadget/udc/dummy_hcd.c @@ -751,7 +751,7 @@ static int dummy_dequeue(struct usb_ep *_ep, struct usb_request *_req) struct dummy *dum; int retval = -EINVAL; unsigned long flags; - struct dummy_request *req = NULL; + struct dummy_request *req = NULL, *iter; if (!_ep || !_req) return retval; @@ -763,13 +763,14 @@ static int dummy_dequeue(struct usb_ep *_ep, struct usb_request *_req) local_irq_save(flags); spin_lock(&dum->lock); - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) { - list_del_init(&req->queue); - _req->status = -ECONNRESET; - retval = 0; - break; - } + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + list_del_init(&iter->queue); + _req->status = -ECONNRESET; + req = iter; + retval = 0; + break; } spin_unlock(&dum->lock); @@ -2765,7 +2766,7 @@ static struct platform_driver dummy_hcd_driver = { static struct platform_device *the_udc_pdev[MAX_NUM_UDC]; static struct platform_device *the_hcd_pdev[MAX_NUM_UDC]; -static int __init init(void) +static int __init dummy_hcd_init(void) { int retval = -ENOMEM; int i; @@ -2887,9 +2888,9 @@ err_alloc_udc: platform_device_put(the_hcd_pdev[i]); return retval; } -module_init(init); +module_init(dummy_hcd_init); -static void __exit cleanup(void) +static void __exit dummy_hcd_cleanup(void) { int i; @@ -2905,4 +2906,4 @@ static void __exit cleanup(void) platform_driver_unregister(&dummy_udc_driver); platform_driver_unregister(&dummy_hcd_driver); } -module_exit(cleanup); +module_exit(dummy_hcd_cleanup); diff --git a/drivers/usb/gadget/udc/fsl_qe_udc.c b/drivers/usb/gadget/udc/fsl_qe_udc.c index 15db7a3868fe..bf745358e28e 100644 --- a/drivers/usb/gadget/udc/fsl_qe_udc.c +++ b/drivers/usb/gadget/udc/fsl_qe_udc.c @@ -1776,7 +1776,8 @@ static int qe_ep_queue(struct usb_ep *_ep, struct usb_request *_req, static int qe_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct qe_ep *ep = container_of(_ep, struct qe_ep, ep); - struct qe_req *req; + struct qe_req *req = NULL; + struct qe_req *iter; unsigned long flags; if (!_ep || !_req) @@ -1785,12 +1786,14 @@ static int qe_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&ep->udc->lock, flags); /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { spin_unlock_irqrestore(&ep->udc->lock, flags); return -EINVAL; } diff --git a/drivers/usb/gadget/udc/fsl_udc_core.c b/drivers/usb/gadget/udc/fsl_udc_core.c index 29fcb9b461d7..50435e804118 100644 --- a/drivers/usb/gadget/udc/fsl_udc_core.c +++ b/drivers/usb/gadget/udc/fsl_udc_core.c @@ -918,7 +918,8 @@ fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep); - struct fsl_req *req; + struct fsl_req *req = NULL; + struct fsl_req *iter; unsigned long flags; int ep_num, stopped, ret = 0; u32 epctrl; @@ -940,11 +941,13 @@ static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]); /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { ret = -EINVAL; goto out; } diff --git a/drivers/usb/gadget/udc/goku_udc.c b/drivers/usb/gadget/udc/goku_udc.c index 3757a772a55e..bdc56b24b5c9 100644 --- a/drivers/usb/gadget/udc/goku_udc.c +++ b/drivers/usb/gadget/udc/goku_udc.c @@ -809,7 +809,7 @@ static void nuke(struct goku_ep *ep, int status) /* dequeue JUST ONE request */ static int goku_dequeue(struct usb_ep *_ep, struct usb_request *_req) { - struct goku_request *req; + struct goku_request *req = NULL, *iter; struct goku_ep *ep; struct goku_udc *dev; unsigned long flags; @@ -833,11 +833,13 @@ static int goku_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&dev->lock, flags); /* make sure it's actually queued on this endpoint */ - list_for_each_entry (req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { spin_unlock_irqrestore (&dev->lock, flags); return -EINVAL; } diff --git a/drivers/usb/gadget/udc/gr_udc.c b/drivers/usb/gadget/udc/gr_udc.c index 4b35739d3695..22096f8505de 100644 --- a/drivers/usb/gadget/udc/gr_udc.c +++ b/drivers/usb/gadget/udc/gr_udc.c @@ -1690,7 +1690,7 @@ static int gr_queue_ext(struct usb_ep *_ep, struct usb_request *_req, /* Dequeue JUST ONE request */ static int gr_dequeue(struct usb_ep *_ep, struct usb_request *_req) { - struct gr_request *req; + struct gr_request *req = NULL, *iter; struct gr_ep *ep; struct gr_udc *dev; int ret = 0; @@ -1710,11 +1710,13 @@ static int gr_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&dev->lock, flags); /* Make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { ret = -EINVAL; goto out; } diff --git a/drivers/usb/gadget/udc/lpc32xx_udc.c b/drivers/usb/gadget/udc/lpc32xx_udc.c index a25d01c89564..6117ae8e7242 100644 --- a/drivers/usb/gadget/udc/lpc32xx_udc.c +++ b/drivers/usb/gadget/udc/lpc32xx_udc.c @@ -1830,7 +1830,7 @@ static int lpc32xx_ep_queue(struct usb_ep *_ep, static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct lpc32xx_ep *ep; - struct lpc32xx_request *req; + struct lpc32xx_request *req = NULL, *iter; unsigned long flags; ep = container_of(_ep, struct lpc32xx_ep, ep); @@ -1840,11 +1840,13 @@ static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&ep->udc->lock, flags); /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { spin_unlock_irqrestore(&ep->udc->lock, flags); return -EINVAL; } diff --git a/drivers/usb/gadget/udc/max3420_udc.c b/drivers/usb/gadget/udc/max3420_udc.c index 7d9bd16190c0..3074da00c3df 100644 --- a/drivers/usb/gadget/udc/max3420_udc.c +++ b/drivers/usb/gadget/udc/max3420_udc.c @@ -1044,22 +1044,26 @@ static int max3420_ep_queue(struct usb_ep *_ep, struct usb_request *_req, static int max3420_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { - struct max3420_req *t, *req = to_max3420_req(_req); + struct max3420_req *t = NULL; + struct max3420_req *req = to_max3420_req(_req); + struct max3420_req *iter; struct max3420_ep *ep = to_max3420_ep(_ep); unsigned long flags; spin_lock_irqsave(&ep->lock, flags); /* Pluck the descriptor from queue */ - list_for_each_entry(t, &ep->queue, queue) - if (t == req) { - list_del_init(&req->queue); - break; - } + list_for_each_entry(iter, &ep->queue, queue) { + if (iter != req) + continue; + list_del_init(&req->queue); + t = iter; + break; + } spin_unlock_irqrestore(&ep->lock, flags); - if (t == req) + if (t) max3420_req_done(req, -ECONNRESET); return 0; diff --git a/drivers/usb/gadget/udc/mv_u3d_core.c b/drivers/usb/gadget/udc/mv_u3d_core.c index a1057ddfbda3..598654a3cb41 100644 --- a/drivers/usb/gadget/udc/mv_u3d_core.c +++ b/drivers/usb/gadget/udc/mv_u3d_core.c @@ -844,7 +844,7 @@ mv_u3d_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct mv_u3d_ep *ep; - struct mv_u3d_req *req; + struct mv_u3d_req *req = NULL, *iter; struct mv_u3d *u3d; struct mv_u3d_ep_context *ep_context; struct mv_u3d_req *next_req; @@ -861,11 +861,13 @@ static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&ep->u3d->lock, flags); /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { ret = -EINVAL; goto out; } diff --git a/drivers/usb/gadget/udc/mv_udc_core.c b/drivers/usb/gadget/udc/mv_udc_core.c index b6d34dda028b..fdb17d86cd65 100644 --- a/drivers/usb/gadget/udc/mv_udc_core.c +++ b/drivers/usb/gadget/udc/mv_udc_core.c @@ -771,7 +771,7 @@ static void mv_prime_ep(struct mv_ep *ep, struct mv_req *req) static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct mv_ep *ep = container_of(_ep, struct mv_ep, ep); - struct mv_req *req; + struct mv_req *req = NULL, *iter; struct mv_udc *udc = ep->udc; unsigned long flags; int stopped, ret = 0; @@ -793,11 +793,13 @@ static int mv_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) writel(epctrlx, &udc->op_regs->epctrlx[ep->ep_num]); /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { ret = -EINVAL; goto out; } diff --git a/drivers/usb/gadget/udc/net2272.c b/drivers/usb/gadget/udc/net2272.c index 7c38057dcb4a..6a8884632273 100644 --- a/drivers/usb/gadget/udc/net2272.c +++ b/drivers/usb/gadget/udc/net2272.c @@ -926,7 +926,7 @@ static int net2272_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct net2272_ep *ep; - struct net2272_request *req; + struct net2272_request *req = NULL, *iter; unsigned long flags; int stopped; @@ -939,11 +939,13 @@ net2272_dequeue(struct usb_ep *_ep, struct usb_request *_req) ep->stopped = 1; /* make sure it's still queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { ep->stopped = stopped; spin_unlock_irqrestore(&ep->dev->lock, flags); return -EINVAL; @@ -954,7 +956,6 @@ net2272_dequeue(struct usb_ep *_ep, struct usb_request *_req) dev_dbg(ep->dev->dev, "unlink (%s) pio\n", _ep->name); net2272_done(ep, req, -ECONNRESET); } - req = NULL; ep->stopped = stopped; spin_unlock_irqrestore(&ep->dev->lock, flags); diff --git a/drivers/usb/gadget/udc/net2280.c b/drivers/usb/gadget/udc/net2280.c index 16e7d2db6411..051d024b369e 100644 --- a/drivers/usb/gadget/udc/net2280.c +++ b/drivers/usb/gadget/udc/net2280.c @@ -1240,7 +1240,8 @@ static void nuke(struct net2280_ep *ep) static int net2280_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct net2280_ep *ep; - struct net2280_request *req; + struct net2280_request *req = NULL; + struct net2280_request *iter; unsigned long flags; u32 dmactl; int stopped; @@ -1266,11 +1267,13 @@ static int net2280_dequeue(struct usb_ep *_ep, struct usb_request *_req) } /* make sure it's still queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { ep->stopped = stopped; spin_unlock_irqrestore(&ep->dev->lock, flags); ep_dbg(ep->dev, "%s: Request mismatch\n", __func__); diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c index 494da00398d7..2d9815dad2ff 100644 --- a/drivers/usb/gadget/udc/omap_udc.c +++ b/drivers/usb/gadget/udc/omap_udc.c @@ -1003,7 +1003,7 @@ irq_wait: static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct omap_ep *ep = container_of(_ep, struct omap_ep, ep); - struct omap_req *req; + struct omap_req *req = NULL, *iter; unsigned long flags; if (!_ep || !_req) @@ -1012,11 +1012,13 @@ static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&ep->udc->lock, flags); /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { spin_unlock_irqrestore(&ep->udc->lock, flags); return -EINVAL; } diff --git a/drivers/usb/gadget/udc/pxa25x_udc.c b/drivers/usb/gadget/udc/pxa25x_udc.c index b38747fd3bb0..6c414c99d01c 100644 --- a/drivers/usb/gadget/udc/pxa25x_udc.c +++ b/drivers/usb/gadget/udc/pxa25x_udc.c @@ -966,7 +966,8 @@ static void nuke(struct pxa25x_ep *ep, int status) static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct pxa25x_ep *ep; - struct pxa25x_request *req; + struct pxa25x_request *req = NULL; + struct pxa25x_request *iter; unsigned long flags; ep = container_of(_ep, struct pxa25x_ep, ep); @@ -976,11 +977,13 @@ static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) local_irq_save(flags); /* make sure it's actually queued on this endpoint */ - list_for_each_entry (req, &ep->queue, queue) { - if (&req->req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + break; } - if (&req->req != _req) { + if (!req) { local_irq_restore(flags); return -EINVAL; } diff --git a/drivers/usb/gadget/udc/pxa27x_udc.c b/drivers/usb/gadget/udc/pxa27x_udc.c index f4b7a2a3e711..ac980d6a4740 100644 --- a/drivers/usb/gadget/udc/pxa27x_udc.c +++ b/drivers/usb/gadget/udc/pxa27x_udc.c @@ -1159,7 +1159,7 @@ static int pxa_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct pxa_ep *ep; struct udc_usb_ep *udc_usb_ep; - struct pxa27x_request *req; + struct pxa27x_request *req = NULL, *iter; unsigned long flags; int rc = -EINVAL; @@ -1173,11 +1173,12 @@ static int pxa_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&ep->lock, flags); /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) { - rc = 0; - break; - } + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + req = iter; + rc = 0; + break; } spin_unlock_irqrestore(&ep->lock, flags); diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c index 601829a6b4ba..648be3fd476a 100644 --- a/drivers/usb/gadget/udc/renesas_usb3.c +++ b/drivers/usb/gadget/udc/renesas_usb3.c @@ -2730,7 +2730,7 @@ static const struct soc_device_attribute renesas_usb3_quirks_match[] = { .soc_id = "r8a7795", .revision = "ES1.*", .data = &renesas_usb3_priv_r8a7795_es1, }, - { /* sentinel */ }, + { /* sentinel */ } }; static const unsigned int renesas_usb3_cable[] = { diff --git a/drivers/usb/gadget/udc/s3c-hsudc.c b/drivers/usb/gadget/udc/s3c-hsudc.c index 89f1f8c9f02e..bf803e013458 100644 --- a/drivers/usb/gadget/udc/s3c-hsudc.c +++ b/drivers/usb/gadget/udc/s3c-hsudc.c @@ -877,7 +877,7 @@ static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct s3c_hsudc_ep *hsep = our_ep(_ep); struct s3c_hsudc *hsudc = hsep->dev; - struct s3c_hsudc_req *hsreq; + struct s3c_hsudc_req *hsreq = NULL, *iter; unsigned long flags; hsep = our_ep(_ep); @@ -886,11 +886,13 @@ static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req) spin_lock_irqsave(&hsudc->lock, flags); - list_for_each_entry(hsreq, &hsep->queue, queue) { - if (&hsreq->req == _req) - break; + list_for_each_entry(iter, &hsep->queue, queue) { + if (&iter->req != _req) + continue; + hsreq = iter; + break; } - if (&hsreq->req != _req) { + if (!hsreq) { spin_unlock_irqrestore(&hsudc->lock, flags); return -EINVAL; } diff --git a/drivers/usb/gadget/udc/s3c2410_udc.c b/drivers/usb/gadget/udc/s3c2410_udc.c index e3931da24277..c6625aeb7bca 100644 --- a/drivers/usb/gadget/udc/s3c2410_udc.c +++ b/drivers/usb/gadget/udc/s3c2410_udc.c @@ -1265,7 +1265,7 @@ static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req) struct s3c2410_ep *ep = to_s3c2410_ep(_ep); int retval = -EINVAL; unsigned long flags; - struct s3c2410_request *req = NULL; + struct s3c2410_request *req = NULL, *iter; dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req); @@ -1277,13 +1277,14 @@ static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req) local_irq_save(flags); - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) { - list_del_init(&req->queue); - _req->status = -ECONNRESET; - retval = 0; - break; - } + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->req != _req) + continue; + list_del_init(&iter->queue); + _req->status = -ECONNRESET; + req = iter; + retval = 0; + break; } if (retval == 0) { diff --git a/drivers/usb/gadget/udc/snps_udc_core.c b/drivers/usb/gadget/udc/snps_udc_core.c index d046c09fa566..52ea4dcf6a92 100644 --- a/drivers/usb/gadget/udc/snps_udc_core.c +++ b/drivers/usb/gadget/udc/snps_udc_core.c @@ -80,7 +80,7 @@ static int stop_timer; * This cannot be solved by letting the RX DMA disabled until a * request gets queued because there may be other OUT packets * in the FIFO (important for not blocking control traffic). - * The value of set_rde controls the correspondig timer. + * The value of set_rde controls the corresponding timer. * * set_rde -1 == not used, means it is alloed to be set to 0 or 1 * set_rde 0 == do not touch RDE, do no start the RDE timer diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c index 43f1b0d461c1..d9c406bdb680 100644 --- a/drivers/usb/gadget/udc/tegra-xudc.c +++ b/drivers/usb/gadget/udc/tegra-xudc.c @@ -32,9 +32,6 @@ #include /* XUSB_DEV registers */ -#define SPARAM 0x000 -#define SPARAM_ERSTMAX_MASK GENMASK(20, 16) -#define SPARAM_ERSTMAX(x) (((x) << 16) & SPARAM_ERSTMAX_MASK) #define DB 0x004 #define DB_TARGET_MASK GENMASK(15, 8) #define DB_TARGET(x) (((x) << 8) & DB_TARGET_MASK) @@ -275,8 +272,10 @@ BUILD_EP_CONTEXT_RW(deq_hi, deq_hi, 0, 0xffffffff) BUILD_EP_CONTEXT_RW(avg_trb_len, tx_info, 0, 0xffff) BUILD_EP_CONTEXT_RW(max_esit_payload, tx_info, 16, 0xffff) BUILD_EP_CONTEXT_RW(edtla, rsvd[0], 0, 0xffffff) -BUILD_EP_CONTEXT_RW(seq_num, rsvd[0], 24, 0xff) +BUILD_EP_CONTEXT_RW(rsvd, rsvd[0], 24, 0x1) BUILD_EP_CONTEXT_RW(partial_td, rsvd[0], 25, 0x1) +BUILD_EP_CONTEXT_RW(splitxstate, rsvd[0], 26, 0x1) +BUILD_EP_CONTEXT_RW(seq_num, rsvd[0], 27, 0x1f) BUILD_EP_CONTEXT_RW(cerrcnt, rsvd[1], 18, 0x3) BUILD_EP_CONTEXT_RW(data_offset, rsvd[2], 0, 0x1ffff) BUILD_EP_CONTEXT_RW(numtrbs, rsvd[2], 22, 0x1f) @@ -1413,18 +1412,20 @@ __tegra_xudc_ep_dequeue(struct tegra_xudc_ep *ep, struct tegra_xudc_request *req) { struct tegra_xudc *xudc = ep->xudc; - struct tegra_xudc_request *r; + struct tegra_xudc_request *r = NULL, *iter; struct tegra_xudc_trb *deq_trb; bool busy, kick_queue = false; int ret = 0; /* Make sure the request is actually queued to this endpoint. */ - list_for_each_entry(r, &ep->queue, list) { - if (r == req) - break; + list_for_each_entry(iter, &ep->queue, list) { + if (iter != req) + continue; + r = iter; + break; } - if (r != req) + if (!r) return -EINVAL; /* Request hasn't been queued in the transfer ring yet. */ @@ -1557,6 +1558,9 @@ static int __tegra_xudc_ep_set_halt(struct tegra_xudc_ep *ep, bool halt) ep_reload(xudc, ep->index); ep_ctx_write_state(ep->context, EP_STATE_RUNNING); + ep_ctx_write_rsvd(ep->context, 0); + ep_ctx_write_partial_td(ep->context, 0); + ep_ctx_write_splitxstate(ep->context, 0); ep_ctx_write_seq_num(ep->context, 0); ep_reload(xudc, ep->index); @@ -2812,7 +2816,10 @@ static void tegra_xudc_reset(struct tegra_xudc *xudc) xudc->setup_seq_num = 0; xudc->queued_setup_packet = false; - ep_ctx_write_seq_num(ep0->context, xudc->setup_seq_num); + ep_ctx_write_rsvd(ep0->context, 0); + ep_ctx_write_partial_td(ep0->context, 0); + ep_ctx_write_splitxstate(ep0->context, 0); + ep_ctx_write_seq_num(ep0->context, 0); deq_ptr = trb_virt_to_phys(ep0, &ep0->transfer_ring[ep0->deq_ptr]); @@ -3295,11 +3302,6 @@ static void tegra_xudc_init_event_ring(struct tegra_xudc *xudc) unsigned int i; u32 val; - val = xudc_readl(xudc, SPARAM); - val &= ~(SPARAM_ERSTMAX_MASK); - val |= SPARAM_ERSTMAX(XUDC_NR_EVENT_RINGS); - xudc_writel(xudc, val, SPARAM); - for (i = 0; i < ARRAY_SIZE(xudc->event_ring); i++) { memset(xudc->event_ring[i], 0, XUDC_EVENT_RING_SIZE * sizeof(*xudc->event_ring[i])); diff --git a/drivers/usb/gadget/udc/udc-xilinx.c b/drivers/usb/gadget/udc/udc-xilinx.c index 2907fad04e2c..428c755cf2e1 100644 --- a/drivers/usb/gadget/udc/udc-xilinx.c +++ b/drivers/usb/gadget/udc/udc-xilinx.c @@ -1136,17 +1136,20 @@ static int xudc_ep_queue(struct usb_ep *_ep, struct usb_request *_req, static int xudc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) { struct xusb_ep *ep = to_xusb_ep(_ep); - struct xusb_req *req = to_xusb_req(_req); + struct xusb_req *req = NULL; + struct xusb_req *iter; struct xusb_udc *udc = ep->udc; unsigned long flags; spin_lock_irqsave(&udc->lock, flags); /* Make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->usb_req == _req) - break; + list_for_each_entry(iter, &ep->queue, queue) { + if (&iter->usb_req != _req) + continue; + req = iter; + break; } - if (&req->usb_req != _req) { + if (!req) { spin_unlock_irqrestore(&udc->lock, flags); return -EINVAL; } diff --git a/drivers/usb/host/ehci-dbg.c b/drivers/usb/host/ehci-dbg.c index 0b7f1edd9eec..c063fb042926 100644 --- a/drivers/usb/host/ehci-dbg.c +++ b/drivers/usb/host/ehci-dbg.c @@ -931,7 +931,7 @@ static struct debug_buffer *alloc_buffer(struct usb_bus *bus, static int fill_buffer(struct debug_buffer *buf) { - int ret = 0; + int ret; if (!buf->output_buf) buf->output_buf = vmalloc(buf->alloc_size); @@ -956,7 +956,7 @@ static ssize_t debug_output(struct file *file, char __user *user_buf, size_t len, loff_t *offset) { struct debug_buffer *buf = file->private_data; - int ret = 0; + int ret; mutex_lock(&buf->mutex); if (buf->count == 0) { diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index e87cf3a00fa4..638f03b89739 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -21,6 +21,9 @@ static const char hcd_name[] = "ehci-pci"; /* defined here to avoid adding to pci_ids.h for single instance use */ #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 +#define PCI_VENDOR_ID_ASPEED 0x1a03 +#define PCI_DEVICE_ID_ASPEED_EHCI 0x2603 + /*-------------------------------------------------------------------------*/ #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939 static inline bool is_intel_quark_x1000(struct pci_dev *pdev) @@ -222,6 +225,12 @@ static int ehci_pci_setup(struct usb_hcd *hcd) ehci->has_synopsys_hc_bug = 1; } break; + case PCI_VENDOR_ID_ASPEED: + if (pdev->device == PCI_DEVICE_ID_ASPEED_EHCI) { + ehci_info(ehci, "applying Aspeed HC workaround\n"); + ehci->is_aspeed = 1; + } + break; } /* optional debug port, normally in the first BAR */ diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c index c3dc906274d9..1115431a255d 100644 --- a/drivers/usb/host/ehci-platform.c +++ b/drivers/usb/host/ehci-platform.c @@ -43,7 +43,6 @@ #define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv) #define BCM_USB_FIFO_THRESHOLD 0x00800040 -#define bcm_iproc_insnreg01 hostpc[0] struct ehci_platform_priv { struct clk *clks[EHCI_MAX_CLKS]; @@ -81,7 +80,7 @@ static int ehci_platform_reset(struct usb_hcd *hcd) if (of_device_is_compatible(pdev->dev.of_node, "brcm,xgs-iproc-ehci")) ehci_writel(ehci, BCM_USB_FIFO_THRESHOLD, - &ehci->regs->bcm_iproc_insnreg01); + &ehci->regs->brcm_insnreg[1]); return 0; } diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c index 2cbf4f85bff3..a2a5c2996350 100644 --- a/drivers/usb/host/ehci-q.c +++ b/drivers/usb/host/ehci-q.c @@ -33,12 +33,13 @@ /* fill a qtd, returning how much of the buffer we were able to queue up */ -static int +static unsigned int qtd_fill(struct ehci_hcd *ehci, struct ehci_qtd *qtd, dma_addr_t buf, size_t len, int token, int maxpacket) { - int i, count; + unsigned int count; u64 addr = buf; + int i; /* one buffer entry per 4K ... first might be short or unaligned */ qtd->hw_buf[0] = cpu_to_hc32(ehci, (u32)addr); @@ -652,7 +653,7 @@ qh_urb_transaction ( * and may serve as a control status ack */ for (;;) { - int this_qtd_len; + unsigned int this_qtd_len; this_qtd_len = qtd_fill(ehci, qtd, buf, this_sg_len, token, maxpacket); diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c index 0f85aa9b2fb1..bd542b6fc46b 100644 --- a/drivers/usb/host/ehci-sched.c +++ b/drivers/usb/host/ehci-sched.c @@ -1165,10 +1165,8 @@ static struct ehci_iso_sched * iso_sched_alloc(unsigned packets, gfp_t mem_flags) { struct ehci_iso_sched *iso_sched; - int size = sizeof(*iso_sched); - size += packets * sizeof(struct ehci_iso_packet); - iso_sched = kzalloc(size, mem_flags); + iso_sched = kzalloc(struct_size(iso_sched, packet, packets), mem_flags); if (likely(iso_sched != NULL)) INIT_LIST_HEAD(&iso_sched->td_list); diff --git a/drivers/usb/host/fotg210-hcd.c b/drivers/usb/host/fotg210-hcd.c index 7af17c8e069b..c3fd375b4778 100644 --- a/drivers/usb/host/fotg210-hcd.c +++ b/drivers/usb/host/fotg210-hcd.c @@ -4014,10 +4014,8 @@ static struct fotg210_iso_sched *iso_sched_alloc(unsigned packets, gfp_t mem_flags) { struct fotg210_iso_sched *iso_sched; - int size = sizeof(*iso_sched); - size += packets * sizeof(struct fotg210_iso_packet); - iso_sched = kzalloc(size, mem_flags); + iso_sched = kzalloc(struct_size(iso_sched, packet, packets), mem_flags); if (likely(iso_sched != NULL)) INIT_LIST_HEAD(&iso_sched->td_list); diff --git a/drivers/usb/host/ohci-dbg.c b/drivers/usb/host/ohci-dbg.c index 4f267dc93882..76bc8d56325d 100644 --- a/drivers/usb/host/ohci-dbg.c +++ b/drivers/usb/host/ohci-dbg.c @@ -680,7 +680,7 @@ static struct debug_buffer *alloc_buffer(struct ohci_hcd *ohci, static int fill_buffer(struct debug_buffer *buf) { - int ret = 0; + int ret; if (!buf->page) buf->page = (char *)get_zeroed_page(GFP_KERNEL); @@ -705,7 +705,7 @@ static ssize_t debug_output(struct file *file, char __user *user_buf, size_t len, loff_t *offset) { struct debug_buffer *buf = file->private_data; - int ret = 0; + int ret; mutex_lock(&buf->mutex); if (buf->count == 0) { diff --git a/drivers/usb/host/oxu210hp-hcd.c b/drivers/usb/host/oxu210hp-hcd.c index e82ff2a49672..b741670525e3 100644 --- a/drivers/usb/host/oxu210hp-hcd.c +++ b/drivers/usb/host/oxu210hp-hcd.c @@ -1685,7 +1685,7 @@ static struct list_head *qh_urb_transaction(struct oxu_hcd *oxu, token |= (1 /* "in" */ << 8); /* else it's already initted to "out" pid (0 << 8) */ - maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input)); + maxpacket = usb_maxpacket(urb->dev, urb->pipe, !is_input); /* * buffer gets wrapped in one or more qtds; diff --git a/drivers/usb/host/xen-hcd.c b/drivers/usb/host/xen-hcd.c index 19b8c7ed74cb..210f91bf661c 100644 --- a/drivers/usb/host/xen-hcd.c +++ b/drivers/usb/host/xen-hcd.c @@ -51,6 +51,7 @@ struct vdevice_status { struct usb_shadow { struct xenusb_urb_request req; struct urb *urb; + bool in_flight; }; struct xenhcd_info { @@ -589,14 +590,12 @@ static void xenhcd_gnttab_map(struct xenhcd_info *info, void *addr, int length, int nr_pages, int flags) { grant_ref_t ref; - unsigned long buffer_mfn; unsigned int offset; unsigned int len = length; unsigned int bytes; int i; for (i = 0; i < nr_pages; i++) { - buffer_mfn = PFN_DOWN(arbitrary_virt_to_machine(addr).maddr); offset = offset_in_page(addr); bytes = PAGE_SIZE - offset; @@ -605,7 +604,7 @@ static void xenhcd_gnttab_map(struct xenhcd_info *info, void *addr, int length, ref = gnttab_claim_grant_reference(gref_head); gnttab_grant_foreign_access_ref(ref, info->xbdev->otherend_id, - buffer_mfn, flags); + virt_to_gfn(addr), flags); seg[i].gref = ref; seg[i].offset = (__u16)offset; seg[i].length = (__u16)bytes; @@ -722,6 +721,12 @@ static void xenhcd_gnttab_done(struct xenhcd_info *info, unsigned int id) int nr_segs = 0; int i; + if (!shadow->in_flight) { + xenhcd_set_error(info, "Illegal request id"); + return; + } + shadow->in_flight = false; + nr_segs = shadow->req.nr_buffer_segs; if (xenusb_pipeisoc(shadow->req.pipe)) @@ -805,6 +810,7 @@ static int xenhcd_do_request(struct xenhcd_info *info, struct urb_priv *urbp) info->urb_ring.req_prod_pvt++; info->shadow[id].urb = urb; + info->shadow[id].in_flight = true; RING_PUSH_REQUESTS_AND_CHECK_NOTIFY(&info->urb_ring, notify); if (notify) @@ -933,10 +939,27 @@ static int xenhcd_unlink_urb(struct xenhcd_info *info, struct urb_priv *urbp) return ret; } -static int xenhcd_urb_request_done(struct xenhcd_info *info) +static void xenhcd_res_to_urb(struct xenhcd_info *info, + struct xenusb_urb_response *res, struct urb *urb) +{ + if (unlikely(!urb)) + return; + + if (res->actual_length > urb->transfer_buffer_length) + urb->actual_length = urb->transfer_buffer_length; + else if (res->actual_length < 0) + urb->actual_length = 0; + else + urb->actual_length = res->actual_length; + urb->error_count = res->error_count; + urb->start_frame = res->start_frame; + xenhcd_giveback_urb(info, urb, res->status); +} + +static int xenhcd_urb_request_done(struct xenhcd_info *info, + unsigned int *eoiflag) { struct xenusb_urb_response res; - struct urb *urb; RING_IDX i, rp; __u16 id; int more_to_do = 0; @@ -963,16 +986,12 @@ static int xenhcd_urb_request_done(struct xenhcd_info *info) xenhcd_gnttab_done(info, id); if (info->error) goto err; - urb = info->shadow[id].urb; - if (likely(urb)) { - urb->actual_length = res.actual_length; - urb->error_count = res.error_count; - urb->start_frame = res.start_frame; - xenhcd_giveback_urb(info, urb, res.status); - } + xenhcd_res_to_urb(info, &res, info->shadow[id].urb); } xenhcd_add_id_to_freelist(info, id); + + *eoiflag = 0; } info->urb_ring.rsp_cons = i; @@ -990,7 +1009,7 @@ static int xenhcd_urb_request_done(struct xenhcd_info *info) return 0; } -static int xenhcd_conn_notify(struct xenhcd_info *info) +static int xenhcd_conn_notify(struct xenhcd_info *info, unsigned int *eoiflag) { struct xenusb_conn_response res; struct xenusb_conn_request *req; @@ -1035,6 +1054,8 @@ static int xenhcd_conn_notify(struct xenhcd_info *info) info->conn_ring.req_prod_pvt); req->id = id; info->conn_ring.req_prod_pvt++; + + *eoiflag = 0; } if (rc != info->conn_ring.req_prod_pvt) @@ -1057,14 +1078,19 @@ static int xenhcd_conn_notify(struct xenhcd_info *info) static irqreturn_t xenhcd_int(int irq, void *dev_id) { struct xenhcd_info *info = (struct xenhcd_info *)dev_id; + unsigned int eoiflag = XEN_EOI_FLAG_SPURIOUS; - if (unlikely(info->error)) + if (unlikely(info->error)) { + xen_irq_lateeoi(irq, XEN_EOI_FLAG_SPURIOUS); return IRQ_HANDLED; + } - while (xenhcd_urb_request_done(info) | xenhcd_conn_notify(info)) + while (xenhcd_urb_request_done(info, &eoiflag) | + xenhcd_conn_notify(info, &eoiflag)) /* Yield point for this unbounded loop. */ cond_resched(); + xen_irq_lateeoi(irq, eoiflag); return IRQ_HANDLED; } @@ -1141,9 +1167,9 @@ static int xenhcd_setup_rings(struct xenbus_device *dev, goto fail; } - err = bind_evtchn_to_irq(info->evtchn); + err = bind_evtchn_to_irq_lateeoi(info->evtchn); if (err <= 0) { - xenbus_dev_fatal(dev, err, "bind_evtchn_to_irq"); + xenbus_dev_fatal(dev, err, "bind_evtchn_to_irq_lateeoi"); goto fail; } @@ -1496,6 +1522,7 @@ static struct usb_hcd *xenhcd_create_hcd(struct xenbus_device *dev) for (i = 0; i < XENUSB_URB_RING_SIZE; i++) { info->shadow[i].req.id = i + 1; info->shadow[i].urb = NULL; + info->shadow[i].in_flight = false; } info->shadow[XENUSB_URB_RING_SIZE - 1].req.id = 0x0fff; diff --git a/drivers/usb/host/xhci-dbgcap.c b/drivers/usb/host/xhci-dbgcap.c index ccb0156fcebe..e61155fa6379 100644 --- a/drivers/usb/host/xhci-dbgcap.c +++ b/drivers/usb/host/xhci-dbgcap.c @@ -914,59 +914,6 @@ static void xhci_dbc_handle_events(struct work_struct *work) mod_delayed_work(system_wq, &dbc->event_work, 1); } -static void xhci_do_dbc_exit(struct xhci_hcd *xhci) -{ - unsigned long flags; - - spin_lock_irqsave(&xhci->lock, flags); - kfree(xhci->dbc); - xhci->dbc = NULL; - spin_unlock_irqrestore(&xhci->lock, flags); -} - -static int xhci_do_dbc_init(struct xhci_hcd *xhci) -{ - u32 reg; - struct xhci_dbc *dbc; - unsigned long flags; - void __iomem *base; - int dbc_cap_offs; - - base = &xhci->cap_regs->hc_capbase; - dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG); - if (!dbc_cap_offs) - return -ENODEV; - - dbc = kzalloc(sizeof(*dbc), GFP_KERNEL); - if (!dbc) - return -ENOMEM; - - dbc->regs = base + dbc_cap_offs; - - /* We will avoid using DbC in xhci driver if it's in use. */ - reg = readl(&dbc->regs->control); - if (reg & DBC_CTRL_DBC_ENABLE) { - kfree(dbc); - return -EBUSY; - } - - spin_lock_irqsave(&xhci->lock, flags); - if (xhci->dbc) { - spin_unlock_irqrestore(&xhci->lock, flags); - kfree(dbc); - return -EBUSY; - } - xhci->dbc = dbc; - spin_unlock_irqrestore(&xhci->lock, flags); - - dbc->xhci = xhci; - dbc->dev = xhci_to_hcd(xhci)->self.sysdev; - INIT_DELAYED_WORK(&dbc->event_work, xhci_dbc_handle_events); - spin_lock_init(&dbc->lock); - - return 0; -} - static ssize_t dbc_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -1026,44 +973,86 @@ static ssize_t dbc_store(struct device *dev, static DEVICE_ATTR_RW(dbc); -int xhci_dbc_init(struct xhci_hcd *xhci) +struct xhci_dbc * +xhci_alloc_dbc(struct device *dev, void __iomem *base, const struct dbc_driver *driver) { + struct xhci_dbc *dbc; int ret; - struct device *dev = xhci_to_hcd(xhci)->self.controller; - ret = xhci_do_dbc_init(xhci); - if (ret) - goto init_err3; + dbc = kzalloc(sizeof(*dbc), GFP_KERNEL); + if (!dbc) + return NULL; - ret = xhci_dbc_tty_probe(xhci); - if (ret) - goto init_err2; + dbc->regs = base; + dbc->dev = dev; + dbc->driver = driver; + + if (readl(&dbc->regs->control) & DBC_CTRL_DBC_ENABLE) + return NULL; + + INIT_DELAYED_WORK(&dbc->event_work, xhci_dbc_handle_events); + spin_lock_init(&dbc->lock); ret = device_create_file(dev, &dev_attr_dbc); if (ret) - goto init_err1; + goto err; - return 0; + return dbc; +err: + kfree(dbc); + return NULL; +} + +/* undo what xhci_alloc_dbc() did */ +void xhci_dbc_remove(struct xhci_dbc *dbc) +{ + if (!dbc) + return; + /* stop hw, stop wq and call dbc->ops->stop() */ + xhci_dbc_stop(dbc); + + /* remove sysfs files */ + device_remove_file(dbc->dev, &dev_attr_dbc); + + kfree(dbc); +} + + +int xhci_create_dbc_dev(struct xhci_hcd *xhci) +{ + struct device *dev; + void __iomem *base; + int ret; + int dbc_cap_offs; + + /* create all parameters needed resembling a dbc device */ + dev = xhci_to_hcd(xhci)->self.controller; + base = &xhci->cap_regs->hc_capbase; + + dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG); + if (!dbc_cap_offs) + return -ENODEV; + + /* already allocated and in use */ + if (xhci->dbc) + return -EBUSY; + + ret = xhci_dbc_tty_probe(dev, base + dbc_cap_offs, xhci); -init_err1: - xhci_dbc_tty_remove(xhci->dbc); -init_err2: - xhci_do_dbc_exit(xhci); -init_err3: return ret; } -void xhci_dbc_exit(struct xhci_hcd *xhci) +void xhci_remove_dbc_dev(struct xhci_hcd *xhci) { - struct device *dev = xhci_to_hcd(xhci)->self.controller; + unsigned long flags; if (!xhci->dbc) return; - device_remove_file(dev, &dev_attr_dbc); xhci_dbc_tty_remove(xhci->dbc); - xhci_dbc_stop(xhci->dbc); - xhci_do_dbc_exit(xhci); + spin_lock_irqsave(&xhci->lock, flags); + xhci->dbc = NULL; + spin_unlock_irqrestore(&xhci->lock, flags); } #ifdef CONFIG_PM @@ -1098,3 +1087,13 @@ int xhci_dbc_resume(struct xhci_hcd *xhci) return ret; } #endif /* CONFIG_PM */ + +int xhci_dbc_init(void) +{ + return dbc_tty_init(); +} + +void xhci_dbc_exit(void) +{ + dbc_tty_exit(); +} diff --git a/drivers/usb/host/xhci-dbgcap.h b/drivers/usb/host/xhci-dbgcap.h index c70b78d504eb..ca04192fdab1 100644 --- a/drivers/usb/host/xhci-dbgcap.h +++ b/drivers/usb/host/xhci-dbgcap.h @@ -100,6 +100,7 @@ struct dbc_ep { struct dbc_port { struct tty_port port; spinlock_t port_lock; /* port access */ + int minor; struct list_head read_pool; struct list_head read_queue; @@ -194,10 +195,17 @@ static inline struct dbc_ep *get_out_ep(struct xhci_dbc *dbc) } #ifdef CONFIG_USB_XHCI_DBGCAP -int xhci_dbc_init(struct xhci_hcd *xhci); -void xhci_dbc_exit(struct xhci_hcd *xhci); -int xhci_dbc_tty_probe(struct xhci_hcd *xhci); +int xhci_create_dbc_dev(struct xhci_hcd *xhci); +void xhci_remove_dbc_dev(struct xhci_hcd *xhci); +int xhci_dbc_init(void); +void xhci_dbc_exit(void); +int dbc_tty_init(void); +void dbc_tty_exit(void); +int xhci_dbc_tty_probe(struct device *dev, void __iomem *res, struct xhci_hcd *xhci); void xhci_dbc_tty_remove(struct xhci_dbc *dbc); +struct xhci_dbc *xhci_alloc_dbc(struct device *dev, void __iomem *res, + const struct dbc_driver *driver); +void xhci_dbc_remove(struct xhci_dbc *dbc); struct dbc_request *dbc_alloc_request(struct xhci_dbc *dbc, unsigned int direction, gfp_t flags); @@ -208,15 +216,21 @@ int xhci_dbc_suspend(struct xhci_hcd *xhci); int xhci_dbc_resume(struct xhci_hcd *xhci); #endif /* CONFIG_PM */ #else -static inline int xhci_dbc_init(struct xhci_hcd *xhci) +static inline int xhci_create_dbc_dev(struct xhci_hcd *xhci) { return 0; } -static inline void xhci_dbc_exit(struct xhci_hcd *xhci) +static inline void xhci_remove_dbc_dev(struct xhci_hcd *xhci) +{ +} +static inline int xhci_dbc_init(void) +{ + return 0; +} +static inline void xhci_dbc_exit(void) { } - static inline int xhci_dbc_suspend(struct xhci_hcd *xhci) { return 0; diff --git a/drivers/usb/host/xhci-dbgtty.c b/drivers/usb/host/xhci-dbgtty.c index eb46e642e87a..d3acc0829ee5 100644 --- a/drivers/usb/host/xhci-dbgtty.c +++ b/drivers/usb/host/xhci-dbgtty.c @@ -10,14 +10,14 @@ #include #include #include +#include #include "xhci.h" #include "xhci-dbgcap.h" -static int dbc_tty_init(void); -static void dbc_tty_exit(void); - static struct tty_driver *dbc_tty_driver; +static struct idr dbc_tty_minors; +static DEFINE_MUTEX(dbc_tty_minors_lock); static inline struct dbc_port *dbc_to_port(struct xhci_dbc *dbc) { @@ -180,7 +180,14 @@ xhci_dbc_free_requests(struct list_head *head) static int dbc_tty_install(struct tty_driver *driver, struct tty_struct *tty) { - struct dbc_port *port = driver->driver_state; + struct dbc_port *port; + + mutex_lock(&dbc_tty_minors_lock); + port = idr_find(&dbc_tty_minors, tty->index); + mutex_unlock(&dbc_tty_minors_lock); + + if (!port) + return -ENXIO; tty->driver_data = port; @@ -409,6 +416,15 @@ static int xhci_dbc_tty_register_device(struct xhci_dbc *dbc) xhci_dbc_tty_init_port(dbc, port); + mutex_lock(&dbc_tty_minors_lock); + port->minor = idr_alloc(&dbc_tty_minors, port, 0, 64, GFP_KERNEL); + mutex_unlock(&dbc_tty_minors_lock); + + if (port->minor < 0) { + ret = port->minor; + goto err_idr; + } + ret = kfifo_alloc(&port->write_fifo, DBC_WRITE_BUF_SIZE, GFP_KERNEL); if (ret) goto err_exit_port; @@ -424,7 +440,7 @@ static int xhci_dbc_tty_register_device(struct xhci_dbc *dbc) goto err_free_requests; tty_dev = tty_port_register_device(&port->port, - dbc_tty_driver, 0, NULL); + dbc_tty_driver, port->minor, NULL); if (IS_ERR(tty_dev)) { ret = PTR_ERR(tty_dev); goto err_free_requests; @@ -440,6 +456,8 @@ err_free_requests: err_free_fifo: kfifo_free(&port->write_fifo); err_exit_port: + idr_remove(&dbc_tty_minors, port->minor); +err_idr: xhci_dbc_tty_exit_port(port); dev_err(dbc->dev, "can't register tty port, err %d\n", ret); @@ -453,10 +471,14 @@ static void xhci_dbc_tty_unregister_device(struct xhci_dbc *dbc) if (!port->registered) return; - tty_unregister_device(dbc_tty_driver, 0); + tty_unregister_device(dbc_tty_driver, port->minor); xhci_dbc_tty_exit_port(port); port->registered = false; + mutex_lock(&dbc_tty_minors_lock); + idr_remove(&dbc_tty_minors, port->minor); + mutex_unlock(&dbc_tty_minors_lock); + kfifo_free(&port->write_fifo); xhci_dbc_free_requests(&port->read_pool); xhci_dbc_free_requests(&port->read_queue); @@ -468,33 +490,35 @@ static const struct dbc_driver dbc_driver = { .disconnect = xhci_dbc_tty_unregister_device, }; -int xhci_dbc_tty_probe(struct xhci_hcd *xhci) +int xhci_dbc_tty_probe(struct device *dev, void __iomem *base, struct xhci_hcd *xhci) { - struct xhci_dbc *dbc = xhci->dbc; + struct xhci_dbc *dbc; struct dbc_port *port; int status; - /* dbc_tty_init will be called by module init() in the future */ - status = dbc_tty_init(); - if (status) - return status; + if (!dbc_tty_driver) + return -ENODEV; port = kzalloc(sizeof(*port), GFP_KERNEL); - if (!port) { + if (!port) + return -ENOMEM; + + dbc = xhci_alloc_dbc(dev, base, &dbc_driver); + + if (!dbc) { status = -ENOMEM; - goto out; + goto out2; } - dbc->driver = &dbc_driver; dbc->priv = port; - - dbc_tty_driver->driver_state = port; + /* get rid of xhci once this is a real driver binding to a device */ + xhci->dbc = dbc; return 0; -out: - /* dbc_tty_exit will be called by module_exit() in the future */ - dbc_tty_exit(); +out2: + kfree(port); + return status; } @@ -506,22 +530,22 @@ void xhci_dbc_tty_remove(struct xhci_dbc *dbc) { struct dbc_port *port = dbc_to_port(dbc); - dbc->driver = NULL; - dbc->priv = NULL; + xhci_dbc_remove(dbc); kfree(port); - - /* dbc_tty_exit will be called by module_exit() in the future */ - dbc_tty_exit(); } -static int dbc_tty_init(void) +int dbc_tty_init(void) { int ret; - dbc_tty_driver = tty_alloc_driver(1, TTY_DRIVER_REAL_RAW | + idr_init(&dbc_tty_minors); + + dbc_tty_driver = tty_alloc_driver(64, TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV); - if (IS_ERR(dbc_tty_driver)) + if (IS_ERR(dbc_tty_driver)) { + idr_destroy(&dbc_tty_minors); return PTR_ERR(dbc_tty_driver); + } dbc_tty_driver->driver_name = "dbc_serial"; dbc_tty_driver->name = "ttyDBC"; @@ -540,15 +564,19 @@ static int dbc_tty_init(void) if (ret) { pr_err("Can't register dbc tty driver\n"); tty_driver_kref_put(dbc_tty_driver); + idr_destroy(&dbc_tty_minors); } + return ret; } -static void dbc_tty_exit(void) +void dbc_tty_exit(void) { if (dbc_tty_driver) { tty_unregister_driver(dbc_tty_driver); tty_driver_kref_put(dbc_tty_driver); dbc_tty_driver = NULL; } + + idr_destroy(&dbc_tty_minors); } diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c index df3522dab31b..1e7dc130c39a 100644 --- a/drivers/usb/host/xhci-hub.c +++ b/drivers/usb/host/xhci-hub.c @@ -762,7 +762,7 @@ static int xhci_exit_test_mode(struct xhci_hcd *xhci) } pm_runtime_allow(xhci_to_hcd(xhci)->self.controller); xhci->test_mode = 0; - return xhci_reset(xhci); + return xhci_reset(xhci, XHCI_RESET_SHORT_USEC); } void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port, @@ -1088,6 +1088,9 @@ static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status, if (link_state == XDEV_U2) *status |= USB_PORT_STAT_L1; if (link_state == XDEV_U0) { + if (bus_state->resume_done[portnum]) + usb_hcd_end_port_resume(&port->rhub->hcd->self, + portnum); bus_state->resume_done[portnum] = 0; clear_bit(portnum, &bus_state->resuming_ports); if (bus_state->suspended_ports & (1 << portnum)) { diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 0e312066c5c6..bbb27ee2c6a3 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -57,7 +57,7 @@ static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */ if (cycle_state == 0) { for (i = 0; i < TRBS_PER_SEGMENT; i++) - seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE); + seg->trbs[i].link.control = cpu_to_le32(TRB_CYCLE); } seg->dma = dma; seg->next = NULL; @@ -433,8 +433,7 @@ int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, (TRBS_PER_SEGMENT - 1); /* Allocate number of segments we needed, or double the ring size */ - num_segs = ring->num_segs > num_segs_needed ? - ring->num_segs : num_segs_needed; + num_segs = max(ring->num_segs, num_segs_needed); ret = xhci_alloc_segments_for_ring(xhci, &first, &last, num_segs, ring->cycle_state, ring->type, @@ -1846,9 +1845,6 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci) xhci->event_ring = NULL; xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring"); - if (xhci->lpm_command) - xhci_free_command(xhci, xhci->lpm_command); - xhci->lpm_command = NULL; if (xhci->cmd_ring) xhci_ring_free(xhci, xhci->cmd_ring); xhci->cmd_ring = NULL; @@ -2395,11 +2391,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) page_size = readl(&xhci->op_regs->page_size); xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Supported page size register = 0x%x", page_size); - for (i = 0; i < 16; i++) { - if ((0x1 & page_size) != 0) - break; - page_size = page_size >> 1; - } + i = ffs(page_size); if (i < 16) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Supported page size of %iK", (1 << (i+12)) / 1024); @@ -2425,7 +2417,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) writel(val, &xhci->op_regs->config_reg); /* - * xHCI section 5.4.6 - doorbell array must be + * xHCI section 5.4.6 - Device Context array must be * "physically contiguous and 64-byte (cache line) aligned". */ xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma, @@ -2488,10 +2480,6 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) "// Setting command ring address to 0x%016llx", val_64); xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring); - xhci->lpm_command = xhci_alloc_command_with_ctx(xhci, true, flags); - if (!xhci->lpm_command) - goto fail; - /* Reserve one command ring TRB for disabling LPM. * Since the USB core grabs the shared usb_bus bandwidth mutex before * disabling LPM, we only need to reserve one TRB for all devices. @@ -2583,7 +2571,7 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags) fail: xhci_halt(xhci); - xhci_reset(xhci); + xhci_reset(xhci, XHCI_RESET_SHORT_USEC); xhci_mem_cleanup(xhci); return -ENOMEM; } diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c index edbfa82c6565..f3139ce7b0a9 100644 --- a/drivers/usb/host/xhci-mtk-sch.c +++ b/drivers/usb/host/xhci-mtk-sch.c @@ -248,7 +248,6 @@ create_sch_ep(struct xhci_hcd_mtk *mtk, struct usb_device *udev, struct mu3h_sch_bw_info *bw_info; struct mu3h_sch_tt *tt = NULL; u32 len_bw_budget_table; - size_t mem_size; bw_info = get_bw_info(mtk, udev, ep); if (!bw_info) @@ -262,9 +261,9 @@ create_sch_ep(struct xhci_hcd_mtk *mtk, struct usb_device *udev, else len_bw_budget_table = 1; - mem_size = sizeof(struct mu3h_sch_ep_info) + - len_bw_budget_table * sizeof(u32); - sch_ep = kzalloc(mem_size, GFP_KERNEL); + sch_ep = kzalloc(struct_size(sch_ep, bw_budget_table, + len_bw_budget_table), + GFP_KERNEL); if (!sch_ep) return ERR_PTR(-ENOMEM); diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 91738af0ab14..b1045f534a4b 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -95,6 +95,19 @@ #define WC0_SSUSB0_CDEN BIT(6) #define WC0_IS_SPM_EN BIT(1) +/* mt8195 */ +#define PERI_WK_CTRL0_8195 0x04 +#define WC0_IS_P_95 BIT(30) /* polarity */ +#define WC0_IS_C_95(x) ((u32)(((x) & 0x7) << 27)) +#define WC0_IS_EN_P3_95 BIT(26) +#define WC0_IS_EN_P2_95 BIT(25) +#define WC0_IS_EN_P1_95 BIT(24) + +#define PERI_WK_CTRL1_8195 0x20 +#define WC1_IS_C_95(x) ((u32)(((x) & 0xf) << 28)) +#define WC1_IS_P_95 BIT(12) +#define WC1_IS_EN_P0_95 BIT(6) + /* mt2712 etc */ #define PERI_SSUSB_SPM_CTRL 0x0 #define SSC_IP_SLEEP_EN BIT(4) @@ -105,6 +118,10 @@ enum ssusb_uwk_vers { SSUSB_UWK_V2, SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */ SSUSB_UWK_V1_2, /* specific revision 1.2 */ + SSUSB_UWK_V1_3, /* mt8195 IP0 */ + SSUSB_UWK_V1_4, /* mt8195 IP1 */ + SSUSB_UWK_V1_5, /* mt8195 IP2 */ + SSUSB_UWK_V1_6, /* mt8195 IP3 */ }; /* @@ -308,6 +325,26 @@ static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable) msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN; val = enable ? msk : 0; break; + case SSUSB_UWK_V1_3: + reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195; + msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95; + val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0; + break; + case SSUSB_UWK_V1_4: + reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195; + msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; + val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0; + break; + case SSUSB_UWK_V1_5: + reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195; + msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; + val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0; + break; + case SSUSB_UWK_V1_6: + reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195; + msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95; + val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0; + break; case SSUSB_UWK_V2: reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL; msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN; @@ -364,29 +401,14 @@ static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk) return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks); } -static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk) +static int xhci_mtk_vregs_get(struct xhci_hcd_mtk *mtk) { - int ret; + struct regulator_bulk_data *supplies = mtk->supplies; - ret = regulator_enable(mtk->vbus); - if (ret) { - dev_err(mtk->dev, "failed to enable vbus\n"); - return ret; - } + supplies[0].supply = "vbus"; + supplies[1].supply = "vusb33"; - ret = regulator_enable(mtk->vusb33); - if (ret) { - dev_err(mtk->dev, "failed to enable vusb33\n"); - regulator_disable(mtk->vbus); - return ret; - } - return 0; -} - -static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk) -{ - regulator_disable(mtk->vbus); - regulator_disable(mtk->vusb33); + return devm_regulator_bulk_get(mtk->dev, BULK_VREGS_NUM, supplies); } static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) @@ -476,17 +498,10 @@ static int xhci_mtk_probe(struct platform_device *pdev) return -ENOMEM; mtk->dev = dev; - mtk->vbus = devm_regulator_get(dev, "vbus"); - if (IS_ERR(mtk->vbus)) { - dev_err(dev, "fail to get vbus\n"); - return PTR_ERR(mtk->vbus); - } - mtk->vusb33 = devm_regulator_get(dev, "vusb33"); - if (IS_ERR(mtk->vusb33)) { - dev_err(dev, "fail to get vusb33\n"); - return PTR_ERR(mtk->vusb33); - } + ret = xhci_mtk_vregs_get(mtk); + if (ret) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); ret = xhci_mtk_clks_get(mtk); if (ret) @@ -527,7 +542,7 @@ static int xhci_mtk_probe(struct platform_device *pdev) pm_runtime_enable(dev); pm_runtime_get_sync(dev); - ret = xhci_mtk_ldos_enable(mtk); + ret = regulator_bulk_enable(BULK_VREGS_NUM, mtk->supplies); if (ret) goto disable_pm; @@ -636,7 +651,7 @@ disable_clk: clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); disable_ldos: - xhci_mtk_ldos_disable(mtk); + regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies); disable_pm: pm_runtime_put_noidle(dev); @@ -664,7 +679,7 @@ static int xhci_mtk_remove(struct platform_device *pdev) usb_put_hcd(hcd); xhci_mtk_sch_exit(mtk); clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks); - xhci_mtk_ldos_disable(mtk); + regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies); pm_runtime_disable(dev); pm_runtime_put_noidle(dev); diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h index 4b1ea89f959a..ffd4b493b4ba 100644 --- a/drivers/usb/host/xhci-mtk.h +++ b/drivers/usb/host/xhci-mtk.h @@ -11,10 +11,12 @@ #include #include +#include #include "xhci.h" #define BULK_CLKS_NUM 5 +#define BULK_VREGS_NUM 2 /* support at most 64 ep, use 32 size hash table */ #define SCH_EP_HASH_BITS 5 @@ -150,9 +152,8 @@ struct xhci_hcd_mtk { int num_u3_ports; int u2p_dis_msk; int u3p_dis_msk; - struct regulator *vusb33; - struct regulator *vbus; struct clk_bulk_data clks[BULK_CLKS_NUM]; + struct regulator_bulk_data supplies[BULK_VREGS_NUM]; unsigned int has_ippc:1; unsigned int lpm_support:1; unsigned int u2_lpm_disable:1; diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index dc570ce4e831..8094da34825e 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -226,20 +226,13 @@ static int xhci_plat_probe(struct platform_device *pdev) if (!sysdev) sysdev = &pdev->dev; - /* Try to set 64-bit DMA first */ if (WARN_ON(!sysdev->dma_mask)) /* Platform did not initialize dma_mask */ - ret = dma_coerce_mask_and_coherent(sysdev, - DMA_BIT_MASK(64)); + ret = dma_coerce_mask_and_coherent(sysdev, DMA_BIT_MASK(64)); else ret = dma_set_mask_and_coherent(sysdev, DMA_BIT_MASK(64)); - - /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */ - if (ret) { - ret = dma_set_mask_and_coherent(sysdev, DMA_BIT_MASK(32)); - if (ret) - return ret; - } + if (ret) + return ret; pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 9888ba7d85b6..aef0258a7160 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -82,7 +82,7 @@ static const struct soc_device_attribute rcar_quirks_match[] = { .soc_id = "r8a7795", .revision = "ES1.*", .data = (void *)RCAR_XHCI_FIRMWARE_V2, }, - { /* sentinel */ }, + { /* sentinel */ } }; static void xhci_rcar_start_gen2(struct usb_hcd *hcd) diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 2d378543bc3a..642610c78f58 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -65,7 +65,7 @@ static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring) * handshake done). There are two failure modes: "usec" have passed (major * hardware flakeout), or the register reads as all-ones (hardware removed). */ -int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) +int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us) { u32 result; int ret; @@ -73,7 +73,7 @@ int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec) ret = readl_poll_timeout_atomic(ptr, result, (result & mask) == done || result == U32_MAX, - 1, usec); + 1, timeout_us); if (result == U32_MAX) /* card removed */ return -ENODEV; @@ -110,6 +110,7 @@ void xhci_quiesce(struct xhci_hcd *xhci) int xhci_halt(struct xhci_hcd *xhci) { int ret; + xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC"); xhci_quiesce(xhci); @@ -119,8 +120,10 @@ int xhci_halt(struct xhci_hcd *xhci) xhci_warn(xhci, "Host halt failed, %d\n", ret); return ret; } + xhci->xhc_state |= XHCI_STATE_HALTED; xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; + return ret; } @@ -162,7 +165,7 @@ int xhci_start(struct xhci_hcd *xhci) * Transactions will be terminated immediately, and operational registers * will be set to their defaults. */ -int xhci_reset(struct xhci_hcd *xhci) +int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us) { u32 command; u32 state; @@ -195,8 +198,7 @@ int xhci_reset(struct xhci_hcd *xhci) if (xhci->quirks & XHCI_INTEL_HOST) udelay(1000); - ret = xhci_handshake(&xhci->op_regs->command, - CMD_RESET, 0, 10 * 1000 * 1000); + ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us); if (ret) return ret; @@ -209,8 +211,7 @@ int xhci_reset(struct xhci_hcd *xhci) * xHCI cannot write to any doorbells or operational registers other * than status until the "Controller Not Ready" flag is cleared. */ - ret = xhci_handshake(&xhci->op_regs->status, - STS_CNR, 0, 10 * 1000 * 1000); + ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us); xhci->usb2_rhub.bus_state.port_c_suspend = 0; xhci->usb2_rhub.bus_state.suspended_ports = 0; @@ -324,7 +325,7 @@ static int xhci_setup_msi(struct xhci_hcd *xhci) */ static int xhci_setup_msix(struct xhci_hcd *xhci) { - int i, ret = 0; + int i, ret; struct usb_hcd *hcd = xhci_to_hcd(xhci); struct pci_dev *pdev = to_pci_dev(hcd->self.controller); @@ -578,7 +579,7 @@ static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci) static int xhci_init(struct usb_hcd *hcd) { struct xhci_hcd *xhci = hcd_to_xhci(hcd); - int retval = 0; + int retval; xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init"); spin_lock_init(&xhci->lock); @@ -695,7 +696,7 @@ int xhci_run(struct usb_hcd *hcd) xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_run for USB2 roothub"); - xhci_dbc_init(xhci); + xhci_create_dbc_dev(xhci); xhci_debugfs_init(xhci); @@ -725,13 +726,13 @@ static void xhci_stop(struct usb_hcd *hcd) return; } - xhci_dbc_exit(xhci); + xhci_remove_dbc_dev(xhci); spin_lock_irq(&xhci->lock); xhci->xhc_state |= XHCI_STATE_HALTED; xhci->cmd_ring_state = CMD_RING_STATE_STOPPED; xhci_halt(xhci); - xhci_reset(xhci); + xhci_reset(xhci, XHCI_RESET_SHORT_USEC); spin_unlock_irq(&xhci->lock); xhci_cleanup_msix(xhci); @@ -784,7 +785,7 @@ void xhci_shutdown(struct usb_hcd *hcd) xhci_halt(xhci); /* Workaround for spurious wakeups at shutdown with HSW */ if (xhci->quirks & XHCI_SPURIOUS_WAKEUP) - xhci_reset(xhci); + xhci_reset(xhci, XHCI_RESET_SHORT_USEC); spin_unlock_irq(&xhci->lock); xhci_cleanup_msix(xhci); @@ -1170,7 +1171,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated) xhci_dbg(xhci, "Stop HCD\n"); xhci_halt(xhci); xhci_zero_64b_regs(xhci); - retval = xhci_reset(xhci); + retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC); spin_unlock_irq(&xhci->lock); if (retval) return retval; @@ -3160,8 +3161,6 @@ rescan: ep_index = xhci_get_endpoint_index(&host_ep->desc); ep = &vdev->eps[ep_index]; - if (!ep) - goto done; /* wait for hub_tt_work to finish clearing hub TT */ if (ep->ep_state & EP_CLEARING_TT) { @@ -3219,8 +3218,6 @@ static void xhci_endpoint_reset(struct usb_hcd *hcd, return; ep_index = xhci_get_endpoint_index(&host_ep->desc); ep = &vdev->eps[ep_index]; - if (!ep) - return; /* Bail out if toggle is already being cleared by a endpoint reset */ spin_lock_irqsave(&xhci->lock, flags); @@ -3978,7 +3975,7 @@ int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id) struct xhci_command *command; unsigned long flags; u32 state; - int ret = 0; + int ret; command = xhci_alloc_command(xhci, true, GFP_KERNEL); if (!command) @@ -4014,7 +4011,7 @@ int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id) xhci_free_command(xhci, command); - return ret; + return 0; } /* @@ -4354,6 +4351,10 @@ static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, unsigned long flags; int ret; + command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL); + if (!command) + return -ENOMEM; + spin_lock_irqsave(&xhci->lock, flags); virt_dev = xhci->devs[udev->slot_id]; @@ -4370,10 +4371,10 @@ static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, } /* Attempt to issue an Evaluate Context command to change the MEL. */ - command = xhci->lpm_command; ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); if (!ctrl_ctx) { spin_unlock_irqrestore(&xhci->lock, flags); + xhci_free_command(xhci, command); xhci_warn(xhci, "%s: Could not get input context, bad type.\n", __func__); return -ENOMEM; @@ -4400,6 +4401,9 @@ static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci, virt_dev->current_mel = max_exit_latency; spin_unlock_irqrestore(&xhci->lock, flags); } + + xhci_free_command(xhci, command); + return ret; } @@ -4520,18 +4524,8 @@ static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, exit_latency = xhci_besl_encoding[hird]; spin_unlock_irqrestore(&xhci->lock, flags); - /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx - * input context for link powermanagement evaluate - * context commands. It is protected by hcd->bandwidth - * mutex and is shared by all devices. We need to set - * the max ext latency in USB 2 BESL LPM as well, so - * use the same mutex and xhci_change_max_exit_latency() - */ - mutex_lock(hcd->bandwidth_mutex); ret = xhci_change_max_exit_latency(xhci, udev, exit_latency); - mutex_unlock(hcd->bandwidth_mutex); - if (ret < 0) return ret; spin_lock_irqsave(&xhci->lock, flags); @@ -4559,9 +4553,7 @@ static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, readl(pm_addr); if (udev->usb2_hw_lpm_besl_capable) { spin_unlock_irqrestore(&xhci->lock, flags); - mutex_lock(hcd->bandwidth_mutex); xhci_change_max_exit_latency(xhci, udev, 0); - mutex_unlock(hcd->bandwidth_mutex); readl_poll_timeout(ports[port_num]->addr, pm_val, (pm_val & PORT_PLS_MASK) == XDEV_U0, 100, 10000); @@ -5290,8 +5282,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1); xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2); xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3); - xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase); - xhci->hci_version = HC_VERSION(xhci->hcc_params); + xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase)); xhci->hcc_params = readl(&xhci->cap_regs->hcc_params); if (xhci->hci_version > 0x100) xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2); @@ -5316,7 +5307,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks) xhci_dbg(xhci, "Resetting HCD\n"); /* Reset the internal HC memory state and registers. */ - retval = xhci_reset(xhci); + retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC); if (retval) return retval; xhci_dbg(xhci, "Reset complete\n"); @@ -5505,6 +5496,7 @@ static int __init xhci_hcd_init(void) return -ENODEV; xhci_debugfs_create_root(); + xhci_dbc_init(); return 0; } @@ -5516,6 +5508,7 @@ static int __init xhci_hcd_init(void) static void __exit xhci_hcd_fini(void) { xhci_debugfs_remove_root(); + xhci_dbc_exit(); } module_init(xhci_hcd_init); diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 5a75fe563123..473a33ce299e 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -229,6 +229,9 @@ struct xhci_op_regs { #define CMD_ETE (1 << 14) /* bits 15:31 are reserved (and should be preserved on writes). */ +#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000) +#define XHCI_RESET_SHORT_USEC (250 * 1000) + /* IMAN - Interrupt Management Register */ #define IMAN_IE (1 << 1) #define IMAN_IP (1 << 0) @@ -1812,8 +1815,6 @@ struct xhci_hcd { /* slot enabling and address device helpers */ /* these are not thread safe so use mutex */ struct mutex mutex; - /* For USB 3.0 LPM enable/disable. */ - struct xhci_command *lpm_command; /* Internal mirror of the HW's dcbaa */ struct xhci_virt_device *devs[MAX_HC_SLOTS]; /* For keeping track of bandwidth domains per roothub. */ @@ -2083,11 +2084,11 @@ void xhci_free_container_ctx(struct xhci_hcd *xhci, /* xHCI host controller glue */ typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); -int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); +int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us); void xhci_quiesce(struct xhci_hcd *xhci); int xhci_halt(struct xhci_hcd *xhci); int xhci_start(struct xhci_hcd *xhci); -int xhci_reset(struct xhci_hcd *xhci); +int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us); int xhci_run(struct usb_hcd *hcd); int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); void xhci_shutdown(struct usb_hcd *hcd); @@ -2467,6 +2468,8 @@ static inline const char *xhci_decode_ctrl_ctx(char *str, unsigned int bit; int ret = 0; + str[0] = '\0'; + if (drop) { ret = sprintf(str, "Drop:"); for_each_set_bit(bit, &drop, 32) @@ -2624,8 +2627,11 @@ static inline const char *xhci_decode_usbsts(char *str, u32 usbsts) { int ret = 0; + ret = sprintf(str, " 0x%08x", usbsts); + if (usbsts == ~(u32)0) - return " 0xffffffff"; + return str; + if (usbsts & STS_HALT) ret += sprintf(str + ret, " HCHalted"); if (usbsts & STS_FATAL) diff --git a/drivers/usb/isp1760/isp1760-hcd.c b/drivers/usb/isp1760/isp1760-hcd.c index 79d571f1429b..893becb077d3 100644 --- a/drivers/usb/isp1760/isp1760-hcd.c +++ b/drivers/usb/isp1760/isp1760-hcd.c @@ -1768,7 +1768,6 @@ static void qtd_list_free(struct list_head *qtd_list) * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. * Also calculate the PID type (SETUP/IN/OUT) for each packet. */ -#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) static void packetize_urb(struct usb_hcd *hcd, struct urb *urb, struct list_head *head, gfp_t flags) { @@ -1809,8 +1808,8 @@ static void packetize_urb(struct usb_hcd *hcd, packet_type = IN_PID; } - maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe, - usb_pipeout(urb->pipe))); + maxpacketsize = usb_maxpacket(urb->dev, urb->pipe, + usb_pipeout(urb->pipe)); /* * buffer gets wrapped in one or more qtds; diff --git a/drivers/usb/misc/Kconfig b/drivers/usb/misc/Kconfig index 8f1144359012..4c5ddbd75b7e 100644 --- a/drivers/usb/misc/Kconfig +++ b/drivers/usb/misc/Kconfig @@ -137,6 +137,17 @@ config USB_APPLEDISPLAY Say Y here if you want to control the backlight of Apple Cinema Displays over USB. This driver provides a sysfs interface. +config USB_QCOM_EUD + tristate "QCOM Embedded USB Debugger(EUD) Driver" + depends on ARCH_QCOM || COMPILE_TEST + select USB_ROLE_SWITCH + help + This module enables support for Qualcomm Technologies, Inc. + Embedded USB Debugger (EUD). The EUD is a control peripheral + which reports VBUS attach/detach events and has USB-based + debug and trace capabilities. On selecting m, the module name + that is built is qcom_eud.ko + config APPLE_MFI_FASTCHARGE tristate "Fast charge control for iOS devices" select POWER_SUPPLY diff --git a/drivers/usb/misc/Makefile b/drivers/usb/misc/Makefile index 5f4e598573ab..35bdb4b6c3b6 100644 --- a/drivers/usb/misc/Makefile +++ b/drivers/usb/misc/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_USB_ISIGHTFW) += isight_firmware.o obj-$(CONFIG_USB_LCD) += usblcd.o obj-$(CONFIG_USB_LD) += ldusb.o obj-$(CONFIG_USB_LEGOTOWER) += legousbtower.o +obj-$(CONFIG_USB_QCOM_EUD) += qcom_eud.o obj-$(CONFIG_USB_TEST) += usbtest.o obj-$(CONFIG_USB_EHSET_TEST_FIXTURE) += ehset.o obj-$(CONFIG_USB_TRANCEVIBRATOR) += trancevibrator.o diff --git a/drivers/usb/misc/qcom_eud.c b/drivers/usb/misc/qcom_eud.c new file mode 100644 index 000000000000..f929bffdc5d1 --- /dev/null +++ b/drivers/usb/misc/qcom_eud.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EUD_REG_INT1_EN_MASK 0x0024 +#define EUD_REG_INT_STATUS_1 0x0044 +#define EUD_REG_CTL_OUT_1 0x0074 +#define EUD_REG_VBUS_INT_CLR 0x0080 +#define EUD_REG_CSR_EUD_EN 0x1014 +#define EUD_REG_SW_ATTACH_DET 0x1018 +#define EUD_REG_EUD_EN2 0x0000 + +#define EUD_ENABLE BIT(0) +#define EUD_INT_PET_EUD BIT(0) +#define EUD_INT_VBUS BIT(2) +#define EUD_INT_SAFE_MODE BIT(4) +#define EUD_INT_ALL (EUD_INT_VBUS | EUD_INT_SAFE_MODE) + +struct eud_chip { + struct device *dev; + struct usb_role_switch *role_sw; + void __iomem *base; + void __iomem *mode_mgr; + unsigned int int_status; + int irq; + bool enabled; + bool usb_attached; +}; + +static int enable_eud(struct eud_chip *priv) +{ + writel(EUD_ENABLE, priv->base + EUD_REG_CSR_EUD_EN); + writel(EUD_INT_VBUS | EUD_INT_SAFE_MODE, + priv->base + EUD_REG_INT1_EN_MASK); + writel(1, priv->mode_mgr + EUD_REG_EUD_EN2); + + return usb_role_switch_set_role(priv->role_sw, USB_ROLE_DEVICE); +} + +static void disable_eud(struct eud_chip *priv) +{ + writel(0, priv->base + EUD_REG_CSR_EUD_EN); + writel(0, priv->mode_mgr + EUD_REG_EUD_EN2); +} + +static ssize_t enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct eud_chip *chip = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%d\n", chip->enabled); +} + +static ssize_t enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct eud_chip *chip = dev_get_drvdata(dev); + bool enable; + int ret; + + if (kstrtobool(buf, &enable)) + return -EINVAL; + + if (enable) { + ret = enable_eud(chip); + if (!ret) + chip->enabled = enable; + else + disable_eud(chip); + } else { + disable_eud(chip); + } + + return count; +} + +static DEVICE_ATTR_RW(enable); + +static struct attribute *eud_attrs[] = { + &dev_attr_enable.attr, + NULL, +}; +ATTRIBUTE_GROUPS(eud); + +static void usb_attach_detach(struct eud_chip *chip) +{ + u32 reg; + + /* read ctl_out_1[4] to find USB attach or detach event */ + reg = readl(chip->base + EUD_REG_CTL_OUT_1); + chip->usb_attached = reg & EUD_INT_SAFE_MODE; +} + +static void pet_eud(struct eud_chip *chip) +{ + u32 reg; + int ret; + + /* When the EUD_INT_PET_EUD in SW_ATTACH_DET is set, the cable has been + * disconnected and we need to detach the pet to check if EUD is in safe + * mode before attaching again. + */ + reg = readl(chip->base + EUD_REG_SW_ATTACH_DET); + if (reg & EUD_INT_PET_EUD) { + /* Detach & Attach pet for EUD */ + writel(0, chip->base + EUD_REG_SW_ATTACH_DET); + /* Delay to make sure detach pet is done before attach pet */ + ret = readl_poll_timeout(chip->base + EUD_REG_SW_ATTACH_DET, + reg, (reg == 0), 1, 100); + if (ret) { + dev_err(chip->dev, "Detach pet failed\n"); + return; + } + } + /* Attach pet for EUD */ + writel(EUD_INT_PET_EUD, chip->base + EUD_REG_SW_ATTACH_DET); +} + +static irqreturn_t handle_eud_irq(int irq, void *data) +{ + struct eud_chip *chip = data; + u32 reg; + + reg = readl(chip->base + EUD_REG_INT_STATUS_1); + switch (reg & EUD_INT_ALL) { + case EUD_INT_VBUS: + usb_attach_detach(chip); + return IRQ_WAKE_THREAD; + case EUD_INT_SAFE_MODE: + pet_eud(chip); + return IRQ_HANDLED; + default: + return IRQ_NONE; + } +} + +static irqreturn_t handle_eud_irq_thread(int irq, void *data) +{ + struct eud_chip *chip = data; + int ret; + + if (chip->usb_attached) + ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_DEVICE); + else + ret = usb_role_switch_set_role(chip->role_sw, USB_ROLE_HOST); + if (ret) + dev_err(chip->dev, "failed to set role switch\n"); + + /* set and clear vbus_int_clr[0] to clear interrupt */ + writel(BIT(0), chip->base + EUD_REG_VBUS_INT_CLR); + writel(0, chip->base + EUD_REG_VBUS_INT_CLR); + + return IRQ_HANDLED; +} + +static void eud_role_switch_release(void *data) +{ + struct eud_chip *chip = data; + + usb_role_switch_put(chip->role_sw); +} + +static int eud_probe(struct platform_device *pdev) +{ + struct eud_chip *chip; + int ret; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->dev = &pdev->dev; + + ret = devm_add_action_or_reset(chip->dev, eud_role_switch_release, chip); + if (ret) + return dev_err_probe(chip->dev, ret, + "failed to add role switch release action\n"); + + chip->role_sw = usb_role_switch_get(&pdev->dev); + if (IS_ERR(chip->role_sw)) + return dev_err_probe(chip->dev, PTR_ERR(chip->role_sw), + "failed to get role switch\n"); + + chip->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(chip->base)) + return PTR_ERR(chip->base); + + chip->mode_mgr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(chip->mode_mgr)) + return PTR_ERR(chip->mode_mgr); + + chip->irq = platform_get_irq(pdev, 0); + ret = devm_request_threaded_irq(&pdev->dev, chip->irq, handle_eud_irq, + handle_eud_irq_thread, IRQF_ONESHOT, NULL, chip); + if (ret) + return dev_err_probe(chip->dev, ret, "failed to allocate irq\n"); + + enable_irq_wake(chip->irq); + + platform_set_drvdata(pdev, chip); + + return 0; +} + +static int eud_remove(struct platform_device *pdev) +{ + struct eud_chip *chip = platform_get_drvdata(pdev); + + if (chip->enabled) + disable_eud(chip); + + device_init_wakeup(&pdev->dev, false); + disable_irq_wake(chip->irq); + + return 0; +} + +static const struct of_device_id eud_dt_match[] = { + { .compatible = "qcom,sc7280-eud" }, + { } +}; +MODULE_DEVICE_TABLE(of, eud_dt_match); + +static struct platform_driver eud_driver = { + .probe = eud_probe, + .remove = eud_remove, + .driver = { + .name = "qcom_eud", + .dev_groups = eud_groups, + .of_match_table = eud_dt_match, + }, +}; +module_platform_driver(eud_driver); + +MODULE_DESCRIPTION("QTI EUD driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/usb/serial/Kconfig b/drivers/usb/serial/Kconfig index de5c01257060..ef8d1c73c754 100644 --- a/drivers/usb/serial/Kconfig +++ b/drivers/usb/serial/Kconfig @@ -66,6 +66,7 @@ config USB_SERIAL_SIMPLE - Libtransistor USB console - a number of Motorola phones - Motorola Tetra devices + - Nokia mobile phones - Novatel Wireless GPS receivers - Siemens USB/MPI adapter. - ViVOtech ViVOpay USB device. diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c index a70fd86f735c..88b284d61681 100644 --- a/drivers/usb/serial/pl2303.c +++ b/drivers/usb/serial/pl2303.c @@ -116,6 +116,7 @@ static const struct usb_device_id id_table[] = { { USB_DEVICE(ADLINK_VENDOR_ID, ADLINK_ND6530GC_PRODUCT_ID) }, { USB_DEVICE(SMART_VENDOR_ID, SMART_PRODUCT_ID) }, { USB_DEVICE(AT_VENDOR_ID, AT_VTKIT3_PRODUCT_ID) }, + { USB_DEVICE(IBM_VENDOR_ID, IBM_PRODUCT_ID) }, { } /* Terminating entry */ }; @@ -435,6 +436,7 @@ static int pl2303_detect_type(struct usb_serial *serial) case 0x105: case 0x305: case 0x405: + case 0x605: /* * Assume it's an HXN-type if the device doesn't * support the old read request value. diff --git a/drivers/usb/serial/pl2303.h b/drivers/usb/serial/pl2303.h index 6097ee8fccb2..c5406452b774 100644 --- a/drivers/usb/serial/pl2303.h +++ b/drivers/usb/serial/pl2303.h @@ -35,6 +35,9 @@ #define ATEN_PRODUCT_UC232B 0x2022 #define ATEN_PRODUCT_ID2 0x2118 +#define IBM_VENDOR_ID 0x04b3 +#define IBM_PRODUCT_ID 0x4016 + #define IODATA_VENDOR_ID 0x04bb #define IODATA_PRODUCT_ID 0x0a03 #define IODATA_PRODUCT_ID_RSAQ5 0x0a0e diff --git a/drivers/usb/serial/usb-serial-simple.c b/drivers/usb/serial/usb-serial-simple.c index bd23a7cb1be2..4c6747889a19 100644 --- a/drivers/usb/serial/usb-serial-simple.c +++ b/drivers/usb/serial/usb-serial-simple.c @@ -91,6 +91,11 @@ DEVICE(moto_modem, MOTO_IDS); { USB_DEVICE(0x0cad, 0x9016) } /* TPG2200 */ DEVICE(motorola_tetra, MOTOROLA_TETRA_IDS); +/* Nokia mobile phone driver */ +#define NOKIA_IDS() \ + { USB_DEVICE(0x0421, 0x069a) } /* Nokia 130 (RM-1035) */ +DEVICE(nokia, NOKIA_IDS); + /* Novatel Wireless GPS driver */ #define NOVATEL_IDS() \ { USB_DEVICE(0x09d7, 0x0100) } /* NovAtel FlexPack GPS */ @@ -123,6 +128,7 @@ static struct usb_serial_driver * const serial_drivers[] = { &vivopay_device, &moto_modem_device, &motorola_tetra_device, + &nokia_device, &novatel_gps_device, &hp4x_device, &suunto_device, @@ -140,6 +146,7 @@ static const struct usb_device_id id_table[] = { VIVOPAY_IDS(), MOTO_IDS(), MOTOROLA_TETRA_IDS(), + NOKIA_IDS(), NOVATEL_IDS(), HP4X_IDS(), SUUNTO_IDS(), diff --git a/drivers/usb/serial/usb_wwan.c b/drivers/usb/serial/usb_wwan.c index cb01283d4d15..dab38b63eaf7 100644 --- a/drivers/usb/serial/usb_wwan.c +++ b/drivers/usb/serial/usb_wwan.c @@ -148,7 +148,6 @@ int usb_wwan_write(struct tty_struct *tty, struct usb_serial_port *port, dev_dbg(&port->dev, "%s: write (%d chars)\n", __func__, count); - i = 0; left = count; for (i = 0; left > 0 && i < N_OUT_URB; i++) { todo = left; diff --git a/drivers/usb/storage/ene_ub6250.c b/drivers/usb/storage/ene_ub6250.c index 5f7d678502be..6012603f3630 100644 --- a/drivers/usb/storage/ene_ub6250.c +++ b/drivers/usb/storage/ene_ub6250.c @@ -237,36 +237,33 @@ static struct us_unusual_dev ene_ub6250_unusual_dev_list[] = { #define memstick_logaddr(logadr1, logadr0) ((((u16)(logadr1)) << 8) | (logadr0)) -struct SD_STATUS { - u8 Insert:1; - u8 Ready:1; - u8 MediaChange:1; - u8 IsMMC:1; - u8 HiCapacity:1; - u8 HiSpeed:1; - u8 WtP:1; - u8 Reserved:1; -}; +/* SD_STATUS bits */ +#define SD_Insert BIT(0) +#define SD_Ready BIT(1) +#define SD_MediaChange BIT(2) +#define SD_IsMMC BIT(3) +#define SD_HiCapacity BIT(4) +#define SD_HiSpeed BIT(5) +#define SD_WtP BIT(6) + /* Bit 7 reserved */ -struct MS_STATUS { - u8 Insert:1; - u8 Ready:1; - u8 MediaChange:1; - u8 IsMSPro:1; - u8 IsMSPHG:1; - u8 Reserved1:1; - u8 WtP:1; - u8 Reserved2:1; -}; +/* MS_STATUS bits */ +#define MS_Insert BIT(0) +#define MS_Ready BIT(1) +#define MS_MediaChange BIT(2) +#define MS_IsMSPro BIT(3) +#define MS_IsMSPHG BIT(4) + /* Bit 5 reserved */ +#define MS_WtP BIT(6) + /* Bit 7 reserved */ -struct SM_STATUS { - u8 Insert:1; - u8 Ready:1; - u8 MediaChange:1; - u8 Reserved:3; - u8 WtP:1; - u8 IsMS:1; -}; +/* SM_STATUS bits */ +#define SM_Insert BIT(0) +#define SM_Ready BIT(1) +#define SM_MediaChange BIT(2) + /* Bits 3-5 reserved */ +#define SM_WtP BIT(6) +#define SM_IsMS BIT(7) struct ms_bootblock_cis { u8 bCistplDEVICE[6]; /* 0 */ @@ -437,9 +434,9 @@ struct ene_ub6250_info { u8 *bbuf; /* for 6250 code */ - struct SD_STATUS SD_Status; - struct MS_STATUS MS_Status; - struct SM_STATUS SM_Status; + u8 SD_Status; + u8 MS_Status; + u8 SM_Status; /* ----- SD Control Data ---------------- */ /*SD_REGISTER SD_Regs; */ @@ -602,7 +599,7 @@ static int sd_scsi_test_unit_ready(struct us_data *us, struct scsi_cmnd *srb) { struct ene_ub6250_info *info = (struct ene_ub6250_info *) us->extra; - if (info->SD_Status.Insert && info->SD_Status.Ready) + if ((info->SD_Status & SD_Insert) && (info->SD_Status & SD_Ready)) return USB_STOR_TRANSPORT_GOOD; else { ene_sd_init(us); @@ -622,7 +619,7 @@ static int sd_scsi_mode_sense(struct us_data *us, struct scsi_cmnd *srb) 0x0b, 0x00, 0x80, 0x08, 0x00, 0x00, 0x71, 0xc0, 0x00, 0x00, 0x02, 0x00 }; - if (info->SD_Status.WtP) + if (info->SD_Status & SD_WtP) usb_stor_set_xfer_buf(mediaWP, 12, srb); else usb_stor_set_xfer_buf(mediaNoWP, 12, srb); @@ -641,9 +638,9 @@ static int sd_scsi_read_capacity(struct us_data *us, struct scsi_cmnd *srb) struct ene_ub6250_info *info = (struct ene_ub6250_info *) us->extra; usb_stor_dbg(us, "sd_scsi_read_capacity\n"); - if (info->SD_Status.HiCapacity) { + if (info->SD_Status & SD_HiCapacity) { bl_len = 0x200; - if (info->SD_Status.IsMMC) + if (info->SD_Status & SD_IsMMC) bl_num = info->HC_C_SIZE-1; else bl_num = (info->HC_C_SIZE + 1) * 1024 - 1; @@ -693,7 +690,7 @@ static int sd_scsi_read(struct us_data *us, struct scsi_cmnd *srb) return USB_STOR_TRANSPORT_ERROR; } - if (info->SD_Status.HiCapacity) + if (info->SD_Status & SD_HiCapacity) bnByte = bn; /* set up the command wrapper */ @@ -733,7 +730,7 @@ static int sd_scsi_write(struct us_data *us, struct scsi_cmnd *srb) return USB_STOR_TRANSPORT_ERROR; } - if (info->SD_Status.HiCapacity) + if (info->SD_Status & SD_HiCapacity) bnByte = bn; /* set up the command wrapper */ @@ -1456,7 +1453,7 @@ static int ms_scsi_test_unit_ready(struct us_data *us, struct scsi_cmnd *srb) struct ene_ub6250_info *info = (struct ene_ub6250_info *)(us->extra); /* pr_info("MS_SCSI_Test_Unit_Ready\n"); */ - if (info->MS_Status.Insert && info->MS_Status.Ready) { + if ((info->MS_Status & MS_Insert) && (info->MS_Status & MS_Ready)) { return USB_STOR_TRANSPORT_GOOD; } else { ene_ms_init(us); @@ -1476,7 +1473,7 @@ static int ms_scsi_mode_sense(struct us_data *us, struct scsi_cmnd *srb) 0x0b, 0x00, 0x80, 0x08, 0x00, 0x00, 0x71, 0xc0, 0x00, 0x00, 0x02, 0x00 }; - if (info->MS_Status.WtP) + if (info->MS_Status & MS_WtP) usb_stor_set_xfer_buf(mediaWP, 12, srb); else usb_stor_set_xfer_buf(mediaNoWP, 12, srb); @@ -1495,7 +1492,7 @@ static int ms_scsi_read_capacity(struct us_data *us, struct scsi_cmnd *srb) usb_stor_dbg(us, "ms_scsi_read_capacity\n"); bl_len = 0x200; - if (info->MS_Status.IsMSPro) + if (info->MS_Status & MS_IsMSPro) bl_num = info->MSP_TotalBlock - 1; else bl_num = info->MS_Lib.NumberOfLogBlock * info->MS_Lib.blockSize * 2 - 1; @@ -1650,7 +1647,7 @@ static int ms_scsi_read(struct us_data *us, struct scsi_cmnd *srb) if (bn > info->bl_num) return USB_STOR_TRANSPORT_ERROR; - if (info->MS_Status.IsMSPro) { + if (info->MS_Status & MS_IsMSPro) { result = ene_load_bincode(us, MSP_RW_PATTERN); if (result != USB_STOR_XFER_GOOD) { usb_stor_dbg(us, "Load MPS RW pattern Fail !!\n"); @@ -1751,7 +1748,7 @@ static int ms_scsi_write(struct us_data *us, struct scsi_cmnd *srb) if (bn > info->bl_num) return USB_STOR_TRANSPORT_ERROR; - if (info->MS_Status.IsMSPro) { + if (info->MS_Status & MS_IsMSPro) { result = ene_load_bincode(us, MSP_RW_PATTERN); if (result != USB_STOR_XFER_GOOD) { pr_info("Load MSP RW pattern Fail !!\n"); @@ -1859,12 +1856,12 @@ static int ene_get_card_status(struct us_data *us, u8 *buf) tmpreg = (u16) reg4b; reg4b = *(u32 *)(&buf[0x14]); - if (info->SD_Status.HiCapacity && !info->SD_Status.IsMMC) + if ((info->SD_Status & SD_HiCapacity) && !(info->SD_Status & SD_IsMMC)) info->HC_C_SIZE = (reg4b >> 8) & 0x3fffff; info->SD_C_SIZE = ((tmpreg & 0x03) << 10) | (u16)(reg4b >> 22); info->SD_C_SIZE_MULT = (u8)(reg4b >> 7) & 0x07; - if (info->SD_Status.HiCapacity && info->SD_Status.IsMMC) + if ((info->SD_Status & SD_HiCapacity) && (info->SD_Status & SD_IsMMC)) info->HC_C_SIZE = *(u32 *)(&buf[0x100]); if (info->SD_READ_BL_LEN > SD_BLOCK_LEN) { @@ -2076,6 +2073,7 @@ static int ene_ms_init(struct us_data *us) u16 MSP_BlockSize, MSP_UserAreaBlocks; struct ene_ub6250_info *info = (struct ene_ub6250_info *) us->extra; u8 *bbuf = info->bbuf; + unsigned int s; printk(KERN_INFO "transport --- ENE_MSInit\n"); @@ -2100,15 +2098,16 @@ static int ene_ms_init(struct us_data *us) return USB_STOR_TRANSPORT_ERROR; } /* the same part to test ENE */ - info->MS_Status = *(struct MS_STATUS *) bbuf; + info->MS_Status = bbuf[0]; - if (info->MS_Status.Insert && info->MS_Status.Ready) { - printk(KERN_INFO "Insert = %x\n", info->MS_Status.Insert); - printk(KERN_INFO "Ready = %x\n", info->MS_Status.Ready); - printk(KERN_INFO "IsMSPro = %x\n", info->MS_Status.IsMSPro); - printk(KERN_INFO "IsMSPHG = %x\n", info->MS_Status.IsMSPHG); - printk(KERN_INFO "WtP= %x\n", info->MS_Status.WtP); - if (info->MS_Status.IsMSPro) { + s = info->MS_Status; + if ((s & MS_Insert) && (s & MS_Ready)) { + printk(KERN_INFO "Insert = %x\n", !!(s & MS_Insert)); + printk(KERN_INFO "Ready = %x\n", !!(s & MS_Ready)); + printk(KERN_INFO "IsMSPro = %x\n", !!(s & MS_IsMSPro)); + printk(KERN_INFO "IsMSPHG = %x\n", !!(s & MS_IsMSPHG)); + printk(KERN_INFO "WtP= %x\n", !!(s & MS_WtP)); + if (s & MS_IsMSPro) { MSP_BlockSize = (bbuf[6] << 8) | bbuf[7]; MSP_UserAreaBlocks = (bbuf[10] << 8) | bbuf[11]; info->MSP_TotalBlock = MSP_BlockSize * MSP_UserAreaBlocks; @@ -2169,17 +2168,17 @@ static int ene_sd_init(struct us_data *us) return USB_STOR_TRANSPORT_ERROR; } - info->SD_Status = *(struct SD_STATUS *) bbuf; - if (info->SD_Status.Insert && info->SD_Status.Ready) { - struct SD_STATUS *s = &info->SD_Status; + info->SD_Status = bbuf[0]; + if ((info->SD_Status & SD_Insert) && (info->SD_Status & SD_Ready)) { + unsigned int s = info->SD_Status; ene_get_card_status(us, bbuf); - usb_stor_dbg(us, "Insert = %x\n", s->Insert); - usb_stor_dbg(us, "Ready = %x\n", s->Ready); - usb_stor_dbg(us, "IsMMC = %x\n", s->IsMMC); - usb_stor_dbg(us, "HiCapacity = %x\n", s->HiCapacity); - usb_stor_dbg(us, "HiSpeed = %x\n", s->HiSpeed); - usb_stor_dbg(us, "WtP = %x\n", s->WtP); + usb_stor_dbg(us, "Insert = %x\n", !!(s & SD_Insert)); + usb_stor_dbg(us, "Ready = %x\n", !!(s & SD_Ready)); + usb_stor_dbg(us, "IsMMC = %x\n", !!(s & SD_IsMMC)); + usb_stor_dbg(us, "HiCapacity = %x\n", !!(s & SD_HiCapacity)); + usb_stor_dbg(us, "HiSpeed = %x\n", !!(s & SD_HiSpeed)); + usb_stor_dbg(us, "WtP = %x\n", !!(s & SD_WtP)); } else { usb_stor_dbg(us, "SD Card Not Ready --- %x\n", bbuf[0]); return USB_STOR_TRANSPORT_ERROR; @@ -2201,14 +2200,14 @@ static int ene_init(struct us_data *us) misc_reg03 = bbuf[0]; if (misc_reg03 & 0x01) { - if (!info->SD_Status.Ready) { + if (!(info->SD_Status & SD_Ready)) { result = ene_sd_init(us); if (result != USB_STOR_XFER_GOOD) return USB_STOR_TRANSPORT_ERROR; } } if (misc_reg03 & 0x02) { - if (!info->MS_Status.Ready) { + if (!(info->MS_Status & MS_Ready)) { result = ene_ms_init(us); if (result != USB_STOR_XFER_GOOD) return USB_STOR_TRANSPORT_ERROR; @@ -2307,14 +2306,14 @@ static int ene_transport(struct scsi_cmnd *srb, struct us_data *us) /*US_DEBUG(usb_stor_show_command(us, srb)); */ scsi_set_resid(srb, 0); - if (unlikely(!(info->SD_Status.Ready || info->MS_Status.Ready))) + if (unlikely(!(info->SD_Status & SD_Ready) || (info->MS_Status & MS_Ready))) result = ene_init(us); if (result == USB_STOR_XFER_GOOD) { result = USB_STOR_TRANSPORT_ERROR; - if (info->SD_Status.Ready) + if (info->SD_Status & SD_Ready) result = sd_scsi_irp(us, srb); - if (info->MS_Status.Ready) + if (info->MS_Status & MS_Ready) result = ms_scsi_irp(us, srb); } return result; @@ -2378,7 +2377,6 @@ static int ene_ub6250_probe(struct usb_interface *intf, static int ene_ub6250_resume(struct usb_interface *iface) { - u8 tmp = 0; struct us_data *us = usb_get_intfdata(iface); struct ene_ub6250_info *info = (struct ene_ub6250_info *)(us->extra); @@ -2390,17 +2388,16 @@ static int ene_ub6250_resume(struct usb_interface *iface) mutex_unlock(&us->dev_mutex); info->Power_IsResum = true; - /*info->SD_Status.Ready = 0; */ - info->SD_Status = *(struct SD_STATUS *)&tmp; - info->MS_Status = *(struct MS_STATUS *)&tmp; - info->SM_Status = *(struct SM_STATUS *)&tmp; + /* info->SD_Status &= ~SD_Ready; */ + info->SD_Status = 0; + info->MS_Status = 0; + info->SM_Status = 0; return 0; } static int ene_ub6250_reset_resume(struct usb_interface *iface) { - u8 tmp = 0; struct us_data *us = usb_get_intfdata(iface); struct ene_ub6250_info *info = (struct ene_ub6250_info *)(us->extra); @@ -2412,10 +2409,10 @@ static int ene_ub6250_reset_resume(struct usb_interface *iface) * the device */ info->Power_IsResum = true; - /*info->SD_Status.Ready = 0; */ - info->SD_Status = *(struct SD_STATUS *)&tmp; - info->MS_Status = *(struct MS_STATUS *)&tmp; - info->SM_Status = *(struct SM_STATUS *)&tmp; + /* info->SD_Status &= ~SD_Ready; */ + info->SD_Status = 0; + info->MS_Status = 0; + info->SM_Status = 0; return 0; } diff --git a/drivers/usb/storage/realtek_cr.c b/drivers/usb/storage/realtek_cr.c index 3789698d9d3c..0c423916d7bf 100644 --- a/drivers/usb/storage/realtek_cr.c +++ b/drivers/usb/storage/realtek_cr.c @@ -365,7 +365,7 @@ static int rts51x_read_mem(struct us_data *us, u16 addr, u8 *data, u16 len) buf = kmalloc(len, GFP_NOIO); if (buf == NULL) - return USB_STOR_TRANSPORT_ERROR; + return -ENOMEM; usb_stor_dbg(us, "addr = 0x%x, len = %d\n", addr, len); diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig index ab480f38523a..8f921213b17d 100644 --- a/drivers/usb/typec/Kconfig +++ b/drivers/usb/typec/Kconfig @@ -52,6 +52,18 @@ source "drivers/usb/typec/ucsi/Kconfig" source "drivers/usb/typec/tipd/Kconfig" +config TYPEC_RT1719 + tristate "Richtek RT1719 Sink Only Type-C controller driver" + depends on USB_ROLE_SWITCH || !USB_ROLE_SWITCH + depends on I2C + select REGMAP_I2C + help + Say Y or M here if your system has Richtek RT1719 sink only + Type-C port controller driver. + + If you choose to build this driver as a dynamically linked module, the + module will be called rt1719.ko + config TYPEC_HD3SS3220 tristate "TI HD3SS3220 Type-C DRP Port controller driver" depends on I2C @@ -88,6 +100,16 @@ config TYPEC_QCOM_PMIC It will also enable the VBUS output to connected devices when a DFP connection is made. +config TYPEC_WUSB3801 + tristate "Willsemi WUSB3801 Type-C port controller driver" + depends on I2C + select REGMAP_I2C + help + Say Y or M here if your system has a WUSB3801 Type-C port controller. + + If you choose to build this driver as a dynamically linked module, the + module will be called wusb3801.ko. + source "drivers/usb/typec/mux/Kconfig" source "drivers/usb/typec/altmodes/Kconfig" diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile index 57870a2bd787..43626acc0aaf 100644 --- a/drivers/usb/typec/Makefile +++ b/drivers/usb/typec/Makefile @@ -9,4 +9,6 @@ obj-$(CONFIG_TYPEC_TPS6598X) += tipd/ obj-$(CONFIG_TYPEC_HD3SS3220) += hd3ss3220.o obj-$(CONFIG_TYPEC_QCOM_PMIC) += qcom-pmic-typec.o obj-$(CONFIG_TYPEC_STUSB160X) += stusb160x.o +obj-$(CONFIG_TYPEC_RT1719) += rt1719.o +obj-$(CONFIG_TYPEC_WUSB3801) += wusb3801.o obj-$(CONFIG_TYPEC) += mux/ diff --git a/drivers/usb/typec/class.c b/drivers/usb/typec/class.c index 45a6f0c807cb..ee0e520707dd 100644 --- a/drivers/usb/typec/class.c +++ b/drivers/usb/typec/class.c @@ -1894,6 +1894,49 @@ void *typec_get_drvdata(struct typec_port *port) } EXPORT_SYMBOL_GPL(typec_get_drvdata); +int typec_get_fw_cap(struct typec_capability *cap, + struct fwnode_handle *fwnode) +{ + const char *cap_str; + int ret; + + cap->fwnode = fwnode; + + ret = fwnode_property_read_string(fwnode, "power-role", &cap_str); + if (ret < 0) + return ret; + + ret = typec_find_port_power_role(cap_str); + if (ret < 0) + return ret; + cap->type = ret; + + /* USB data support is optional */ + ret = fwnode_property_read_string(fwnode, "data-role", &cap_str); + if (ret == 0) { + ret = typec_find_port_data_role(cap_str); + if (ret < 0) + return ret; + cap->data = ret; + } + + /* Get the preferred power role for a DRP */ + if (cap->type == TYPEC_PORT_DRP) { + cap->prefer_role = TYPEC_NO_PREFERRED_ROLE; + + ret = fwnode_property_read_string(fwnode, "try-power-role", &cap_str); + if (ret == 0) { + ret = typec_find_power_role(cap_str); + if (ret < 0) + return ret; + cap->prefer_role = ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(typec_get_fw_cap); + /** * typec_port_register_altmode - Register USB Type-C Port Alternate Mode * @port: USB Type-C Port that supports the alternate mode diff --git a/drivers/usb/typec/rt1719.c b/drivers/usb/typec/rt1719.c new file mode 100644 index 000000000000..f1b698edd7eb --- /dev/null +++ b/drivers/usb/typec/rt1719.c @@ -0,0 +1,961 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RT1719_REG_TXCTRL1 0x03 +#define RT1719_REG_TXCTRL2 0x04 +#define RT1719_REG_POLICYINFO 0x0E +#define RT1719_REG_SRCPDO1 0x11 +#define RT1719_REG_MASKS 0x2D +#define RT1719_REG_EVENTS 0x33 +#define RT1719_REG_STATS 0x37 +#define RT1719_REG_PSELINFO 0x3C +#define RT1719_REG_USBSETINFO 0x3E +#define RT1719_REG_VENID 0x82 + +#define RT1719_UNIQUE_PID 0x1719 +#define RT1719_REQDRSWAP_MASK BIT(7) +#define RT1719_EVALMODE_MASK BIT(4) +#define RT1719_REQSRCPDO_MASK GENMASK(2, 0) +#define RT1719_TXSPDOREQ_MASK BIT(7) +#define RT1719_INT_DRSW_ACCEPT BIT(23) +#define RT1719_INT_RX_SRCCAP BIT(21) +#define RT1719_INT_VBUS_DCT BIT(6) +#define RT1719_INT_VBUS_PRESENT BIT(5) +#define RT1719_INT_PE_SNK_RDY BIT(2) +#define RT1719_CC1_STAT GENMASK(9, 8) +#define RT1719_CC2_STAT GENMASK(11, 10) +#define RT1719_POLARITY_MASK BIT(23) +#define RT1719_DATAROLE_MASK BIT(22) +#define RT1719_PDSPECREV_MASK GENMASK(21, 20) +#define RT1719_SPDOSEL_MASK GENMASK(18, 16) +#define RT1719_SPDONUM_MASK GENMASK(15, 13) +#define RT1719_ATTACH_VBUS BIT(12) +#define RT1719_ATTACH_DBG BIT(10) +#define RT1719_ATTACH_SNK BIT(9) +#define RT1719_ATTACHDEV_MASK (RT1719_ATTACH_VBUS | RT1719_ATTACH_DBG | \ + RT1719_ATTACH_SNK) +#define RT1719_PE_EXP_CONTRACT BIT(2) +#define RT1719_PSEL_SUPPORT BIT(15) +#define RT1719_TBLSEL_MASK BIT(6) +#define RT1719_LATPSEL_MASK GENMASK(5, 0) +#define RT1719_USBINFO_MASK GENMASK(1, 0) +#define RT1719_USB_DFPUFP 3 +#define RT1719_MAX_SRCPDO 7 + +enum { + SNK_PWR_OPEN = 0, + SNK_PWR_DEF, + SNK_PWR_1P5A, + SNK_PWR_3A +}; + +enum { + USBPD_SPECREV_1_0 = 0, + USBPD_SPECREV_2_0, + USBPD_SPECREV_3_0 +}; + +enum rt1719_snkcap { + RT1719_SNKCAP_5V = 0, + RT1719_SNKCAP_9V, + RT1719_SNKCAP_12V, + RT1719_SNKCAP_15V, + RT1719_SNKCAP_20V, + RT1719_MAX_SNKCAP +}; + +struct rt1719_psel_cap { + u8 lomask; + u8 himask; + u32 milliwatt; + u32 milliamp; +}; + +struct rt1719_data { + struct device *dev; + struct regmap *regmap; + struct typec_port *port; + struct usb_role_switch *role_sw; + struct power_supply *psy; + struct typec_partner *partner; + struct power_supply_desc psy_desc; + struct usb_pd_identity partner_ident; + struct typec_partner_desc partner_desc; + struct completion req_completion; + enum power_supply_usb_type usb_type; + bool attached; + bool pd_capable; + bool drswap_support; + u32 voltage; + u32 req_voltage; + u32 max_current; + u32 op_current; + u32 spdos[RT1719_MAX_SRCPDO]; + u16 snkcaps[RT1719_MAX_SNKCAP]; + int spdo_num; + int spdo_sel; + u32 conn_info; + u16 conn_stat; +}; + +static const enum power_supply_usb_type rt1719_psy_usb_types[] = { + POWER_SUPPLY_USB_TYPE_C, + POWER_SUPPLY_USB_TYPE_PD, + POWER_SUPPLY_USB_TYPE_PD_PPS +}; + +static const enum power_supply_property rt1719_psy_properties[] = { + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_USB_TYPE, + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_CURRENT_MAX, + POWER_SUPPLY_PROP_CURRENT_NOW +}; + +static int rt1719_read16(struct rt1719_data *data, unsigned int reg, u16 *val) +{ + __le16 regval; + int ret; + + ret = regmap_raw_read(data->regmap, reg, ®val, sizeof(regval)); + if (ret) + return ret; + + *val = le16_to_cpu(regval); + return 0; +} + +static int rt1719_read32(struct rt1719_data *data, unsigned int reg, u32 *val) +{ + __le32 regval; + int ret; + + ret = regmap_raw_read(data->regmap, reg, ®val, sizeof(regval)); + if (ret) + return ret; + + *val = le32_to_cpu(regval); + return 0; +} + +static int rt1719_write32(struct rt1719_data *data, unsigned int reg, u32 val) +{ + __le32 regval = cpu_to_le32(val); + + return regmap_raw_write(data->regmap, reg, ®val, sizeof(regval)); +} + +static enum typec_pwr_opmode rt1719_get_pwr_opmode(u32 conn, u16 stat) +{ + u16 cc1, cc2, cc_stat; + + cc1 = FIELD_GET(RT1719_CC1_STAT, stat); + cc2 = FIELD_GET(RT1719_CC2_STAT, stat); + + if (conn & RT1719_ATTACH_SNK) { + if (conn & RT1719_POLARITY_MASK) + cc_stat = cc2; + else + cc_stat = cc1; + + switch (cc_stat) { + case SNK_PWR_3A: + return TYPEC_PWR_MODE_3_0A; + case SNK_PWR_1P5A: + return TYPEC_PWR_MODE_1_5A; + } + } else if (conn & RT1719_ATTACH_DBG) { + if ((cc1 == SNK_PWR_1P5A && cc2 == SNK_PWR_DEF) || + (cc1 == SNK_PWR_DEF && cc2 == SNK_PWR_1P5A)) + return TYPEC_PWR_MODE_1_5A; + else if ((cc1 == SNK_PWR_3A && cc2 == SNK_PWR_DEF) || + (cc1 == SNK_PWR_DEF && cc2 == SNK_PWR_3A)) + return TYPEC_PWR_MODE_3_0A; + } + + return TYPEC_PWR_MODE_USB; +} + +static enum typec_data_role rt1719_get_data_role(u32 conn) +{ + if (conn & RT1719_DATAROLE_MASK) + return TYPEC_HOST; + return TYPEC_DEVICE; +} + +static void rt1719_set_data_role(struct rt1719_data *data, + enum typec_data_role data_role, + bool attached) +{ + enum usb_role usb_role = USB_ROLE_NONE; + + if (attached) { + if (data_role == TYPEC_HOST) + usb_role = USB_ROLE_HOST; + else + usb_role = USB_ROLE_DEVICE; + } + + usb_role_switch_set_role(data->role_sw, usb_role); + typec_set_data_role(data->port, data_role); +} + +static void rt1719_update_data_role(struct rt1719_data *data) +{ + if (!data->attached) + return; + + rt1719_set_data_role(data, rt1719_get_data_role(data->conn_info), true); +} + +static void rt1719_register_partner(struct rt1719_data *data) +{ + u16 spec_rev = 0; + + if (data->pd_capable) { + u32 rev; + + rev = FIELD_GET(RT1719_PDSPECREV_MASK, data->conn_info); + switch (rev) { + case USBPD_SPECREV_3_0: + spec_rev = 0x0300; + break; + case USBPD_SPECREV_2_0: + spec_rev = 0x0200; + break; + default: + spec_rev = 0x0100; + break; + } + } + + /* Just to prevent multiple times attach */ + if (data->partner) + typec_unregister_partner(data->partner); + + memset(&data->partner_ident, 0, sizeof(data->partner_ident)); + data->partner_desc.usb_pd = data->pd_capable; + data->partner_desc.pd_revision = spec_rev; + + if (data->conn_info & RT1719_ATTACH_DBG) + data->partner_desc.accessory = TYPEC_ACCESSORY_DEBUG; + else + data->partner_desc.accessory = TYPEC_ACCESSORY_NONE; + + data->partner = typec_register_partner(data->port, &data->partner_desc); +} + +static void rt1719_attach(struct rt1719_data *data) +{ + enum typec_pwr_opmode pwr_opmode; + enum typec_data_role data_role; + u32 volt = 5000, curr = 500; + + if (!(data->conn_info & RT1719_ATTACHDEV_MASK)) + return; + + pwr_opmode = rt1719_get_pwr_opmode(data->conn_info, data->conn_stat); + data_role = rt1719_get_data_role(data->conn_info); + + typec_set_pwr_opmode(data->port, pwr_opmode); + rt1719_set_data_role(data, data_role, true); + + if (data->conn_info & RT1719_ATTACH_SNK) + rt1719_register_partner(data); + + if (pwr_opmode == TYPEC_PWR_MODE_3_0A) + curr = 3000; + else if (pwr_opmode == TYPEC_PWR_MODE_1_5A) + curr = 1500; + + data->voltage = volt * 1000; + data->max_current = data->op_current = curr * 1000; + data->attached = true; + + power_supply_changed(data->psy); +} + +static void rt1719_detach(struct rt1719_data *data) +{ + if (!data->attached || (data->conn_info & RT1719_ATTACHDEV_MASK)) + return; + + typec_unregister_partner(data->partner); + data->partner = NULL; + + typec_set_pwr_opmode(data->port, TYPEC_PWR_MODE_USB); + rt1719_set_data_role(data, TYPEC_DEVICE, false); + + memset32(data->spdos, 0, RT1719_MAX_SRCPDO); + data->spdo_num = 0; + data->voltage = data->max_current = data->op_current = 0; + data->attached = data->pd_capable = false; + + data->usb_type = POWER_SUPPLY_USB_TYPE_C; + + power_supply_changed(data->psy); +} + +static void rt1719_update_operating_status(struct rt1719_data *data) +{ + enum power_supply_usb_type usb_type = POWER_SUPPLY_USB_TYPE_PD; + u32 voltage, max_current, op_current; + int i, snk_sel; + + for (i = 0; i < data->spdo_num; i++) { + u32 pdo = data->spdos[i]; + enum pd_pdo_type type = pdo_type(pdo); + + if (type == PDO_TYPE_APDO) { + usb_type = POWER_SUPPLY_USB_TYPE_PD_PPS; + break; + } + } + + data->spdo_sel = FIELD_GET(RT1719_SPDOSEL_MASK, data->conn_info); + if (data->spdo_sel <= 0) + return; + + data->usb_type = usb_type; + + voltage = pdo_fixed_voltage(data->spdos[data->spdo_sel - 1]); + max_current = pdo_max_current(data->spdos[data->spdo_sel - 1]); + + switch (voltage) { + case 5000: + snk_sel = RT1719_SNKCAP_5V; + break; + case 9000: + snk_sel = RT1719_SNKCAP_9V; + break; + case 12000: + snk_sel = RT1719_SNKCAP_12V; + break; + case 15000: + snk_sel = RT1719_SNKCAP_15V; + break; + case 20000: + snk_sel = RT1719_SNKCAP_20V; + break; + default: + return; + } + + op_current = min(max_current, pdo_max_current(data->snkcaps[snk_sel])); + + /* covert mV/mA to uV/uA */ + data->voltage = voltage * 1000; + data->max_current = max_current * 1000; + data->op_current = op_current * 1000; + + power_supply_changed(data->psy); +} + +static void rt1719_update_pwr_opmode(struct rt1719_data *data) +{ + if (!data->attached) + return; + + if (!data->pd_capable) { + data->pd_capable = true; + + typec_set_pwr_opmode(data->port, TYPEC_PWR_MODE_PD); + rt1719_register_partner(data); + } + + rt1719_update_operating_status(data); +} + +static void rt1719_update_source_pdos(struct rt1719_data *data) +{ + int spdo_num = FIELD_GET(RT1719_SPDONUM_MASK, data->conn_info); + __le32 src_pdos[RT1719_MAX_SRCPDO] = { }; + int i, ret; + + if (!data->attached) + return; + + ret = regmap_raw_read(data->regmap, RT1719_REG_SRCPDO1, src_pdos, + sizeof(__le32) * spdo_num); + if (ret) + return; + + data->spdo_num = spdo_num; + for (i = 0; i < spdo_num; i++) + data->spdos[i] = le32_to_cpu(src_pdos[i]); +} + +static int rt1719_dr_set(struct typec_port *port, enum typec_data_role role) +{ + struct rt1719_data *data = typec_get_drvdata(port); + enum typec_data_role cur_role; + int ret; + + if (!data->attached || !data->pd_capable || !data->drswap_support) + return -EOPNOTSUPP; + + if (data->spdo_num > 0 && !(data->spdos[0] & PDO_FIXED_DATA_SWAP)) + return -EINVAL; + + cur_role = rt1719_get_data_role(data->conn_info); + if (cur_role == role) + return 0; + + ret = regmap_update_bits(data->regmap, RT1719_REG_TXCTRL1, + RT1719_REQDRSWAP_MASK, RT1719_REQDRSWAP_MASK); + if (ret) + return ret; + + reinit_completion(&data->req_completion); + ret = wait_for_completion_timeout(&data->req_completion, + msecs_to_jiffies(400)); + if (ret == 0) + return -ETIMEDOUT; + + cur_role = rt1719_get_data_role(data->conn_info); + if (cur_role != role) + return -EAGAIN; + + rt1719_set_data_role(data, role, true); + return 0; +} + +static const struct typec_operations rt1719_port_ops = { + .dr_set = rt1719_dr_set, +}; + +static int rt1719_usbpd_request_voltage(struct rt1719_data *data) +{ + u32 src_voltage; + int snk_sel, src_sel = -1; + int i, ret; + + if (!data->attached || !data->pd_capable || data->spdo_sel <= 0) + return -EINVAL; + + src_voltage = pdo_fixed_voltage(data->spdos[data->spdo_sel - 1]); + if (src_voltage == data->req_voltage) + return 0; + + switch (data->req_voltage) { + case 5000: + snk_sel = RT1719_SNKCAP_5V; + break; + case 9000: + snk_sel = RT1719_SNKCAP_9V; + break; + case 12000: + snk_sel = RT1719_SNKCAP_12V; + break; + case 15000: + snk_sel = RT1719_SNKCAP_15V; + break; + case 20000: + snk_sel = RT1719_SNKCAP_20V; + break; + default: + return -EINVAL; + } + + if (!(data->snkcaps[snk_sel] & RT1719_PSEL_SUPPORT)) + return -EINVAL; + + for (i = 0; i < data->spdo_num; i++) { + enum pd_pdo_type type = pdo_type(data->spdos[i]); + + if (type != PDO_TYPE_FIXED) + continue; + + src_voltage = pdo_fixed_voltage(data->spdos[i]); + if (src_voltage == data->req_voltage) { + src_sel = i; + break; + } + } + + if (src_sel == -1) + return -EOPNOTSUPP; + + ret = regmap_update_bits(data->regmap, RT1719_REG_TXCTRL1, + RT1719_EVALMODE_MASK | RT1719_REQSRCPDO_MASK, + RT1719_EVALMODE_MASK | (src_sel + 1)); + ret |= regmap_update_bits(data->regmap, RT1719_REG_TXCTRL2, + RT1719_TXSPDOREQ_MASK, RT1719_TXSPDOREQ_MASK); + if (ret) + return ret; + + reinit_completion(&data->req_completion); + ret = wait_for_completion_timeout(&data->req_completion, + msecs_to_jiffies(400)); + if (!ret) + return -ETIMEDOUT; + + return 0; +} + +static int rt1719_psy_set_property(struct power_supply *psy, + enum power_supply_property psp, + const union power_supply_propval *val) +{ + struct rt1719_data *data = power_supply_get_drvdata(psy); + + if (psp == POWER_SUPPLY_PROP_VOLTAGE_NOW) { + data->req_voltage = val->intval / 1000; + return rt1719_usbpd_request_voltage(data); + } + + return -EINVAL; +} + +static int rt1719_psy_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct rt1719_data *data = power_supply_get_drvdata(psy); + int ret = 0; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + val->intval = data->attached ? 1 : 0; + break; + case POWER_SUPPLY_PROP_USB_TYPE: + val->intval = data->usb_type; + break; + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + val->intval = data->voltage; + break; + case POWER_SUPPLY_PROP_CURRENT_MAX: + val->intval = data->max_current; + break; + case POWER_SUPPLY_PROP_CURRENT_NOW: + val->intval = data->op_current; + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int rt1719_psy_property_is_writeable(struct power_supply *psy, + enum power_supply_property psp) +{ + if (psp == POWER_SUPPLY_PROP_VOLTAGE_NOW) + return 1; + return 0; +} + +static int devm_rt1719_psy_register(struct rt1719_data *data) +{ + struct power_supply_config psy_cfg = { }; + char *psy_name; + + psy_cfg.fwnode = dev_fwnode(data->dev); + psy_cfg.drv_data = data; + + psy_name = devm_kasprintf(data->dev, GFP_KERNEL, "rt1719-source-psy-%s", + dev_name(data->dev)); + if (!psy_name) + return -ENOMEM; + + data->psy_desc.name = psy_name; + data->psy_desc.type = POWER_SUPPLY_TYPE_USB; + data->psy_desc.usb_types = rt1719_psy_usb_types; + data->psy_desc.num_usb_types = ARRAY_SIZE(rt1719_psy_usb_types); + data->psy_desc.properties = rt1719_psy_properties; + data->psy_desc.num_properties = ARRAY_SIZE(rt1719_psy_properties); + data->psy_desc.get_property = rt1719_psy_get_property; + data->psy_desc.set_property = rt1719_psy_set_property; + data->psy_desc.property_is_writeable = rt1719_psy_property_is_writeable; + + data->usb_type = POWER_SUPPLY_USB_TYPE_C; + + data->psy = devm_power_supply_register(data->dev, &data->psy_desc, + &psy_cfg); + + return PTR_ERR_OR_ZERO(data->psy); +} + +static irqreturn_t rt1719_irq_handler(int irq, void *priv) +{ + struct rt1719_data *data = priv; + u32 events, conn_info; + u16 conn_stat; + int ret; + + ret = rt1719_read32(data, RT1719_REG_EVENTS, &events); + ret |= rt1719_read32(data, RT1719_REG_POLICYINFO, &conn_info); + ret |= rt1719_read16(data, RT1719_REG_STATS, &conn_stat); + if (ret) + return IRQ_NONE; + + data->conn_info = conn_info; + data->conn_stat = conn_stat; + + events &= (RT1719_INT_DRSW_ACCEPT | RT1719_INT_RX_SRCCAP | + RT1719_INT_VBUS_PRESENT | RT1719_INT_VBUS_DCT | + RT1719_INT_PE_SNK_RDY); + + if (events & RT1719_INT_DRSW_ACCEPT) + rt1719_update_data_role(data); + + if (events & RT1719_INT_VBUS_PRESENT) + rt1719_attach(data); + + if (events & RT1719_INT_VBUS_DCT) + rt1719_detach(data); + + if (events & RT1719_INT_RX_SRCCAP) + rt1719_update_source_pdos(data); + + if (events & RT1719_INT_PE_SNK_RDY) { + complete(&data->req_completion); + rt1719_update_pwr_opmode(data); + } + + /* Write 1 to clear already handled events */ + rt1719_write32(data, RT1719_REG_EVENTS, events); + + return IRQ_HANDLED; +} + +static int rt1719_irq_init(struct rt1719_data *data) +{ + struct i2c_client *i2c = to_i2c_client(data->dev); + u32 irq_enable; + int ret; + + irq_enable = RT1719_INT_DRSW_ACCEPT | RT1719_INT_RX_SRCCAP | + RT1719_INT_VBUS_DCT | RT1719_INT_VBUS_PRESENT | + RT1719_INT_PE_SNK_RDY; + + ret = rt1719_write32(data, RT1719_REG_MASKS, irq_enable); + if (ret) { + dev_err(&i2c->dev, "Failed to config irq enable\n"); + return ret; + } + + return devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, + rt1719_irq_handler, IRQF_ONESHOT, + dev_name(&i2c->dev), data); +} + +static int rt1719_init_attach_state(struct rt1719_data *data) +{ + u32 conn_info, irq_clear; + u16 conn_stat; + int ret; + + irq_clear = RT1719_INT_DRSW_ACCEPT | RT1719_INT_RX_SRCCAP | + RT1719_INT_VBUS_DCT | RT1719_INT_VBUS_PRESENT | + RT1719_INT_PE_SNK_RDY; + + ret = rt1719_read32(data, RT1719_REG_POLICYINFO, &conn_info); + ret |= rt1719_read16(data, RT1719_REG_STATS, &conn_stat); + ret |= rt1719_write32(data, RT1719_REG_EVENTS, irq_clear); + if (ret) + return ret; + + data->conn_info = conn_info; + data->conn_stat = conn_stat; + + if (conn_info & RT1719_ATTACHDEV_MASK) + rt1719_attach(data); + + if (conn_info & RT1719_PE_EXP_CONTRACT) { + rt1719_update_source_pdos(data); + rt1719_update_pwr_opmode(data); + } + + return 0; +} + +#define RT1719_PSEL_CAPINFO(_lomask, _milliwatt, _himask, _milliamp) { \ + .lomask = _lomask, \ + .milliwatt = _milliwatt, \ + .himask = _himask, \ + .milliamp = _milliamp, \ +} + +static const struct rt1719_psel_cap rt1719_psel_caps[] = { + RT1719_PSEL_CAPINFO(0x18, 75000, 0x10, 5000), + RT1719_PSEL_CAPINFO(0x18, 60000, 0x10, 4500), + RT1719_PSEL_CAPINFO(0x18, 45000, 0x10, 4000), + RT1719_PSEL_CAPINFO(0x18, 30000, 0x10, 3500), + RT1719_PSEL_CAPINFO(0x18, 25000, 0x10, 3000), + RT1719_PSEL_CAPINFO(0x18, 20000, 0x10, 2500), + RT1719_PSEL_CAPINFO(0x18, 15000, 0x10, 2000), + RT1719_PSEL_CAPINFO(0x18, 10000, 0x10, 1000), + RT1719_PSEL_CAPINFO(0x1C, 60000, 0x1F, 5000), + RT1719_PSEL_CAPINFO(0x1C, 45000, 0x1F, 4500), + RT1719_PSEL_CAPINFO(0x1C, 30000, 0x1F, 4000), + RT1719_PSEL_CAPINFO(0x1C, 24000, 0x1F, 3500), + RT1719_PSEL_CAPINFO(0x1C, 15000, 0x1F, 3000), + RT1719_PSEL_CAPINFO(0x1C, 10000, 0x1F, 2500), + RT1719_PSEL_CAPINFO(0x0C, 60000, 0x1F, 2000), + RT1719_PSEL_CAPINFO(0x0C, 45000, 0x1F, 1000), + RT1719_PSEL_CAPINFO(0x0C, 36000, 0x08, 5000), + RT1719_PSEL_CAPINFO(0x0C, 30000, 0x08, 4500), + RT1719_PSEL_CAPINFO(0x0C, 24000, 0x08, 4000), + RT1719_PSEL_CAPINFO(0x0C, 15000, 0x08, 3500), + RT1719_PSEL_CAPINFO(0x0C, 10000, 0x08, 3000), + RT1719_PSEL_CAPINFO(0x1E, 45000, 0x08, 2500), + RT1719_PSEL_CAPINFO(0x1E, 36000, 0x08, 2000), + RT1719_PSEL_CAPINFO(0x1E, 27000, 0x08, 1500), + RT1719_PSEL_CAPINFO(0x1E, 20000, 0x08, 1000), + RT1719_PSEL_CAPINFO(0x1E, 15000, 0x0F, 5000), + RT1719_PSEL_CAPINFO(0x1E, 9000, 0x0F, 4500), + RT1719_PSEL_CAPINFO(0x0E, 45000, 0x0F, 4000), + RT1719_PSEL_CAPINFO(0x0E, 36000, 0x0F, 3500), + RT1719_PSEL_CAPINFO(0x0E, 27000, 0x0F, 3000), + RT1719_PSEL_CAPINFO(0x0E, 20000, 0x0F, 2500), + RT1719_PSEL_CAPINFO(0x0E, 15000, 0x0F, 2000), + RT1719_PSEL_CAPINFO(0x0E, 9000, 0x0F, 1500), + RT1719_PSEL_CAPINFO(0x06, 45000, 0x0F, 1000), + RT1719_PSEL_CAPINFO(0x06, 36000, 0x0F, 500), + RT1719_PSEL_CAPINFO(0x06, 27000, 0x04, 5000), + RT1719_PSEL_CAPINFO(0x06, 24000, 0x04, 4500), + RT1719_PSEL_CAPINFO(0x06, 18000, 0x04, 4000), + RT1719_PSEL_CAPINFO(0x06, 12000, 0x04, 3500), + RT1719_PSEL_CAPINFO(0x06, 9000, 0x04, 3000), + RT1719_PSEL_CAPINFO(0x1F, 25000, 0x04, 2500), + RT1719_PSEL_CAPINFO(0x1F, 20000, 0x04, 2000), + RT1719_PSEL_CAPINFO(0x1F, 15000, 0x04, 1500), + RT1719_PSEL_CAPINFO(0x1F, 10000, 0x04, 1000), + RT1719_PSEL_CAPINFO(0x1F, 7500, 0x07, 5000), + RT1719_PSEL_CAPINFO(0x0F, 25000, 0x07, 4500), + RT1719_PSEL_CAPINFO(0x0F, 20000, 0x07, 4000), + RT1719_PSEL_CAPINFO(0x0F, 15000, 0x07, 3500), + RT1719_PSEL_CAPINFO(0x0F, 10000, 0x07, 3000), + RT1719_PSEL_CAPINFO(0x0F, 7500, 0x07, 2500), + RT1719_PSEL_CAPINFO(0x07, 25000, 0x07, 2000), + RT1719_PSEL_CAPINFO(0x07, 20000, 0x07, 1500), + RT1719_PSEL_CAPINFO(0x07, 15000, 0x07, 1000), + RT1719_PSEL_CAPINFO(0x07, 10000, 0x07, 500), + RT1719_PSEL_CAPINFO(0x07, 7500, 0x03, 5000), + RT1719_PSEL_CAPINFO(0x03, 25000, 0x03, 4500), + RT1719_PSEL_CAPINFO(0x03, 20000, 0x03, 4000), + RT1719_PSEL_CAPINFO(0x03, 15000, 0x03, 3500), + RT1719_PSEL_CAPINFO(0x03, 10000, 0x03, 3000), + RT1719_PSEL_CAPINFO(0x03, 7500, 0x03, 2500), + RT1719_PSEL_CAPINFO(0x01, 15000, 0x03, 2000), + RT1719_PSEL_CAPINFO(0x01, 10000, 0x03, 1500), + RT1719_PSEL_CAPINFO(0x01, 7500, 0x03, 1000), + RT1719_PSEL_CAPINFO(0x01, 2500, 0x03, 500) +}; + +static u16 rt1719_gen_snkcap_by_current(const struct rt1719_psel_cap *psel_cap, + enum rt1719_snkcap capsel) +{ + u16 cap = RT1719_PSEL_SUPPORT; + + if (!(psel_cap->himask & BIT(capsel))) + return 0; + + cap |= psel_cap->milliamp / 10; + return cap; +} + +static u16 rt1719_gen_snkcap_by_watt(const struct rt1719_psel_cap *psel_cap, + enum rt1719_snkcap capsel) +{ + u32 volt_div[RT1719_MAX_SNKCAP] = { 5, 9, 12, 15, 20 }; + u16 cap = RT1719_PSEL_SUPPORT; + + if (!(psel_cap->lomask & BIT(capsel))) + return 0; + + cap |= min(psel_cap->milliwatt / volt_div[capsel], (u32)5000) / 10; + return cap; +} + +static u16 rt1719_gen_snkcap(unsigned int pselinfo, enum rt1719_snkcap capsel) +{ + int psel = FIELD_GET(RT1719_LATPSEL_MASK, pselinfo); + const struct rt1719_psel_cap *psel_cap; + bool by_current = false; + + if (pselinfo & RT1719_TBLSEL_MASK) + by_current = true; + + psel_cap = rt1719_psel_caps + psel; + if (by_current) + return rt1719_gen_snkcap_by_current(psel_cap, capsel); + + return rt1719_gen_snkcap_by_watt(psel_cap, capsel); +} + +static int rt1719_get_caps(struct rt1719_data *data) +{ + unsigned int pselinfo, usbinfo; + int i, ret; + + ret = regmap_read(data->regmap, RT1719_REG_PSELINFO, &pselinfo); + ret |= regmap_read(data->regmap, RT1719_REG_USBSETINFO, &usbinfo); + if (ret) + return ret; + + for (i = 0; i < RT1719_MAX_SNKCAP; i++) + data->snkcaps[i] = rt1719_gen_snkcap(pselinfo, i); + + usbinfo = FIELD_GET(RT1719_USBINFO_MASK, usbinfo); + if (usbinfo == RT1719_USB_DFPUFP) + data->drswap_support = true; + + return 0; +} + +static int rt1719_check_exist(struct rt1719_data *data) +{ + u16 pid; + int ret; + + ret = rt1719_read16(data, RT1719_REG_VENID, &pid); + if (ret) + return ret; + + if (pid != RT1719_UNIQUE_PID) { + dev_err(data->dev, "Incorrect PID 0x%04x\n", pid); + return -ENODEV; + } + + return 0; +} + +static const struct regmap_config rt1719_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff, +}; + +static int rt1719_probe(struct i2c_client *i2c) +{ + struct rt1719_data *data; + struct fwnode_handle *fwnode; + struct typec_capability typec_cap = { }; + int ret; + + data = devm_kzalloc(&i2c->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->dev = &i2c->dev; + init_completion(&data->req_completion); + + data->regmap = devm_regmap_init_i2c(i2c, &rt1719_regmap_config); + if (IS_ERR(data->regmap)) { + ret = PTR_ERR(data->regmap); + dev_err(&i2c->dev, "Failed to init regmap (%d)\n", ret); + return ret; + } + + ret = rt1719_check_exist(data); + if (ret) + return ret; + + ret = rt1719_get_caps(data); + if (ret) + return ret; + + fwnode = device_get_named_child_node(&i2c->dev, "connector"); + if (!fwnode) + return -ENODEV; + + data->role_sw = fwnode_usb_role_switch_get(fwnode); + if (IS_ERR(data->role_sw)) { + ret = PTR_ERR(data->role_sw); + dev_err(&i2c->dev, "Failed to get usb role switch (%d)\n", ret); + goto err_fwnode_put; + } + + ret = devm_rt1719_psy_register(data); + if (ret) { + dev_err(&i2c->dev, "Failed to register psy (%d)\n", ret); + goto err_role_put; + } + + typec_cap.revision = USB_TYPEC_REV_1_2; + typec_cap.pd_revision = 0x300; /* USB-PD spec release 3.0 */ + typec_cap.type = TYPEC_PORT_SNK; + typec_cap.data = TYPEC_PORT_DRD; + typec_cap.ops = &rt1719_port_ops; + typec_cap.fwnode = fwnode; + typec_cap.driver_data = data; + typec_cap.accessory[0] = TYPEC_ACCESSORY_DEBUG; + + data->partner_desc.identity = &data->partner_ident; + + data->port = typec_register_port(&i2c->dev, &typec_cap); + if (IS_ERR(data->port)) { + ret = PTR_ERR(data->port); + dev_err(&i2c->dev, "Failed to register typec port (%d)\n", ret); + goto err_role_put; + } + + ret = rt1719_init_attach_state(data); + if (ret) { + dev_err(&i2c->dev, "Failed to init attach state (%d)\n", ret); + goto err_role_put; + } + + ret = rt1719_irq_init(data); + if (ret) { + dev_err(&i2c->dev, "Failed to init irq\n"); + goto err_role_put; + } + + fwnode_handle_put(fwnode); + + i2c_set_clientdata(i2c, data); + + return 0; + +err_role_put: + usb_role_switch_put(data->role_sw); +err_fwnode_put: + fwnode_handle_put(fwnode); + + return ret; +} + +static int rt1719_remove(struct i2c_client *i2c) +{ + struct rt1719_data *data = i2c_get_clientdata(i2c); + + typec_unregister_port(data->port); + usb_role_switch_put(data->role_sw); + + return 0; +} + +static const struct of_device_id __maybe_unused rt1719_device_table[] = { + { .compatible = "richtek,rt1719", }, + { } +}; +MODULE_DEVICE_TABLE(of, rt1719_device_table); + +static struct i2c_driver rt1719_driver = { + .driver = { + .name = "rt1719", + .of_match_table = rt1719_device_table, + }, + .probe_new = rt1719_probe, + .remove = rt1719_remove, +}; +module_i2c_driver(rt1719_driver); + +MODULE_AUTHOR("ChiYuan Huang "); +MODULE_DESCRIPTION("Richtek RT1719 Sink Only USBPD Controller Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c index 5fce795b69c7..3bc2f4ebd1fe 100644 --- a/drivers/usb/typec/tcpm/tcpm.c +++ b/drivers/usb/typec/tcpm/tcpm.c @@ -5928,7 +5928,6 @@ static int tcpm_fw_get_caps(struct tcpm_port *port, struct fwnode_handle *fwnode) { const char *opmode_str; - const char *cap_str; int ret; u32 mw, frs_current; @@ -5944,23 +5943,10 @@ static int tcpm_fw_get_caps(struct tcpm_port *port, */ fw_devlink_purge_absent_suppliers(fwnode); - /* USB data support is optional */ - ret = fwnode_property_read_string(fwnode, "data-role", &cap_str); - if (ret == 0) { - ret = typec_find_port_data_role(cap_str); - if (ret < 0) - return ret; - port->typec_caps.data = ret; - } - - ret = fwnode_property_read_string(fwnode, "power-role", &cap_str); + ret = typec_get_fw_cap(&port->typec_caps, fwnode); if (ret < 0) return ret; - ret = typec_find_port_power_role(cap_str); - if (ret < 0) - return ret; - port->typec_caps.type = ret; port->port_type = port->typec_caps.type; port->pd_supported = !fwnode_property_read_bool(fwnode, "pd-disable"); @@ -5997,14 +5983,6 @@ static int tcpm_fw_get_caps(struct tcpm_port *port, if (port->port_type == TYPEC_PORT_SRC) return 0; - /* Get the preferred power role for DRP */ - ret = fwnode_property_read_string(fwnode, "try-power-role", &cap_str); - if (ret < 0) - return ret; - - port->typec_caps.prefer_role = typec_find_power_role(cap_str); - if (port->typec_caps.prefer_role < 0) - return -EINVAL; sink: port->self_powered = fwnode_property_read_bool(fwnode, "self-powered"); diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 7ffcda94d323..16b4560216ba 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -256,6 +256,10 @@ static int tps6598x_connect(struct tps6598x *tps, u32 status) typec_set_pwr_opmode(tps->port, mode); typec_set_pwr_role(tps->port, TPS_STATUS_TO_TYPEC_PORTROLE(status)); typec_set_vconn_role(tps->port, TPS_STATUS_TO_TYPEC_VCONN(status)); + if (TPS_STATUS_TO_UPSIDE_DOWN(status)) + typec_set_orientation(tps->port, TYPEC_ORIENTATION_REVERSE); + else + typec_set_orientation(tps->port, TYPEC_ORIENTATION_NORMAL); tps6598x_set_data_role(tps, TPS_STATUS_TO_TYPEC_DATAROLE(status), true); tps->partner = typec_register_partner(tps->port, &desc); @@ -278,6 +282,7 @@ static void tps6598x_disconnect(struct tps6598x *tps, u32 status) typec_set_pwr_opmode(tps->port, TYPEC_PWR_MODE_USB); typec_set_pwr_role(tps->port, TPS_STATUS_TO_TYPEC_PORTROLE(status)); typec_set_vconn_role(tps->port, TPS_STATUS_TO_TYPEC_VCONN(status)); + typec_set_orientation(tps->port, TYPEC_ORIENTATION_NONE); tps6598x_set_data_role(tps, TPS_STATUS_TO_TYPEC_DATAROLE(status), false); power_supply_changed(tps->psy); diff --git a/drivers/usb/typec/tipd/tps6598x.h b/drivers/usb/typec/tipd/tps6598x.h index 3dae84c524fb..527857549d69 100644 --- a/drivers/usb/typec/tipd/tps6598x.h +++ b/drivers/usb/typec/tipd/tps6598x.h @@ -17,6 +17,7 @@ /* TPS_REG_STATUS bits */ #define TPS_STATUS_PLUG_PRESENT BIT(0) #define TPS_STATUS_PLUG_UPSIDE_DOWN BIT(4) +#define TPS_STATUS_TO_UPSIDE_DOWN(s) (!!((s) & TPS_STATUS_PLUG_UPSIDE_DOWN)) #define TPS_STATUS_PORTROLE BIT(5) #define TPS_STATUS_TO_TYPEC_PORTROLE(s) (!!((s) & TPS_STATUS_PORTROLE)) #define TPS_STATUS_DATAROLE BIT(6) diff --git a/drivers/usb/typec/wusb3801.c b/drivers/usb/typec/wusb3801.c new file mode 100644 index 000000000000..e63509f8b01e --- /dev/null +++ b/drivers/usb/typec/wusb3801.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Willsemi WUSB3801 Type-C port controller driver + * + * Copyright (C) 2022 Samuel Holland + */ + +#include +#include +#include +#include +#include + +#define WUSB3801_REG_DEVICE_ID 0x01 +#define WUSB3801_REG_CTRL0 0x02 +#define WUSB3801_REG_INT 0x03 +#define WUSB3801_REG_STAT 0x04 +#define WUSB3801_REG_CTRL1 0x05 +#define WUSB3801_REG_TEST00 0x06 +#define WUSB3801_REG_TEST01 0x07 +#define WUSB3801_REG_TEST02 0x08 +#define WUSB3801_REG_TEST03 0x09 +#define WUSB3801_REG_TEST04 0x0a +#define WUSB3801_REG_TEST05 0x0b +#define WUSB3801_REG_TEST06 0x0c +#define WUSB3801_REG_TEST07 0x0d +#define WUSB3801_REG_TEST08 0x0e +#define WUSB3801_REG_TEST09 0x0f +#define WUSB3801_REG_TEST0A 0x10 +#define WUSB3801_REG_TEST0B 0x11 +#define WUSB3801_REG_TEST0C 0x12 +#define WUSB3801_REG_TEST0D 0x13 +#define WUSB3801_REG_TEST0E 0x14 +#define WUSB3801_REG_TEST0F 0x15 +#define WUSB3801_REG_TEST10 0x16 +#define WUSB3801_REG_TEST11 0x17 +#define WUSB3801_REG_TEST12 0x18 + +#define WUSB3801_DEVICE_ID_VERSION_ID GENMASK(7, 3) +#define WUSB3801_DEVICE_ID_VENDOR_ID GENMASK(2, 0) + +#define WUSB3801_CTRL0_DIS_ACC_SUPPORT BIT(7) +#define WUSB3801_CTRL0_TRY GENMASK(6, 5) +#define WUSB3801_CTRL0_TRY_NONE (0x0 << 5) +#define WUSB3801_CTRL0_TRY_SNK (0x1 << 5) +#define WUSB3801_CTRL0_TRY_SRC (0x2 << 5) +#define WUSB3801_CTRL0_CURRENT GENMASK(4, 3) /* SRC */ +#define WUSB3801_CTRL0_CURRENT_DEFAULT (0x0 << 3) +#define WUSB3801_CTRL0_CURRENT_1_5A (0x1 << 3) +#define WUSB3801_CTRL0_CURRENT_3_0A (0x2 << 3) +#define WUSB3801_CTRL0_ROLE GENMASK(2, 1) +#define WUSB3801_CTRL0_ROLE_SNK (0x0 << 1) +#define WUSB3801_CTRL0_ROLE_SRC (0x1 << 1) +#define WUSB3801_CTRL0_ROLE_DRP (0x2 << 1) +#define WUSB3801_CTRL0_INT_MASK BIT(0) + +#define WUSB3801_INT_ATTACHED BIT(0) +#define WUSB3801_INT_DETACHED BIT(1) + +#define WUSB3801_STAT_VBUS_DETECTED BIT(7) +#define WUSB3801_STAT_CURRENT GENMASK(6, 5) /* SNK */ +#define WUSB3801_STAT_CURRENT_STANDBY (0x0 << 5) +#define WUSB3801_STAT_CURRENT_DEFAULT (0x1 << 5) +#define WUSB3801_STAT_CURRENT_1_5A (0x2 << 5) +#define WUSB3801_STAT_CURRENT_3_0A (0x3 << 5) +#define WUSB3801_STAT_PARTNER GENMASK(4, 2) +#define WUSB3801_STAT_PARTNER_STANDBY (0x0 << 2) +#define WUSB3801_STAT_PARTNER_SNK (0x1 << 2) +#define WUSB3801_STAT_PARTNER_SRC (0x2 << 2) +#define WUSB3801_STAT_PARTNER_AUDIO (0x3 << 2) +#define WUSB3801_STAT_PARTNER_DEBUG (0x4 << 2) +#define WUSB3801_STAT_ORIENTATION GENMASK(1, 0) +#define WUSB3801_STAT_ORIENTATION_NONE (0x0 << 0) +#define WUSB3801_STAT_ORIENTATION_CC1 (0x1 << 0) +#define WUSB3801_STAT_ORIENTATION_CC2 (0x2 << 0) +#define WUSB3801_STAT_ORIENTATION_BOTH (0x3 << 0) + +#define WUSB3801_CTRL1_SM_RESET BIT(0) + +#define WUSB3801_TEST01_VENDOR_SUB_ID (BIT(8) | BIT(6)) + +#define WUSB3801_TEST02_FORCE_ERR_RCY BIT(8) + +#define WUSB3801_TEST0A_WAIT_VBUS BIT(5) + +struct wusb3801 { + struct typec_capability cap; + struct device *dev; + struct typec_partner *partner; + struct typec_port *port; + struct regmap *regmap; + struct regulator *vbus_supply; + unsigned int partner_type; + enum typec_port_type port_type; + enum typec_pwr_opmode pwr_opmode; + bool vbus_on; +}; + +static enum typec_role wusb3801_get_default_role(struct wusb3801 *wusb3801) +{ + switch (wusb3801->port_type) { + case TYPEC_PORT_SRC: + return TYPEC_SOURCE; + case TYPEC_PORT_SNK: + return TYPEC_SINK; + case TYPEC_PORT_DRP: + default: + if (wusb3801->cap.prefer_role == TYPEC_SOURCE) + return TYPEC_SOURCE; + return TYPEC_SINK; + } +} + +static int wusb3801_map_port_type(enum typec_port_type type) +{ + switch (type) { + case TYPEC_PORT_SRC: + return WUSB3801_CTRL0_ROLE_SRC; + case TYPEC_PORT_SNK: + return WUSB3801_CTRL0_ROLE_SNK; + case TYPEC_PORT_DRP: + default: + return WUSB3801_CTRL0_ROLE_DRP; + } +} + +static int wusb3801_map_pwr_opmode(enum typec_pwr_opmode mode) +{ + switch (mode) { + case TYPEC_PWR_MODE_USB: + default: + return WUSB3801_CTRL0_CURRENT_DEFAULT; + case TYPEC_PWR_MODE_1_5A: + return WUSB3801_CTRL0_CURRENT_1_5A; + case TYPEC_PWR_MODE_3_0A: + return WUSB3801_CTRL0_CURRENT_3_0A; + } +} + +static unsigned int wusb3801_map_try_role(int role) +{ + switch (role) { + case TYPEC_NO_PREFERRED_ROLE: + default: + return WUSB3801_CTRL0_TRY_NONE; + case TYPEC_SINK: + return WUSB3801_CTRL0_TRY_SNK; + case TYPEC_SOURCE: + return WUSB3801_CTRL0_TRY_SRC; + } +} + +static enum typec_orientation wusb3801_unmap_orientation(unsigned int status) +{ + switch (status & WUSB3801_STAT_ORIENTATION) { + case WUSB3801_STAT_ORIENTATION_NONE: + case WUSB3801_STAT_ORIENTATION_BOTH: + default: + return TYPEC_ORIENTATION_NONE; + case WUSB3801_STAT_ORIENTATION_CC1: + return TYPEC_ORIENTATION_NORMAL; + case WUSB3801_STAT_ORIENTATION_CC2: + return TYPEC_ORIENTATION_REVERSE; + } +} + +static enum typec_pwr_opmode wusb3801_unmap_pwr_opmode(unsigned int status) +{ + switch (status & WUSB3801_STAT_CURRENT) { + case WUSB3801_STAT_CURRENT_STANDBY: + case WUSB3801_STAT_CURRENT_DEFAULT: + default: + return TYPEC_PWR_MODE_USB; + case WUSB3801_STAT_CURRENT_1_5A: + return TYPEC_PWR_MODE_1_5A; + case WUSB3801_STAT_CURRENT_3_0A: + return TYPEC_PWR_MODE_3_0A; + } +} + +static int wusb3801_try_role(struct typec_port *port, int role) +{ + struct wusb3801 *wusb3801 = typec_get_drvdata(port); + + return regmap_update_bits(wusb3801->regmap, WUSB3801_REG_CTRL0, + WUSB3801_CTRL0_TRY, + wusb3801_map_try_role(role)); +} + +static int wusb3801_port_type_set(struct typec_port *port, + enum typec_port_type type) +{ + struct wusb3801 *wusb3801 = typec_get_drvdata(port); + int ret; + + ret = regmap_update_bits(wusb3801->regmap, WUSB3801_REG_CTRL0, + WUSB3801_CTRL0_ROLE, + wusb3801_map_port_type(type)); + if (ret) + return ret; + + wusb3801->port_type = type; + + return 0; +} + +static const struct typec_operations wusb3801_typec_ops = { + .try_role = wusb3801_try_role, + .port_type_set = wusb3801_port_type_set, +}; + +static int wusb3801_hw_init(struct wusb3801 *wusb3801) +{ + return regmap_write(wusb3801->regmap, WUSB3801_REG_CTRL0, + wusb3801_map_try_role(wusb3801->cap.prefer_role) | + wusb3801_map_pwr_opmode(wusb3801->pwr_opmode) | + wusb3801_map_port_type(wusb3801->port_type)); +} + +static void wusb3801_hw_update(struct wusb3801 *wusb3801) +{ + struct typec_port *port = wusb3801->port; + struct device *dev = wusb3801->dev; + unsigned int partner_type, status; + int ret; + + ret = regmap_read(wusb3801->regmap, WUSB3801_REG_STAT, &status); + if (ret) { + dev_warn(dev, "Failed to read port status: %d\n", ret); + status = 0; + } + dev_dbg(dev, "status = 0x%02x\n", status); + + partner_type = status & WUSB3801_STAT_PARTNER; + + if (partner_type == WUSB3801_STAT_PARTNER_SNK) { + if (!wusb3801->vbus_on) { + ret = regulator_enable(wusb3801->vbus_supply); + if (ret) + dev_warn(dev, "Failed to enable VBUS: %d\n", ret); + wusb3801->vbus_on = true; + } + } else { + if (wusb3801->vbus_on) { + regulator_disable(wusb3801->vbus_supply); + wusb3801->vbus_on = false; + } + } + + if (partner_type != wusb3801->partner_type) { + struct typec_partner_desc desc = {}; + enum typec_data_role data_role; + enum typec_role pwr_role = wusb3801_get_default_role(wusb3801); + + switch (partner_type) { + case WUSB3801_STAT_PARTNER_STANDBY: + break; + case WUSB3801_STAT_PARTNER_SNK: + pwr_role = TYPEC_SOURCE; + break; + case WUSB3801_STAT_PARTNER_SRC: + pwr_role = TYPEC_SINK; + break; + case WUSB3801_STAT_PARTNER_AUDIO: + desc.accessory = TYPEC_ACCESSORY_AUDIO; + break; + case WUSB3801_STAT_PARTNER_DEBUG: + desc.accessory = TYPEC_ACCESSORY_DEBUG; + break; + } + + if (wusb3801->partner) { + typec_unregister_partner(wusb3801->partner); + wusb3801->partner = NULL; + } + + if (partner_type != WUSB3801_STAT_PARTNER_STANDBY) { + wusb3801->partner = typec_register_partner(port, &desc); + if (IS_ERR(wusb3801->partner)) + dev_err(dev, "Failed to register partner: %ld\n", + PTR_ERR(wusb3801->partner)); + } + + data_role = pwr_role == TYPEC_SOURCE ? TYPEC_HOST : TYPEC_DEVICE; + typec_set_data_role(port, data_role); + typec_set_pwr_role(port, pwr_role); + typec_set_vconn_role(port, pwr_role); + } + + typec_set_pwr_opmode(wusb3801->port, + partner_type == WUSB3801_STAT_PARTNER_SRC + ? wusb3801_unmap_pwr_opmode(status) + : wusb3801->pwr_opmode); + typec_set_orientation(wusb3801->port, + wusb3801_unmap_orientation(status)); + + wusb3801->partner_type = partner_type; +} + +static irqreturn_t wusb3801_irq(int irq, void *data) +{ + struct wusb3801 *wusb3801 = data; + unsigned int dummy; + + /* + * The interrupt register must be read in order to clear the IRQ, + * but all of the useful information is in the status register. + */ + regmap_read(wusb3801->regmap, WUSB3801_REG_INT, &dummy); + + wusb3801_hw_update(wusb3801); + + return IRQ_HANDLED; +} + +static const struct regmap_config config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = WUSB3801_REG_TEST12, +}; + +static int wusb3801_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct fwnode_handle *connector; + struct wusb3801 *wusb3801; + const char *cap_str; + int ret; + + wusb3801 = devm_kzalloc(dev, sizeof(*wusb3801), GFP_KERNEL); + if (!wusb3801) + return -ENOMEM; + + i2c_set_clientdata(client, wusb3801); + + wusb3801->dev = dev; + + wusb3801->regmap = devm_regmap_init_i2c(client, &config); + if (IS_ERR(wusb3801->regmap)) + return PTR_ERR(wusb3801->regmap); + + wusb3801->vbus_supply = devm_regulator_get(dev, "vbus"); + if (IS_ERR(wusb3801->vbus_supply)) + return PTR_ERR(wusb3801->vbus_supply); + + connector = device_get_named_child_node(dev, "connector"); + if (!connector) + return -ENODEV; + + ret = typec_get_fw_cap(&wusb3801->cap, connector); + if (ret) + goto err_put_connector; + wusb3801->port_type = wusb3801->cap.type; + + ret = fwnode_property_read_string(connector, "typec-power-opmode", &cap_str); + if (ret) + goto err_put_connector; + + ret = typec_find_pwr_opmode(cap_str); + if (ret < 0 || ret == TYPEC_PWR_MODE_PD) + goto err_put_connector; + wusb3801->pwr_opmode = ret; + + /* Initialize the hardware with the devicetree settings. */ + ret = wusb3801_hw_init(wusb3801); + if (ret) + return ret; + + wusb3801->cap.revision = USB_TYPEC_REV_1_2; + wusb3801->cap.accessory[0] = TYPEC_ACCESSORY_AUDIO; + wusb3801->cap.accessory[1] = TYPEC_ACCESSORY_DEBUG; + wusb3801->cap.orientation_aware = true; + wusb3801->cap.driver_data = wusb3801; + wusb3801->cap.ops = &wusb3801_typec_ops; + + wusb3801->port = typec_register_port(dev, &wusb3801->cap); + if (IS_ERR(wusb3801->port)) { + ret = PTR_ERR(wusb3801->port); + goto err_put_connector; + } + + /* Initialize the port attributes from the hardware state. */ + wusb3801_hw_update(wusb3801); + + ret = request_threaded_irq(client->irq, NULL, wusb3801_irq, + IRQF_ONESHOT, dev_name(dev), wusb3801); + if (ret) + goto err_unregister_port; + + fwnode_handle_put(connector); + + return 0; + +err_unregister_port: + typec_unregister_port(wusb3801->port); +err_put_connector: + fwnode_handle_put(connector); + + return ret; +} + +static int wusb3801_remove(struct i2c_client *client) +{ + struct wusb3801 *wusb3801 = i2c_get_clientdata(client); + + free_irq(client->irq, wusb3801); + + if (wusb3801->partner) + typec_unregister_partner(wusb3801->partner); + typec_unregister_port(wusb3801->port); + + if (wusb3801->vbus_on) + regulator_disable(wusb3801->vbus_supply); + + return 0; +} + +static const struct of_device_id wusb3801_of_match[] = { + { .compatible = "willsemi,wusb3801" }, + {} +}; +MODULE_DEVICE_TABLE(of, wusb3801_of_match); + +static struct i2c_driver wusb3801_driver = { + .probe_new = wusb3801_probe, + .remove = wusb3801_remove, + .driver = { + .name = "wusb3801", + .of_match_table = wusb3801_of_match, + }, +}; + +module_i2c_driver(wusb3801_driver); + +MODULE_AUTHOR("Samuel Holland "); +MODULE_DESCRIPTION("Willsemi WUSB3801 Type-C port controller driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/usb/usbip/vudc_main.c b/drivers/usb/usbip/vudc_main.c index 678faa82598c..993e721cb840 100644 --- a/drivers/usb/usbip/vudc_main.c +++ b/drivers/usb/usbip/vudc_main.c @@ -26,9 +26,9 @@ static struct platform_driver vudc_driver = { }, }; -static struct list_head vudc_devices = LIST_HEAD_INIT(vudc_devices); +static LIST_HEAD(vudc_devices); -static int __init init(void) +static int __init vudc_init(void) { int retval = -ENOMEM; int i; @@ -86,9 +86,9 @@ cleanup: out: return retval; } -module_init(init); +module_init(vudc_init); -static void __exit cleanup(void) +static void __exit vudc_cleanup(void) { struct vudc_device *udc_dev = NULL, *udc_dev2 = NULL; @@ -103,7 +103,7 @@ static void __exit cleanup(void) } platform_driver_unregister(&vudc_driver); } -module_exit(cleanup); +module_exit(vudc_cleanup); MODULE_DESCRIPTION("USB over IP Device Controller"); MODULE_AUTHOR("Krzysztof Opasiak, Karol Kosik, Igor Kotrasinski"); diff --git a/fs/fuse/ioctl.c b/fs/fuse/ioctl.c index df58966bc874..33cde4bbccdc 100644 --- a/fs/fuse/ioctl.c +++ b/fs/fuse/ioctl.c @@ -170,7 +170,7 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg, #else if (flags & FUSE_IOCTL_COMPAT) { inarg.flags |= FUSE_IOCTL_32BIT; -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI if (in_x32_syscall()) inarg.flags |= FUSE_IOCTL_COMPAT_X32; #endif diff --git a/fs/xfs/xfs_ioctl32.c b/fs/xfs/xfs_ioctl32.c index 004ed2a251e8..ca25ed89b706 100644 --- a/fs/xfs/xfs_ioctl32.c +++ b/fs/xfs/xfs_ioctl32.c @@ -217,7 +217,7 @@ xfs_compat_ioc_fsbulkstat( inumbers_fmt_pf inumbers_func = xfs_fsinumbers_fmt_compat; bulkstat_one_fmt_pf bs_one_func = xfs_fsbulkstat_one_fmt_compat; -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI if (in_x32_syscall()) { /* * ... but on x32 the input xfs_fsop_bulkreq has pointers diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index 2a10db2f0bc5..69138e9db787 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -394,6 +394,7 @@ KEEP(*(__jump_table)) \ __stop___jump_table = .; +#ifdef CONFIG_HAVE_STATIC_CALL_INLINE #define STATIC_CALL_DATA \ . = ALIGN(8); \ __start_static_call_sites = .; \ @@ -402,6 +403,9 @@ __start_static_call_tramp_key = .; \ KEEP(*(.static_call_tramp_key)) \ __stop_static_call_tramp_key = .; +#else +#define STATIC_CALL_DATA +#endif /* * Allow architectures to handle ro_after_init data on their diff --git a/include/dt-bindings/gpio/meson-s4-gpio.h b/include/dt-bindings/gpio/meson-s4-gpio.h new file mode 100644 index 000000000000..35aee21b94f1 --- /dev/null +++ b/include/dt-bindings/gpio/meson-s4-gpio.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2021 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song + */ + +#ifndef _DT_BINDINGS_MESON_S4_GPIO_H +#define _DT_BINDINGS_MESON_S4_GPIO_H + +#define GPIOB_0 0 +#define GPIOB_1 1 +#define GPIOB_2 2 +#define GPIOB_3 3 +#define GPIOB_4 4 +#define GPIOB_5 5 +#define GPIOB_6 6 +#define GPIOB_7 7 +#define GPIOB_8 8 +#define GPIOB_9 9 +#define GPIOB_10 10 +#define GPIOB_11 11 +#define GPIOB_12 12 +#define GPIOB_13 13 + +#define GPIOC_0 14 +#define GPIOC_1 15 +#define GPIOC_2 16 +#define GPIOC_3 17 +#define GPIOC_4 18 +#define GPIOC_5 19 +#define GPIOC_6 20 +#define GPIOC_7 21 + +#define GPIOE_0 22 +#define GPIOE_1 23 + +#define GPIOD_0 24 +#define GPIOD_1 25 +#define GPIOD_2 26 +#define GPIOD_3 27 +#define GPIOD_4 28 +#define GPIOD_5 29 +#define GPIOD_6 30 +#define GPIOD_7 31 +#define GPIOD_8 32 +#define GPIOD_9 33 +#define GPIOD_10 34 +#define GPIOD_11 35 + +#define GPIOH_0 36 +#define GPIOH_1 37 +#define GPIOH_2 38 +#define GPIOH_3 39 +#define GPIOH_4 40 +#define GPIOH_5 41 +#define GPIOH_6 42 +#define GPIOH_7 43 +#define GPIOH_8 44 +#define GPIOH_9 45 +#define GPIOH_10 46 +#define GPIOH_11 47 + +#define GPIOX_0 48 +#define GPIOX_1 49 +#define GPIOX_2 50 +#define GPIOX_3 51 +#define GPIOX_4 52 +#define GPIOX_5 53 +#define GPIOX_6 54 +#define GPIOX_7 55 +#define GPIOX_8 56 +#define GPIOX_9 57 +#define GPIOX_10 58 +#define GPIOX_11 59 +#define GPIOX_12 60 +#define GPIOX_13 61 +#define GPIOX_14 62 +#define GPIOX_15 63 +#define GPIOX_16 64 +#define GPIOX_17 65 +#define GPIOX_18 66 +#define GPIOX_19 67 + +#define GPIOZ_0 68 +#define GPIOZ_1 69 +#define GPIOZ_2 70 +#define GPIOZ_3 71 +#define GPIOZ_4 72 +#define GPIOZ_5 73 +#define GPIOZ_6 74 +#define GPIOZ_7 75 +#define GPIOZ_8 76 +#define GPIOZ_9 77 +#define GPIOZ_10 78 +#define GPIOZ_11 79 +#define GPIOZ_12 80 + +#define GPIO_TEST_N 81 +#endif /* _DT_BINDINGS_MESON_S4_GPIO_H */ diff --git a/include/dt-bindings/pinctrl/mt8186-pinfunc.h b/include/dt-bindings/pinctrl/mt8186-pinfunc.h new file mode 100644 index 000000000000..18d6683c6f65 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8186-pinfunc.h @@ -0,0 +1,1174 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Guodong Liu + * + */ + +#ifndef __MT8186_PINFUNC_H +#define __MT8186_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_I2S0_MCK (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_SPI0_CLK_B (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_I2S2_MCK (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_CMFLASH0 (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_SCP_SPI0_CK (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 6) +#define PINMUX_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_I2S0_BCK (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_SPI0_CSB_B (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_I2S2_BCK (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_CMFLASH1 (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_SCP_SPI0_CS (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 6) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_I2S0_LRCK (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_SPI0_MO_B (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_I2S2_LRCK (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_CMFLASH2 (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_SCP_SPI0_MO (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 6) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_I2S0_DI (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_SPI0_MI_B (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_SRCLKENAI1 (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_SCP_SPI0_MI (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 6) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_I2S3_DO (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S1_DO (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 6) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 6) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_I2S3_MCK (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_SPI1_CLK_B (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_DPI_DATA22 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 6) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_I2S3_BCK (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_SPI1_CSB_B (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_I2S1_BCK (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_DPI_DATA23 (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 6) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_I2S3_LRCK (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_SPI1_MO_B (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_I2S1_LRCK (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_CONN_UART0_RXD (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_SSPM_URXD_AO (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_ADSP_UART_RX (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_I2S3_DO (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_SPI1_MI_B (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_I2S1_DO (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_CONN_UART0_TXD (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_ADSP_UART_TX (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_SPI4_CLK_A (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I2S2_MCK (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(10) | 4) +#define PINMUX_GPIO10__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(10) | 6) +#define PINMUX_GPIO10__FUNC_CONN_MCU_TDI (MTK_PIN_NO(10) | 7) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_I2S0_BCK (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_SPI4_CSB_A (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_I2S2_BCK (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(11) | 6) +#define PINMUX_GPIO11__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(11) | 7) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_I2S0_LRCK (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_SPI4_MO_A (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_I2S2_LRCK (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(12) | 6) +#define PINMUX_GPIO12__FUNC_CONN_MCU_TCK (MTK_PIN_NO(12) | 7) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_I2S0_DI (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_SPI4_MI_A (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I2S2_DI (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(13) | 6) +#define PINMUX_GPIO13__FUNC_CONN_MCU_TDO (MTK_PIN_NO(13) | 7) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_CLKM0 (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(14) | 6) +#define PINMUX_GPIO14__FUNC_CONN_MCU_TMS (MTK_PIN_NO(14) | 7) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_SRCLKENAI1 (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_CLKM1 (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_PWM0 (MTK_PIN_NO(15) | 4) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_SRCLKENAI0 (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_CLKM2 (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_PWM1 (MTK_PIN_NO(16) | 4) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_CLKM3 (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_PWM2 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_DBG_MON_A32 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_CMVREF0 (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_SPI2_CLK_B (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_DBG_MON_A26 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_CMVREF1 (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_ANT_SEL3 (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_SPI2_CSB_B (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_A2 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_CMVREF2 (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_ANT_SEL4 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_SPI2_MO_B (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_A3 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_I2S0_MCK (MTK_PIN_NO(21) | 1) +#define PINMUX_GPIO21__FUNC_I2S1_MCK (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_I2S3_MCK (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_ANT_SEL5 (MTK_PIN_NO(21) | 5) +#define PINMUX_GPIO21__FUNC_SPI2_MI_B (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_A4 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_I2S0_BCK (MTK_PIN_NO(22) | 1) +#define PINMUX_GPIO22__FUNC_I2S1_BCK (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_I2S3_BCK (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_TDM_RX_LRCK (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_ANT_SEL6 (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_DBG_MON_A5 (MTK_PIN_NO(22) | 7) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_I2S0_LRCK (MTK_PIN_NO(23) | 1) +#define PINMUX_GPIO23__FUNC_I2S1_LRCK (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_I2S3_LRCK (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_TDM_RX_BCK (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_ANT_SEL7 (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_DBG_MON_A6 (MTK_PIN_NO(23) | 7) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_I2S0_DI (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_I2S1_DO (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_I2S3_DO (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_TDM_RX_MCK (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_DBG_MON_A7 (MTK_PIN_NO(24) | 7) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_I2S2_MCK (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_PCM_CLK (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SPI4_CLK_B (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_DBG_MON_A8 (MTK_PIN_NO(25) | 7) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_I2S2_BCK (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_PCM_SYNC (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_SPI4_CSB_B (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_DBG_MON_A9 (MTK_PIN_NO(26) | 7) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_I2S2_LRCK (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_PCM_DI (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_SPI4_MO_B (MTK_PIN_NO(27) | 3) +#define PINMUX_GPIO27__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_DBG_MON_A10 (MTK_PIN_NO(27) | 7) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_I2S2_DI (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_PCM_DO (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_SPI4_MI_B (MTK_PIN_NO(28) | 3) +#define PINMUX_GPIO28__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(28) | 4) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_ANT_SEL0 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(29) | 2) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_ANT_SEL1 (MTK_PIN_NO(30) | 1) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_ANT_SEL2 (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_SRCLKENAI1 (MTK_PIN_NO(31) | 3) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_URXD0 (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_UTXD0 (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_ADSP_UART_RX (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_TP_URXD1_AO (MTK_PIN_NO(32) | 4) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_UTXD0 (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_URXD0 (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_ADSP_UART_TX (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_TP_UTXD1_AO (MTK_PIN_NO(33) | 4) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_URXD1 (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_TP_URXD2_AO (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_SSPM_URXD_AO (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_ADSP_UART_RX (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_CONN_UART0_RXD (MTK_PIN_NO(34) | 5) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_UTXD1 (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_TP_UTXD2_AO (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_ADSP_UART_TX (MTK_PIN_NO(35) | 4) +#define PINMUX_GPIO35__FUNC_CONN_UART0_TXD (MTK_PIN_NO(35) | 5) +#define PINMUX_GPIO35__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(35) | 6) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_SPI0_CLK_A (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_CLKM0 (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_SCP_SPI0_CK (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_SPINOR_CK (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_DBG_MON_A11 (MTK_PIN_NO(36) | 7) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_SPI0_CSB_A (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_CLKM1 (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_PWM0 (MTK_PIN_NO(37) | 3) +#define PINMUX_GPIO37__FUNC_SCP_SPI0_CS (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_SPINOR_CS (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_DBG_MON_A12 (MTK_PIN_NO(37) | 7) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_SPI0_MO_A (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_CLKM2 (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_PWM1 (MTK_PIN_NO(38) | 3) +#define PINMUX_GPIO38__FUNC_SCP_SPI0_MO (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_SPINOR_IO0 (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_DBG_MON_A13 (MTK_PIN_NO(38) | 7) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_SPI0_MI_A (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_CLKM3 (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_PWM2 (MTK_PIN_NO(39) | 3) +#define PINMUX_GPIO39__FUNC_SCP_SPI0_MI (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_SPINOR_IO1 (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_DBG_MON_A14 (MTK_PIN_NO(39) | 7) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_SPI1_CLK_A (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_SCP_SPI1_CK (MTK_PIN_NO(40) | 2) +#define PINMUX_GPIO40__FUNC_UCTS0 (MTK_PIN_NO(40) | 4) +#define PINMUX_GPIO40__FUNC_SPINOR_IO2 (MTK_PIN_NO(40) | 5) +#define PINMUX_GPIO40__FUNC_TP_UCTS1_AO (MTK_PIN_NO(40) | 6) +#define PINMUX_GPIO40__FUNC_DBG_MON_A15 (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_SPI1_CSB_A (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_SCP_SPI1_CS (MTK_PIN_NO(41) | 2) +#define PINMUX_GPIO41__FUNC_PWM0 (MTK_PIN_NO(41) | 3) +#define PINMUX_GPIO41__FUNC_URTS0 (MTK_PIN_NO(41) | 4) +#define PINMUX_GPIO41__FUNC_SPINOR_IO3 (MTK_PIN_NO(41) | 5) +#define PINMUX_GPIO41__FUNC_TP_URTS1_AO (MTK_PIN_NO(41) | 6) +#define PINMUX_GPIO41__FUNC_DBG_MON_A16 (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_SCP_SPI1_MO (MTK_PIN_NO(42) | 2) +#define PINMUX_GPIO42__FUNC_PWM1 (MTK_PIN_NO(42) | 3) +#define PINMUX_GPIO42__FUNC_UCTS1 (MTK_PIN_NO(42) | 4) +#define PINMUX_GPIO42__FUNC_TP_UCTS2_AO (MTK_PIN_NO(42) | 6) +#define PINMUX_GPIO42__FUNC_DBG_MON_A17 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_SPI1_MI_A (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_SCP_SPI1_MI (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_PWM2 (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_URTS1 (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_TP_URTS2_AO (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_DBG_MON_A18 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_SPI2_CLK_A (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_SCP_SPI0_CK (MTK_PIN_NO(44) | 2) +#define PINMUX_GPIO44__FUNC_DBG_MON_A19 (MTK_PIN_NO(44) | 7) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_SPI2_CSB_A (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_SCP_SPI0_CS (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_DBG_MON_A20 (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_SCP_SPI0_MO (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_DBG_MON_A21 (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_SPI2_MI_A (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_SCP_SPI0_MI (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_DBG_MON_A22 (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_SPI3_CLK (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_TP_URXD1_AO (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_TP_URXD2_AO (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_URXD1 (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_SCP_SPI0_CK (MTK_PIN_NO(48) | 6) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_SPI3_CSB (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_TP_UTXD1_AO (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_TP_UTXD2_AO (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_UTXD1 (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_I2S2_BCK (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_SCP_SPI0_CS (MTK_PIN_NO(49) | 6) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_SPI3_MO (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_I2S2_LRCK (MTK_PIN_NO(50) | 5) +#define PINMUX_GPIO50__FUNC_SCP_SPI0_MO (MTK_PIN_NO(50) | 6) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_SPI3_MI (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_I2S2_DI (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_SCP_SPI0_MI (MTK_PIN_NO(51) | 6) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_SPI5_CLK (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_I2S2_MCK (MTK_PIN_NO(52) | 2) +#define PINMUX_GPIO52__FUNC_I2S1_MCK (MTK_PIN_NO(52) | 3) +#define PINMUX_GPIO52__FUNC_SCP_SPI1_CK (MTK_PIN_NO(52) | 4) +#define PINMUX_GPIO52__FUNC_LVTS_26M (MTK_PIN_NO(52) | 5) +#define PINMUX_GPIO52__FUNC_DFD_TCK_XI (MTK_PIN_NO(52) | 6) +#define PINMUX_GPIO52__FUNC_DBG_MON_B30 (MTK_PIN_NO(52) | 7) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_SPI5_CSB (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_I2S2_BCK (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_I2S1_BCK (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_SCP_SPI1_CS (MTK_PIN_NO(53) | 4) +#define PINMUX_GPIO53__FUNC_LVTS_FOUT (MTK_PIN_NO(53) | 5) +#define PINMUX_GPIO53__FUNC_DFD_TDI (MTK_PIN_NO(53) | 6) +#define PINMUX_GPIO53__FUNC_DBG_MON_B31 (MTK_PIN_NO(53) | 7) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_SPI5_MO (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_I2S2_LRCK (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_I2S1_LRCK (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_SCP_SPI1_MO (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_LVTS_SCK (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_DFD_TDO (MTK_PIN_NO(54) | 6) +#define PINMUX_GPIO54__FUNC_DBG_MON_A1 (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_SPI5_MI (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_I2S2_DI (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_I2S1_DO (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_SCP_SPI1_MI (MTK_PIN_NO(55) | 4) +#define PINMUX_GPIO55__FUNC_LVTS_SDO (MTK_PIN_NO(55) | 5) +#define PINMUX_GPIO55__FUNC_DFD_TMS (MTK_PIN_NO(55) | 6) +#define PINMUX_GPIO55__FUNC_DBG_MON_B32 (MTK_PIN_NO(55) | 7) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_I2S1_DO (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_I2S3_DO (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_DBG_MON_A23 (MTK_PIN_NO(56) | 7) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_I2S1_BCK (MTK_PIN_NO(57) | 1) +#define PINMUX_GPIO57__FUNC_I2S3_BCK (MTK_PIN_NO(57) | 2) +#define PINMUX_GPIO57__FUNC_DBG_MON_A24 (MTK_PIN_NO(57) | 7) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_I2S1_LRCK (MTK_PIN_NO(58) | 1) +#define PINMUX_GPIO58__FUNC_I2S3_LRCK (MTK_PIN_NO(58) | 2) +#define PINMUX_GPIO58__FUNC_DBG_MON_A25 (MTK_PIN_NO(58) | 7) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_I2S1_MCK (MTK_PIN_NO(59) | 1) +#define PINMUX_GPIO59__FUNC_I2S3_MCK (MTK_PIN_NO(59) | 2) +#define PINMUX_GPIO59__FUNC_DBG_MON_A27 (MTK_PIN_NO(59) | 7) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_TDM_RX_LRCK (MTK_PIN_NO(60) | 1) +#define PINMUX_GPIO60__FUNC_ANT_SEL3 (MTK_PIN_NO(60) | 2) +#define PINMUX_GPIO60__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(60) | 5) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_TDM_RX_BCK (MTK_PIN_NO(61) | 1) +#define PINMUX_GPIO61__FUNC_ANT_SEL4 (MTK_PIN_NO(61) | 2) +#define PINMUX_GPIO61__FUNC_SPINOR_CK (MTK_PIN_NO(61) | 4) +#define PINMUX_GPIO61__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(61) | 5) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_TDM_RX_MCK (MTK_PIN_NO(62) | 1) +#define PINMUX_GPIO62__FUNC_ANT_SEL5 (MTK_PIN_NO(62) | 2) +#define PINMUX_GPIO62__FUNC_SPINOR_CS (MTK_PIN_NO(62) | 4) +#define PINMUX_GPIO62__FUNC_CONN_MCU_TDI (MTK_PIN_NO(62) | 5) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_TDM_RX_DATA0 (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_ANT_SEL6 (MTK_PIN_NO(63) | 2) +#define PINMUX_GPIO63__FUNC_SPINOR_IO0 (MTK_PIN_NO(63) | 4) +#define PINMUX_GPIO63__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(63) | 5) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_TDM_RX_DATA1 (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_ANT_SEL7 (MTK_PIN_NO(64) | 2) +#define PINMUX_GPIO64__FUNC_PWM0 (MTK_PIN_NO(64) | 3) +#define PINMUX_GPIO64__FUNC_SPINOR_IO1 (MTK_PIN_NO(64) | 4) +#define PINMUX_GPIO64__FUNC_CONN_MCU_TCK (MTK_PIN_NO(64) | 5) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_TDM_RX_DATA2 (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_UCTS0 (MTK_PIN_NO(65) | 2) +#define PINMUX_GPIO65__FUNC_PWM1 (MTK_PIN_NO(65) | 3) +#define PINMUX_GPIO65__FUNC_SPINOR_IO2 (MTK_PIN_NO(65) | 4) +#define PINMUX_GPIO65__FUNC_CONN_MCU_TDO (MTK_PIN_NO(65) | 5) +#define PINMUX_GPIO65__FUNC_TP_UCTS1_AO (MTK_PIN_NO(65) | 6) +#define PINMUX_GPIO65__FUNC_TP_UCTS2_AO (MTK_PIN_NO(65) | 7) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_TDM_RX_DATA3 (MTK_PIN_NO(66) | 1) +#define PINMUX_GPIO66__FUNC_URTS0 (MTK_PIN_NO(66) | 2) +#define PINMUX_GPIO66__FUNC_PWM2 (MTK_PIN_NO(66) | 3) +#define PINMUX_GPIO66__FUNC_SPINOR_IO3 (MTK_PIN_NO(66) | 4) +#define PINMUX_GPIO66__FUNC_CONN_MCU_TMS (MTK_PIN_NO(66) | 5) +#define PINMUX_GPIO66__FUNC_TP_URTS1_AO (MTK_PIN_NO(66) | 6) +#define PINMUX_GPIO66__FUNC_TP_URTS2_AO (MTK_PIN_NO(66) | 7) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_MSDC0_DSL (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_MSDC0_CLK (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_MSDC0_CMD (MTK_PIN_NO(69) | 1) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_MSDC0_RSTB (MTK_PIN_NO(70) | 1) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_MSDC0_DAT0 (MTK_PIN_NO(71) | 1) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_MSDC0_DAT1 (MTK_PIN_NO(72) | 1) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_MSDC0_DAT2 (MTK_PIN_NO(73) | 1) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_MSDC0_DAT3 (MTK_PIN_NO(74) | 1) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_MSDC0_DAT4 (MTK_PIN_NO(75) | 1) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_MSDC0_DAT5 (MTK_PIN_NO(76) | 1) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_MSDC0_DAT6 (MTK_PIN_NO(77) | 1) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_MSDC0_DAT7 (MTK_PIN_NO(78) | 1) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_KPCOL0 (MTK_PIN_NO(79) | 1) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_KPCOL1 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_PWM0 (MTK_PIN_NO(80) | 3) +#define PINMUX_GPIO80__FUNC_CLKM0 (MTK_PIN_NO(80) | 4) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_KPROW0 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_PWM1 (MTK_PIN_NO(81) | 3) +#define PINMUX_GPIO81__FUNC_CLKM1 (MTK_PIN_NO(81) | 4) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_KPROW1 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_PWM2 (MTK_PIN_NO(82) | 3) +#define PINMUX_GPIO82__FUNC_CLKM2 (MTK_PIN_NO(82) | 4) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_AP_GOOD (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_GPS_PPS (MTK_PIN_NO(83) | 2) +#define PINMUX_GPIO83__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(83) | 4) +#define PINMUX_GPIO83__FUNC_DBG_MON_A28 (MTK_PIN_NO(83) | 7) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_MSDC1_CLK (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(84) | 2) +#define PINMUX_GPIO84__FUNC_UDI_TCK (MTK_PIN_NO(84) | 4) +#define PINMUX_GPIO84__FUNC_CONN_DSP_JCK (MTK_PIN_NO(84) | 5) +#define PINMUX_GPIO84__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(84) | 6) +#define PINMUX_GPIO84__FUNC_DFD_TCK_XI (MTK_PIN_NO(84) | 7) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_MSDC1_CMD (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(85) | 2) +#define PINMUX_GPIO85__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(85) | 3) +#define PINMUX_GPIO85__FUNC_UDI_TMS (MTK_PIN_NO(85) | 4) +#define PINMUX_GPIO85__FUNC_CONN_DSP_JMS (MTK_PIN_NO(85) | 5) +#define PINMUX_GPIO85__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(85) | 6) +#define PINMUX_GPIO85__FUNC_DFD_TMS (MTK_PIN_NO(85) | 7) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_MSDC1_DAT0 (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(86) | 2) +#define PINMUX_GPIO86__FUNC_UDI_TDI (MTK_PIN_NO(86) | 4) +#define PINMUX_GPIO86__FUNC_CONN_DSP_JDI (MTK_PIN_NO(86) | 5) +#define PINMUX_GPIO86__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(86) | 6) +#define PINMUX_GPIO86__FUNC_DFD_TDI (MTK_PIN_NO(86) | 7) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_MSDC1_DAT1 (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(87) | 2) +#define PINMUX_GPIO87__FUNC_UDI_TDO (MTK_PIN_NO(87) | 4) +#define PINMUX_GPIO87__FUNC_CONN_DSP_JDO (MTK_PIN_NO(87) | 5) +#define PINMUX_GPIO87__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(87) | 6) +#define PINMUX_GPIO87__FUNC_DFD_TDO (MTK_PIN_NO(87) | 7) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_MSDC1_DAT2 (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(88) | 2) +#define PINMUX_GPIO88__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 3) +#define PINMUX_GPIO88__FUNC_UDI_NTRST (MTK_PIN_NO(88) | 4) +#define PINMUX_GPIO88__FUNC_CONN_WIFI_TXD (MTK_PIN_NO(88) | 5) +#define PINMUX_GPIO88__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(88) | 6) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_MSDC1_DAT3 (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(89) | 5) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_IDDIG_P0 (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_PGD_HV_HSC_PWR4 (MTK_PIN_NO(90) | 4) +#define PINMUX_GPIO90__FUNC_GDU_SUM_TROOP2_2 (MTK_PIN_NO(90) | 5) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_USB_DRVVBUS_P0 (MTK_PIN_NO(91) | 1) +#define PINMUX_GPIO91__FUNC_PGD_HV_HSC_PWR5 (MTK_PIN_NO(91) | 4) +#define PINMUX_GPIO91__FUNC_GDU_TROOPS_DET0 (MTK_PIN_NO(91) | 5) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_VBUS_VALID_P0 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_PGD_DA_EFUSE_RDY (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_GDU_TROOPS_DET1 (MTK_PIN_NO(92) | 5) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_IDDIG_P1 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_PWM0 (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_CLKM0 (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_PGD_DA_EFUSE_RDY_PRE (MTK_PIN_NO(93) | 4) +#define PINMUX_GPIO93__FUNC_GDU_TROOPS_DET2 (MTK_PIN_NO(93) | 5) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_USB_DRVVBUS_P1 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_PWM1 (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_CLKM1 (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_PGD_DA_PWRGD_RESET (MTK_PIN_NO(94) | 4) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_VBUS_VALID_P1 (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_PWM2 (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_CLKM2 (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_PGD_DA_PWRGD_ENB (MTK_PIN_NO(95) | 4) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_DSI_TE (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_DBG_MON_A29 (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_DISP_PWM (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_DBG_MON_A30 (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_LCM_RST (MTK_PIN_NO(98) | 1) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_DPI_PCLK (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(99) | 3) +#define PINMUX_GPIO99__FUNC_ANT_SEL0 (MTK_PIN_NO(99) | 5) +#define PINMUX_GPIO99__FUNC_TP_GPIO0_AO (MTK_PIN_NO(99) | 6) +#define PINMUX_GPIO99__FUNC_PGD_LV_LSC_PWR0 (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_DPI_VSYNC (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_KPCOL2 (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_ANT_SEL1 (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_TP_GPIO1_AO (MTK_PIN_NO(100) | 6) +#define PINMUX_GPIO100__FUNC_PGD_LV_LSC_PWR1 (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_DPI_HSYNC (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_KPROW2 (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_ANT_SEL2 (MTK_PIN_NO(101) | 5) +#define PINMUX_GPIO101__FUNC_TP_GPIO2_AO (MTK_PIN_NO(101) | 6) +#define PINMUX_GPIO101__FUNC_PGD_LV_LSC_PWR2 (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_DPI_DE (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_ANT_SEL3 (MTK_PIN_NO(102) | 5) +#define PINMUX_GPIO102__FUNC_TP_GPIO3_AO (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_PGD_LV_LSC_PWR3 (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_DPI_DATA0 (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(103) | 3) +#define PINMUX_GPIO103__FUNC_CLKM0 (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_ANT_SEL4 (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_TP_GPIO4_AO (MTK_PIN_NO(103) | 6) +#define PINMUX_GPIO103__FUNC_PGD_LV_LSC_PWR4 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_DPI_DATA1 (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_GPS_PPS (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_UCTS2 (MTK_PIN_NO(104) | 3) +#define PINMUX_GPIO104__FUNC_CLKM1 (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_ANT_SEL5 (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_TP_GPIO5_AO (MTK_PIN_NO(104) | 6) +#define PINMUX_GPIO104__FUNC_PGD_LV_LSC_PWR5 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_DPI_DATA2 (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_URTS2 (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_CLKM2 (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_ANT_SEL6 (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_TP_GPIO6_AO (MTK_PIN_NO(105) | 6) +#define PINMUX_GPIO105__FUNC_PGD_LV_HSC_PWR0 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_DPI_DATA3 (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_TP_UTXD1_AO (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_UTXD2 (MTK_PIN_NO(106) | 3) +#define PINMUX_GPIO106__FUNC_PWM0 (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_ANT_SEL7 (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_TP_GPIO7_AO (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_PGD_LV_HSC_PWR1 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_DPI_DATA4 (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_TP_URXD1_AO (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_URXD2 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_PWM1 (MTK_PIN_NO(107) | 4) +#define PINMUX_GPIO107__FUNC_GDU_SUM_TROOP0_0 (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_PGD_LV_HSC_PWR2 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_DPI_DATA5 (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_TP_UCTS1_AO (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_UCTS0 (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_PWM2 (MTK_PIN_NO(108) | 4) +#define PINMUX_GPIO108__FUNC_GDU_SUM_TROOP0_1 (MTK_PIN_NO(108) | 6) +#define PINMUX_GPIO108__FUNC_PGD_LV_HSC_PWR3 (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_DPI_DATA6 (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_TP_URTS1_AO (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_URTS0 (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_I2S0_DI (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_I2S2_DI (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_GDU_SUM_TROOP0_2 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_PGD_LV_HSC_PWR4 (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_DPI_DATA7 (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_TP_UCTS2_AO (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_UCTS1 (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_GDU_SUM_TROOP1_0 (MTK_PIN_NO(110) | 6) +#define PINMUX_GPIO110__FUNC_PGD_LV_HSC_PWR5 (MTK_PIN_NO(110) | 7) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_DPI_DATA8 (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_TP_URTS2_AO (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_URTS1 (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_I2S3_MCK (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_GDU_SUM_TROOP1_1 (MTK_PIN_NO(111) | 6) +#define PINMUX_GPIO111__FUNC_PGD_HV_HSC_PWR0 (MTK_PIN_NO(111) | 7) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_DPI_DATA9 (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_TP_URXD2_AO (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_URXD1 (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_I2S3_LRCK (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_I2S1_LRCK (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_GDU_SUM_TROOP1_2 (MTK_PIN_NO(112) | 6) +#define PINMUX_GPIO112__FUNC_PGD_HV_HSC_PWR1 (MTK_PIN_NO(112) | 7) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_DPI_DATA10 (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_TP_UTXD2_AO (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_UTXD1 (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_GDU_SUM_TROOP2_0 (MTK_PIN_NO(113) | 6) +#define PINMUX_GPIO113__FUNC_PGD_HV_HSC_PWR2 (MTK_PIN_NO(113) | 7) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_DPI_DATA11 (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_GDU_SUM_TROOP2_1 (MTK_PIN_NO(114) | 6) +#define PINMUX_GPIO114__FUNC_PGD_HV_HSC_PWR3 (MTK_PIN_NO(114) | 7) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_PCM_CLK (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_I2S0_BCK (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_I2S2_BCK (MTK_PIN_NO(115) | 3) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_PCM_SYNC (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_I2S0_LRCK (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_I2S2_LRCK (MTK_PIN_NO(116) | 3) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_PCM_DI (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_I2S0_DI (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_I2S2_DI (MTK_PIN_NO(117) | 3) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_PCM_DO (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_I2S0_MCK (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_I2S2_MCK (MTK_PIN_NO(118) | 3) +#define PINMUX_GPIO118__FUNC_I2S3_DO (MTK_PIN_NO(118) | 4) +#define PINMUX_GPIO118__FUNC_I2S1_DO (MTK_PIN_NO(118) | 5) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_JTMS_SEL1 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_UDI_TMS (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_DFD_TMS (MTK_PIN_NO(119) | 3) +#define PINMUX_GPIO119__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(119) | 4) +#define PINMUX_GPIO119__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(119) | 5) +#define PINMUX_GPIO119__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(119) | 6) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_JTCK_SEL1 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_UDI_TCK (MTK_PIN_NO(120) | 2) +#define PINMUX_GPIO120__FUNC_DFD_TCK_XI (MTK_PIN_NO(120) | 3) +#define PINMUX_GPIO120__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(120) | 4) +#define PINMUX_GPIO120__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(120) | 5) +#define PINMUX_GPIO120__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(120) | 6) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_JTDI_SEL1 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_UDI_TDI (MTK_PIN_NO(121) | 2) +#define PINMUX_GPIO121__FUNC_DFD_TDI (MTK_PIN_NO(121) | 3) +#define PINMUX_GPIO121__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(121) | 4) +#define PINMUX_GPIO121__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(121) | 5) +#define PINMUX_GPIO121__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(121) | 6) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_JTDO_SEL1 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_UDI_TDO (MTK_PIN_NO(122) | 2) +#define PINMUX_GPIO122__FUNC_DFD_TDO (MTK_PIN_NO(122) | 3) +#define PINMUX_GPIO122__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(122) | 4) +#define PINMUX_GPIO122__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(122) | 5) +#define PINMUX_GPIO122__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(122) | 6) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_UDI_NTRST (MTK_PIN_NO(123) | 2) +#define PINMUX_GPIO123__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(123) | 4) +#define PINMUX_GPIO123__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(123) | 5) +#define PINMUX_GPIO123__FUNC_ADSP_JTAG_TRSTN (MTK_PIN_NO(123) | 6) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_CMMCLK0 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_CLKM0 (MTK_PIN_NO(124) | 2) +#define PINMUX_GPIO124__FUNC_PWM0 (MTK_PIN_NO(124) | 3) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_CMMCLK1 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_CLKM1 (MTK_PIN_NO(125) | 2) +#define PINMUX_GPIO125__FUNC_PWM1 (MTK_PIN_NO(125) | 3) +#define PINMUX_GPIO125__FUNC_DBG_MON_B0 (MTK_PIN_NO(125) | 7) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_CMMCLK2 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_CLKM2 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_PWM2 (MTK_PIN_NO(126) | 3) +#define PINMUX_GPIO126__FUNC_DBG_MON_B1 (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_SCL0 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_SCP_SCL0 (MTK_PIN_NO(127) | 4) +#define PINMUX_GPIO127__FUNC_SCP_SCL1 (MTK_PIN_NO(127) | 5) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_SDA0 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_SCP_SDA0 (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_SCP_SDA1 (MTK_PIN_NO(128) | 5) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_SCL1 (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_SCP_SCL0 (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_SCP_SCL1 (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_DBG_MON_B4 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_SDA1 (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_SCP_SDA0 (MTK_PIN_NO(130) | 4) +#define PINMUX_GPIO130__FUNC_SCP_SDA1 (MTK_PIN_NO(130) | 5) +#define PINMUX_GPIO130__FUNC_DBG_MON_B5 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_SCL2 (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_CONN_UART0_TXD (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_SCP_SCL0 (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_SCP_SCL1 (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_DBG_MON_B6 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_SDA2 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_SSPM_URXD_AO (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_CONN_UART0_RXD (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_SCP_SDA0 (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_SCP_SDA1 (MTK_PIN_NO(132) | 5) +#define PINMUX_GPIO132__FUNC_DBG_MON_B7 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_SCL3 (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_SCP_SCL0 (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_SCP_SCL1 (MTK_PIN_NO(133) | 5) +#define PINMUX_GPIO133__FUNC_DBG_MON_B8 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_SDA3 (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_GPS_PPS (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_SCP_SDA0 (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_SCP_SDA1 (MTK_PIN_NO(134) | 5) +#define PINMUX_GPIO134__FUNC_DBG_MON_B9 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_SCL4 (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_TP_UTXD1_AO (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_UTXD1 (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_SCP_SCL0 (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_SCP_SCL1 (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_DBG_MON_B10 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_SDA4 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_TP_URXD1_AO (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_URXD1 (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_SCP_SDA0 (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_SCP_SDA1 (MTK_PIN_NO(136) | 5) +#define PINMUX_GPIO136__FUNC_DBG_MON_B11 (MTK_PIN_NO(136) | 7) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_SCL5 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_UTXD2 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_UCTS1 (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_SCP_SCL0 (MTK_PIN_NO(137) | 4) +#define PINMUX_GPIO137__FUNC_SCP_SCL1 (MTK_PIN_NO(137) | 5) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_SDA5 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_URXD2 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_URTS1 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_SCP_SDA0 (MTK_PIN_NO(138) | 4) +#define PINMUX_GPIO138__FUNC_SCP_SDA1 (MTK_PIN_NO(138) | 5) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_SCL6 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_UTXD1 (MTK_PIN_NO(139) | 2) +#define PINMUX_GPIO139__FUNC_TP_UTXD1_AO (MTK_PIN_NO(139) | 3) +#define PINMUX_GPIO139__FUNC_SCP_SCL0 (MTK_PIN_NO(139) | 4) +#define PINMUX_GPIO139__FUNC_SCP_SCL1 (MTK_PIN_NO(139) | 5) +#define PINMUX_GPIO139__FUNC_DBG_MON_B12 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_SDA6 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_URXD1 (MTK_PIN_NO(140) | 2) +#define PINMUX_GPIO140__FUNC_TP_URXD1_AO (MTK_PIN_NO(140) | 3) +#define PINMUX_GPIO140__FUNC_SCP_SDA0 (MTK_PIN_NO(140) | 4) +#define PINMUX_GPIO140__FUNC_SCP_SDA1 (MTK_PIN_NO(140) | 5) +#define PINMUX_GPIO140__FUNC_DBG_MON_B13 (MTK_PIN_NO(140) | 7) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_SCL7 (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_URTS0 (MTK_PIN_NO(141) | 2) +#define PINMUX_GPIO141__FUNC_TP_URTS1_AO (MTK_PIN_NO(141) | 3) +#define PINMUX_GPIO141__FUNC_SCP_SCL0 (MTK_PIN_NO(141) | 4) +#define PINMUX_GPIO141__FUNC_SCP_SCL1 (MTK_PIN_NO(141) | 5) +#define PINMUX_GPIO141__FUNC_UDI_TCK (MTK_PIN_NO(141) | 6) +#define PINMUX_GPIO141__FUNC_DBG_MON_B14 (MTK_PIN_NO(141) | 7) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SDA7 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_UCTS0 (MTK_PIN_NO(142) | 2) +#define PINMUX_GPIO142__FUNC_TP_UCTS1_AO (MTK_PIN_NO(142) | 3) +#define PINMUX_GPIO142__FUNC_SCP_SDA0 (MTK_PIN_NO(142) | 4) +#define PINMUX_GPIO142__FUNC_SCP_SDA1 (MTK_PIN_NO(142) | 5) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_SCL8 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_SCP_SCL0 (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_SCP_SCL1 (MTK_PIN_NO(143) | 5) +#define PINMUX_GPIO143__FUNC_DBG_MON_B16 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_SDA8 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_SCP_SDA0 (MTK_PIN_NO(144) | 4) +#define PINMUX_GPIO144__FUNC_SCP_SDA1 (MTK_PIN_NO(144) | 5) +#define PINMUX_GPIO144__FUNC_DBG_MON_B17 (MTK_PIN_NO(144) | 7) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_SCL9 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_CMVREF1 (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_GPS_PPS (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_SCP_SCL0 (MTK_PIN_NO(145) | 4) +#define PINMUX_GPIO145__FUNC_SCP_SCL1 (MTK_PIN_NO(145) | 5) +#define PINMUX_GPIO145__FUNC_DBG_MON_B18 (MTK_PIN_NO(145) | 7) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_SDA9 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_CMVREF0 (MTK_PIN_NO(146) | 2) +#define PINMUX_GPIO146__FUNC_SCP_SDA0 (MTK_PIN_NO(146) | 4) +#define PINMUX_GPIO146__FUNC_SCP_SDA1 (MTK_PIN_NO(146) | 5) +#define PINMUX_GPIO146__FUNC_DBG_MON_B19 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_CMFLASH0 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_LVTS_SDI (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_DPI_DATA12 (MTK_PIN_NO(147) | 3) +#define PINMUX_GPIO147__FUNC_TP_GPIO0_AO (MTK_PIN_NO(147) | 4) +#define PINMUX_GPIO147__FUNC_ANT_SEL3 (MTK_PIN_NO(147) | 5) +#define PINMUX_GPIO147__FUNC_DFD_TCK_XI (MTK_PIN_NO(147) | 6) +#define PINMUX_GPIO147__FUNC_DBG_MON_B20 (MTK_PIN_NO(147) | 7) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_CMFLASH1 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_LVTS_SCF (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_DPI_DATA13 (MTK_PIN_NO(148) | 3) +#define PINMUX_GPIO148__FUNC_TP_GPIO1_AO (MTK_PIN_NO(148) | 4) +#define PINMUX_GPIO148__FUNC_ANT_SEL4 (MTK_PIN_NO(148) | 5) +#define PINMUX_GPIO148__FUNC_DFD_TMS (MTK_PIN_NO(148) | 6) +#define PINMUX_GPIO148__FUNC_DBG_MON_B21 (MTK_PIN_NO(148) | 7) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_CMFLASH2 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_DPI_DATA14 (MTK_PIN_NO(149) | 3) +#define PINMUX_GPIO149__FUNC_TP_GPIO2_AO (MTK_PIN_NO(149) | 4) +#define PINMUX_GPIO149__FUNC_ANT_SEL5 (MTK_PIN_NO(149) | 5) +#define PINMUX_GPIO149__FUNC_DFD_TDI (MTK_PIN_NO(149) | 6) +#define PINMUX_GPIO149__FUNC_DBG_MON_B22 (MTK_PIN_NO(149) | 7) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_DPI_DATA15 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_TP_GPIO3_AO (MTK_PIN_NO(150) | 4) +#define PINMUX_GPIO150__FUNC_ANT_SEL6 (MTK_PIN_NO(150) | 5) +#define PINMUX_GPIO150__FUNC_DFD_TDO (MTK_PIN_NO(150) | 6) +#define PINMUX_GPIO150__FUNC_DBG_MON_B23 (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_DPI_DATA16 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_TP_GPIO4_AO (MTK_PIN_NO(151) | 4) +#define PINMUX_GPIO151__FUNC_ANT_SEL7 (MTK_PIN_NO(151) | 5) +#define PINMUX_GPIO151__FUNC_UDI_TMS (MTK_PIN_NO(151) | 6) +#define PINMUX_GPIO151__FUNC_DBG_MON_B24 (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_CLKM3 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_DPI_DATA17 (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_TP_GPIO5_AO (MTK_PIN_NO(152) | 4) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_DPI_DATA18 (MTK_PIN_NO(153) | 3) +#define PINMUX_GPIO153__FUNC_TP_GPIO6_AO (MTK_PIN_NO(153) | 4) +#define PINMUX_GPIO153__FUNC_UDI_TDI (MTK_PIN_NO(153) | 6) +#define PINMUX_GPIO153__FUNC_DBG_MON_B26 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_PWM0 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_CMVREF2 (MTK_PIN_NO(154) | 2) +#define PINMUX_GPIO154__FUNC_DPI_DATA19 (MTK_PIN_NO(154) | 3) +#define PINMUX_GPIO154__FUNC_TP_GPIO7_AO (MTK_PIN_NO(154) | 4) +#define PINMUX_GPIO154__FUNC_UDI_TDO (MTK_PIN_NO(154) | 6) +#define PINMUX_GPIO154__FUNC_DBG_MON_B27 (MTK_PIN_NO(154) | 7) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_PWM1 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_CMVREF1 (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_DPI_DATA20 (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_UDI_NTRST (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_B28 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_PWM2 (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_CMVREF0 (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_DPI_DATA21 (MTK_PIN_NO(156) | 3) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(157) | 1) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(158) | 1) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(159) | 2) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(160) | 2) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SRCLKENA0 (MTK_PIN_NO(161) | 1) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_SRCLKENA1 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_DBG_MON_A31 (MTK_PIN_NO(162) | 7) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(163) | 2) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_RTC32K_CK (MTK_PIN_NO(164) | 1) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_WATCHDOG (MTK_PIN_NO(165) | 1) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_AUD_CLK_MISO (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_I2S1_MCK (MTK_PIN_NO(166) | 3) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(167) | 2) +#define PINMUX_GPIO167__FUNC_I2S1_BCK (MTK_PIN_NO(167) | 3) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_I2S1_LRCK (MTK_PIN_NO(168) | 3) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_I2S1_DO (MTK_PIN_NO(169) | 3) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_AUD_CLK_MISO (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_I2S2_MCK (MTK_PIN_NO(170) | 3) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_I2S2_BCK (MTK_PIN_NO(171) | 3) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(172) | 2) +#define PINMUX_GPIO172__FUNC_I2S2_LRCK (MTK_PIN_NO(172) | 3) +#define PINMUX_GPIO172__FUNC_VOW_DAT_MISO (MTK_PIN_NO(172) | 4) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(173) | 2) +#define PINMUX_GPIO173__FUNC_I2S2_DI (MTK_PIN_NO(173) | 3) +#define PINMUX_GPIO173__FUNC_VOW_CLK_MISO (MTK_PIN_NO(173) | 4) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_CONN_TOP_CLK (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_AUXIF_CLK (MTK_PIN_NO(174) | 2) +#define PINMUX_GPIO174__FUNC_DFD_TCK_XI (MTK_PIN_NO(174) | 3) +#define PINMUX_GPIO174__FUNC_DBG_MON_B3 (MTK_PIN_NO(174) | 7) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_CONN_TOP_DATA (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_AUXIF_ST (MTK_PIN_NO(175) | 2) +#define PINMUX_GPIO175__FUNC_DFD_TMS (MTK_PIN_NO(175) | 3) +#define PINMUX_GPIO175__FUNC_DBG_MON_B15 (MTK_PIN_NO(175) | 7) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_DFD_TDI (MTK_PIN_NO(176) | 3) +#define PINMUX_GPIO176__FUNC_DBG_MON_B2 (MTK_PIN_NO(176) | 7) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_DFD_TDO (MTK_PIN_NO(177) | 3) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_CONN_HRST_B (MTK_PIN_NO(178) | 1) +#define PINMUX_GPIO178__FUNC_UDI_TMS (MTK_PIN_NO(178) | 3) +#define PINMUX_GPIO178__FUNC_DBG_MON_B25 (MTK_PIN_NO(178) | 7) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_CONN_WB_PTA (MTK_PIN_NO(179) | 1) +#define PINMUX_GPIO179__FUNC_UDI_TCK (MTK_PIN_NO(179) | 3) +#define PINMUX_GPIO179__FUNC_DBG_MON_B29 (MTK_PIN_NO(179) | 7) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(180) | 1) +#define PINMUX_GPIO180__FUNC_UDI_TDI (MTK_PIN_NO(180) | 3) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(181) | 1) +#define PINMUX_GPIO181__FUNC_UDI_TDO (MTK_PIN_NO(181) | 3) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(182) | 1) +#define PINMUX_GPIO182__FUNC_UDI_NTRST (MTK_PIN_NO(182) | 3) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_SPMI_SCL (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_SPMI_SDA (MTK_PIN_NO(184) | 1) + +#endif /* __MT8186_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/sppctl-sp7021.h b/include/dt-bindings/pinctrl/sppctl-sp7021.h new file mode 100644 index 000000000000..629aa9b5ffbc --- /dev/null +++ b/include/dt-bindings/pinctrl/sppctl-sp7021.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Sunplus SP7021 dt-bindings Pinctrl header file + * Copyright (C) Sunplus Tech/Tibbo Tech. + * Author: Dvorkin Dmitry + */ + +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ +#define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ + +#include + +/* + * Please don't change the order of the following defines. + * They are based on order of 'hardware' control register + * defined in MOON2 ~ MOON3 registers. + */ +#define MUXF_GPIO 0 +#define MUXF_IOP 1 +#define MUXF_L2SW_CLK_OUT 2 +#define MUXF_L2SW_MAC_SMI_MDC 3 +#define MUXF_L2SW_LED_FLASH0 4 +#define MUXF_L2SW_LED_FLASH1 5 +#define MUXF_L2SW_LED_ON0 6 +#define MUXF_L2SW_LED_ON1 7 +#define MUXF_L2SW_MAC_SMI_MDIO 8 +#define MUXF_L2SW_P0_MAC_RMII_TXEN 9 +#define MUXF_L2SW_P0_MAC_RMII_TXD0 10 +#define MUXF_L2SW_P0_MAC_RMII_TXD1 11 +#define MUXF_L2SW_P0_MAC_RMII_CRSDV 12 +#define MUXF_L2SW_P0_MAC_RMII_RXD0 13 +#define MUXF_L2SW_P0_MAC_RMII_RXD1 14 +#define MUXF_L2SW_P0_MAC_RMII_RXER 15 +#define MUXF_L2SW_P1_MAC_RMII_TXEN 16 +#define MUXF_L2SW_P1_MAC_RMII_TXD0 17 +#define MUXF_L2SW_P1_MAC_RMII_TXD1 18 +#define MUXF_L2SW_P1_MAC_RMII_CRSDV 19 +#define MUXF_L2SW_P1_MAC_RMII_RXD0 20 +#define MUXF_L2SW_P1_MAC_RMII_RXD1 21 +#define MUXF_L2SW_P1_MAC_RMII_RXER 22 +#define MUXF_DAISY_MODE 23 +#define MUXF_SDIO_CLK 24 +#define MUXF_SDIO_CMD 25 +#define MUXF_SDIO_D0 26 +#define MUXF_SDIO_D1 27 +#define MUXF_SDIO_D2 28 +#define MUXF_SDIO_D3 29 +#define MUXF_PWM0 30 +#define MUXF_PWM1 31 +#define MUXF_PWM2 32 +#define MUXF_PWM3 33 +#define MUXF_PWM4 34 +#define MUXF_PWM5 35 +#define MUXF_PWM6 36 +#define MUXF_PWM7 37 +#define MUXF_ICM0_D 38 +#define MUXF_ICM1_D 39 +#define MUXF_ICM2_D 40 +#define MUXF_ICM3_D 41 +#define MUXF_ICM0_CLK 42 +#define MUXF_ICM1_CLK 43 +#define MUXF_ICM2_CLK 44 +#define MUXF_ICM3_CLK 45 +#define MUXF_SPIM0_INT 46 +#define MUXF_SPIM0_CLK 47 +#define MUXF_SPIM0_EN 48 +#define MUXF_SPIM0_DO 49 +#define MUXF_SPIM0_DI 50 +#define MUXF_SPIM1_INT 51 +#define MUXF_SPIM1_CLK 52 +#define MUXF_SPIM1_EN 53 +#define MUXF_SPIM1_DO 54 +#define MUXF_SPIM1_DI 55 +#define MUXF_SPIM2_INT 56 +#define MUXF_SPIM2_CLK 57 +#define MUXF_SPIM2_EN 58 +#define MUXF_SPIM2_DO 59 +#define MUXF_SPIM2_DI 60 +#define MUXF_SPIM3_INT 61 +#define MUXF_SPIM3_CLK 62 +#define MUXF_SPIM3_EN 63 +#define MUXF_SPIM3_DO 64 +#define MUXF_SPIM3_DI 65 +#define MUXF_SPI0S_INT 66 +#define MUXF_SPI0S_CLK 67 +#define MUXF_SPI0S_EN 68 +#define MUXF_SPI0S_DO 69 +#define MUXF_SPI0S_DI 70 +#define MUXF_SPI1S_INT 71 +#define MUXF_SPI1S_CLK 72 +#define MUXF_SPI1S_EN 73 +#define MUXF_SPI1S_DO 74 +#define MUXF_SPI1S_DI 75 +#define MUXF_SPI2S_INT 76 +#define MUXF_SPI2S_CLK 77 +#define MUXF_SPI2S_EN 78 +#define MUXF_SPI2S_DO 79 +#define MUXF_SPI2S_DI 80 +#define MUXF_SPI3S_INT 81 +#define MUXF_SPI3S_CLK 82 +#define MUXF_SPI3S_EN 83 +#define MUXF_SPI3S_DO 84 +#define MUXF_SPI3S_DI 85 +#define MUXF_I2CM0_CLK 86 +#define MUXF_I2CM0_DAT 87 +#define MUXF_I2CM1_CLK 88 +#define MUXF_I2CM1_DAT 89 +#define MUXF_I2CM2_CLK 90 +#define MUXF_I2CM2_DAT 91 +#define MUXF_I2CM3_CLK 92 +#define MUXF_I2CM3_DAT 93 +#define MUXF_UA1_TX 94 +#define MUXF_UA1_RX 95 +#define MUXF_UA1_CTS 96 +#define MUXF_UA1_RTS 97 +#define MUXF_UA2_TX 98 +#define MUXF_UA2_RX 99 +#define MUXF_UA2_CTS 100 +#define MUXF_UA2_RTS 101 +#define MUXF_UA3_TX 102 +#define MUXF_UA3_RX 103 +#define MUXF_UA3_CTS 104 +#define MUXF_UA3_RTS 105 +#define MUXF_UA4_TX 106 +#define MUXF_UA4_RX 107 +#define MUXF_UA4_CTS 108 +#define MUXF_UA4_RTS 109 +#define MUXF_TIMER0_INT 110 +#define MUXF_TIMER1_INT 111 +#define MUXF_TIMER2_INT 112 +#define MUXF_TIMER3_INT 113 +#define MUXF_GPIO_INT0 114 +#define MUXF_GPIO_INT1 115 +#define MUXF_GPIO_INT2 116 +#define MUXF_GPIO_INT3 117 +#define MUXF_GPIO_INT4 118 +#define MUXF_GPIO_INT5 119 +#define MUXF_GPIO_INT6 120 +#define MUXF_GPIO_INT7 121 + +/* + * Please don't change the order of the following defines. + * They are based on order of items in array 'sppctl_list_funcs' + * in Sunplus pinctrl driver. + */ +#define GROP_SPI_FLASH 122 +#define GROP_SPI_FLASH_4BIT 123 +#define GROP_SPI_NAND 124 +#define GROP_CARD0_EMMC 125 +#define GROP_SD_CARD 126 +#define GROP_UA0 127 +#define GROP_ACHIP_DEBUG 128 +#define GROP_ACHIP_UA2AXI 129 +#define GROP_FPGA_IFX 130 +#define GROP_HDMI_TX 131 +#define GROP_AUD_EXT_ADC_IFX0 132 +#define GROP_AUD_EXT_DAC_IFX0 133 +#define GROP_SPDIF_RX 134 +#define GROP_SPDIF_TX 135 +#define GROP_TDMTX_IFX0 136 +#define GROP_TDMRX_IFX0 137 +#define GROP_PDMRX_IFX0 138 +#define GROP_PCM_IEC_TX 139 +#define GROP_LCDIF 140 +#define GROP_DVD_DSP_DEBUG 141 +#define GROP_I2C_DEBUG 142 +#define GROP_I2C_SLAVE 143 +#define GROP_WAKEUP 144 +#define GROP_UART2AXI 145 +#define GROP_USB0_I2C 146 +#define GROP_USB1_I2C 147 +#define GROP_USB0_OTG 148 +#define GROP_USB1_OTG 149 +#define GROP_UPHY0_DEBUG 150 +#define GROP_UPHY1_DEBUG 151 +#define GROP_UPHY0_EXT 152 +#define GROP_PROBE_PORT 153 + +#endif diff --git a/include/dt-bindings/pinctrl/sppctl.h b/include/dt-bindings/pinctrl/sppctl.h new file mode 100644 index 000000000000..50557265dbfc --- /dev/null +++ b/include/dt-bindings/pinctrl/sppctl.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Sunplus dt-bindings Pinctrl header file + * Copyright (C) Sunplus Tech / Tibbo Tech. + * Author: Dvorkin Dmitry + */ + +#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_H__ +#define __DT_BINDINGS_PINCTRL_SPPCTL_H__ + +#define IOP_G_MASTE (0x01 << 0) +#define IOP_G_FIRST (0x01 << 1) + +#define SPPCTL_PCTL_G_PMUX (0x00 | IOP_G_MASTE) +#define SPPCTL_PCTL_G_GPIO (IOP_G_FIRST | IOP_G_MASTE) +#define SPPCTL_PCTL_G_IOPP (IOP_G_FIRST | 0x00) + +#define SPPCTL_PCTL_L_OUT (0x01 << 0) /* Output LOW */ +#define SPPCTL_PCTL_L_OU1 (0x01 << 1) /* Output HIGH */ +#define SPPCTL_PCTL_L_INV (0x01 << 2) /* Input Invert */ +#define SPPCTL_PCTL_L_ONV (0x01 << 3) /* Output Invert */ +#define SPPCTL_PCTL_L_ODR (0x01 << 4) /* Output Open Drain */ + +/* + * pack into 32-bit value: + * pin# (8bit), typ (8bit), function (8bit), flag (8bit) + */ +#define SPPCTL_IOPAD(pin, typ, fun, flg) (((pin) << 24) | ((typ) << 16) | \ + ((fun) << 8) | (flg)) + +#endif diff --git a/include/linux/cfi.h b/include/linux/cfi.h index 879744aaa6e0..c6dfc1ed0626 100644 --- a/include/linux/cfi.h +++ b/include/linux/cfi.h @@ -34,8 +34,17 @@ static inline void cfi_module_remove(struct module *mod, unsigned long base_addr #else /* !CONFIG_CFI_CLANG */ -#define __CFI_ADDRESSABLE(fn, __attr) +#ifdef CONFIG_X86_KERNEL_IBT + +#define __CFI_ADDRESSABLE(fn, __attr) \ + const void *__cfi_jt_ ## fn __visible __attr = (void *)&fn + +#endif /* CONFIG_X86_KERNEL_IBT */ #endif /* CONFIG_CFI_CLANG */ +#ifndef __CFI_ADDRESSABLE +#define __CFI_ADDRESSABLE(fn, __attr) +#endif + #endif /* _LINUX_CFI_H */ diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 0f7fd205ab7e..219aa5ddbc73 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -125,18 +125,11 @@ void ftrace_likely_update(struct ftrace_likely_data *f, int val, }) #define annotate_unreachable() __annotate_unreachable(__COUNTER__) -#define ASM_REACHABLE \ - "998:\n\t" \ - ".pushsection .discard.reachable\n\t" \ - ".long 998b - .\n\t" \ - ".popsection\n\t" - /* Annotate a C jump table to allow objtool to follow the code flow */ #define __annotate_jump_table __section(".rodata..c_jump_table") #else #define annotate_unreachable() -# define ASM_REACHABLE #define __annotate_jump_table #endif diff --git a/include/linux/cred.h b/include/linux/cred.h index fcbc6885cc09..9ed9232af934 100644 --- a/include/linux/cred.h +++ b/include/linux/cred.h @@ -176,7 +176,7 @@ extern int set_cred_ucounts(struct cred *); * check for validity of credentials */ #ifdef CONFIG_DEBUG_CREDENTIALS -extern void __invalid_creds(const struct cred *, const char *, unsigned); +extern void __noreturn __invalid_creds(const struct cred *, const char *, unsigned); extern void __validate_process_creds(struct task_struct *, const char *, unsigned); diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index 6150d11a607e..dca2b1355bb1 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -61,14 +61,6 @@ */ #define DMA_ATTR_PRIVILEGED (1UL << 9) -/* - * This is a hint to the DMA-mapping subsystem that the device is expected - * to overwrite the entire mapped size, thus the caller does not require any - * of the previous buffer contents to be preserved. This allows - * bounce-buffering implementations to optimise DMA_FROM_DEVICE transfers. - */ -#define DMA_ATTR_OVERWRITE (1UL << 10) - /* * A dma_addr_t can hold any valid DMA or bus address for the platform. It can * be given to a device to use as a DMA source or target. It is specific to a diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h index 5f1859836deb..312ff997c743 100644 --- a/include/linux/kprobes.h +++ b/include/linux/kprobes.h @@ -265,7 +265,6 @@ extern int arch_init_kprobes(void); extern void kprobes_inc_nmissed_count(struct kprobe *p); extern bool arch_within_kprobe_blacklist(unsigned long addr); extern int arch_populate_kprobe_blacklist(void); -extern bool arch_kprobe_on_func_entry(unsigned long offset); extern int kprobe_on_func_entry(kprobe_opcode_t *addr, const char *sym, unsigned long offset); extern bool within_kprobe_blacklist(unsigned long addr); @@ -384,6 +383,8 @@ static inline struct kprobe_ctlblk *get_kprobe_ctlblk(void) } kprobe_opcode_t *kprobe_lookup_name(const char *name, unsigned int offset); +kprobe_opcode_t *arch_adjust_kprobe_addr(unsigned long addr, unsigned long offset, bool *on_func_entry); + int register_kprobe(struct kprobe *p); void unregister_kprobe(struct kprobe *p); int register_kprobes(struct kprobe **kps, int num); diff --git a/include/linux/objtool.h b/include/linux/objtool.h index aca52db2f3f3..586d35720f13 100644 --- a/include/linux/objtool.h +++ b/include/linux/objtool.h @@ -77,6 +77,18 @@ struct unwind_hint { #define STACK_FRAME_NON_STANDARD_FP(func) #endif +#define ANNOTATE_NOENDBR \ + "986: \n\t" \ + ".pushsection .discard.noendbr\n\t" \ + _ASM_PTR " 986b\n\t" \ + ".popsection\n\t" + +#define ASM_REACHABLE \ + "998:\n\t" \ + ".pushsection .discard.reachable\n\t" \ + ".long 998b - .\n\t" \ + ".popsection\n\t" + #else /* __ASSEMBLY__ */ /* @@ -129,6 +141,20 @@ struct unwind_hint { .popsection .endm +.macro ANNOTATE_NOENDBR +.Lhere_\@: + .pushsection .discard.noendbr + .quad .Lhere_\@ + .popsection +.endm + +.macro REACHABLE +.Lhere_\@: + .pushsection .discard.reachable + .long .Lhere_\@ - . + .popsection +.endm + #endif /* __ASSEMBLY__ */ #else /* !CONFIG_STACK_VALIDATION */ @@ -139,12 +165,18 @@ struct unwind_hint { "\n\t" #define STACK_FRAME_NON_STANDARD(func) #define STACK_FRAME_NON_STANDARD_FP(func) +#define ANNOTATE_NOENDBR +#define ASM_REACHABLE #else #define ANNOTATE_INTRA_FUNCTION_CALL .macro UNWIND_HINT sp_reg:req sp_offset=0 type:req end=0 .endm .macro STACK_FRAME_NON_STANDARD func:req .endm +.macro ANNOTATE_NOENDBR +.endm +.macro REACHABLE +.endm #endif #endif /* CONFIG_STACK_VALIDATION */ diff --git a/include/linux/sched/task.h b/include/linux/sched/task.h index e84e54d1b490..719c9a6cac8d 100644 --- a/include/linux/sched/task.h +++ b/include/linux/sched/task.h @@ -79,7 +79,7 @@ static inline void exit_thread(struct task_struct *tsk) { } #endif -extern void do_group_exit(int); +extern __noreturn void do_group_exit(int); extern void exit_files(struct task_struct *); extern void exit_itimers(struct signal_struct *); diff --git a/include/linux/soc/ti/ti-msgmgr.h b/include/linux/soc/ti/ti-msgmgr.h index 1f6e76d423cf..69a8d7682c4b 100644 --- a/include/linux/soc/ti/ti-msgmgr.h +++ b/include/linux/soc/ti/ti-msgmgr.h @@ -1,7 +1,7 @@ /* * Texas Instruments' Message Manager * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/ * Nishanth Menon * * This program is free software; you can redistribute it and/or modify @@ -17,10 +17,14 @@ #ifndef TI_MSGMGR_H #define TI_MSGMGR_H +struct mbox_chan; + /** * struct ti_msgmgr_message - Message Manager structure * @len: Length of data in the Buffer * @buf: Buffer pointer + * @chan_rx: Expected channel for response, must be provided to use polled rx + * @timeout_rx_ms: Timeout value to use if polling for response * * This is the structure for data used in mbox_send_message * the length of data buffer used depends on the SoC integration @@ -30,6 +34,8 @@ struct ti_msgmgr_message { size_t len; u8 *buf; + struct mbox_chan *chan_rx; + int timeout_rx_ms; }; #endif /* TI_MSGMGR_H */ diff --git a/include/linux/usb/typec.h b/include/linux/usb/typec.h index 7ba45a97eeae..fdf737d48b3b 100644 --- a/include/linux/usb/typec.h +++ b/include/linux/usb/typec.h @@ -295,6 +295,9 @@ int typec_set_mode(struct typec_port *port, int mode); void *typec_get_drvdata(struct typec_port *port); +int typec_get_fw_cap(struct typec_capability *cap, + struct fwnode_handle *fwnode); + int typec_find_pwr_opmode(const char *name); int typec_find_orientation(const char *name); int typec_find_port_power_role(const char *name); diff --git a/include/linux/usb/xhci-dbgp.h b/include/linux/usb/xhci-dbgp.h index 0a37f1283bf0..01fe768873f9 100644 --- a/include/linux/usb/xhci-dbgp.h +++ b/include/linux/usb/xhci-dbgp.h @@ -15,7 +15,7 @@ #define __LINUX_XHCI_DBGP_H #ifdef CONFIG_EARLY_PRINTK_USB_XDBC -int __init early_xdbc_parse_parameter(char *s); +int __init early_xdbc_parse_parameter(char *s, int keep_early); int __init early_xdbc_setup_hardware(void); void __init early_xdbc_register_console(void); #else diff --git a/kernel/bpf/trampoline.c b/kernel/bpf/trampoline.c index 0b41fa993825..ada97751ae1b 100644 --- a/kernel/bpf/trampoline.c +++ b/kernel/bpf/trampoline.c @@ -117,18 +117,6 @@ static void bpf_trampoline_module_put(struct bpf_trampoline *tr) tr->mod = NULL; } -static int is_ftrace_location(void *ip) -{ - long addr; - - addr = ftrace_location((long)ip); - if (!addr) - return 0; - if (WARN_ON_ONCE(addr != (long)ip)) - return -EFAULT; - return 1; -} - static int unregister_fentry(struct bpf_trampoline *tr, void *old_addr) { void *ip = tr->func.addr; @@ -160,12 +148,12 @@ static int modify_fentry(struct bpf_trampoline *tr, void *old_addr, void *new_ad static int register_fentry(struct bpf_trampoline *tr, void *new_addr) { void *ip = tr->func.addr; + unsigned long faddr; int ret; - ret = is_ftrace_location(ip); - if (ret < 0) - return ret; - tr->func.ftrace_managed = ret; + faddr = ftrace_location((unsigned long)ip); + if (faddr) + tr->func.ftrace_managed = true; if (bpf_trampoline_module_get(tr)) return -ENOENT; diff --git a/kernel/cred.c b/kernel/cred.c index bd863bc50f0e..d4a529cd4737 100644 --- a/kernel/cred.c +++ b/kernel/cred.c @@ -876,7 +876,7 @@ static void dump_invalid_creds(const struct cred *cred, const char *label, /* * report use of invalid credentials */ -void __invalid_creds(const struct cred *cred, const char *file, unsigned line) +void __noreturn __invalid_creds(const struct cred *cred, const char *file, unsigned line) { printk(KERN_ERR "CRED: Invalid credentials\n"); printk(KERN_ERR "CRED: At %s:%u\n", file, line); diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c index bfc56cb21705..6c350555e5a1 100644 --- a/kernel/dma/swiotlb.c +++ b/kernel/dma/swiotlb.c @@ -627,10 +627,14 @@ phys_addr_t swiotlb_tbl_map_single(struct device *dev, phys_addr_t orig_addr, for (i = 0; i < nr_slots(alloc_size + offset); i++) mem->slots[index + i].orig_addr = slot_addr(orig_addr, i); tlb_addr = slot_addr(mem->start, index) + offset; - if (!(attrs & DMA_ATTR_SKIP_CPU_SYNC) && - (!(attrs & DMA_ATTR_OVERWRITE) || dir == DMA_TO_DEVICE || - dir == DMA_BIDIRECTIONAL)) - swiotlb_bounce(dev, tlb_addr, mapping_size, DMA_TO_DEVICE); + /* + * When dir == DMA_FROM_DEVICE we could omit the copy from the orig + * to the tlb buffer, if we knew for sure the device will + * overwirte the entire current content. But we don't. Thus + * unconditional bounce may prevent leaking swiotlb content (i.e. + * kernel memory) to user-space. + */ + swiotlb_bounce(dev, tlb_addr, mapping_size, DMA_TO_DEVICE); return tlb_addr; } diff --git a/kernel/exit.c b/kernel/exit.c index 9b1862488bf2..c8ce55541a25 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -895,7 +895,7 @@ SYSCALL_DEFINE1(exit, int, error_code) * Take down every thread in the group. This is called by fatal signals * as well as by sys_exit_group (below). */ -void +void __noreturn do_group_exit(int exit_code) { struct signal_struct *sig = current->signal; diff --git a/kernel/kprobes.c b/kernel/kprobes.c index 94cab8c9ce56..185badc780b7 100644 --- a/kernel/kprobes.c +++ b/kernel/kprobes.c @@ -1488,25 +1488,69 @@ bool within_kprobe_blacklist(unsigned long addr) return false; } +/* + * arch_adjust_kprobe_addr - adjust the address + * @addr: symbol base address + * @offset: offset within the symbol + * @on_func_entry: was this @addr+@offset on the function entry + * + * Typically returns @addr + @offset, except for special cases where the + * function might be prefixed by a CFI landing pad, in that case any offset + * inside the landing pad is mapped to the first 'real' instruction of the + * symbol. + * + * Specifically, for things like IBT/BTI, skip the resp. ENDBR/BTI.C + * instruction at +0. + */ +kprobe_opcode_t *__weak arch_adjust_kprobe_addr(unsigned long addr, + unsigned long offset, + bool *on_func_entry) +{ + *on_func_entry = !offset; + return (kprobe_opcode_t *)(addr + offset); +} + /* * If 'symbol_name' is specified, look it up and add the 'offset' * to it. This way, we can specify a relative address to a symbol. * This returns encoded errors if it fails to look up symbol or invalid * combination of parameters. */ -static kprobe_opcode_t *_kprobe_addr(kprobe_opcode_t *addr, - const char *symbol_name, unsigned int offset) +static kprobe_opcode_t * +_kprobe_addr(kprobe_opcode_t *addr, const char *symbol_name, + unsigned long offset, bool *on_func_entry) { if ((symbol_name && addr) || (!symbol_name && !addr)) goto invalid; if (symbol_name) { + /* + * Input: @sym + @offset + * Output: @addr + @offset + * + * NOTE: kprobe_lookup_name() does *NOT* fold the offset + * argument into it's output! + */ addr = kprobe_lookup_name(symbol_name, offset); if (!addr) return ERR_PTR(-ENOENT); } - addr = (kprobe_opcode_t *)(((char *)addr) + offset); + /* + * So here we have @addr + @offset, displace it into a new + * @addr' + @offset' where @addr' is the symbol start address. + */ + addr = (void *)addr + offset; + if (!kallsyms_lookup_size_offset((unsigned long)addr, NULL, &offset)) + return ERR_PTR(-ENOENT); + addr = (void *)addr - offset; + + /* + * Then ask the architecture to re-combine them, taking care of + * magical function entry details while telling us if this was indeed + * at the start of the function. + */ + addr = arch_adjust_kprobe_addr((unsigned long)addr, offset, on_func_entry); if (addr) return addr; @@ -1516,7 +1560,8 @@ invalid: static kprobe_opcode_t *kprobe_addr(struct kprobe *p) { - return _kprobe_addr(p->addr, p->symbol_name, p->offset); + bool on_func_entry; + return _kprobe_addr(p->addr, p->symbol_name, p->offset, &on_func_entry); } /* @@ -1562,14 +1607,10 @@ static inline int warn_kprobe_rereg(struct kprobe *p) static int check_ftrace_location(struct kprobe *p) { - unsigned long ftrace_addr; + unsigned long addr = (unsigned long)p->addr; - ftrace_addr = ftrace_location((unsigned long)p->addr); - if (ftrace_addr) { + if (ftrace_location(addr) == addr) { #ifdef CONFIG_KPROBES_ON_FTRACE - /* Given address is not on the instruction boundary */ - if ((unsigned long)p->addr != ftrace_addr) - return -EILSEQ; p->flags |= KPROBE_FLAG_FTRACE; #else /* !CONFIG_KPROBES_ON_FTRACE */ return -EINVAL; @@ -2047,11 +2088,6 @@ static int pre_handler_kretprobe(struct kprobe *p, struct pt_regs *regs) } NOKPROBE_SYMBOL(pre_handler_kretprobe); -bool __weak arch_kprobe_on_func_entry(unsigned long offset) -{ - return !offset; -} - /** * kprobe_on_func_entry() -- check whether given address is function entry * @addr: Target address @@ -2067,15 +2103,13 @@ bool __weak arch_kprobe_on_func_entry(unsigned long offset) */ int kprobe_on_func_entry(kprobe_opcode_t *addr, const char *sym, unsigned long offset) { - kprobe_opcode_t *kp_addr = _kprobe_addr(addr, sym, offset); + bool on_func_entry; + kprobe_opcode_t *kp_addr = _kprobe_addr(addr, sym, offset, &on_func_entry); if (IS_ERR(kp_addr)) return PTR_ERR(kp_addr); - if (!kallsyms_lookup_size_offset((unsigned long)kp_addr, NULL, &offset)) - return -ENOENT; - - if (!arch_kprobe_on_func_entry(offset)) + if (!on_func_entry) return -EINVAL; return 0; diff --git a/kernel/livepatch/patch.c b/kernel/livepatch/patch.c index fe316c021d73..c172bf92b576 100644 --- a/kernel/livepatch/patch.c +++ b/kernel/livepatch/patch.c @@ -124,19 +124,6 @@ unlock: ftrace_test_recursion_unlock(bit); } -/* - * Convert a function address into the appropriate ftrace location. - * - * Usually this is just the address of the function, but on some architectures - * it's more complicated so allow them to provide a custom behaviour. - */ -#ifndef klp_get_ftrace_location -static unsigned long klp_get_ftrace_location(unsigned long faddr) -{ - return faddr; -} -#endif - static void klp_unpatch_func(struct klp_func *func) { struct klp_ops *ops; @@ -153,8 +140,7 @@ static void klp_unpatch_func(struct klp_func *func) if (list_is_singular(&ops->func_stack)) { unsigned long ftrace_loc; - ftrace_loc = - klp_get_ftrace_location((unsigned long)func->old_func); + ftrace_loc = ftrace_location((unsigned long)func->old_func); if (WARN_ON(!ftrace_loc)) return; @@ -186,8 +172,7 @@ static int klp_patch_func(struct klp_func *func) if (!ops) { unsigned long ftrace_loc; - ftrace_loc = - klp_get_ftrace_location((unsigned long)func->old_func); + ftrace_loc = ftrace_location((unsigned long)func->old_func); if (!ftrace_loc) { pr_err("failed to find location for function '%s'\n", func->old_name); diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 2e114659f7f8..4f1d2f5e7263 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -1568,17 +1568,34 @@ unsigned long ftrace_location_range(unsigned long start, unsigned long end) } /** - * ftrace_location - return true if the ip giving is a traced location + * ftrace_location - return the ftrace location * @ip: the instruction pointer to check * - * Returns rec->ip if @ip given is a pointer to a ftrace location. - * That is, the instruction that is either a NOP or call to - * the function tracer. It checks the ftrace internal tables to - * determine if the address belongs or not. + * If @ip matches the ftrace location, return @ip. + * If @ip matches sym+0, return sym's ftrace location. + * Otherwise, return 0. */ unsigned long ftrace_location(unsigned long ip) { - return ftrace_location_range(ip, ip); + struct dyn_ftrace *rec; + unsigned long offset; + unsigned long size; + + rec = lookup_rec(ip, ip); + if (!rec) { + if (!kallsyms_lookup_size_offset(ip, &size, &offset)) + goto out; + + /* map sym+0 to __fentry__ */ + if (!offset) + rec = lookup_rec(ip, ip + size - 1); + } + + if (rec) + return rec->ip; + +out: + return 0; } /** @@ -4962,7 +4979,8 @@ __ftrace_match_addr(struct ftrace_hash *hash, unsigned long ip, int remove) { struct ftrace_func_entry *entry; - if (!ftrace_location(ip)) + ip = ftrace_location(ip); + if (!ip) return -EINVAL; if (remove) { @@ -5131,11 +5149,16 @@ int register_ftrace_direct(unsigned long ip, unsigned long addr) struct ftrace_func_entry *entry; struct ftrace_hash *free_hash = NULL; struct dyn_ftrace *rec; - int ret = -EBUSY; + int ret = -ENODEV; mutex_lock(&direct_mutex); + ip = ftrace_location(ip); + if (!ip) + goto out_unlock; + /* See if there's a direct function at @ip already */ + ret = -EBUSY; if (ftrace_find_rec_direct(ip)) goto out_unlock; @@ -5243,6 +5266,10 @@ int unregister_ftrace_direct(unsigned long ip, unsigned long addr) mutex_lock(&direct_mutex); + ip = ftrace_location(ip); + if (!ip) + goto out_unlock; + entry = find_direct_entry(&ip, NULL); if (!entry) goto out_unlock; @@ -5375,6 +5402,11 @@ int modify_ftrace_direct(unsigned long ip, mutex_lock(&direct_mutex); mutex_lock(&ftrace_lock); + + ip = ftrace_location(ip); + if (!ip) + goto out_unlock; + entry = find_direct_entry(&ip, &rec); if (!entry) goto out_unlock; diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index cffbcc4cf28b..4823593a945f 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -3674,12 +3674,17 @@ static char *trace_iter_expand_format(struct trace_iterator *iter) } /* Returns true if the string is safe to dereference from an event */ -static bool trace_safe_str(struct trace_iterator *iter, const char *str) +static bool trace_safe_str(struct trace_iterator *iter, const char *str, + bool star, int len) { unsigned long addr = (unsigned long)str; struct trace_event *trace_event; struct trace_event_call *event; + /* Ignore strings with no length */ + if (star && !len) + return true; + /* OK if part of the event data */ if ((addr >= (unsigned long)iter->ent) && (addr < (unsigned long)iter->ent + iter->ent_size)) @@ -3865,7 +3870,7 @@ void trace_check_vprintf(struct trace_iterator *iter, const char *fmt, * instead. See samples/trace_events/trace-events-sample.h * for reference. */ - if (WARN_ONCE(!trace_safe_str(iter, str), + if (WARN_ONCE(!trace_safe_str(iter, str, star, len), "fmt: '%s' current_buffer: '%s'", fmt, show_buffer(&iter->seq))) { int ret; diff --git a/mm/memblock.c b/mm/memblock.c index 7519e66859ba..837245518df6 100644 --- a/mm/memblock.c +++ b/mm/memblock.c @@ -1284,11 +1284,10 @@ __next_mem_pfn_range_in_zone(u64 *idx, struct zone *zone, { int zone_nid = zone_to_nid(zone); phys_addr_t spa, epa; - int nid; __next_mem_range(idx, zone_nid, MEMBLOCK_NONE, &memblock.memory, &memblock.reserved, - &spa, &epa, &nid); + &spa, &epa, NULL); while (*idx != U64_MAX) { unsigned long epfn = PFN_DOWN(epa); @@ -1315,7 +1314,7 @@ __next_mem_pfn_range_in_zone(u64 *idx, struct zone *zone, __next_mem_range(idx, zone_nid, MEMBLOCK_NONE, &memblock.memory, &memblock.reserved, - &spa, &epa, &nid); + &spa, &epa, NULL); } /* signal end of iteration */ diff --git a/mm/slab.c b/mm/slab.c index d9dec7a8fd79..b04e40078bdf 100644 --- a/mm/slab.c +++ b/mm/slab.c @@ -3422,6 +3422,7 @@ static __always_inline void __cache_free(struct kmem_cache *cachep, void *objp, if (is_kfence_address(objp)) { kmemleak_free_recursive(objp, cachep->flags); + memcg_slab_free_hook(cachep, &objp, 1); __kfence_free(objp); return; } diff --git a/samples/ftrace/ftrace-direct-modify.c b/samples/ftrace/ftrace-direct-modify.c index 2c7c31893551..39146fa83e20 100644 --- a/samples/ftrace/ftrace-direct-modify.c +++ b/samples/ftrace/ftrace-direct-modify.c @@ -24,20 +24,25 @@ static unsigned long my_ip = (unsigned long)schedule; #ifdef CONFIG_X86_64 +#include + asm ( " .pushsection .text, \"ax\", @progbits\n" " .type my_tramp1, @function\n" " .globl my_tramp1\n" " my_tramp1:" + ASM_ENDBR " pushq %rbp\n" " movq %rsp, %rbp\n" " call my_direct_func1\n" " leave\n" " .size my_tramp1, .-my_tramp1\n" ASM_RET + " .type my_tramp2, @function\n" " .globl my_tramp2\n" " my_tramp2:" + ASM_ENDBR " pushq %rbp\n" " movq %rsp, %rbp\n" " call my_direct_func2\n" diff --git a/samples/ftrace/ftrace-direct-multi-modify.c b/samples/ftrace/ftrace-direct-multi-modify.c index 6f43a39decd0..65aa94d96f4e 100644 --- a/samples/ftrace/ftrace-direct-multi-modify.c +++ b/samples/ftrace/ftrace-direct-multi-modify.c @@ -22,11 +22,14 @@ extern void my_tramp2(void *); #ifdef CONFIG_X86_64 +#include + asm ( " .pushsection .text, \"ax\", @progbits\n" " .type my_tramp1, @function\n" " .globl my_tramp1\n" " my_tramp1:" + ASM_ENDBR " pushq %rbp\n" " movq %rsp, %rbp\n" " pushq %rdi\n" @@ -34,12 +37,13 @@ asm ( " call my_direct_func1\n" " popq %rdi\n" " leave\n" -" ret\n" + ASM_RET " .size my_tramp1, .-my_tramp1\n" + " .type my_tramp2, @function\n" -"\n" " .globl my_tramp2\n" " my_tramp2:" + ASM_ENDBR " pushq %rbp\n" " movq %rsp, %rbp\n" " pushq %rdi\n" @@ -47,7 +51,7 @@ asm ( " call my_direct_func2\n" " popq %rdi\n" " leave\n" -" ret\n" + ASM_RET " .size my_tramp2, .-my_tramp2\n" " .popsection\n" ); diff --git a/samples/ftrace/ftrace-direct-multi.c b/samples/ftrace/ftrace-direct-multi.c index 2fafc9afcbf0..41ded7c615c7 100644 --- a/samples/ftrace/ftrace-direct-multi.c +++ b/samples/ftrace/ftrace-direct-multi.c @@ -17,11 +17,14 @@ extern void my_tramp(void *); #ifdef CONFIG_X86_64 +#include + asm ( " .pushsection .text, \"ax\", @progbits\n" " .type my_tramp, @function\n" " .globl my_tramp\n" " my_tramp:" + ASM_ENDBR " pushq %rbp\n" " movq %rsp, %rbp\n" " pushq %rdi\n" @@ -29,7 +32,7 @@ asm ( " call my_direct_func\n" " popq %rdi\n" " leave\n" -" ret\n" + ASM_RET " .size my_tramp, .-my_tramp\n" " .popsection\n" ); diff --git a/samples/ftrace/ftrace-direct-too.c b/samples/ftrace/ftrace-direct-too.c index c93fb0e95173..6690468c5cc2 100644 --- a/samples/ftrace/ftrace-direct-too.c +++ b/samples/ftrace/ftrace-direct-too.c @@ -19,11 +19,14 @@ extern void my_tramp(void *); #ifdef CONFIG_X86_64 +#include + asm ( " .pushsection .text, \"ax\", @progbits\n" " .type my_tramp, @function\n" " .globl my_tramp\n" " my_tramp:" + ASM_ENDBR " pushq %rbp\n" " movq %rsp, %rbp\n" " pushq %rdi\n" diff --git a/samples/ftrace/ftrace-direct.c b/samples/ftrace/ftrace-direct.c index 8b551e503a48..e8f1e440b9b8 100644 --- a/samples/ftrace/ftrace-direct.c +++ b/samples/ftrace/ftrace-direct.c @@ -16,11 +16,14 @@ extern void my_tramp(void *); #ifdef CONFIG_X86_64 +#include + asm ( " .pushsection .text, \"ax\", @progbits\n" " .type my_tramp, @function\n" " .globl my_tramp\n" " my_tramp:" + ASM_ENDBR " pushq %rbp\n" " movq %rsp, %rbp\n" " pushq %rdi\n" diff --git a/samples/landlock/sandboxer.c b/samples/landlock/sandboxer.c index 7a15910d2171..8859fc193542 100644 --- a/samples/landlock/sandboxer.c +++ b/samples/landlock/sandboxer.c @@ -134,6 +134,7 @@ static int populate_ruleset( ret = 0; out_free_name: + free(path_list); free(env_path_name); return ret; } diff --git a/scripts/Makefile.build b/scripts/Makefile.build index a4b89b757287..2173a6729f30 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -88,8 +88,8 @@ endif targets-for-modules := $(patsubst %.o, %.mod, $(filter %.o, $(obj-m))) -ifdef CONFIG_LTO_CLANG -targets-for-modules += $(patsubst %.o, %.lto.o, $(filter %.o, $(obj-m))) +ifneq ($(CONFIG_LTO_CLANG)$(CONFIG_X86_KERNEL_IBT),) +targets-for-modules += $(patsubst %.o, %.prelink.o, $(filter %.o, $(obj-m))) endif ifdef need-modorder @@ -230,6 +230,7 @@ objtool := $(objtree)/tools/objtool/objtool objtool_args = \ $(if $(CONFIG_UNWINDER_ORC),orc generate,check) \ $(if $(part-of-module), --module) \ + $(if $(CONFIG_X86_KERNEL_IBT), --lto --ibt) \ $(if $(CONFIG_FRAME_POINTER),, --no-fp) \ $(if $(CONFIG_GCOV_KERNEL)$(CONFIG_LTO_CLANG), --no-unreachable)\ $(if $(CONFIG_RETPOLINE), --retpoline) \ @@ -242,7 +243,7 @@ cmd_gen_objtooldep = $(if $(objtool-enabled), { echo ; echo '$@: $$(wildcard $(o endif # CONFIG_STACK_VALIDATION -ifdef CONFIG_LTO_CLANG +ifneq ($(CONFIG_LTO_CLANG)$(CONFIG_X86_KERNEL_IBT),) # Skip objtool for LLVM bitcode $(obj)/%.o: objtool-enabled := @@ -288,24 +289,24 @@ $(obj)/%.o: $(src)/%.c $(recordmcount_source) FORCE $(call if_changed_rule,cc_o_c) $(call cmd,force_checksrc) -ifdef CONFIG_LTO_CLANG +ifneq ($(CONFIG_LTO_CLANG)$(CONFIG_X86_KERNEL_IBT),) # Module .o files may contain LLVM bitcode, compile them into native code # before ELF processing -quiet_cmd_cc_lto_link_modules = LTO [M] $@ -cmd_cc_lto_link_modules = \ +quiet_cmd_cc_prelink_modules = LD [M] $@ + cmd_cc_prelink_modules = \ $(LD) $(ld_flags) -r -o $@ \ - $(shell [ -s $(@:.lto.o=.o.symversions) ] && \ - echo -T $(@:.lto.o=.o.symversions)) \ + $(shell [ -s $(@:.prelink.o=.o.symversions) ] && \ + echo -T $(@:.prelink.o=.o.symversions)) \ --whole-archive $(filter-out FORCE,$^) \ $(cmd_objtool) # objtool was skipped for LLVM bitcode, run it now that we have compiled # modules into native code -$(obj)/%.lto.o: objtool-enabled = y -$(obj)/%.lto.o: part-of-module := y +$(obj)/%.prelink.o: objtool-enabled = y +$(obj)/%.prelink.o: part-of-module := y -$(obj)/%.lto.o: $(obj)/%.o FORCE - $(call if_changed,cc_lto_link_modules) +$(obj)/%.prelink.o: $(obj)/%.o FORCE + $(call if_changed,cc_prelink_modules) endif cmd_mod = { \ @@ -469,7 +470,7 @@ $(obj)/lib.a: $(lib-y) FORCE # Do not replace $(filter %.o,^) with $(real-prereqs). When a single object # module is turned into a multi object module, $^ will contain header file # dependencies recorded in the .*.cmd file. -ifdef CONFIG_LTO_CLANG +ifneq ($(CONFIG_LTO_CLANG)$(CONFIG_X86_KERNEL_IBT),) quiet_cmd_link_multi-m = AR [M] $@ cmd_link_multi-m = \ $(cmd_update_lto_symversions); \ diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index bb51430537ef..3d44931d7a92 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -227,11 +227,11 @@ dtc_cpp_flags = -Wp,-MMD,$(depfile).pre.tmp -nostdinc \ $(addprefix -I,$(DTC_INCLUDE)) \ -undef -D__DTS__ -ifeq ($(CONFIG_LTO_CLANG),y) +ifneq ($(CONFIG_LTO_CLANG)$(CONFIG_X86_KERNEL_IBT),) # With CONFIG_LTO_CLANG, .o files in modules might be LLVM bitcode, so we # need to run LTO to compile them into native code (.lto.o) before further # processing. -mod-prelink-ext := .lto +mod-prelink-ext := .prelink endif # Useful for describing the dependency of composite objects diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinux.sh index 666f7bbc13eb..f704034ebbe6 100755 --- a/scripts/link-vmlinux.sh +++ b/scripts/link-vmlinux.sh @@ -108,14 +108,20 @@ objtool_link() local objtoolcmd; local objtoolopt; - if is_enabled CONFIG_LTO_CLANG && is_enabled CONFIG_STACK_VALIDATION; then + if is_enabled CONFIG_STACK_VALIDATION && \ + ( is_enabled CONFIG_LTO_CLANG || is_enabled CONFIG_X86_KERNEL_IBT ); then + # Don't perform vmlinux validation unless explicitly requested, # but run objtool on vmlinux.o now that we have an object file. if is_enabled CONFIG_UNWINDER_ORC; then objtoolcmd="orc generate" fi - objtoolopt="${objtoolopt} --duplicate" + objtoolopt="${objtoolopt} --lto" + + if is_enabled CONFIG_X86_KERNEL_IBT; then + objtoolopt="${objtoolopt} --ibt" + fi if is_enabled CONFIG_FTRACE_MCOUNT_USE_OBJTOOL; then objtoolopt="${objtoolopt} --mcount" @@ -168,7 +174,7 @@ vmlinux_link() # skip output file argument shift - if is_enabled CONFIG_LTO_CLANG; then + if is_enabled CONFIG_LTO_CLANG || is_enabled CONFIG_X86_KERNEL_IBT; then # Use vmlinux.o instead of performing the slow LTO link again. objs=vmlinux.o libs= diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index feb8eb15a5de..6fbc4eb0edf8 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -1997,9 +1997,9 @@ static char *remove_dot(char *s) if (m && (s[n + m] == '.' || s[n + m] == 0)) s[n] = 0; - /* strip trailing .lto */ - if (strends(s, ".lto")) - s[strlen(s) - 4] = '\0'; + /* strip trailing .prelink */ + if (strends(s, ".prelink")) + s[strlen(s) - 8] = '\0'; } return s; } @@ -2023,9 +2023,9 @@ static void read_symbols(const char *modname) /* strip trailing .o */ tmp = NOFAIL(strdup(modname)); tmp[strlen(tmp) - 2] = '\0'; - /* strip trailing .lto */ - if (strends(tmp, ".lto")) - tmp[strlen(tmp) - 4] = '\0'; + /* strip trailing .prelink */ + if (strends(tmp, ".prelink")) + tmp[strlen(tmp) - 8] = '\0'; mod = new_module(tmp); free(tmp); } diff --git a/security/landlock/syscalls.c b/security/landlock/syscalls.c index 32396962f04d..7e27ce394020 100644 --- a/security/landlock/syscalls.c +++ b/security/landlock/syscalls.c @@ -192,7 +192,7 @@ SYSCALL_DEFINE3(landlock_create_ruleset, return PTR_ERR(ruleset); /* Creates anonymous FD referring to the ruleset. */ - ruleset_fd = anon_inode_getfd("landlock-ruleset", &ruleset_fops, + ruleset_fd = anon_inode_getfd("[landlock-ruleset]", &ruleset_fops, ruleset, O_RDWR | O_CLOEXEC); if (ruleset_fd < 0) landlock_put_ruleset(ruleset); diff --git a/sound/core/control_compat.c b/sound/core/control_compat.c index edff063e088d..d8a86d1a99d6 100644 --- a/sound/core/control_compat.c +++ b/sound/core/control_compat.c @@ -150,7 +150,7 @@ struct snd_ctl_elem_value32 { unsigned char reserved[128]; }; -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI /* x32 has a different alignment for 64bit values from ia32 */ struct snd_ctl_elem_value_x32 { struct snd_ctl_elem_id id; @@ -162,7 +162,7 @@ struct snd_ctl_elem_value_x32 { } value; unsigned char reserved[128]; }; -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ /* get the value type and count of the control */ static int get_ctl_type(struct snd_card *card, struct snd_ctl_elem_id *id, @@ -347,7 +347,7 @@ static int snd_ctl_elem_write_user_compat(struct snd_ctl_file *file, return ctl_elem_write_user(file, data32, &data32->value); } -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI static int snd_ctl_elem_read_user_x32(struct snd_card *card, struct snd_ctl_elem_value_x32 __user *data32) { @@ -359,7 +359,7 @@ static int snd_ctl_elem_write_user_x32(struct snd_ctl_file *file, { return ctl_elem_write_user(file, data32, &data32->value); } -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ /* add or replace a user control */ static int snd_ctl_elem_add_compat(struct snd_ctl_file *file, @@ -418,10 +418,10 @@ enum { SNDRV_CTL_IOCTL_ELEM_WRITE32 = _IOWR('U', 0x13, struct snd_ctl_elem_value32), SNDRV_CTL_IOCTL_ELEM_ADD32 = _IOWR('U', 0x17, struct snd_ctl_elem_info32), SNDRV_CTL_IOCTL_ELEM_REPLACE32 = _IOWR('U', 0x18, struct snd_ctl_elem_info32), -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI SNDRV_CTL_IOCTL_ELEM_READ_X32 = _IOWR('U', 0x12, struct snd_ctl_elem_value_x32), SNDRV_CTL_IOCTL_ELEM_WRITE_X32 = _IOWR('U', 0x13, struct snd_ctl_elem_value_x32), -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ }; static inline long snd_ctl_ioctl_compat(struct file *file, unsigned int cmd, unsigned long arg) @@ -460,12 +460,12 @@ static inline long snd_ctl_ioctl_compat(struct file *file, unsigned int cmd, uns return snd_ctl_elem_add_compat(ctl, argp, 0); case SNDRV_CTL_IOCTL_ELEM_REPLACE32: return snd_ctl_elem_add_compat(ctl, argp, 1); -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI case SNDRV_CTL_IOCTL_ELEM_READ_X32: return snd_ctl_elem_read_user_x32(ctl->card, argp); case SNDRV_CTL_IOCTL_ELEM_WRITE_X32: return snd_ctl_elem_write_user_x32(ctl, argp); -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ } down_read(&snd_ioctl_rwsem); diff --git a/sound/core/pcm_compat.c b/sound/core/pcm_compat.c index e4e176854ce7..917c5b4f19d7 100644 --- a/sound/core/pcm_compat.c +++ b/sound/core/pcm_compat.c @@ -147,13 +147,13 @@ static int snd_pcm_ioctl_channel_info_compat(struct snd_pcm_substream *substream return err; } -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI /* X32 ABI has the same struct as x86-64 for snd_pcm_channel_info */ static int snd_pcm_channel_info_user(struct snd_pcm_substream *substream, struct snd_pcm_channel_info __user *src); #define snd_pcm_ioctl_channel_info_x32(s, p) \ snd_pcm_channel_info_user(s, p) -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ struct compat_snd_pcm_status64 { snd_pcm_state_t state; @@ -375,7 +375,7 @@ static int snd_pcm_ioctl_xfern_compat(struct snd_pcm_substream *substream, return err; } -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI /* X32 ABI has 64bit timespec and 64bit alignment */ struct snd_pcm_mmap_status_x32 { snd_pcm_state_t state; @@ -468,7 +468,7 @@ static int snd_pcm_ioctl_sync_ptr_x32(struct snd_pcm_substream *substream, return 0; } -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ #ifdef __BIG_ENDIAN typedef char __pad_before_u32[4]; @@ -560,10 +560,10 @@ enum { SNDRV_PCM_IOCTL_READN_FRAMES32 = _IOR('A', 0x53, struct snd_xfern32), SNDRV_PCM_IOCTL_STATUS_COMPAT64 = _IOR('A', 0x20, struct compat_snd_pcm_status64), SNDRV_PCM_IOCTL_STATUS_EXT_COMPAT64 = _IOWR('A', 0x24, struct compat_snd_pcm_status64), -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI SNDRV_PCM_IOCTL_CHANNEL_INFO_X32 = _IOR('A', 0x32, struct snd_pcm_channel_info), SNDRV_PCM_IOCTL_SYNC_PTR_X32 = _IOWR('A', 0x23, struct snd_pcm_sync_ptr_x32), -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ }; static long snd_pcm_ioctl_compat(struct file *file, unsigned int cmd, unsigned long arg) @@ -607,10 +607,10 @@ static long snd_pcm_ioctl_compat(struct file *file, unsigned int cmd, unsigned l case __SNDRV_PCM_IOCTL_SYNC_PTR32: return snd_pcm_common_ioctl(file, substream, cmd, argp); case __SNDRV_PCM_IOCTL_SYNC_PTR64: -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI if (in_x32_syscall()) return snd_pcm_ioctl_sync_ptr_x32(substream, argp); -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ return snd_pcm_ioctl_sync_ptr_buggy(substream, argp); case SNDRV_PCM_IOCTL_HW_REFINE32: return snd_pcm_ioctl_hw_params_compat(substream, 1, argp); @@ -642,10 +642,10 @@ static long snd_pcm_ioctl_compat(struct file *file, unsigned int cmd, unsigned l return snd_pcm_status_user_compat64(substream, argp, false); case SNDRV_PCM_IOCTL_STATUS_EXT_COMPAT64: return snd_pcm_status_user_compat64(substream, argp, true); -#ifdef CONFIG_X86_X32 +#ifdef CONFIG_X86_X32_ABI case SNDRV_PCM_IOCTL_CHANNEL_INFO_X32: return snd_pcm_ioctl_channel_info_x32(substream, argp); -#endif /* CONFIG_X86_X32 */ +#endif /* CONFIG_X86_X32_ABI */ } return -ENOIOCTLCMD; diff --git a/tools/arch/arm64/include/asm/cputype.h b/tools/arch/arm64/include/asm/cputype.h new file mode 100644 index 000000000000..9afcc6467a09 --- /dev/null +++ b/tools/arch/arm64/include/asm/cputype.h @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2012 ARM Ltd. + */ +#ifndef __ASM_CPUTYPE_H +#define __ASM_CPUTYPE_H + +#define INVALID_HWID ULONG_MAX + +#define MPIDR_UP_BITMASK (0x1 << 30) +#define MPIDR_MT_BITMASK (0x1 << 24) +#define MPIDR_HWID_BITMASK UL(0xff00ffffff) + +#define MPIDR_LEVEL_BITS_SHIFT 3 +#define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) +#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) + +#define MPIDR_LEVEL_SHIFT(level) \ + (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) + +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) + +#define MIDR_REVISION_MASK 0xf +#define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) +#define MIDR_PARTNUM_SHIFT 4 +#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) +#define MIDR_PARTNUM(midr) \ + (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) +#define MIDR_ARCHITECTURE_SHIFT 16 +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) +#define MIDR_ARCHITECTURE(midr) \ + (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) +#define MIDR_VARIANT_SHIFT 20 +#define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) +#define MIDR_VARIANT(midr) \ + (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) +#define MIDR_IMPLEMENTOR_SHIFT 24 +#define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_IMPLEMENTOR(midr) \ + (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) + +#define MIDR_CPU_MODEL(imp, partnum) \ + (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + +#define MIDR_CPU_VAR_REV(var, rev) \ + (((var) << MIDR_VARIANT_SHIFT) | (rev)) + +#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ + MIDR_ARCHITECTURE_MASK) + +#define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_IMP_APM 0x50 +#define ARM_CPU_IMP_CAVIUM 0x43 +#define ARM_CPU_IMP_BRCM 0x42 +#define ARM_CPU_IMP_QCOM 0x51 +#define ARM_CPU_IMP_NVIDIA 0x4E +#define ARM_CPU_IMP_FUJITSU 0x46 +#define ARM_CPU_IMP_HISI 0x48 +#define ARM_CPU_IMP_APPLE 0x61 + +#define ARM_CPU_PART_AEM_V8 0xD0F +#define ARM_CPU_PART_FOUNDATION 0xD00 +#define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 +#define ARM_CPU_PART_CORTEX_A53 0xD03 +#define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A +#define ARM_CPU_PART_CORTEX_A35 0xD04 +#define ARM_CPU_PART_CORTEX_A55 0xD05 +#define ARM_CPU_PART_CORTEX_A76 0xD0B +#define ARM_CPU_PART_NEOVERSE_N1 0xD0C +#define ARM_CPU_PART_CORTEX_A77 0xD0D +#define ARM_CPU_PART_NEOVERSE_V1 0xD40 +#define ARM_CPU_PART_CORTEX_A78 0xD41 +#define ARM_CPU_PART_CORTEX_X1 0xD44 +#define ARM_CPU_PART_CORTEX_A510 0xD46 +#define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_X2 0xD48 +#define ARM_CPU_PART_NEOVERSE_N2 0xD49 +#define ARM_CPU_PART_CORTEX_A78C 0xD4B + +#define APM_CPU_PART_POTENZA 0x000 + +#define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 +#define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 +#define CAVIUM_CPU_PART_THUNDERX2 0x0AF +/* OcteonTx2 series */ +#define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1 +#define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2 +#define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3 +#define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4 +#define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5 +#define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6 + +#define BRCM_CPU_PART_BRAHMA_B53 0x100 +#define BRCM_CPU_PART_VULCAN 0x516 + +#define QCOM_CPU_PART_FALKOR_V1 0x800 +#define QCOM_CPU_PART_FALKOR 0xC00 +#define QCOM_CPU_PART_KRYO 0x200 +#define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800 +#define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801 +#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803 +#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804 +#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805 + +#define NVIDIA_CPU_PART_DENVER 0x003 +#define NVIDIA_CPU_PART_CARMEL 0x004 + +#define FUJITSU_CPU_PART_A64FX 0x001 + +#define HISI_CPU_PART_TSV110 0xD01 + +#define APPLE_CPU_PART_M1_ICESTORM 0x022 +#define APPLE_CPU_PART_M1_FIRESTORM 0x023 + +#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) +#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) +#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) +#define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35) +#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) +#define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) +#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) +#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) +#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1) +#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78) +#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) +#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) +#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) +#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) +#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) +#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) +#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) +#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) +#define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX) +#define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX) +#define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX) +#define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN) +#define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM) +#define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO) +#define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) +#define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53) +#define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) +#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) +#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) +#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) +#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD) +#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER) +#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER) +#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD) +#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER) +#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) +#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) +#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX) +#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110) +#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM) +#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM) + +/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ +#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX +#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0)) +#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0) + +#ifndef __ASSEMBLY__ + +#include "sysreg.h" + +#define read_cpuid(reg) read_sysreg_s(SYS_ ## reg) + +/* + * Represent a range of MIDR values for a given CPU model and a + * range of variant/revision values. + * + * @model - CPU model as defined by MIDR_CPU_MODEL + * @rv_min - Minimum value for the revision/variant as defined by + * MIDR_CPU_VAR_REV + * @rv_max - Maximum value for the variant/revision for the range. + */ +struct midr_range { + u32 model; + u32 rv_min; + u32 rv_max; +}; + +#define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \ + { \ + .model = m, \ + .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \ + .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \ + } + +#define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max) +#define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r) +#define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf) + +static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min, + u32 rv_max) +{ + u32 _model = midr & MIDR_CPU_MODEL_MASK; + u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); + + return _model == model && rv >= rv_min && rv <= rv_max; +} + +static inline bool is_midr_in_range(u32 midr, struct midr_range const *range) +{ + return midr_is_cpu_model_range(midr, range->model, + range->rv_min, range->rv_max); +} + +static inline bool +is_midr_in_range_list(u32 midr, struct midr_range const *ranges) +{ + while (ranges->model) + if (is_midr_in_range(midr, ranges++)) + return true; + return false; +} + +/* + * The CPU ID never changes at run time, so we might as well tell the + * compiler that it's constant. Use this function to read the CPU ID + * rather than directly reading processor_id or read_cpuid() directly. + */ +static inline u32 __attribute_const__ read_cpuid_id(void) +{ + return read_cpuid(MIDR_EL1); +} + +static inline u64 __attribute_const__ read_cpuid_mpidr(void) +{ + return read_cpuid(MPIDR_EL1); +} + +static inline unsigned int __attribute_const__ read_cpuid_implementor(void) +{ + return MIDR_IMPLEMENTOR(read_cpuid_id()); +} + +static inline unsigned int __attribute_const__ read_cpuid_part_number(void) +{ + return MIDR_PARTNUM(read_cpuid_id()); +} + +static inline u32 __attribute_const__ read_cpuid_cachetype(void) +{ + return read_cpuid(CTR_EL0); +} +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index 65d147974f8d..3edf05e98e58 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -299,9 +299,6 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ -#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */ -#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */ -#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ @@ -330,6 +327,7 @@ #define X86_FEATURE_HWP_ACT_WINDOW (14*32+ 9) /* HWP Activity Window */ #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ +#define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */ /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ @@ -390,7 +388,10 @@ #define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ +#define X86_FEATURE_AMX_BF16 (18*32+22) /* AMX bf16 Support */ #define X86_FEATURE_AVX512_FP16 (18*32+23) /* AVX512 FP16 */ +#define X86_FEATURE_AMX_TILE (18*32+24) /* AMX tile Support */ +#define X86_FEATURE_AMX_INT8 (18*32+25) /* AMX int8 Support */ #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ diff --git a/tools/arch/x86/include/asm/disabled-features.h b/tools/arch/x86/include/asm/disabled-features.h index 8f28fafa98b3..1231d63f836d 100644 --- a/tools/arch/x86/include/asm/disabled-features.h +++ b/tools/arch/x86/include/asm/disabled-features.h @@ -56,8 +56,11 @@ # define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31)) #endif -/* Force disable because it's broken beyond repair */ -#define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31)) +#ifdef CONFIG_INTEL_IOMMU_SVM +# define DISABLE_ENQCMD 0 +#else +# define DISABLE_ENQCMD (1 << (X86_FEATURE_ENQCMD & 31)) +#endif #ifdef CONFIG_X86_SGX # define DISABLE_SGX 0 diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index a4a39c3e0f19..0e7f303542bf 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -705,12 +705,14 @@ #define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) #define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) +#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26) #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 #define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) +#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25) /* Thermal Thresholds Support */ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) @@ -959,4 +961,8 @@ #define MSR_VM_IGNNE 0xc0010115 #define MSR_VM_HSAVE_PA 0xc0010117 +/* Hardware Feedback Interface */ +#define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 +#define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 + #endif /* _ASM_X86_MSR_INDEX_H */ diff --git a/tools/include/linux/atomic.h b/tools/include/linux/atomic.h index 00a6c4ca562b..01907b33537e 100644 --- a/tools/include/linux/atomic.h +++ b/tools/include/linux/atomic.h @@ -4,6 +4,8 @@ #include +void atomic_long_set(atomic_long_t *v, long i); + /* atomic_cmpxchg_relaxed */ #ifndef atomic_cmpxchg_relaxed #define atomic_cmpxchg_relaxed atomic_cmpxchg diff --git a/tools/include/linux/cache.h b/tools/include/linux/cache.h new file mode 100644 index 000000000000..9e9d585f0b9d --- /dev/null +++ b/tools/include/linux/cache.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _TOOLS_LINUX_CACHE_H +#define _TOOLS_LINUX_CACHE_H + +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +#endif diff --git a/tools/include/linux/compiler.h b/tools/include/linux/compiler.h index ff872dc2637c..90ba44a99199 100644 --- a/tools/include/linux/compiler.h +++ b/tools/include/linux/compiler.h @@ -102,10 +102,6 @@ # define __init #endif -#ifndef noinline -# define noinline -#endif - #include /* diff --git a/tools/include/linux/coresight-pmu.h b/tools/include/linux/coresight-pmu.h index 4ac5c081af93..6c2fd6cc5a98 100644 --- a/tools/include/linux/coresight-pmu.h +++ b/tools/include/linux/coresight-pmu.h @@ -18,6 +18,7 @@ * ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and * directly use below macros as config bits. */ +#define ETM_OPT_BRANCH_BROADCAST 8 #define ETM_OPT_CYCACC 12 #define ETM_OPT_CTXTID 14 #define ETM_OPT_CTXTID2 15 @@ -25,6 +26,7 @@ #define ETM_OPT_RETSTK 29 /* ETMv4 CONFIGR programming bits for the ETM OPTs */ +#define ETM4_CFG_BIT_BB 3 #define ETM4_CFG_BIT_CYCACC 4 #define ETM4_CFG_BIT_CTXTID 6 #define ETM4_CFG_BIT_VMID 7 diff --git a/tools/include/linux/debugfs.h b/tools/include/linux/debugfs.h new file mode 100644 index 000000000000..4ba06140b1be --- /dev/null +++ b/tools/include/linux/debugfs.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _TOOLS_DEBUGFS_H +#define _TOOLS_DEBUGFS_H + +#endif diff --git a/tools/include/linux/gfp.h b/tools/include/linux/gfp.h index 22030756fbc0..b238dbc9eb85 100644 --- a/tools/include/linux/gfp.h +++ b/tools/include/linux/gfp.h @@ -1,4 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _TOOLS_INCLUDE_LINUX_GFP_H #define _TOOLS_INCLUDE_LINUX_GFP_H +#include + +#define __GFP_BITS_SHIFT 26 +#define __GFP_BITS_MASK ((gfp_t)((1 << __GFP_BITS_SHIFT) - 1)) + +#define __GFP_HIGH 0x20u +#define __GFP_IO 0x40u +#define __GFP_FS 0x80u +#define __GFP_NOWARN 0x200u +#define __GFP_ZERO 0x8000u +#define __GFP_ATOMIC 0x80000u +#define __GFP_ACCOUNT 0x100000u +#define __GFP_DIRECT_RECLAIM 0x400000u +#define __GFP_KSWAPD_RECLAIM 0x2000000u + +#define __GFP_RECLAIM (__GFP_DIRECT_RECLAIM | __GFP_KSWAPD_RECLAIM) + +#define GFP_ZONEMASK 0x0fu +#define GFP_ATOMIC (__GFP_HIGH | __GFP_ATOMIC | __GFP_KSWAPD_RECLAIM) +#define GFP_KERNEL (__GFP_RECLAIM | __GFP_IO | __GFP_FS) +#define GFP_NOWAIT (__GFP_KSWAPD_RECLAIM) + +static inline bool gfpflags_allow_blocking(const gfp_t gfp_flags) +{ + return !!(gfp_flags & __GFP_DIRECT_RECLAIM); +} + #endif /* _TOOLS_INCLUDE_LINUX_GFP_H */ diff --git a/tools/include/linux/io.h b/tools/include/linux/io.h new file mode 100644 index 000000000000..e129871fe661 --- /dev/null +++ b/tools/include/linux/io.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _TOOLS_IO_H +#define _TOOLS_IO_H + +#endif diff --git a/tools/include/linux/kernel.h b/tools/include/linux/kernel.h index 9701e8307db0..4b0673bf52c2 100644 --- a/tools/include/linux/kernel.h +++ b/tools/include/linux/kernel.h @@ -15,6 +15,8 @@ #define UINT_MAX (~0U) #endif +#define _RET_IP_ ((unsigned long)__builtin_return_address(0)) + #define PERF_ALIGN(x, a) __PERF_ALIGN_MASK(x, (typeof(x))(a)-1) #define __PERF_ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) @@ -51,6 +53,10 @@ _min1 < _min2 ? _min1 : _min2; }) #endif +#define max_t(type, x, y) max((type)x, (type)y) +#define min_t(type, x, y) min((type)x, (type)y) +#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) + #ifndef BUG_ON #ifdef NDEBUG #define BUG_ON(cond) do { if (cond) {} } while (0) diff --git a/tools/include/linux/mm.h b/tools/include/linux/mm.h new file mode 100644 index 000000000000..a03d9bba5151 --- /dev/null +++ b/tools/include/linux/mm.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _TOOLS_LINUX_MM_H +#define _TOOLS_LINUX_MM_H + +#include +#include + +#define PAGE_SHIFT 12 +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE - 1)) + +#define PHYS_ADDR_MAX (~(phys_addr_t)0) + +#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1) +#define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) +#define ALIGN(x, a) __ALIGN_KERNEL((x), (a)) +#define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) + +#define PAGE_ALIGN(addr) ALIGN(addr, PAGE_SIZE) + +#define __va(x) ((void *)((unsigned long)(x))) +#define __pa(x) ((unsigned long)(x)) + +#define pfn_to_page(pfn) ((void *)((pfn) * PAGE_SIZE)) + +#define phys_to_virt phys_to_virt +static inline void *phys_to_virt(unsigned long address) +{ + return __va(address); +} + +void reserve_bootmem_region(phys_addr_t start, phys_addr_t end); + +static inline void totalram_pages_inc(void) +{ +} + +static inline void totalram_pages_add(long count) +{ +} + +#endif diff --git a/tools/include/linux/objtool.h b/tools/include/linux/objtool.h index aca52db2f3f3..586d35720f13 100644 --- a/tools/include/linux/objtool.h +++ b/tools/include/linux/objtool.h @@ -77,6 +77,18 @@ struct unwind_hint { #define STACK_FRAME_NON_STANDARD_FP(func) #endif +#define ANNOTATE_NOENDBR \ + "986: \n\t" \ + ".pushsection .discard.noendbr\n\t" \ + _ASM_PTR " 986b\n\t" \ + ".popsection\n\t" + +#define ASM_REACHABLE \ + "998:\n\t" \ + ".pushsection .discard.reachable\n\t" \ + ".long 998b - .\n\t" \ + ".popsection\n\t" + #else /* __ASSEMBLY__ */ /* @@ -129,6 +141,20 @@ struct unwind_hint { .popsection .endm +.macro ANNOTATE_NOENDBR +.Lhere_\@: + .pushsection .discard.noendbr + .quad .Lhere_\@ + .popsection +.endm + +.macro REACHABLE +.Lhere_\@: + .pushsection .discard.reachable + .long .Lhere_\@ - . + .popsection +.endm + #endif /* __ASSEMBLY__ */ #else /* !CONFIG_STACK_VALIDATION */ @@ -139,12 +165,18 @@ struct unwind_hint { "\n\t" #define STACK_FRAME_NON_STANDARD(func) #define STACK_FRAME_NON_STANDARD_FP(func) +#define ANNOTATE_NOENDBR +#define ASM_REACHABLE #else #define ANNOTATE_INTRA_FUNCTION_CALL .macro UNWIND_HINT sp_reg:req sp_offset=0 type:req end=0 .endm .macro STACK_FRAME_NON_STANDARD func:req .endm +.macro ANNOTATE_NOENDBR +.endm +.macro REACHABLE +.endm #endif #endif /* CONFIG_STACK_VALIDATION */ diff --git a/tools/include/linux/pfn.h b/tools/include/linux/pfn.h new file mode 100644 index 000000000000..7512a58189eb --- /dev/null +++ b/tools/include/linux/pfn.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _TOOLS_LINUX_PFN_H_ +#define _TOOLS_LINUX_PFN_H_ + +#include + +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT) +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) +#define PFN_PHYS(x) ((phys_addr_t)(x) << PAGE_SHIFT) +#endif diff --git a/tools/testing/radix-tree/linux/slab.h b/tools/include/linux/slab.h similarity index 61% rename from tools/testing/radix-tree/linux/slab.h rename to tools/include/linux/slab.h index 2958830ce4d7..f41d8a0eb1a4 100644 --- a/tools/testing/radix-tree/linux/slab.h +++ b/tools/include/linux/slab.h @@ -1,20 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0 */ -#ifndef SLAB_H -#define SLAB_H +#ifndef _TOOLS_SLAB_H +#define _TOOLS_SLAB_H #include #include -#define SLAB_HWCACHE_ALIGN 1 #define SLAB_PANIC 2 #define SLAB_RECLAIM_ACCOUNT 0x00020000UL /* Objects are reclaimable */ -void *kmalloc(size_t size, gfp_t); -void kfree(void *); +#define kzalloc_node(size, flags, node) kmalloc(size, flags) + +void *kmalloc(size_t size, gfp_t gfp); +void kfree(void *p); + +bool slab_is_available(void); + +enum slab_state { + DOWN, + PARTIAL, + PARTIAL_NODE, + UP, + FULL +}; static inline void *kzalloc(size_t size, gfp_t gfp) { - return kmalloc(size, gfp | __GFP_ZERO); + return kmalloc(size, gfp | __GFP_ZERO); } void *kmem_cache_alloc(struct kmem_cache *cachep, int flags); @@ -24,4 +35,4 @@ struct kmem_cache *kmem_cache_create(const char *name, unsigned int size, unsigned int align, unsigned int flags, void (*ctor)(void *)); -#endif /* SLAB_H */ +#endif /* _TOOLS_SLAB_H */ diff --git a/tools/include/linux/types.h b/tools/include/linux/types.h index 6c18c54e7d7f..051fdeaf2670 100644 --- a/tools/include/linux/types.h +++ b/tools/include/linux/types.h @@ -63,10 +63,20 @@ typedef __u64 __bitwise __be64; typedef __u16 __bitwise __sum16; typedef __u32 __bitwise __wsum; +#ifdef CONFIG_PHYS_ADDR_T_64BIT +typedef u64 phys_addr_t; +#else +typedef u32 phys_addr_t; +#endif + typedef struct { int counter; } atomic_t; +typedef struct { + long counter; +} atomic_long_t; + #ifndef __aligned_u64 # define __aligned_u64 __u64 __attribute__((aligned(8))) #endif diff --git a/tools/lib/api/fd/array.c b/tools/lib/api/fd/array.c index 5e6cb9debe37..f0f195207fca 100644 --- a/tools/lib/api/fd/array.c +++ b/tools/lib/api/fd/array.c @@ -88,6 +88,23 @@ int fdarray__add(struct fdarray *fda, int fd, short revents, enum fdarray_flags return pos; } +int fdarray__dup_entry_from(struct fdarray *fda, int pos, struct fdarray *from) +{ + struct pollfd *entry; + int npos; + + if (pos >= from->nr) + return -EINVAL; + + entry = &from->entries[pos]; + + npos = fdarray__add(fda, entry->fd, entry->events, from->priv[pos].flags); + if (npos >= 0) + fda->priv[npos] = from->priv[pos]; + + return npos; +} + int fdarray__filter(struct fdarray *fda, short revents, void (*entry_destructor)(struct fdarray *fda, int fd, void *arg), void *arg) diff --git a/tools/lib/api/fd/array.h b/tools/lib/api/fd/array.h index 7fcf21a33c0c..60ad197c8ee9 100644 --- a/tools/lib/api/fd/array.h +++ b/tools/lib/api/fd/array.h @@ -42,6 +42,7 @@ struct fdarray *fdarray__new(int nr_alloc, int nr_autogrow); void fdarray__delete(struct fdarray *fda); int fdarray__add(struct fdarray *fda, int fd, short revents, enum fdarray_flags flags); +int fdarray__dup_entry_from(struct fdarray *fda, int pos, struct fdarray *from); int fdarray__poll(struct fdarray *fda, int timeout); int fdarray__filter(struct fdarray *fda, short revents, void (*entry_destructor)(struct fdarray *fda, int fd, void *arg), diff --git a/tools/lib/perf/Documentation/libperf.txt b/tools/lib/perf/Documentation/libperf.txt index 32c5051c24eb..a8f1a237931b 100644 --- a/tools/lib/perf/Documentation/libperf.txt +++ b/tools/lib/perf/Documentation/libperf.txt @@ -62,11 +62,12 @@ SYNOPSIS struct perf_thread_map; struct perf_thread_map *perf_thread_map__new_dummy(void); + struct perf_thread_map *perf_thread_map__new_array(int nr_threads, pid_t *array); - void perf_thread_map__set_pid(struct perf_thread_map *map, int thread, pid_t pid); - char *perf_thread_map__comm(struct perf_thread_map *map, int thread); + void perf_thread_map__set_pid(struct perf_thread_map *map, int idx, pid_t pid); + char *perf_thread_map__comm(struct perf_thread_map *map, int idx); int perf_thread_map__nr(struct perf_thread_map *threads); - pid_t perf_thread_map__pid(struct perf_thread_map *map, int thread); + pid_t perf_thread_map__pid(struct perf_thread_map *map, int idx); struct perf_thread_map *perf_thread_map__get(struct perf_thread_map *map); void perf_thread_map__put(struct perf_thread_map *map); diff --git a/tools/lib/perf/include/perf/threadmap.h b/tools/lib/perf/include/perf/threadmap.h index a7c50de8d010..8b40e7777cea 100644 --- a/tools/lib/perf/include/perf/threadmap.h +++ b/tools/lib/perf/include/perf/threadmap.h @@ -8,11 +8,12 @@ struct perf_thread_map; LIBPERF_API struct perf_thread_map *perf_thread_map__new_dummy(void); +LIBPERF_API struct perf_thread_map *perf_thread_map__new_array(int nr_threads, pid_t *array); -LIBPERF_API void perf_thread_map__set_pid(struct perf_thread_map *map, int thread, pid_t pid); -LIBPERF_API char *perf_thread_map__comm(struct perf_thread_map *map, int thread); +LIBPERF_API void perf_thread_map__set_pid(struct perf_thread_map *map, int idx, pid_t pid); +LIBPERF_API char *perf_thread_map__comm(struct perf_thread_map *map, int idx); LIBPERF_API int perf_thread_map__nr(struct perf_thread_map *threads); -LIBPERF_API pid_t perf_thread_map__pid(struct perf_thread_map *map, int thread); +LIBPERF_API pid_t perf_thread_map__pid(struct perf_thread_map *map, int idx); LIBPERF_API struct perf_thread_map *perf_thread_map__get(struct perf_thread_map *map); LIBPERF_API void perf_thread_map__put(struct perf_thread_map *map); diff --git a/tools/lib/perf/libperf.map b/tools/lib/perf/libperf.map index 6fa0d651576b..190b56ae923a 100644 --- a/tools/lib/perf/libperf.map +++ b/tools/lib/perf/libperf.map @@ -12,6 +12,7 @@ LIBPERF_0.0.1 { perf_cpu_map__empty; perf_cpu_map__max; perf_cpu_map__has; + perf_thread_map__new_array; perf_thread_map__new_dummy; perf_thread_map__set_pid; perf_thread_map__comm; diff --git a/tools/lib/perf/tests/test-evlist.c b/tools/lib/perf/tests/test-evlist.c index fa854c83b7e7..ed616fc19b4f 100644 --- a/tools/lib/perf/tests/test-evlist.c +++ b/tools/lib/perf/tests/test-evlist.c @@ -69,7 +69,7 @@ static int test_stat_cpu(void) perf_evlist__set_maps(evlist, cpus, NULL); err = perf_evlist__open(evlist); - __T("failed to open evsel", err == 0); + __T("failed to open evlist", err == 0); perf_evlist__for_each_evsel(evlist, evsel) { cpus = perf_evsel__cpus(evsel); @@ -130,7 +130,7 @@ static int test_stat_thread(void) perf_evlist__set_maps(evlist, NULL, threads); err = perf_evlist__open(evlist); - __T("failed to open evsel", err == 0); + __T("failed to open evlist", err == 0); perf_evlist__for_each_evsel(evlist, evsel) { perf_evsel__read(evsel, 0, 0, &counts); @@ -187,7 +187,7 @@ static int test_stat_thread_enable(void) perf_evlist__set_maps(evlist, NULL, threads); err = perf_evlist__open(evlist); - __T("failed to open evsel", err == 0); + __T("failed to open evlist", err == 0); perf_evlist__for_each_evsel(evlist, evsel) { perf_evsel__read(evsel, 0, 0, &counts); @@ -507,7 +507,7 @@ static int test_stat_multiplexing(void) perf_evlist__set_maps(evlist, NULL, threads); err = perf_evlist__open(evlist); - __T("failed to open evsel", err == 0); + __T("failed to open evlist", err == 0); perf_evlist__enable(evlist); diff --git a/tools/lib/perf/tests/test-threadmap.c b/tools/lib/perf/tests/test-threadmap.c index 5e2a0291e94c..f728ad7002bb 100644 --- a/tools/lib/perf/tests/test-threadmap.c +++ b/tools/lib/perf/tests/test-threadmap.c @@ -11,9 +11,43 @@ static int libperf_print(enum libperf_print_level level, return vfprintf(stderr, fmt, ap); } +static int test_threadmap_array(int nr, pid_t *array) +{ + struct perf_thread_map *threads; + int i; + + threads = perf_thread_map__new_array(nr, array); + __T("Failed to allocate new thread map", threads); + + __T("Unexpected number of threads", perf_thread_map__nr(threads) == nr); + + for (i = 0; i < nr; i++) { + __T("Unexpected initial value of thread", + perf_thread_map__pid(threads, i) == (array ? array[i] : -1)); + } + + for (i = 1; i < nr; i++) + perf_thread_map__set_pid(threads, i, i * 100); + + __T("Unexpected value of thread 0", + perf_thread_map__pid(threads, 0) == (array ? array[0] : -1)); + + for (i = 1; i < nr; i++) { + __T("Unexpected thread value", + perf_thread_map__pid(threads, i) == i * 100); + } + + perf_thread_map__put(threads); + + return 0; +} + +#define THREADS_NR 10 int test_threadmap(int argc, char **argv) { struct perf_thread_map *threads; + pid_t thr_array[THREADS_NR]; + int i; __T_START; @@ -27,6 +61,13 @@ int test_threadmap(int argc, char **argv) perf_thread_map__put(threads); perf_thread_map__put(threads); + test_threadmap_array(THREADS_NR, NULL); + + for (i = 0; i < THREADS_NR; i++) + thr_array[i] = i + 100; + + test_threadmap_array(THREADS_NR, thr_array); + __T_END; return tests_failed == 0 ? 0 : -1; } diff --git a/tools/lib/perf/threadmap.c b/tools/lib/perf/threadmap.c index e92c368b0a6c..07968f3ea093 100644 --- a/tools/lib/perf/threadmap.c +++ b/tools/lib/perf/threadmap.c @@ -32,26 +32,36 @@ struct perf_thread_map *perf_thread_map__realloc(struct perf_thread_map *map, in #define thread_map__alloc(__nr) perf_thread_map__realloc(NULL, __nr) -void perf_thread_map__set_pid(struct perf_thread_map *map, int thread, pid_t pid) +void perf_thread_map__set_pid(struct perf_thread_map *map, int idx, pid_t pid) { - map->map[thread].pid = pid; + map->map[idx].pid = pid; } -char *perf_thread_map__comm(struct perf_thread_map *map, int thread) +char *perf_thread_map__comm(struct perf_thread_map *map, int idx) { - return map->map[thread].comm; + return map->map[idx].comm; +} + +struct perf_thread_map *perf_thread_map__new_array(int nr_threads, pid_t *array) +{ + struct perf_thread_map *threads = thread_map__alloc(nr_threads); + int i; + + if (!threads) + return NULL; + + for (i = 0; i < nr_threads; i++) + perf_thread_map__set_pid(threads, i, array ? array[i] : -1); + + threads->nr = nr_threads; + refcount_set(&threads->refcnt, 1); + + return threads; } struct perf_thread_map *perf_thread_map__new_dummy(void) { - struct perf_thread_map *threads = thread_map__alloc(1); - - if (threads != NULL) { - perf_thread_map__set_pid(threads, 0, -1); - threads->nr = 1; - refcount_set(&threads->refcnt, 1); - } - return threads; + return perf_thread_map__new_array(1, NULL); } static void perf_thread_map__delete(struct perf_thread_map *threads) @@ -85,7 +95,7 @@ int perf_thread_map__nr(struct perf_thread_map *threads) return threads ? threads->nr : 1; } -pid_t perf_thread_map__pid(struct perf_thread_map *map, int thread) +pid_t perf_thread_map__pid(struct perf_thread_map *map, int idx) { - return map->map[thread].pid; + return map->map[idx].pid; } diff --git a/tools/lib/slab.c b/tools/lib/slab.c new file mode 100644 index 000000000000..959997fb0652 --- /dev/null +++ b/tools/lib/slab.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include + +#include +#include +#include +#include + +int kmalloc_nr_allocated; +int kmalloc_verbose; + +void *kmalloc(size_t size, gfp_t gfp) +{ + void *ret; + + if (!(gfp & __GFP_DIRECT_RECLAIM)) + return NULL; + + ret = malloc(size); + uatomic_inc(&kmalloc_nr_allocated); + if (kmalloc_verbose) + printf("Allocating %p from malloc\n", ret); + if (gfp & __GFP_ZERO) + memset(ret, 0, size); + return ret; +} + +void kfree(void *p) +{ + if (!p) + return; + uatomic_dec(&kmalloc_nr_allocated); + if (kmalloc_verbose) + printf("Freeing %p to malloc\n", p); + free(p); +} diff --git a/tools/objtool/arch/x86/decode.c b/tools/objtool/arch/x86/decode.c index 479e769ca324..943cb41cddf7 100644 --- a/tools/objtool/arch/x86/decode.c +++ b/tools/objtool/arch/x86/decode.c @@ -103,6 +103,18 @@ unsigned long arch_jump_destination(struct instruction *insn) #define rm_is_mem(reg) (mod_is_mem() && !is_RIP() && rm_is(reg)) #define rm_is_reg(reg) (mod_is_reg() && modrm_rm == (reg)) +static bool has_notrack_prefix(struct insn *insn) +{ + int i; + + for (i = 0; i < insn->prefixes.nbytes; i++) { + if (insn->prefixes.bytes[i] == 0x3e) + return true; + } + + return false; +} + int arch_decode_instruction(struct objtool_file *file, const struct section *sec, unsigned long offset, unsigned int maxlen, unsigned int *len, enum insn_type *type, @@ -112,7 +124,7 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec const struct elf *elf = file->elf; struct insn insn; int x86_64, ret; - unsigned char op1, op2, op3, + unsigned char op1, op2, op3, prefix, rex = 0, rex_b = 0, rex_r = 0, rex_w = 0, rex_x = 0, modrm = 0, modrm_mod = 0, modrm_rm = 0, modrm_reg = 0, sib = 0, /* sib_scale = 0, */ sib_index = 0, sib_base = 0; @@ -137,6 +149,8 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec if (insn.vex_prefix.nbytes) return 0; + prefix = insn.prefixes.bytes[0]; + op1 = insn.opcode.bytes[0]; op2 = insn.opcode.bytes[1]; op3 = insn.opcode.bytes[2]; @@ -492,6 +506,12 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec /* nopl/nopw */ *type = INSN_NOP; + } else if (op2 == 0x1e) { + + if (prefix == 0xf3 && (modrm == 0xfa || modrm == 0xfb)) + *type = INSN_ENDBR; + + } else if (op2 == 0x38 && op3 == 0xf8) { if (insn.prefixes.nbytes == 1 && insn.prefixes.bytes[0] == 0xf2) { @@ -636,20 +656,24 @@ int arch_decode_instruction(struct objtool_file *file, const struct section *sec break; case 0xff: - if (modrm_reg == 2 || modrm_reg == 3) + if (modrm_reg == 2 || modrm_reg == 3) { *type = INSN_CALL_DYNAMIC; + if (has_notrack_prefix(&insn)) + WARN("notrack prefix found at %s:0x%lx", sec->name, offset); - else if (modrm_reg == 4) + } else if (modrm_reg == 4) { *type = INSN_JUMP_DYNAMIC; + if (has_notrack_prefix(&insn)) + WARN("notrack prefix found at %s:0x%lx", sec->name, offset); - else if (modrm_reg == 5) + } else if (modrm_reg == 5) { /* jmpf */ *type = INSN_CONTEXT_SWITCH; - else if (modrm_reg == 6) { + } else if (modrm_reg == 6) { /* push from mem */ ADD_OP(op) { diff --git a/tools/objtool/builtin-check.c b/tools/objtool/builtin-check.c index 38070f26105b..fc6975ab8b06 100644 --- a/tools/objtool/builtin-check.c +++ b/tools/objtool/builtin-check.c @@ -20,7 +20,8 @@ #include bool no_fp, no_unreachable, retpoline, module, backtrace, uaccess, stats, - validate_dup, vmlinux, mcount, noinstr, backup, sls; + lto, vmlinux, mcount, noinstr, backup, sls, dryrun, + ibt; static const char * const check_usage[] = { "objtool check [] file.o", @@ -40,12 +41,14 @@ const struct option check_options[] = { OPT_BOOLEAN('b', "backtrace", &backtrace, "unwind on error"), OPT_BOOLEAN('a', "uaccess", &uaccess, "enable uaccess checking"), OPT_BOOLEAN('s', "stats", &stats, "print statistics"), - OPT_BOOLEAN('d', "duplicate", &validate_dup, "duplicate validation for vmlinux.o"), + OPT_BOOLEAN(0, "lto", <o, "whole-archive like runs"), OPT_BOOLEAN('n', "noinstr", &noinstr, "noinstr validation for vmlinux.o"), OPT_BOOLEAN('l', "vmlinux", &vmlinux, "vmlinux.o validation"), OPT_BOOLEAN('M', "mcount", &mcount, "generate __mcount_loc"), OPT_BOOLEAN('B', "backup", &backup, "create .orig files before modification"), OPT_BOOLEAN('S', "sls", &sls, "validate straight-line-speculation"), + OPT_BOOLEAN(0, "dry-run", &dryrun, "don't write the modifications"), + OPT_BOOLEAN(0, "ibt", &ibt, "validate ENDBR placement"), OPT_END(), }; diff --git a/tools/objtool/check.c b/tools/objtool/check.c index 7c33ec67c4a9..6de5085e3e5a 100644 --- a/tools/objtool/check.c +++ b/tools/objtool/check.c @@ -181,6 +181,9 @@ static bool __dead_end_function(struct objtool_file *file, struct symbol *func, "kunit_try_catch_throw", "xen_start_kernel", "cpu_bringup_and_idle", + "do_group_exit", + "stop_this_cpu", + "__invalid_creds", }; if (!func) @@ -380,6 +383,7 @@ static int decode_instructions(struct objtool_file *file) memset(insn, 0, sizeof(*insn)); INIT_LIST_HEAD(&insn->alts); INIT_LIST_HEAD(&insn->stack_ops); + INIT_LIST_HEAD(&insn->call_node); insn->sec = sec; insn->offset = offset; @@ -392,6 +396,14 @@ static int decode_instructions(struct objtool_file *file) if (ret) goto err; + /* + * By default, "ud2" is a dead end unless otherwise + * annotated, because GCC 7 inserts it for certain + * divide-by-zero cases. + */ + if (insn->type == INSN_BUG) + insn->dead_end = true; + hash_add(file->insn_hash, &insn->hash, sec_offset_hash(sec, insn->offset)); list_add_tail(&insn->list, &file->insn_list); nr_insns++; @@ -407,8 +419,17 @@ static int decode_instructions(struct objtool_file *file) return -1; } - sym_for_each_insn(file, func, insn) + sym_for_each_insn(file, func, insn) { insn->func = func; + if (insn->type == INSN_ENDBR && list_empty(&insn->call_node)) { + if (insn->offset == insn->func->offset) { + list_add_tail(&insn->call_node, &file->endbr_list); + file->nr_endbr++; + } else { + file->nr_endbr_int++; + } + } + } } } @@ -520,14 +541,6 @@ static int add_dead_ends(struct objtool_file *file) struct reloc *reloc; struct instruction *insn; - /* - * By default, "ud2" is a dead end unless otherwise annotated, because - * GCC 7 inserts it for certain divide-by-zero cases. - */ - for_each_insn(file, insn) - if (insn->type == INSN_BUG) - insn->dead_end = true; - /* * Check for manually annotated dead ends. */ @@ -731,6 +744,58 @@ static int create_retpoline_sites_sections(struct objtool_file *file) return 0; } +static int create_ibt_endbr_seal_sections(struct objtool_file *file) +{ + struct instruction *insn; + struct section *sec; + int idx; + + sec = find_section_by_name(file->elf, ".ibt_endbr_seal"); + if (sec) { + WARN("file already has .ibt_endbr_seal, skipping"); + return 0; + } + + idx = 0; + list_for_each_entry(insn, &file->endbr_list, call_node) + idx++; + + if (stats) { + printf("ibt: ENDBR at function start: %d\n", file->nr_endbr); + printf("ibt: ENDBR inside functions: %d\n", file->nr_endbr_int); + printf("ibt: superfluous ENDBR: %d\n", idx); + } + + if (!idx) + return 0; + + sec = elf_create_section(file->elf, ".ibt_endbr_seal", 0, + sizeof(int), idx); + if (!sec) { + WARN("elf_create_section: .ibt_endbr_seal"); + return -1; + } + + idx = 0; + list_for_each_entry(insn, &file->endbr_list, call_node) { + + int *site = (int *)sec->data->d_buf + idx; + *site = 0; + + if (elf_add_reloc_to_insn(file->elf, sec, + idx * sizeof(int), + R_X86_64_PC32, + insn->sec, insn->offset)) { + WARN("elf_add_reloc_to_insn: .ibt_endbr_seal"); + return -1; + } + + idx++; + } + + return 0; +} + static int create_mcount_loc_sections(struct objtool_file *file) { struct section *sec; @@ -1111,6 +1176,9 @@ static void annotate_call_site(struct objtool_file *file, list_add_tail(&insn->call_node, &file->mcount_loc_list); return; } + + if (!sibling && dead_end_function(file, sym)) + insn->dead_end = true; } static void add_call_dest(struct objtool_file *file, struct instruction *insn, @@ -1165,6 +1233,19 @@ static void add_retpoline_call(struct objtool_file *file, struct instruction *in annotate_call_site(file, insn, false); } + +static bool same_function(struct instruction *insn1, struct instruction *insn2) +{ + return insn1->func->pfunc == insn2->func->pfunc; +} + +static bool is_first_func_insn(struct instruction *insn) +{ + return insn->offset == insn->func->offset || + (insn->type == INSN_ENDBR && + insn->offset == insn->func->offset + insn->len); +} + /* * Find the destination instructions for all jumps. */ @@ -1245,8 +1326,8 @@ static int add_jump_destinations(struct objtool_file *file) insn->func->cfunc = insn->jump_dest->func; insn->jump_dest->func->pfunc = insn->func; - } else if (insn->jump_dest->func->pfunc != insn->func->pfunc && - insn->jump_dest->offset == insn->jump_dest->func->offset) { + } else if (!same_function(insn, insn->jump_dest) && + is_first_func_insn(insn->jump_dest)) { /* internal sibling call (without reloc) */ add_call_dest(file, insn, insn->jump_dest->func, true); } @@ -1836,6 +1917,16 @@ static int read_unwind_hints(struct objtool_file *file) insn->hint = true; + if (ibt && hint->type == UNWIND_HINT_TYPE_REGS_PARTIAL) { + struct symbol *sym = find_symbol_by_offset(insn->sec, insn->offset); + + if (sym && sym->bind == STB_GLOBAL && + insn->type != INSN_ENDBR && !insn->noendbr) { + WARN_FUNC("UNWIND_HINT_IRET_REGS without ENDBR", + insn->sec, insn->offset); + } + } + if (hint->type == UNWIND_HINT_TYPE_FUNC) { insn->cfi = &func_cfi; continue; @@ -1860,6 +1951,32 @@ static int read_unwind_hints(struct objtool_file *file) return 0; } +static int read_noendbr_hints(struct objtool_file *file) +{ + struct section *sec; + struct instruction *insn; + struct reloc *reloc; + + sec = find_section_by_name(file->elf, ".rela.discard.noendbr"); + if (!sec) + return 0; + + list_for_each_entry(reloc, &sec->reloc_list, list) { + insn = find_insn(file, reloc->sym->sec, reloc->sym->offset + reloc->addend); + if (!insn) { + WARN("bad .discard.noendbr entry"); + return -1; + } + + if (insn->type == INSN_ENDBR) + WARN_FUNC("ANNOTATE_NOENDBR on ENDBR", insn->sec, insn->offset); + + insn->noendbr = 1; + } + + return 0; +} + static int read_retpoline_hints(struct objtool_file *file) { struct section *sec; @@ -2086,10 +2203,6 @@ static int decode_sections(struct objtool_file *file) if (ret) return ret; - ret = add_dead_ends(file); - if (ret) - return ret; - add_ignores(file); add_uaccess_safe(file); @@ -2097,6 +2210,13 @@ static int decode_sections(struct objtool_file *file) if (ret) return ret; + /* + * Must be before read_unwind_hints() since that needs insn->noendbr. + */ + ret = read_noendbr_hints(file); + if (ret) + return ret; + /* * Must be before add_{jump_call}_destination. */ @@ -2128,6 +2248,14 @@ static int decode_sections(struct objtool_file *file) if (ret) return ret; + /* + * Must be after add_call_destinations() such that it can override + * dead_end_function() marks. + */ + ret = add_dead_ends(file); + if (ret) + return ret; + ret = add_jump_table_alts(file); if (ret) return ret; @@ -3026,6 +3154,115 @@ static struct instruction *next_insn_to_validate(struct objtool_file *file, return next_insn_same_sec(file, insn); } +static struct instruction * +validate_ibt_reloc(struct objtool_file *file, struct reloc *reloc) +{ + struct instruction *dest; + struct section *sec; + unsigned long off; + + sec = reloc->sym->sec; + off = reloc->sym->offset; + + if ((reloc->sec->base->sh.sh_flags & SHF_EXECINSTR) && + (reloc->type == R_X86_64_PC32 || reloc->type == R_X86_64_PLT32)) + off += arch_dest_reloc_offset(reloc->addend); + else + off += reloc->addend; + + dest = find_insn(file, sec, off); + if (!dest) + return NULL; + + if (dest->type == INSN_ENDBR) { + if (!list_empty(&dest->call_node)) + list_del_init(&dest->call_node); + + return NULL; + } + + if (reloc->sym->static_call_tramp) + return NULL; + + return dest; +} + +static void warn_noendbr(const char *msg, struct section *sec, unsigned long offset, + struct instruction *dest) +{ + WARN_FUNC("%srelocation to !ENDBR: %s+0x%lx", sec, offset, msg, + dest->func ? dest->func->name : dest->sec->name, + dest->func ? dest->offset - dest->func->offset : dest->offset); +} + +static void validate_ibt_dest(struct objtool_file *file, struct instruction *insn, + struct instruction *dest) +{ + if (dest->func && dest->func == insn->func) { + /* + * Anything from->to self is either _THIS_IP_ or IRET-to-self. + * + * There is no sane way to annotate _THIS_IP_ since the compiler treats the + * relocation as a constant and is happy to fold in offsets, skewing any + * annotation we do, leading to vast amounts of false-positives. + * + * There's also compiler generated _THIS_IP_ through KCOV and + * such which we have no hope of annotating. + * + * As such, blanket accept self-references without issue. + */ + return; + } + + if (dest->noendbr) + return; + + warn_noendbr("", insn->sec, insn->offset, dest); +} + +static void validate_ibt_insn(struct objtool_file *file, struct instruction *insn) +{ + struct instruction *dest; + struct reloc *reloc; + + switch (insn->type) { + case INSN_CALL: + case INSN_CALL_DYNAMIC: + case INSN_JUMP_CONDITIONAL: + case INSN_JUMP_UNCONDITIONAL: + case INSN_JUMP_DYNAMIC: + case INSN_JUMP_DYNAMIC_CONDITIONAL: + case INSN_RETURN: + /* + * We're looking for code references setting up indirect code + * flow. As such, ignore direct code flow and the actual + * dynamic branches. + */ + return; + + case INSN_NOP: + /* + * handle_group_alt() will create INSN_NOP instruction that + * don't belong to any section, ignore all NOP since they won't + * carry a (useful) relocation anyway. + */ + return; + + default: + break; + } + + for (reloc = insn_reloc(file, insn); + reloc; + reloc = find_reloc_by_dest_range(file->elf, insn->sec, + reloc->offset + 1, + (insn->offset + insn->len) - (reloc->offset + 1))) { + dest = validate_ibt_reloc(file, reloc); + if (dest) + validate_ibt_dest(file, insn, dest); + } +} + /* * Follow the branch starting at the given instruction, and recursively follow * any other branches (jumps). Meanwhile, track the frame pointer state at @@ -3115,9 +3352,8 @@ static int validate_branch(struct objtool_file *file, struct symbol *func, switch (insn->type) { case INSN_RETURN: - if (next_insn && next_insn->type == INSN_TRAP) { - next_insn->ignore = true; - } else if (sls && !insn->retpoline_safe) { + if (sls && !insn->retpoline_safe && + next_insn && next_insn->type != INSN_TRAP) { WARN_FUNC("missing int3 after ret", insn->sec, insn->offset); } @@ -3136,7 +3372,7 @@ static int validate_branch(struct objtool_file *file, struct symbol *func, return 1; } - if (dead_end_function(file, insn->call_dest)) + if (insn->dead_end) return 0; break; @@ -3164,9 +3400,8 @@ static int validate_branch(struct objtool_file *file, struct symbol *func, break; case INSN_JUMP_DYNAMIC: - if (next_insn && next_insn->type == INSN_TRAP) { - next_insn->ignore = true; - } else if (sls && !insn->retpoline_safe) { + if (sls && !insn->retpoline_safe && + next_insn && next_insn->type != INSN_TRAP) { WARN_FUNC("missing int3 after indirect jump", insn->sec, insn->offset); } @@ -3237,6 +3472,9 @@ static int validate_branch(struct objtool_file *file, struct symbol *func, break; } + if (ibt) + validate_ibt_insn(file, insn); + if (insn->dead_end) return 0; @@ -3337,7 +3575,7 @@ static bool ignore_unreachable_insn(struct objtool_file *file, struct instructio int i; struct instruction *prev_insn; - if (insn->ignore || insn->type == INSN_NOP) + if (insn->ignore || insn->type == INSN_NOP || insn->type == INSN_TRAP) return true; /* @@ -3348,6 +3586,49 @@ static bool ignore_unreachable_insn(struct objtool_file *file, struct instructio !strcmp(insn->sec->name, ".altinstr_aux")) return true; + /* + * Whole archive runs might encounder dead code from weak symbols. + * This is where the linker will have dropped the weak symbol in + * favour of a regular symbol, but leaves the code in place. + * + * In this case we'll find a piece of code (whole function) that is not + * covered by a !section symbol. Ignore them. + */ + if (!insn->func && lto) { + int size = find_symbol_hole_containing(insn->sec, insn->offset); + unsigned long end = insn->offset + size; + + if (!size) /* not a hole */ + return false; + + if (size < 0) /* hole until the end */ + return true; + + sec_for_each_insn_continue(file, insn) { + /* + * If we reach a visited instruction at or before the + * end of the hole, ignore the unreachable. + */ + if (insn->visited) + return true; + + if (insn->offset >= end) + break; + + /* + * If this hole jumps to a .cold function, mark it ignore too. + */ + if (insn->jump_dest && insn->jump_dest->func && + strstr(insn->jump_dest->func->name, ".cold")) { + struct instruction *dest = insn->jump_dest; + func_for_each_insn(file, dest->func, dest) + dest->ignore = true; + } + } + + return false; + } + if (!insn->func) return false; @@ -3479,6 +3760,53 @@ static int validate_functions(struct objtool_file *file) return warnings; } +static int validate_ibt(struct objtool_file *file) +{ + struct section *sec; + struct reloc *reloc; + + for_each_sec(file, sec) { + bool is_data; + + /* already done in validate_branch() */ + if (sec->sh.sh_flags & SHF_EXECINSTR) + continue; + + if (!sec->reloc) + continue; + + if (!strncmp(sec->name, ".orc", 4)) + continue; + + if (!strncmp(sec->name, ".discard", 8)) + continue; + + if (!strncmp(sec->name, ".debug", 6)) + continue; + + if (!strcmp(sec->name, "_error_injection_whitelist")) + continue; + + if (!strcmp(sec->name, "_kprobe_blacklist")) + continue; + + is_data = strstr(sec->name, ".data") || strstr(sec->name, ".rodata"); + + list_for_each_entry(reloc, &sec->reloc->reloc_list, list) { + struct instruction *dest; + + dest = validate_ibt_reloc(file, reloc); + if (is_data && dest && !dest->noendbr) { + warn_noendbr("data ", reloc->sym->sec, + reloc->sym->offset + reloc->addend, + dest); + } + } + } + + return 0; +} + static int validate_reachable_instructions(struct objtool_file *file) { struct instruction *insn; @@ -3501,6 +3829,16 @@ int check(struct objtool_file *file) { int ret, warnings = 0; + if (lto && !(vmlinux || module)) { + fprintf(stderr, "--lto requires: --vmlinux or --module\n"); + return 1; + } + + if (ibt && !lto) { + fprintf(stderr, "--ibt requires: --lto\n"); + return 1; + } + arch_initial_func_cfi_state(&initial_func_cfi); init_cfi_state(&init_cfi); init_cfi_state(&func_cfi); @@ -3521,7 +3859,7 @@ int check(struct objtool_file *file) if (list_empty(&file->insn_list)) goto out; - if (vmlinux && !validate_dup) { + if (vmlinux && !lto) { ret = validate_vmlinux_functions(file); if (ret < 0) goto out; @@ -3547,6 +3885,13 @@ int check(struct objtool_file *file) goto out; warnings += ret; + if (ibt) { + ret = validate_ibt(file); + if (ret < 0) + goto out; + warnings += ret; + } + if (!warnings) { ret = validate_reachable_instructions(file); if (ret < 0) @@ -3573,6 +3918,13 @@ int check(struct objtool_file *file) warnings += ret; } + if (ibt) { + ret = create_ibt_endbr_seal_sections(file); + if (ret < 0) + goto out; + warnings += ret; + } + if (stats) { printf("nr_insns_visited: %ld\n", nr_insns_visited); printf("nr_cfi: %ld\n", nr_cfi); diff --git a/tools/objtool/elf.c b/tools/objtool/elf.c index 4b384c907027..d7b99a737496 100644 --- a/tools/objtool/elf.c +++ b/tools/objtool/elf.c @@ -83,6 +83,31 @@ static int symbol_by_offset(const void *key, const struct rb_node *node) return 0; } +struct symbol_hole { + unsigned long key; + const struct symbol *sym; +}; + +/* + * Find !section symbol where @offset is after it. + */ +static int symbol_hole_by_offset(const void *key, const struct rb_node *node) +{ + const struct symbol *s = rb_entry(node, struct symbol, node); + struct symbol_hole *sh = (void *)key; + + if (sh->key < s->offset) + return -1; + + if (sh->key >= s->offset + s->len) { + if (s->type != STT_SECTION) + sh->sym = s; + return 1; + } + + return 0; +} + struct section *find_section_by_name(const struct elf *elf, const char *name) { struct section *sec; @@ -162,6 +187,41 @@ struct symbol *find_symbol_containing(const struct section *sec, unsigned long o return NULL; } +/* + * Returns size of hole starting at @offset. + */ +int find_symbol_hole_containing(const struct section *sec, unsigned long offset) +{ + struct symbol_hole hole = { + .key = offset, + .sym = NULL, + }; + struct rb_node *n; + struct symbol *s; + + /* + * Find the rightmost symbol for which @offset is after it. + */ + n = rb_find(&hole, &sec->symbol_tree, symbol_hole_by_offset); + + /* found a symbol that contains @offset */ + if (n) + return 0; /* not a hole */ + + /* didn't find a symbol for which @offset is after it */ + if (!hole.sym) + return 0; /* not a hole */ + + /* @offset >= sym->offset + sym->len, find symbol after it */ + n = rb_next(&hole.sym->node); + if (!n) + return -1; /* until end of address space */ + + /* hole until start of next symbol */ + s = rb_entry(n, struct symbol, node); + return s->offset - offset; +} + struct symbol *find_func_containing(struct section *sec, unsigned long offset) { struct rb_node *node; @@ -1019,6 +1079,9 @@ int elf_write(struct elf *elf) struct section *sec; Elf_Scn *s; + if (dryrun) + return 0; + /* Update changed relocation sections and section headers: */ list_for_each_entry(sec, &elf->sections, list) { if (sec->changed) { diff --git a/tools/objtool/include/objtool/arch.h b/tools/objtool/include/objtool/arch.h index 76bae3078286..9b19cc304195 100644 --- a/tools/objtool/include/objtool/arch.h +++ b/tools/objtool/include/objtool/arch.h @@ -27,6 +27,7 @@ enum insn_type { INSN_STD, INSN_CLD, INSN_TRAP, + INSN_ENDBR, INSN_OTHER, }; diff --git a/tools/objtool/include/objtool/builtin.h b/tools/objtool/include/objtool/builtin.h index 89ba869ed08f..c39dbfaef6dc 100644 --- a/tools/objtool/include/objtool/builtin.h +++ b/tools/objtool/include/objtool/builtin.h @@ -9,7 +9,8 @@ extern const struct option check_options[]; extern bool no_fp, no_unreachable, retpoline, module, backtrace, uaccess, stats, - validate_dup, vmlinux, mcount, noinstr, backup, sls; + lto, vmlinux, mcount, noinstr, backup, sls, dryrun, + ibt; extern int cmd_parse_options(int argc, const char **argv, const char * const usage[]); diff --git a/tools/objtool/include/objtool/check.h b/tools/objtool/include/objtool/check.h index 6cfff078897f..f10d7374f388 100644 --- a/tools/objtool/include/objtool/check.h +++ b/tools/objtool/include/objtool/check.h @@ -45,11 +45,18 @@ struct instruction { unsigned int len; enum insn_type type; unsigned long immediate; - bool dead_end, ignore, ignore_alts; - bool hint; - bool retpoline_safe; + + u8 dead_end : 1, + ignore : 1, + ignore_alts : 1, + hint : 1, + retpoline_safe : 1, + noendbr : 1; + /* 2 bit hole */ s8 instr; u8 visited; + /* u8 hole */ + struct alt_group *alt_group; struct symbol *call_dest; struct instruction *jump_dest; diff --git a/tools/objtool/include/objtool/elf.h b/tools/objtool/include/objtool/elf.h index d22336781401..22ba7e2b816e 100644 --- a/tools/objtool/include/objtool/elf.h +++ b/tools/objtool/include/objtool/elf.h @@ -152,6 +152,7 @@ struct symbol *find_func_by_offset(struct section *sec, unsigned long offset); struct symbol *find_symbol_by_offset(struct section *sec, unsigned long offset); struct symbol *find_symbol_by_name(const struct elf *elf, const char *name); struct symbol *find_symbol_containing(const struct section *sec, unsigned long offset); +int find_symbol_hole_containing(const struct section *sec, unsigned long offset); struct reloc *find_reloc_by_dest(const struct elf *elf, struct section *sec, unsigned long offset); struct reloc *find_reloc_by_dest_range(const struct elf *elf, struct section *sec, unsigned long offset, unsigned int len); diff --git a/tools/objtool/include/objtool/objtool.h b/tools/objtool/include/objtool/objtool.h index f99fbc6078d5..7a5c13a78f87 100644 --- a/tools/objtool/include/objtool/objtool.h +++ b/tools/objtool/include/objtool/objtool.h @@ -26,8 +26,12 @@ struct objtool_file { struct list_head retpoline_call_list; struct list_head static_call_list; struct list_head mcount_loc_list; + struct list_head endbr_list; bool ignore_unreachables, c_file, hints, rodata; + unsigned int nr_endbr; + unsigned int nr_endbr_int; + unsigned long jl_short, jl_long; unsigned long jl_nop_short, jl_nop_long; diff --git a/tools/objtool/include/objtool/warn.h b/tools/objtool/include/objtool/warn.h index d99c4675e4a5..802cfda0a6f6 100644 --- a/tools/objtool/include/objtool/warn.h +++ b/tools/objtool/include/objtool/warn.h @@ -22,6 +22,8 @@ static inline char *offstr(struct section *sec, unsigned long offset) unsigned long name_off; func = find_func_containing(sec, offset); + if (!func) + func = find_symbol_containing(sec, offset); if (func) { name = func->name; name_off = offset - func->offset; diff --git a/tools/objtool/objtool.c b/tools/objtool/objtool.c index bdf699f6552b..b09946f4e1d6 100644 --- a/tools/objtool/objtool.c +++ b/tools/objtool/objtool.c @@ -128,6 +128,7 @@ struct objtool_file *objtool_open_read(const char *_objname) INIT_LIST_HEAD(&file.retpoline_call_list); INIT_LIST_HEAD(&file.static_call_list); INIT_LIST_HEAD(&file.mcount_loc_list); + INIT_LIST_HEAD(&file.endbr_list); file.c_file = !vmlinux && find_section_by_name(file.elf, ".comment"); file.ignore_unreachables = no_unreachable; file.hints = false; diff --git a/tools/perf/Documentation/itrace.txt b/tools/perf/Documentation/itrace.txt index c52755481e2f..6b189669c450 100644 --- a/tools/perf/Documentation/itrace.txt +++ b/tools/perf/Documentation/itrace.txt @@ -7,6 +7,8 @@ p synthesize power events (incl. PSB events for Intel PT) o synthesize other events recorded due to the use of aux-output (refer to perf record) + I synthesize interrupt or similar (asynchronous) events + (e.g. Intel PT Event Trace) e synthesize error events d create a debug log f synthesize first level cache events diff --git a/tools/perf/Documentation/perf-ftrace.txt b/tools/perf/Documentation/perf-ftrace.txt index 6e82b7cc0bf0..df4595563801 100644 --- a/tools/perf/Documentation/perf-ftrace.txt +++ b/tools/perf/Documentation/perf-ftrace.txt @@ -9,32 +9,24 @@ perf-ftrace - simple wrapper for kernel's ftrace functionality SYNOPSIS -------- [verse] -'perf ftrace' +'perf ftrace' {trace|latency} DESCRIPTION ----------- -The 'perf ftrace' command is a simple wrapper of kernel's ftrace -functionality. It only supports single thread tracing currently and -just reads trace_pipe in text and then write it to stdout. +The 'perf ftrace' command provides a collection of subcommands which use +kernel's ftrace infrastructure. + + 'perf ftrace trace' is a simple wrapper of the ftrace. It only supports + single thread tracing currently and just reads trace_pipe in text and then + write it to stdout. + + 'perf ftrace latency' calculates execution latency of a given function + (optionally with BPF) and display it as a histogram. The following options apply to perf ftrace. -OPTIONS -------- - --t:: ---tracer=:: - Tracer to use when neither -G nor -F option is not - specified: function_graph or function. - --v:: ---verbose:: - Increase the verbosity level. - --F:: ---funcs:: - List available functions to trace. It accepts a pattern to - only list interested functions. +COMMON OPTIONS +-------------- -p:: --pid=:: @@ -43,10 +35,6 @@ OPTIONS --tid=:: Trace on existing thread id (comma separated list). --D:: ---delay:: - Time (ms) to wait before starting tracing after program start. - -a:: --all-cpus:: Force system-wide collection. Scripts run without a @@ -61,6 +49,28 @@ OPTIONS Ranges of CPUs are specified with -: 0-2. Default is to trace on all online CPUs. +-v:: +--verbose:: + Increase the verbosity level. + + +OPTIONS for 'perf ftrace trace' +------------------------------- + +-t:: +--tracer=:: + Tracer to use when neither -G nor -F option is not + specified: function_graph or function. + +-F:: +--funcs:: + List available functions to trace. It accepts a pattern to + only list interested functions. + +-D:: +--delay:: + Time (ms) to wait before starting tracing after program start. + -m:: --buffer-size:: Set the size of per-cpu tracing buffer, is expected to @@ -114,6 +124,25 @@ OPTIONS thresh= - Setup trace duration threshold in microseconds. depth= - Set max depth for function graph tracer to follow. + +OPTIONS for 'perf ftrace latency' +--------------------------------- + +-T:: +--trace-funcs=:: + Set the function name to get the histogram. Unlike perf ftrace trace, + it only allows single function to calculate the histogram. + +-b:: +--use-bpf:: + Use BPF to measure function latency instead of using the ftrace (it + uses function_graph tracer internally). + +-n:: +--use-nsec:: + Use nano-second instead of micro-second as a base unit of the histogram. + + SEE ALSO -------- linkperf:perf-record[1], linkperf:perf-trace[1] diff --git a/tools/perf/Documentation/perf-intel-pt.txt b/tools/perf/Documentation/perf-intel-pt.txt index cbb920f5d056..ff58bd4c381b 100644 --- a/tools/perf/Documentation/perf-intel-pt.txt +++ b/tools/perf/Documentation/perf-intel-pt.txt @@ -108,9 +108,10 @@ displayed as follows: perf script --itrace=ibxwpe -F+flags -The flags are "bcrosyiABExgh" which stand for branch, call, return, conditional, +The flags are "bcrosyiABExghDt" which stand for branch, call, return, conditional, system, asynchronous, interrupt, transaction abort, trace begin, trace end, -in transaction, VM-entry, and VM-exit respectively. +in transaction, VM-entry, VM-exit, interrupt disabled, and interrupt disable +toggle respectively. perf script also supports higher level ways to dump instruction traces: @@ -483,6 +484,30 @@ pwr_evt Enable power events. The power events provide information about which contains "1" if the feature is supported and "0" otherwise. +event Enable Event Trace. The events provide information about asynchronous + events. + + Support for this feature is indicated by: + + /sys/bus/event_source/devices/intel_pt/caps/event_trace + + which contains "1" if the feature is supported and + "0" otherwise. + +notnt Disable TNT packets. Without TNT packets, it is not possible to walk + executable code to reconstruct control flow, however FUP, TIP, TIP.PGE + and TIP.PGD packets still indicate asynchronous control flow, and (if + return compression is disabled - see noretcomp) return statements. + The advantage of eliminating TNT packets is reducing the size of the + trace and corresponding tracing overhead. + + Support for this feature is indicated by: + + /sys/bus/event_source/devices/intel_pt/caps/tnt_disable + + which contains "1" if the feature is supported and + "0" otherwise. + AUX area sampling option ~~~~~~~~~~~~~~~~~~~~~~~~ @@ -876,6 +901,8 @@ The letters are: p synthesize "power" events (incl. PSB events) c synthesize branches events (calls only) r synthesize branches events (returns only) + o synthesize PEBS-via-PT events + I synthesize Event Trace events e synthesize tracing error events d create a debug log g synthesize a call chain (use with i or x) @@ -1371,6 +1398,79 @@ There were none. :17006 17006 [001] 11500.262869216: ffffffff8220116e error_entry+0xe ([guest.kernel.kallsyms]) pushq %rax +Event Trace +----------- + +Event Trace records information about asynchronous events, for example interrupts, +faults, VM exits and entries. The information is recorded in CFE and EVD packets, +and also the Interrupt Flag is recorded on the MODE.Exec packet. The CFE packet +contains a type field to identify one of the following: + + 1 INTR interrupt, fault, exception, NMI + 2 IRET interrupt return + 3 SMI system management interrupt + 4 RSM resume from system management mode + 5 SIPI startup interprocessor interrupt + 6 INIT INIT signal + 7 VMENTRY VM-Entry + 8 VMEXIT VM-Entry + 9 VMEXIT_INTR VM-Exit due to interrupt + 10 SHUTDOWN Shutdown + +For more details, refer to the Intel 64 and IA-32 Architectures Software +Developer Manuals (version 076 or later). + +The capability to do Event Trace is indicated by the +/sys/bus/event_source/devices/intel_pt/caps/event_trace file. + +Event trace is selected for recording using the "event" config term. e.g. + + perf record -e intel_pt/event/u uname + +Event trace events are output using the --itrace I option. e.g. + + perf script --itrace=Ie + +perf script displays events containing CFE type, vector and event data, +in the form: + + evt: hw int (t) cfe: INTR IP: 1 vector: 3 PFA: 0x8877665544332211 + +The IP flag indicates if the event binds to an IP, which includes any case where +flow control packet generation is enabled, as well as when CFE packet IP bit is +set. + +perf script displays events containing changes to the Interrupt Flag in the form: + + iflag: t IFLAG: 1->0 via branch + +where "via branch" indicates a branch (interrupt or return from interrupt) and +"non branch" indicates an instruction such as CFI, STI or POPF). + +In addition, the current state of the interrupt flag is indicated by the presence +or absence of the "D" (interrupt disabled) perf script flag. If the interrupt +flag is changed, then the "t" flag is also included i.e. + + no flag, interrupts enabled IF=1 + t interrupts become disabled IF=1 -> IF=0 + D interrupts are disabled IF=0 + Dt interrupts become enabled IF=0 -> IF=1 + +The intel-pt-events.py script illustrates how to access Event Trace information +using a Python script. + + +TNT Disable +----------- + +TNT packets are disabled using the "notnt" config term. e.g. + + perf record -e intel_pt/notnt/u uname + +In that case the --itrace q option is forced because walking executable code +to reconstruct the control flow is not possible. + + SEE ALSO -------- diff --git a/tools/perf/Documentation/perf-lock.txt b/tools/perf/Documentation/perf-lock.txt index 1b4d452923d7..b43222229807 100644 --- a/tools/perf/Documentation/perf-lock.txt +++ b/tools/perf/Documentation/perf-lock.txt @@ -54,6 +54,16 @@ REPORT OPTIONS Sorting key. Possible values: acquired (default), contended, avg_wait, wait_total, wait_max, wait_min. +-F:: +--field=:: + Output fields. By default it shows all the fields but users can + customize that using this. Possible values: acquired, contended, + avg_wait, wait_total, wait_max, wait_min. + +-c:: +--combine-locks:: + Merge lock instances in the same class (based on name). + INFO OPTIONS ------------ diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt index 9ccc75935bc5..465be4e62a17 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -713,6 +713,40 @@ measurements: wait -n ${perf_pid} exit $? +--threads=:: +Write collected trace data into several data files using parallel threads. + value can be user defined list of masks. Masks separated by colon +define CPUs to be monitored by a thread and affinity mask of that thread +is separated by slash: + + /:/:... + +CPUs or affinity masks must not overlap with other corresponding masks. +Invalid CPUs are ignored, but masks containing only invalid CPUs are not +allowed. + +For example user specification like the following: + + 0,2-4/2-4:1,5-7/5-7 + +specifies parallel threads layout that consists of two threads, +the first thread monitors CPUs 0 and 2-4 with the affinity mask 2-4, +the second monitors CPUs 1 and 5-7 with the affinity mask 5-7. + + value can also be a string meaning predefined parallel threads +layout: + + cpu - create new data streaming thread for every monitored cpu + core - create new thread to monitor CPUs grouped by a core + package - create new thread to monitor CPUs grouped by a package + numa - create new threed to monitor CPUs grouped by a NUMA domain + +Predefined layouts can be used on systems with large number of CPUs in +order not to spawn multiple per-cpu streaming threads but still avoid LOST +events in data directory files. Option specified with no or empty value +defaults to CPU layout. Masks defined or provided by the option value are +filtered through the mask provided by -C option. + include::intel-hybrid.txt[] --debuginfod[=URLs]:: diff --git a/tools/perf/Documentation/perf-script.txt b/tools/perf/Documentation/perf-script.txt index b0070718784d..2012a8e6c90b 100644 --- a/tools/perf/Documentation/perf-script.txt +++ b/tools/perf/Documentation/perf-script.txt @@ -129,8 +129,8 @@ OPTIONS Comma separated list of fields to print. Options are: comm, tid, pid, time, cpu, event, trace, ip, sym, dso, addr, symoff, srcline, period, iregs, uregs, brstack, brstacksym, flags, bpf-output, - brstackinsn, brstackoff, callindent, insn, insnlen, synth, phys_addr, - metric, misc, srccode, ipc, data_page_size, code_page_size, ins_lat. + brstackinsn, brstackinsnlen, brstackoff, callindent, insn, insnlen, synth, + phys_addr, metric, misc, srccode, ipc, data_page_size, code_page_size, ins_lat. Field list can be prepended with the type, trace, sw or hw, to indicate to which event type the field list applies. e.g., -F sw:comm,tid,time,ip,sym and -F trace:time,cpu,trace @@ -195,16 +195,19 @@ OPTIONS At this point usage is displayed, and perf-script exits. The flags field is synthesized and may have a value when Instruction - Trace decoding. The flags are "bcrosyiABExgh" which stand for branch, + Trace decoding. The flags are "bcrosyiABExghDt" which stand for branch, call, return, conditional, system, asynchronous, interrupt, - transaction abort, trace begin, trace end, in transaction, VM-Entry, and VM-Exit - respectively. Known combinations of flags are printed more nicely e.g. + transaction abort, trace begin, trace end, in transaction, VM-Entry, + VM-Exit, interrupt disabled and interrupt disable toggle respectively. + Known combinations of flags are printed more nicely e.g. "call" for "bc", "return" for "br", "jcc" for "bo", "jmp" for "b", "int" for "bci", "iret" for "bri", "syscall" for "bcs", "sysret" for "brs", "async" for "by", "hw int" for "bcyi", "tx abrt" for "bA", "tr strt" for "bB", "tr end" for "bE", "vmentry" for "bcg", "vmexit" for "bch". - However the "x" flag will be displayed separately in those - cases e.g. "jcc (x)" for a condition branch within a transaction. + However the "x", "D" and "t" flags will be displayed separately in those + cases e.g. "jcc (xD)" for a condition branch within a transaction + with interrupts disabled. Note, interrupts becoming disabled is "t", + whereas interrupts becoming enabled is "Dt". The callindent field is synthesized and may have a value when Instruction Trace decoding. For calls and returns, it will display the @@ -238,6 +241,10 @@ OPTIONS is printed. This is the full execution path leading to the sample. This is only supported when the sample was recorded with perf record -b or -j any. + Use brstackinsnlen to print the brstackinsn lenght. For example, you + can’t know the next sequential instruction after an unconditional branch unless + you calculate that based on its length. + The brstackoff field will print an offset into a specific dso/binary. With the metric option perf script can compute metrics for diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index ac861e42c8f7..9c935f86d172 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -691,7 +691,7 @@ $(OUTPUT)common-cmds.h: $(wildcard Documentation/perf-*.txt) $(SCRIPTS) : % : %.sh $(QUIET_GEN)$(INSTALL) '$@.sh' '$(OUTPUT)$@' -$(OUTPUT)PERF-VERSION-FILE: ../../.git/HEAD +$(OUTPUT)PERF-VERSION-FILE: ../../.git/HEAD ../../.git/ORIG_HEAD $(Q)$(SHELL_PATH) util/PERF-VERSION-GEN $(OUTPUT) $(Q)touch $(OUTPUT)PERF-VERSION-FILE @@ -1144,7 +1144,7 @@ endif # then force version regeneration: # ifeq ($(wildcard ../../.git/HEAD),) - GIT-HEAD-PHONY = ../../.git/HEAD + GIT-HEAD-PHONY = ../../.git/HEAD ../../.git/ORIG_HEAD else GIT-HEAD-PHONY = endif diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 2e8b2c4365a0..cbc555245959 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -510,6 +510,9 @@ static u64 cs_etmv4_get_config(struct auxtrace_record *itr) if (config_opts & BIT(ETM_OPT_CTXTID2)) config |= BIT(ETM4_CFG_BIT_VMID) | BIT(ETM4_CFG_BIT_VMID_OPT); + if (config_opts & BIT(ETM_OPT_BRANCH_BROADCAST)) + config |= BIT(ETM4_CFG_BIT_BB); + return config; } diff --git a/tools/perf/arch/arm64/util/arm-spe.c b/tools/perf/arch/arm64/util/arm-spe.c index 2100d46ccf5e..5860bbaea95a 100644 --- a/tools/perf/arch/arm64/util/arm-spe.c +++ b/tools/perf/arch/arm64/util/arm-spe.c @@ -158,7 +158,7 @@ static int arm_spe_recording_options(struct auxtrace_record *itr, return -EINVAL; } evsel->core.attr.freq = 0; - evsel->core.attr.sample_period = 1; + evsel->core.attr.sample_period = arm_spe_pmu->default_config->sample_period; arm_spe_evsel = evsel; opts->full_auxtrace = true; } diff --git a/tools/perf/arch/x86/tests/intel-pt-pkt-decoder-test.c b/tools/perf/arch/x86/tests/intel-pt-pkt-decoder-test.c index 2fc882ab24c1..42237656f453 100644 --- a/tools/perf/arch/x86/tests/intel-pt-pkt-decoder-test.c +++ b/tools/perf/arch/x86/tests/intel-pt-pkt-decoder-test.c @@ -17,7 +17,7 @@ * @new_ctx: expected new packet context * @ctx_unchanged: the packet context must not change */ -struct test_data { +static struct test_data { int len; u8 bytes[INTEL_PT_PKT_MAX_SZ]; enum intel_pt_pkt_ctx ctx; @@ -70,8 +70,11 @@ struct test_data { {8, {0x02, 0x43, 3, 4, 6, 8, 10, 12}, 0, {INTEL_PT_PIP, 0, 0xC0A08060403}, 0, 0 }, /* Mode Exec Packet */ {2, {0x99, 0x00}, 0, {INTEL_PT_MODE_EXEC, 0, 16}, 0, 0 }, - {2, {0x99, 0x01}, 0, {INTEL_PT_MODE_EXEC, 0, 64}, 0, 0 }, - {2, {0x99, 0x02}, 0, {INTEL_PT_MODE_EXEC, 0, 32}, 0, 0 }, + {2, {0x99, 0x01}, 0, {INTEL_PT_MODE_EXEC, 1, 64}, 0, 0 }, + {2, {0x99, 0x02}, 0, {INTEL_PT_MODE_EXEC, 2, 32}, 0, 0 }, + {2, {0x99, 0x04}, 0, {INTEL_PT_MODE_EXEC, 4, 16}, 0, 0 }, + {2, {0x99, 0x05}, 0, {INTEL_PT_MODE_EXEC, 5, 64}, 0, 0 }, + {2, {0x99, 0x06}, 0, {INTEL_PT_MODE_EXEC, 6, 32}, 0, 0 }, /* Mode TSX Packet */ {2, {0x99, 0x20}, 0, {INTEL_PT_MODE_TSX, 0, 0}, 0, 0 }, {2, {0x99, 0x21}, 0, {INTEL_PT_MODE_TSX, 0, 1}, 0, 0 }, @@ -166,6 +169,14 @@ struct test_data { {2, {0x02, 0xb3}, INTEL_PT_BLK_4_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 }, {2, {0x02, 0x33}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP, 0, 0}, 0, 0 }, {2, {0x02, 0xb3}, INTEL_PT_BLK_8_CTX, {INTEL_PT_BEP_IP, 0, 0}, 0, 0 }, + /* Control Flow Event Packet */ + {4, {0x02, 0x13, 0x01, 0x03}, 0, {INTEL_PT_CFE, 1, 3}, 0, 0 }, + {4, {0x02, 0x13, 0x81, 0x03}, 0, {INTEL_PT_CFE_IP, 1, 3}, 0, 0 }, + {4, {0x02, 0x13, 0x1f, 0x00}, 0, {INTEL_PT_CFE, 0x1f, 0}, 0, 0 }, + {4, {0x02, 0x13, 0x9f, 0xff}, 0, {INTEL_PT_CFE_IP, 0x1f, 0xff}, 0, 0 }, + /* */ + {11, {0x02, 0x53, 0x09, 1, 2, 3, 4, 5, 6, 7}, 0, {INTEL_PT_EVD, 0x09, 0x7060504030201}, 0, 0 }, + {11, {0x02, 0x53, 0x3f, 2, 3, 4, 5, 6, 7, 8}, 0, {INTEL_PT_EVD, 0x3f, 0x8070605040302}, 0, 0 }, /* Terminator */ {0, {0}, 0, {0, 0, 0}, 0, 0 }, }; diff --git a/tools/perf/arch/x86/util/event.c b/tools/perf/arch/x86/util/event.c index 9b31734ee968..e670f3547581 100644 --- a/tools/perf/arch/x86/util/event.c +++ b/tools/perf/arch/x86/util/event.c @@ -18,7 +18,7 @@ int perf_event__synthesize_extra_kmaps(struct perf_tool *tool, { int rc = 0; struct map *pos; - struct maps *kmaps = &machine->kmaps; + struct maps *kmaps = machine__kernel_maps(machine); union perf_event *event = zalloc(sizeof(event->mmap) + machine->id_hdr_size); diff --git a/tools/perf/arch/x86/util/evlist.c b/tools/perf/arch/x86/util/evlist.c index 8d9b55959256..cfc208d71f00 100644 --- a/tools/perf/arch/x86/util/evlist.c +++ b/tools/perf/arch/x86/util/evlist.c @@ -20,17 +20,27 @@ int arch_evlist__add_default_attrs(struct evlist *evlist) struct evsel *arch_evlist__leader(struct list_head *list) { - struct evsel *evsel, *first; + struct evsel *evsel, *first, *slots = NULL; + bool has_topdown = false; first = list_first_entry(list, struct evsel, core.node); if (!pmu_have_event("cpu", "slots")) return first; + /* If there is a slots event and a topdown event then the slots event comes first. */ __evlist__for_each_entry(list, evsel) { - if (evsel->pmu_name && !strcmp(evsel->pmu_name, "cpu") && - evsel->name && strcasestr(evsel->name, "slots")) - return evsel; + if (evsel->pmu_name && !strcmp(evsel->pmu_name, "cpu") && evsel->name) { + if (strcasestr(evsel->name, "slots")) { + slots = evsel; + if (slots == first) + return first; + } + if (!strncasecmp(evsel->name, "topdown", 7)) + has_topdown = true; + if (slots && has_topdown) + return slots; + } } return first; } diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c index 6df0dc00d73a..8c31578d6f4a 100644 --- a/tools/perf/arch/x86/util/intel-pt.c +++ b/tools/perf/arch/x86/util/intel-pt.c @@ -306,6 +306,7 @@ intel_pt_info_priv_size(struct auxtrace_record *itr, struct evlist *evlist) ptr->priv_size = (INTEL_PT_AUXTRACE_PRIV_MAX * sizeof(u64)) + intel_pt_filter_bytes(filter); + ptr->priv_size += sizeof(u64); /* Cap Event Trace */ return ptr->priv_size; } @@ -335,6 +336,7 @@ static int intel_pt_info_fill(struct auxtrace_record *itr, unsigned long max_non_turbo_ratio; size_t filter_str_len; const char *filter; + int event_trace; __u64 *info; int err; @@ -357,6 +359,9 @@ static int intel_pt_info_fill(struct auxtrace_record *itr, if (perf_pmu__scan_file(intel_pt_pmu, "max_nonturbo_ratio", "%lu", &max_non_turbo_ratio) != 1) max_non_turbo_ratio = 0; + if (perf_pmu__scan_file(intel_pt_pmu, "caps/event_trace", + "%d", &event_trace) != 1) + event_trace = 0; filter = intel_pt_find_filter(session->evlist, ptr->intel_pt_pmu); filter_str_len = filter ? strlen(filter) : 0; @@ -407,6 +412,8 @@ static int intel_pt_info_fill(struct auxtrace_record *itr, info += len >> 3; } + *info++ = event_trace; + return 0; } diff --git a/tools/perf/builtin-annotate.c b/tools/perf/builtin-annotate.c index 490bb9b8cf17..e65dc380be15 100644 --- a/tools/perf/builtin-annotate.c +++ b/tools/perf/builtin-annotate.c @@ -46,7 +46,11 @@ struct perf_annotate { struct perf_tool tool; struct perf_session *session; struct annotation_options opts; - bool use_tui, use_stdio, use_stdio2, use_gtk; +#ifdef HAVE_SLANG_SUPPORT + bool use_tui; +#endif + bool use_stdio, use_stdio2; + bool use_gtk; bool skip_missing; bool has_br_stack; bool group_set; @@ -190,7 +194,6 @@ static int process_branch_callback(struct evsel *evsel, }; struct addr_location a; - int ret; if (machine__resolve(machine, &a, sample) < 0) return -1; @@ -203,8 +206,7 @@ static int process_branch_callback(struct evsel *evsel, hist__account_cycles(sample->branch_stack, al, sample, false, NULL); - ret = hist_entry_iter__add(&iter, &a, PERF_MAX_STACK_DEPTH, ann); - return ret; + return hist_entry_iter__add(&iter, &a, PERF_MAX_STACK_DEPTH, ann); } static bool has_annotation(struct perf_annotate *ann) @@ -503,7 +505,9 @@ int cmd_annotate(int argc, const char **argv) OPT_BOOLEAN('D', "dump-raw-trace", &dump_trace, "dump raw trace in ASCII"), OPT_BOOLEAN(0, "gtk", &annotate.use_gtk, "Use the GTK interface"), +#ifdef HAVE_SLANG_SUPPORT OPT_BOOLEAN(0, "tui", &annotate.use_tui, "Use the TUI interface"), +#endif OPT_BOOLEAN(0, "stdio", &annotate.use_stdio, "Use the stdio interface"), OPT_BOOLEAN(0, "stdio2", &annotate.use_stdio2, "Use the stdio interface"), OPT_BOOLEAN(0, "ignore-vmlinux", &symbol_conf.ignore_vmlinux, @@ -624,8 +628,10 @@ int cmd_annotate(int argc, const char **argv) if (annotate.use_stdio || annotate.use_stdio2) use_browser = 0; +#ifdef HAVE_SLANG_SUPPORT else if (annotate.use_tui) use_browser = 1; +#endif else if (annotate.use_gtk) use_browser = 2; diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index 77dd4afacca4..fbbed434014f 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -44,6 +44,7 @@ #include "../perf.h" #include "pmu.h" #include "pmu-hybrid.h" +#include "string2.h" struct c2c_hists { struct hists hists; @@ -1080,7 +1081,7 @@ node_entry(struct perf_hpp_fmt *fmt __maybe_unused, struct perf_hpp *hpp, bitmap_zero(set, c2c.cpus_cnt); bitmap_and(set, c2c_he->cpuset, c2c.nodes[node], c2c.cpus_cnt); - if (!bitmap_weight(set, c2c.cpus_cnt)) { + if (bitmap_empty(set, c2c.cpus_cnt)) { if (c2c.node_info == 1) { ret = scnprintf(hpp->buf, hpp->size, "%21s", " "); advance_hpp(hpp, ret); @@ -1944,7 +1945,7 @@ static int set_nodestr(struct c2c_hist_entry *c2c_he) if (c2c_he->nodestr) return 0; - if (bitmap_weight(c2c_he->nodeset, c2c.nodes_cnt)) { + if (!bitmap_empty(c2c_he->nodeset, c2c.nodes_cnt)) { len = bitmap_scnprintf(c2c_he->nodeset, c2c.nodes_cnt, buf, sizeof(buf)); } else { @@ -3025,9 +3026,9 @@ int cmd_c2c(int argc, const char **argv) if (!argc) usage_with_options(c2c_usage, c2c_options); - if (!strncmp(argv[0], "rec", 3)) { + if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) { return perf_c2c__record(argc, argv); - } else if (!strncmp(argv[0], "rep", 3)) { + } else if (strlen(argv[0]) > 2 && strstarts("report", argv[0])) { return perf_c2c__report(argc, argv); } else { usage_with_options(c2c_usage, c2c_options); diff --git a/tools/perf/builtin-data.c b/tools/perf/builtin-data.c index b7f9dc85a407..c22d82d2a73c 100644 --- a/tools/perf/builtin-data.c +++ b/tools/perf/builtin-data.c @@ -62,10 +62,17 @@ static int cmd_data_convert(int argc, const char **argv) pr_err("You cannot specify both --to-ctf and --to-json.\n"); return -1; } +#ifdef HAVE_LIBBABELTRACE_SUPPORT if (!to_json && !to_ctf) { pr_err("You must specify one of --to-ctf or --to-json.\n"); return -1; } +#else + if (!to_json) { + pr_err("You must specify --to-json.\n"); + return -1; +} +#endif if (to_json) return bt_convert__perf2json(input_name, to_json, &opts); diff --git a/tools/perf/builtin-ftrace.c b/tools/perf/builtin-ftrace.c index a8785dec5ca6..ad9ce1bfffa1 100644 --- a/tools/perf/builtin-ftrace.c +++ b/tools/perf/builtin-ftrace.c @@ -680,7 +680,8 @@ out: return (done && !workload_exec_errno) ? 0 : -1; } -static void make_histogram(int buckets[], char *buf, size_t len, char *linebuf) +static void make_histogram(int buckets[], char *buf, size_t len, char *linebuf, + bool use_nsec) { char *p, *q; char *unit; @@ -727,6 +728,9 @@ static void make_histogram(int buckets[], char *buf, size_t len, char *linebuf) if (!unit || strncmp(unit, " us", 3)) goto next; + if (use_nsec) + num *= 1000; + i = log2(num); if (i < 0) i = 0; @@ -744,7 +748,7 @@ next: strcat(linebuf, p); } -static void display_histogram(int buckets[]) +static void display_histogram(int buckets[], bool use_nsec) { int i; int total = 0; @@ -770,12 +774,12 @@ static void display_histogram(int buckets[]) for (i = 1; i < NUM_BUCKET - 1; i++) { int start = (1 << (i - 1)); int stop = 1 << i; - const char *unit = "us"; + const char *unit = use_nsec ? "ns" : "us"; if (start >= 1024) { start >>= 10; stop >>= 10; - unit = "ms"; + unit = use_nsec ? "us" : "ms"; } bar_len = buckets[i] * bar_total / total; printf(" %4d - %-4d %s | %10d | %.*s%*s |\n", @@ -785,8 +789,8 @@ static void display_histogram(int buckets[]) bar_len = buckets[NUM_BUCKET - 1] * bar_total / total; printf(" %4d - %-4s %s | %10d | %.*s%*s |\n", - 1, "...", " s", buckets[NUM_BUCKET - 1], bar_len, bar, - bar_total - bar_len, ""); + 1, "...", use_nsec ? "ms" : " s", buckets[NUM_BUCKET - 1], + bar_len, bar, bar_total - bar_len, ""); } @@ -913,7 +917,7 @@ static int __cmd_latency(struct perf_ftrace *ftrace) if (n < 0) break; - make_histogram(buckets, buf, n, line); + make_histogram(buckets, buf, n, line, ftrace->use_nsec); } } @@ -930,12 +934,12 @@ static int __cmd_latency(struct perf_ftrace *ftrace) int n = read(trace_fd, buf, sizeof(buf) - 1); if (n <= 0) break; - make_histogram(buckets, buf, n, line); + make_histogram(buckets, buf, n, line, ftrace->use_nsec); } read_func_latency(ftrace, buckets); - display_histogram(buckets); + display_histogram(buckets, ftrace->use_nsec); out: close(trace_fd); @@ -1171,6 +1175,8 @@ int cmd_ftrace(int argc, const char **argv) OPT_BOOLEAN('b', "use-bpf", &ftrace.target.use_bpf, "Use BPF to measure function latency"), #endif + OPT_BOOLEAN('n', "--use-nsec", &ftrace.use_nsec, + "Use nano-second histogram"), OPT_PARENT(common_options), }; const struct option *options = ftrace_options; diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c index fbf43a454cba..5b50a4abf95f 100644 --- a/tools/perf/builtin-inject.c +++ b/tools/perf/builtin-inject.c @@ -25,6 +25,7 @@ #include "util/synthetic-events.h" #include "util/thread.h" #include "util/namespaces.h" +#include "util/util.h" #include #include @@ -110,7 +111,8 @@ static int perf_event__repipe_op2_synth(struct perf_session *session, static int perf_event__repipe_op4_synth(struct perf_session *session, union perf_event *event, - u64 data __maybe_unused) + u64 data __maybe_unused, + const char *str __maybe_unused) { return perf_event__repipe_synth(session->tool, event); } @@ -354,7 +356,7 @@ static struct dso *findnew_dso(int pid, int tid, const char *filename, nnsi = nsinfo__copy(nsi); if (nnsi) { nsinfo__put(nsi); - nnsi->need_setns = false; + nsinfo__clear_need_setns(nnsi); nsi = nnsi; } dso = machine__findnew_vdso(machine, thread); @@ -550,6 +552,15 @@ static int dso__read_build_id(struct dso *dso) nsinfo__mountns_enter(dso->nsinfo, &nsc); if (filename__read_build_id(dso->long_name, &dso->bid) > 0) dso->has_build_id = true; + else if (dso->nsinfo) { + char *new_name; + + new_name = filename_with_chroot(dso->nsinfo->pid, + dso->long_name); + if (new_name && filename__read_build_id(new_name, &dso->bid) > 0) + dso->has_build_id = true; + free(new_name); + } nsinfo__mountns_exit(&nsc); return dso->has_build_id ? 0 : -1; diff --git a/tools/perf/builtin-kmem.c b/tools/perf/builtin-kmem.c index 99d7ff9a8eff..ebfab2ca1702 100644 --- a/tools/perf/builtin-kmem.c +++ b/tools/perf/builtin-kmem.c @@ -1946,7 +1946,7 @@ int cmd_kmem(int argc, const char **argv) kmem_page = 1; } - if (!strncmp(argv[0], "rec", 3)) { + if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) { symbol__init(NULL); return __cmd_record(argc, argv); } diff --git a/tools/perf/builtin-kvm.c b/tools/perf/builtin-kvm.c index c6f352ee57e6..2fa687f73e5e 100644 --- a/tools/perf/builtin-kvm.c +++ b/tools/perf/builtin-kvm.c @@ -24,6 +24,7 @@ #include "util/ordered-events.h" #include "util/kvm-stat.h" #include "ui/ui.h" +#include "util/string2.h" #include #ifdef HAVE_TIMERFD_SUPPORT @@ -771,7 +772,7 @@ static s64 perf_kvm__mmap_read_idx(struct perf_kvm_stat *kvm, int idx, return -1; } - err = perf_session__queue_event(kvm->session, event, timestamp, 0); + err = perf_session__queue_event(kvm->session, event, timestamp, 0, NULL); /* * FIXME: Here we can't consume the event, as perf_session__queue_event will * point to it, and it'll get possibly overwritten by the kernel. @@ -1500,10 +1501,10 @@ static int kvm_cmd_stat(const char *file_name, int argc, const char **argv) goto perf_stat; } - if (!strncmp(argv[1], "rec", 3)) + if (strlen(argv[1]) > 2 && strstarts("record", argv[1])) return kvm_events_record(&kvm, argc - 1, argv + 1); - if (!strncmp(argv[1], "rep", 3)) + if (strlen(argv[1]) > 2 && strstarts("report", argv[1])) return kvm_events_report(&kvm, argc - 1 , argv + 1); #ifdef HAVE_TIMERFD_SUPPORT @@ -1631,9 +1632,9 @@ int cmd_kvm(int argc, const char **argv) } } - if (!strncmp(argv[0], "rec", 3)) + if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) return __cmd_record(file_name, argc, argv); - else if (!strncmp(argv[0], "rep", 3)) + else if (strlen(argv[0]) > 2 && strstarts("report", argv[0])) return __cmd_report(file_name, argc, argv); else if (!strncmp(argv[0], "diff", 4)) return cmd_diff(argc, argv); diff --git a/tools/perf/builtin-lock.c b/tools/perf/builtin-lock.c index d70131b7b1b1..cdfe1d4ced4b 100644 --- a/tools/perf/builtin-lock.c +++ b/tools/perf/builtin-lock.c @@ -18,6 +18,7 @@ #include "util/session.h" #include "util/tool.h" #include "util/data.h" +#include "util/string2.h" #include #include @@ -38,21 +39,16 @@ static struct perf_session *session; #define LOCKHASH_BITS 12 #define LOCKHASH_SIZE (1UL << LOCKHASH_BITS) -static struct list_head lockhash_table[LOCKHASH_SIZE]; +static struct hlist_head lockhash_table[LOCKHASH_SIZE]; #define __lockhashfn(key) hash_long((unsigned long)key, LOCKHASH_BITS) #define lockhashentry(key) (lockhash_table + __lockhashfn((key))) struct lock_stat { - struct list_head hash_entry; + struct hlist_node hash_entry; struct rb_node rb; /* used for sorting */ - /* - * FIXME: evsel__intval() returns u64, - * so address of lockdep_map should be treated as 64bit. - * Is there more better solution? - */ - void *addr; /* address of lockdep_map, used as ID */ + u64 addr; /* address of lockdep_map, used as ID */ char *name; /* for strcpy(), we cannot use const */ unsigned int nr_acquire; @@ -70,6 +66,7 @@ struct lock_stat { u64 wait_time_max; int discard; /* flag of blacklist */ + int combined; }; /* @@ -106,7 +103,7 @@ struct lock_seq_stat { struct list_head list; int state; u64 prev_event_time; - void *addr; + u64 addr; int read_count; }; @@ -120,6 +117,8 @@ struct thread_stat { static struct rb_root thread_stats; +static bool combine_locks; + static struct thread_stat *thread_stat_find(u32 tid) { struct rb_node *node; @@ -239,28 +238,65 @@ struct lock_key { * e.g. nr_acquired -> acquired, wait_time_total -> wait_total */ const char *name; + /* header: the string printed on the header line */ + const char *header; + /* len: the printing width of the field */ + int len; + /* key: a pointer to function to compare two lock stats for sorting */ int (*key)(struct lock_stat*, struct lock_stat*); + /* print: a pointer to function to print a given lock stats */ + void (*print)(struct lock_key*, struct lock_stat*); + /* list: list entry to link this */ + struct list_head list; }; +#define PRINT_KEY(member) \ +static void lock_stat_key_print_ ## member(struct lock_key *key, \ + struct lock_stat *ls) \ +{ \ + pr_info("%*llu", key->len, (unsigned long long)ls->member); \ +} + +PRINT_KEY(nr_acquired) +PRINT_KEY(nr_contended) +PRINT_KEY(avg_wait_time) +PRINT_KEY(wait_time_total) +PRINT_KEY(wait_time_max) + +static void lock_stat_key_print_wait_time_min(struct lock_key *key, + struct lock_stat *ls) +{ + u64 wait_time = ls->wait_time_min; + + if (wait_time == ULLONG_MAX) + wait_time = 0; + + pr_info("%*"PRIu64, key->len, wait_time); +} + + static const char *sort_key = "acquired"; static int (*compare)(struct lock_stat *, struct lock_stat *); +static struct rb_root sorted; /* place to store intermediate data */ static struct rb_root result; /* place to store sorted data */ -#define DEF_KEY_LOCK(name, fn_suffix) \ - { #name, lock_stat_key_ ## fn_suffix } +static LIST_HEAD(lock_keys); +static const char *output_fields; + +#define DEF_KEY_LOCK(name, header, fn_suffix, len) \ + { #name, header, len, lock_stat_key_ ## fn_suffix, lock_stat_key_print_ ## fn_suffix, {} } struct lock_key keys[] = { - DEF_KEY_LOCK(acquired, nr_acquired), - DEF_KEY_LOCK(contended, nr_contended), - DEF_KEY_LOCK(avg_wait, avg_wait_time), - DEF_KEY_LOCK(wait_total, wait_time_total), - DEF_KEY_LOCK(wait_min, wait_time_min), - DEF_KEY_LOCK(wait_max, wait_time_max), + DEF_KEY_LOCK(acquired, "acquired", nr_acquired, 10), + DEF_KEY_LOCK(contended, "contended", nr_contended, 10), + DEF_KEY_LOCK(avg_wait, "avg wait (ns)", avg_wait_time, 15), + DEF_KEY_LOCK(wait_total, "total wait (ns)", wait_time_total, 15), + DEF_KEY_LOCK(wait_max, "max wait (ns)", wait_time_max, 15), + DEF_KEY_LOCK(wait_min, "min wait (ns)", wait_time_min, 15), /* extra comparisons much complicated should be here */ - - { NULL, NULL } + { } }; static int select_key(void) @@ -270,15 +306,126 @@ static int select_key(void) for (i = 0; keys[i].name; i++) { if (!strcmp(keys[i].name, sort_key)) { compare = keys[i].key; + + /* selected key should be in the output fields */ + if (list_empty(&keys[i].list)) + list_add_tail(&keys[i].list, &lock_keys); + return 0; } } pr_err("Unknown compare key: %s\n", sort_key); - return -1; } +static int add_output_field(struct list_head *head, char *name) +{ + int i; + + for (i = 0; keys[i].name; i++) { + if (strcmp(keys[i].name, name)) + continue; + + /* prevent double link */ + if (list_empty(&keys[i].list)) + list_add_tail(&keys[i].list, head); + + return 0; + } + + pr_err("Unknown output field: %s\n", name); + return -1; +} + +static int setup_output_field(const char *str) +{ + char *tok, *tmp, *orig; + int i, ret = 0; + + /* no output field given: use all of them */ + if (str == NULL) { + for (i = 0; keys[i].name; i++) + list_add_tail(&keys[i].list, &lock_keys); + return 0; + } + + for (i = 0; keys[i].name; i++) + INIT_LIST_HEAD(&keys[i].list); + + orig = tmp = strdup(str); + if (orig == NULL) + return -ENOMEM; + + while ((tok = strsep(&tmp, ",")) != NULL){ + ret = add_output_field(&lock_keys, tok); + if (ret < 0) + break; + } + free(orig); + + return ret; +} + +static void combine_lock_stats(struct lock_stat *st) +{ + struct rb_node **rb = &sorted.rb_node; + struct rb_node *parent = NULL; + struct lock_stat *p; + int ret; + + while (*rb) { + p = container_of(*rb, struct lock_stat, rb); + parent = *rb; + + if (st->name && p->name) + ret = strcmp(st->name, p->name); + else + ret = !!st->name - !!p->name; + + if (ret == 0) { + if (st->discard) + goto out; + + p->nr_acquired += st->nr_acquired; + p->nr_contended += st->nr_contended; + p->wait_time_total += st->wait_time_total; + + if (p->nr_contended) + p->avg_wait_time = p->wait_time_total / p->nr_contended; + + if (p->wait_time_min > st->wait_time_min) + p->wait_time_min = st->wait_time_min; + if (p->wait_time_max < st->wait_time_max) + p->wait_time_max = st->wait_time_max; + + /* now it got a new !discard record */ + p->discard = 0; + +out: + st->combined = 1; + return; + } + + if (ret < 0) + rb = &(*rb)->rb_left; + else + rb = &(*rb)->rb_right; + } + + rb_link_node(&st->rb, parent, rb); + rb_insert_color(&st->rb, &sorted); + + if (st->discard) { + st->nr_acquired = 0; + st->nr_contended = 0; + st->wait_time_total = 0; + st->avg_wait_time = 0; + st->wait_time_min = ULLONG_MAX; + st->wait_time_max = 0; + } +} + static void insert_to_result(struct lock_stat *st, int (*bigger)(struct lock_stat *, struct lock_stat *)) { @@ -286,6 +433,9 @@ static void insert_to_result(struct lock_stat *st, struct rb_node *parent = NULL; struct lock_stat *p; + if (combine_locks && st->combined) + return; + while (*rb) { p = container_of(*rb, struct lock_stat, rb); parent = *rb; @@ -315,12 +465,12 @@ static struct lock_stat *pop_from_result(void) return container_of(node, struct lock_stat, rb); } -static struct lock_stat *lock_stat_findnew(void *addr, const char *name) +static struct lock_stat *lock_stat_findnew(u64 addr, const char *name) { - struct list_head *entry = lockhashentry(addr); + struct hlist_head *entry = lockhashentry(addr); struct lock_stat *ret, *new; - list_for_each_entry(ret, entry, hash_entry) { + hlist_for_each_entry(ret, entry, hash_entry) { if (ret->addr == addr) return ret; } @@ -339,7 +489,7 @@ static struct lock_stat *lock_stat_findnew(void *addr, const char *name) strcpy(new->name, name); new->wait_time_min = ULLONG_MAX; - list_add(&new->hash_entry, entry); + hlist_add_head(&new->hash_entry, entry); return new; alloc_failed: @@ -361,7 +511,7 @@ struct trace_lock_handler { struct perf_sample *sample); }; -static struct lock_seq_stat *get_seq(struct thread_stat *ts, void *addr) +static struct lock_seq_stat *get_seq(struct thread_stat *ts, u64 addr) { struct lock_seq_stat *seq; @@ -400,16 +550,13 @@ enum acquire_flags { static int report_lock_acquire_event(struct evsel *evsel, struct perf_sample *sample) { - void *addr; struct lock_stat *ls; struct thread_stat *ts; struct lock_seq_stat *seq; const char *name = evsel__strval(evsel, sample, "name"); - u64 tmp = evsel__intval(evsel, sample, "lockdep_addr"); + u64 addr = evsel__intval(evsel, sample, "lockdep_addr"); int flag = evsel__intval(evsel, sample, "flags"); - memcpy(&addr, &tmp, sizeof(void *)); - ls = lock_stat_findnew(addr, name); if (!ls) return -ENOMEM; @@ -472,15 +619,12 @@ end: static int report_lock_acquired_event(struct evsel *evsel, struct perf_sample *sample) { - void *addr; struct lock_stat *ls; struct thread_stat *ts; struct lock_seq_stat *seq; u64 contended_term; const char *name = evsel__strval(evsel, sample, "name"); - u64 tmp = evsel__intval(evsel, sample, "lockdep_addr"); - - memcpy(&addr, &tmp, sizeof(void *)); + u64 addr = evsel__intval(evsel, sample, "lockdep_addr"); ls = lock_stat_findnew(addr, name); if (!ls) @@ -535,14 +679,11 @@ end: static int report_lock_contended_event(struct evsel *evsel, struct perf_sample *sample) { - void *addr; struct lock_stat *ls; struct thread_stat *ts; struct lock_seq_stat *seq; const char *name = evsel__strval(evsel, sample, "name"); - u64 tmp = evsel__intval(evsel, sample, "lockdep_addr"); - - memcpy(&addr, &tmp, sizeof(void *)); + u64 addr = evsel__intval(evsel, sample, "lockdep_addr"); ls = lock_stat_findnew(addr, name); if (!ls) @@ -590,14 +731,11 @@ end: static int report_lock_release_event(struct evsel *evsel, struct perf_sample *sample) { - void *addr; struct lock_stat *ls; struct thread_stat *ts; struct lock_seq_stat *seq; const char *name = evsel__strval(evsel, sample, "name"); - u64 tmp = evsel__intval(evsel, sample, "lockdep_addr"); - - memcpy(&addr, &tmp, sizeof(void *)); + u64 addr = evsel__intval(evsel, sample, "lockdep_addr"); ls = lock_stat_findnew(addr, name); if (!ls) @@ -704,18 +842,13 @@ static void print_bad_events(int bad, int total) static void print_result(void) { struct lock_stat *st; + struct lock_key *key; char cut_name[20]; int bad, total; pr_info("%20s ", "Name"); - pr_info("%10s ", "acquired"); - pr_info("%10s ", "contended"); - - pr_info("%15s ", "avg wait (ns)"); - pr_info("%15s ", "total wait (ns)"); - pr_info("%15s ", "max wait (ns)"); - pr_info("%15s ", "min wait (ns)"); - + list_for_each_entry(key, &lock_keys, list) + pr_info("%*s ", key->len, key->header); pr_info("\n\n"); bad = total = 0; @@ -727,7 +860,7 @@ static void print_result(void) } bzero(cut_name, 20); - if (strlen(st->name) < 16) { + if (strlen(st->name) < 20) { /* output raw name */ pr_info("%20s ", st->name); } else { @@ -740,14 +873,10 @@ static void print_result(void) pr_info("%20s ", cut_name); } - pr_info("%10u ", st->nr_acquired); - pr_info("%10u ", st->nr_contended); - - pr_info("%15" PRIu64 " ", st->avg_wait_time); - pr_info("%15" PRIu64 " ", st->wait_time_total); - pr_info("%15" PRIu64 " ", st->wait_time_max); - pr_info("%15" PRIu64 " ", st->wait_time_min == ULLONG_MAX ? - 0 : st->wait_time_min); + list_for_each_entry(key, &lock_keys, list) { + key->print(key, st); + pr_info(" "); + } pr_info("\n"); } @@ -774,6 +903,21 @@ static void dump_threads(void) } } +static int compare_maps(struct lock_stat *a, struct lock_stat *b) +{ + int ret; + + if (a->name && b->name) + ret = strcmp(a->name, b->name); + else + ret = !!a->name - !!b->name; + + if (!ret) + return a->addr < b->addr; + else + return ret < 0; +} + static void dump_map(void) { unsigned int i; @@ -781,10 +925,13 @@ static void dump_map(void) pr_info("Address of instance: name of class\n"); for (i = 0; i < LOCKHASH_SIZE; i++) { - list_for_each_entry(st, &lockhash_table[i], hash_entry) { - pr_info(" %p: %s\n", st->addr, st->name); + hlist_for_each_entry(st, &lockhash_table[i], hash_entry) { + insert_to_result(st, compare_maps); } } + + while ((st = pop_from_result())) + pr_info(" %#llx: %s\n", (unsigned long long)st->addr, st->name); } static int dump_info(void) @@ -832,13 +979,28 @@ static int process_sample_event(struct perf_tool *tool __maybe_unused, return err; } +static void combine_result(void) +{ + unsigned int i; + struct lock_stat *st; + + if (!combine_locks) + return; + + for (i = 0; i < LOCKHASH_SIZE; i++) { + hlist_for_each_entry(st, &lockhash_table[i], hash_entry) { + combine_lock_stats(st); + } + } +} + static void sort_result(void) { unsigned int i; struct lock_stat *st; for (i = 0; i < LOCKHASH_SIZE; i++) { - list_for_each_entry(st, &lockhash_table[i], hash_entry) { + hlist_for_each_entry(st, &lockhash_table[i], hash_entry) { insert_to_result(st, compare); } } @@ -884,6 +1046,9 @@ static int __cmd_report(bool display_info) goto out_delete; } + if (setup_output_field(output_fields)) + goto out_delete; + if (select_key()) goto out_delete; @@ -895,6 +1060,7 @@ static int __cmd_report(bool display_info) if (display_info) /* used for info subcommand */ err = dump_info(); else { + combine_result(); sort_result(); print_result(); } @@ -907,7 +1073,7 @@ out_delete: static int __cmd_record(int argc, const char **argv) { const char *record_args[] = { - "record", "-R", "-m", "1024", "-c", "1", + "record", "-R", "-m", "1024", "-c", "1", "--synth", "no", }; unsigned int rec_argc, i, j, ret; const char **rec_argv; @@ -968,7 +1134,11 @@ int cmd_lock(int argc, const char **argv) const struct option report_options[] = { OPT_STRING('k', "key", &sort_key, "acquired", "key for sorting (acquired / contended / avg_wait / wait_total / wait_max / wait_min)"), + OPT_STRING('F', "field", &output_fields, NULL, + "output fields (acquired / contended / avg_wait / wait_total / wait_max / wait_min)"), /* TODO: type */ + OPT_BOOLEAN('c', "combine-locks", &combine_locks, + "combine locks in the same class"), OPT_PARENT(lock_options) }; @@ -990,16 +1160,16 @@ int cmd_lock(int argc, const char **argv) int rc = 0; for (i = 0; i < LOCKHASH_SIZE; i++) - INIT_LIST_HEAD(lockhash_table + i); + INIT_HLIST_HEAD(lockhash_table + i); argc = parse_options_subcommand(argc, argv, lock_options, lock_subcommands, lock_usage, PARSE_OPT_STOP_AT_NON_OPTION); if (!argc) usage_with_options(lock_usage, lock_options); - if (!strncmp(argv[0], "rec", 3)) { + if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) { return __cmd_record(argc, argv); - } else if (!strncmp(argv[0], "report", 6)) { + } else if (strlen(argv[0]) > 2 && strstarts("report", argv[0])) { trace_handler = &report_lock_ops; if (argc) { argc = parse_options(argc, argv, diff --git a/tools/perf/builtin-mem.c b/tools/perf/builtin-mem.c index fcf65a59bea2..9e435fd23503 100644 --- a/tools/perf/builtin-mem.c +++ b/tools/perf/builtin-mem.c @@ -20,6 +20,7 @@ #include "util/symbol.h" #include "util/pmu.h" #include "util/pmu-hybrid.h" +#include "util/string2.h" #include #define MEM_OPERATION_LOAD 0x1 @@ -496,9 +497,9 @@ int cmd_mem(int argc, const char **argv) mem.input_name = "perf.data"; } - if (!strncmp(argv[0], "rec", 3)) + if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) return __cmd_record(argc, argv, &mem); - else if (!strncmp(argv[0], "rep", 3)) + else if (strlen(argv[0]) > 2 && strstarts("report", argv[0])) return report_events(argc, argv, &mem); else usage_with_options(mem_usage, mem_options); diff --git a/tools/perf/builtin-probe.c b/tools/perf/builtin-probe.c index c31627af75d4..f62298f5db3b 100644 --- a/tools/perf/builtin-probe.c +++ b/tools/perf/builtin-probe.c @@ -217,7 +217,7 @@ static int opt_set_target_ns(const struct option *opt __maybe_unused, return ret; } nsip = nsinfo__new(ns_pid); - if (nsip && nsip->need_setns) + if (nsip && nsinfo__need_setns(nsip)) params.nsi = nsinfo__get(nsip); nsinfo__put(nsip); diff --git a/tools/perf/builtin-record.c b/tools/perf/builtin-record.c index bb716c953d02..0b4abed555d8 100644 --- a/tools/perf/builtin-record.c +++ b/tools/perf/builtin-record.c @@ -51,6 +51,7 @@ #include "util/evlist-hybrid.h" #include "asm/bug.h" #include "perf.h" +#include "cputopo.h" #include #include @@ -58,6 +59,9 @@ #include #include #include +#ifndef HAVE_GETTID +#include +#endif #include #include #ifdef HAVE_EVENTFD_SUPPORT @@ -87,6 +91,57 @@ struct switch_output { int cur_file; }; +struct thread_mask { + struct mmap_cpu_mask maps; + struct mmap_cpu_mask affinity; +}; + +struct record_thread { + pid_t tid; + struct thread_mask *mask; + struct { + int msg[2]; + int ack[2]; + } pipes; + struct fdarray pollfd; + int ctlfd_pos; + int nr_mmaps; + struct mmap **maps; + struct mmap **overwrite_maps; + struct record *rec; + unsigned long long samples; + unsigned long waking; + u64 bytes_written; + u64 bytes_transferred; + u64 bytes_compressed; +}; + +static __thread struct record_thread *thread; + +enum thread_msg { + THREAD_MSG__UNDEFINED = 0, + THREAD_MSG__READY, + THREAD_MSG__MAX, +}; + +static const char *thread_msg_tags[THREAD_MSG__MAX] = { + "UNDEFINED", "READY" +}; + +enum thread_spec { + THREAD_SPEC__UNDEFINED = 0, + THREAD_SPEC__CPU, + THREAD_SPEC__CORE, + THREAD_SPEC__PACKAGE, + THREAD_SPEC__NUMA, + THREAD_SPEC__USER, + THREAD_SPEC__MAX, +}; + +static const char *thread_spec_tags[THREAD_SPEC__MAX] = { + "undefined", "cpu", "core", "package", "numa", "user" +}; + struct record { struct perf_tool tool; struct record_opts opts; @@ -109,9 +164,11 @@ struct record { bool timestamp_boundary; struct switch_output switch_output; unsigned long long samples; - struct mmap_cpu_mask affinity_mask; unsigned long output_max_size; /* = 0: unlimited */ struct perf_debuginfod debuginfod; + int nr_threads; + struct thread_mask *thread_masks; + struct record_thread *thread_data; }; static volatile int done; @@ -124,6 +181,18 @@ static const char *affinity_tags[PERF_AFFINITY_MAX] = { "SYS", "NODE", "CPU" }; +#ifndef HAVE_GETTID +static inline pid_t gettid(void) +{ + return (pid_t)syscall(__NR_gettid); +} +#endif + +static int record__threads_enabled(struct record *rec) +{ + return rec->opts.threads_spec; +} + static bool switch_output_signal(struct record *rec) { return rec->switch_output.signal && @@ -143,10 +212,22 @@ static bool switch_output_time(struct record *rec) trigger_is_ready(&switch_output_trigger); } +static u64 record__bytes_written(struct record *rec) +{ + int t; + u64 bytes_written = rec->bytes_written; + struct record_thread *thread_data = rec->thread_data; + + for (t = 0; t < rec->nr_threads; t++) + bytes_written += thread_data[t].bytes_written; + + return bytes_written; +} + static bool record__output_max_size_exceeded(struct record *rec) { return rec->output_max_size && - (rec->bytes_written >= rec->output_max_size); + (record__bytes_written(rec) >= rec->output_max_size); } static int record__write(struct record *rec, struct mmap *map __maybe_unused, @@ -154,17 +235,23 @@ static int record__write(struct record *rec, struct mmap *map __maybe_unused, { struct perf_data_file *file = &rec->session->data->file; + if (map && map->file) + file = map->file; + if (perf_data_file__write(file, bf, size) < 0) { pr_err("failed to write perf data, error: %m\n"); return -1; } - rec->bytes_written += size; + if (map && map->file) + thread->bytes_written += size; + else + rec->bytes_written += size; if (record__output_max_size_exceeded(rec) && !done) { fprintf(stderr, "[ perf record: perf size limit reached (%" PRIu64 " KB)," " stopping session ]\n", - rec->bytes_written >> 10); + record__bytes_written(rec) >> 10); done = 1; } @@ -176,8 +263,8 @@ static int record__write(struct record *rec, struct mmap *map __maybe_unused, static int record__aio_enabled(struct record *rec); static int record__comp_enabled(struct record *rec); -static size_t zstd_compress(struct perf_session *session, void *dst, size_t dst_size, - void *src, size_t src_size); +static size_t zstd_compress(struct perf_session *session, struct mmap *map, + void *dst, size_t dst_size, void *src, size_t src_size); #ifdef HAVE_AIO_SUPPORT static int record__aio_write(struct aiocb *cblock, int trace_fd, @@ -311,7 +398,7 @@ static int record__aio_pushfn(struct mmap *map, void *to, void *buf, size_t size */ if (record__comp_enabled(aio->rec)) { - size = zstd_compress(aio->rec->session, aio->data + aio->size, + size = zstd_compress(aio->rec->session, NULL, aio->data + aio->size, mmap__mmap_len(map) - aio->size, buf, size); } else { @@ -538,11 +625,11 @@ static int record__pushfn(struct mmap *map, void *to, void *bf, size_t size) struct record *rec = to; if (record__comp_enabled(rec)) { - size = zstd_compress(rec->session, map->data, mmap__mmap_len(map), bf, size); + size = zstd_compress(rec->session, map, map->data, mmap__mmap_len(map), bf, size); bf = map->data; } - rec->samples++; + thread->samples++; return record__write(rec, map, bf, size); } @@ -718,6 +805,12 @@ static int record__auxtrace_init(struct record *rec) { int err; + if ((rec->opts.auxtrace_snapshot_opts || rec->opts.auxtrace_sample_opts) + && record__threads_enabled(rec)) { + pr_err("AUX area tracing options are not available in parallel streaming mode.\n"); + return -EINVAL; + } + if (!rec->itr) { rec->itr = auxtrace_record__init(rec->evlist, &err); if (err) @@ -841,9 +934,218 @@ static int record__kcore_copy(struct machine *machine, struct perf_data *data) return kcore_copy(from_dir, kcore_dir); } +static void record__thread_data_init_pipes(struct record_thread *thread_data) +{ + thread_data->pipes.msg[0] = -1; + thread_data->pipes.msg[1] = -1; + thread_data->pipes.ack[0] = -1; + thread_data->pipes.ack[1] = -1; +} + +static int record__thread_data_open_pipes(struct record_thread *thread_data) +{ + if (pipe(thread_data->pipes.msg)) + return -EINVAL; + + if (pipe(thread_data->pipes.ack)) { + close(thread_data->pipes.msg[0]); + thread_data->pipes.msg[0] = -1; + close(thread_data->pipes.msg[1]); + thread_data->pipes.msg[1] = -1; + return -EINVAL; + } + + pr_debug2("thread_data[%p]: msg=[%d,%d], ack=[%d,%d]\n", thread_data, + thread_data->pipes.msg[0], thread_data->pipes.msg[1], + thread_data->pipes.ack[0], thread_data->pipes.ack[1]); + + return 0; +} + +static void record__thread_data_close_pipes(struct record_thread *thread_data) +{ + if (thread_data->pipes.msg[0] != -1) { + close(thread_data->pipes.msg[0]); + thread_data->pipes.msg[0] = -1; + } + if (thread_data->pipes.msg[1] != -1) { + close(thread_data->pipes.msg[1]); + thread_data->pipes.msg[1] = -1; + } + if (thread_data->pipes.ack[0] != -1) { + close(thread_data->pipes.ack[0]); + thread_data->pipes.ack[0] = -1; + } + if (thread_data->pipes.ack[1] != -1) { + close(thread_data->pipes.ack[1]); + thread_data->pipes.ack[1] = -1; + } +} + +static int record__thread_data_init_maps(struct record_thread *thread_data, struct evlist *evlist) +{ + int m, tm, nr_mmaps = evlist->core.nr_mmaps; + struct mmap *mmap = evlist->mmap; + struct mmap *overwrite_mmap = evlist->overwrite_mmap; + struct perf_cpu_map *cpus = evlist->core.cpus; + + thread_data->nr_mmaps = bitmap_weight(thread_data->mask->maps.bits, + thread_data->mask->maps.nbits); + if (mmap) { + thread_data->maps = zalloc(thread_data->nr_mmaps * sizeof(struct mmap *)); + if (!thread_data->maps) + return -ENOMEM; + } + if (overwrite_mmap) { + thread_data->overwrite_maps = zalloc(thread_data->nr_mmaps * sizeof(struct mmap *)); + if (!thread_data->overwrite_maps) { + zfree(&thread_data->maps); + return -ENOMEM; + } + } + pr_debug2("thread_data[%p]: nr_mmaps=%d, maps=%p, ow_maps=%p\n", thread_data, + thread_data->nr_mmaps, thread_data->maps, thread_data->overwrite_maps); + + for (m = 0, tm = 0; m < nr_mmaps && tm < thread_data->nr_mmaps; m++) { + if (test_bit(cpus->map[m].cpu, thread_data->mask->maps.bits)) { + if (thread_data->maps) { + thread_data->maps[tm] = &mmap[m]; + pr_debug2("thread_data[%p]: cpu%d: maps[%d] -> mmap[%d]\n", + thread_data, cpus->map[m].cpu, tm, m); + } + if (thread_data->overwrite_maps) { + thread_data->overwrite_maps[tm] = &overwrite_mmap[m]; + pr_debug2("thread_data[%p]: cpu%d: ow_maps[%d] -> ow_mmap[%d]\n", + thread_data, cpus->map[m].cpu, tm, m); + } + tm++; + } + } + + return 0; +} + +static int record__thread_data_init_pollfd(struct record_thread *thread_data, struct evlist *evlist) +{ + int f, tm, pos; + struct mmap *map, *overwrite_map; + + fdarray__init(&thread_data->pollfd, 64); + + for (tm = 0; tm < thread_data->nr_mmaps; tm++) { + map = thread_data->maps ? thread_data->maps[tm] : NULL; + overwrite_map = thread_data->overwrite_maps ? + thread_data->overwrite_maps[tm] : NULL; + + for (f = 0; f < evlist->core.pollfd.nr; f++) { + void *ptr = evlist->core.pollfd.priv[f].ptr; + + if ((map && ptr == map) || (overwrite_map && ptr == overwrite_map)) { + pos = fdarray__dup_entry_from(&thread_data->pollfd, f, + &evlist->core.pollfd); + if (pos < 0) + return pos; + pr_debug2("thread_data[%p]: pollfd[%d] <- event_fd=%d\n", + thread_data, pos, evlist->core.pollfd.entries[f].fd); + } + } + } + + return 0; +} + +static void record__free_thread_data(struct record *rec) +{ + int t; + struct record_thread *thread_data = rec->thread_data; + + if (thread_data == NULL) + return; + + for (t = 0; t < rec->nr_threads; t++) { + record__thread_data_close_pipes(&thread_data[t]); + zfree(&thread_data[t].maps); + zfree(&thread_data[t].overwrite_maps); + fdarray__exit(&thread_data[t].pollfd); + } + + zfree(&rec->thread_data); +} + +static int record__alloc_thread_data(struct record *rec, struct evlist *evlist) +{ + int t, ret; + struct record_thread *thread_data; + + rec->thread_data = zalloc(rec->nr_threads * sizeof(*(rec->thread_data))); + if (!rec->thread_data) { + pr_err("Failed to allocate thread data\n"); + return -ENOMEM; + } + thread_data = rec->thread_data; + + for (t = 0; t < rec->nr_threads; t++) + record__thread_data_init_pipes(&thread_data[t]); + + for (t = 0; t < rec->nr_threads; t++) { + thread_data[t].rec = rec; + thread_data[t].mask = &rec->thread_masks[t]; + ret = record__thread_data_init_maps(&thread_data[t], evlist); + if (ret) { + pr_err("Failed to initialize thread[%d] maps\n", t); + goto out_free; + } + ret = record__thread_data_init_pollfd(&thread_data[t], evlist); + if (ret) { + pr_err("Failed to initialize thread[%d] pollfd\n", t); + goto out_free; + } + if (t) { + thread_data[t].tid = -1; + ret = record__thread_data_open_pipes(&thread_data[t]); + if (ret) { + pr_err("Failed to open thread[%d] communication pipes\n", t); + goto out_free; + } + ret = fdarray__add(&thread_data[t].pollfd, thread_data[t].pipes.msg[0], + POLLIN | POLLERR | POLLHUP, fdarray_flag__nonfilterable); + if (ret < 0) { + pr_err("Failed to add descriptor to thread[%d] pollfd\n", t); + goto out_free; + } + thread_data[t].ctlfd_pos = ret; + pr_debug2("thread_data[%p]: pollfd[%d] <- ctl_fd=%d\n", + thread_data, thread_data[t].ctlfd_pos, + thread_data[t].pipes.msg[0]); + } else { + thread_data[t].tid = gettid(); + if (evlist->ctl_fd.pos == -1) + continue; + ret = fdarray__dup_entry_from(&thread_data[t].pollfd, evlist->ctl_fd.pos, + &evlist->core.pollfd); + if (ret < 0) { + pr_err("Failed to duplicate descriptor in main thread pollfd\n"); + goto out_free; + } + thread_data[t].ctlfd_pos = ret; + pr_debug2("thread_data[%p]: pollfd[%d] <- ctl_fd=%d\n", + thread_data, thread_data[t].ctlfd_pos, + evlist->core.pollfd.entries[evlist->ctl_fd.pos].fd); + } + } + + return 0; + +out_free: + record__free_thread_data(rec); + + return ret; +} + static int record__mmap_evlist(struct record *rec, struct evlist *evlist) { + int i, ret; struct record_opts *opts = &rec->opts; bool auxtrace_overwrite = opts->auxtrace_snapshot_mode || opts->auxtrace_sample_mode; @@ -874,6 +1176,28 @@ static int record__mmap_evlist(struct record *rec, return -EINVAL; } } + + if (evlist__initialize_ctlfd(evlist, opts->ctl_fd, opts->ctl_fd_ack)) + return -1; + + ret = record__alloc_thread_data(rec, evlist); + if (ret) + return ret; + + if (record__threads_enabled(rec)) { + ret = perf_data__create_dir(&rec->data, evlist->core.nr_mmaps); + if (ret) { + pr_err("Failed to create data directory: %s\n", strerror(-ret)); + return ret; + } + for (i = 0; i < evlist->core.nr_mmaps; i++) { + if (evlist->mmap) + evlist->mmap[i].file = &rec->data.dir.files[i]; + if (evlist->overwrite_mmap) + evlist->overwrite_mmap[i].file = &rec->data.dir.files[i]; + } + } + return 0; } @@ -1065,15 +1389,17 @@ static struct perf_event_header finished_round_event = { static void record__adjust_affinity(struct record *rec, struct mmap *map) { if (rec->opts.affinity != PERF_AFFINITY_SYS && - !bitmap_equal(rec->affinity_mask.bits, map->affinity_mask.bits, - rec->affinity_mask.nbits)) { - bitmap_zero(rec->affinity_mask.bits, rec->affinity_mask.nbits); - bitmap_or(rec->affinity_mask.bits, rec->affinity_mask.bits, - map->affinity_mask.bits, rec->affinity_mask.nbits); - sched_setaffinity(0, MMAP_CPU_MASK_BYTES(&rec->affinity_mask), - (cpu_set_t *)rec->affinity_mask.bits); - if (verbose == 2) - mmap_cpu_mask__scnprintf(&rec->affinity_mask, "thread"); + !bitmap_equal(thread->mask->affinity.bits, map->affinity_mask.bits, + thread->mask->affinity.nbits)) { + bitmap_zero(thread->mask->affinity.bits, thread->mask->affinity.nbits); + bitmap_or(thread->mask->affinity.bits, thread->mask->affinity.bits, + map->affinity_mask.bits, thread->mask->affinity.nbits); + sched_setaffinity(0, MMAP_CPU_MASK_BYTES(&thread->mask->affinity), + (cpu_set_t *)thread->mask->affinity.bits); + if (verbose == 2) { + pr_debug("threads[%d]: running on cpu%d: ", thread->tid, sched_getcpu()); + mmap_cpu_mask__scnprintf(&thread->mask->affinity, "affinity"); + } } } @@ -1093,17 +1419,26 @@ static size_t process_comp_header(void *record, size_t increment) return size; } -static size_t zstd_compress(struct perf_session *session, void *dst, size_t dst_size, - void *src, size_t src_size) +static size_t zstd_compress(struct perf_session *session, struct mmap *map, + void *dst, size_t dst_size, void *src, size_t src_size) { size_t compressed; size_t max_record_size = PERF_SAMPLE_MAX_SIZE - sizeof(struct perf_record_compressed) - 1; + struct zstd_data *zstd_data = &session->zstd_data; - compressed = zstd_compress_stream_to_records(&session->zstd_data, dst, dst_size, src, src_size, + if (map && map->file) + zstd_data = &map->zstd_data; + + compressed = zstd_compress_stream_to_records(zstd_data, dst, dst_size, src, src_size, max_record_size, process_comp_header); - session->bytes_transferred += src_size; - session->bytes_compressed += compressed; + if (map && map->file) { + thread->bytes_transferred += src_size; + thread->bytes_compressed += compressed; + } else { + session->bytes_transferred += src_size; + session->bytes_compressed += compressed; + } return compressed; } @@ -1114,14 +1449,17 @@ static int record__mmap_read_evlist(struct record *rec, struct evlist *evlist, u64 bytes_written = rec->bytes_written; int i; int rc = 0; - struct mmap *maps; + int nr_mmaps; + struct mmap **maps; int trace_fd = rec->data.file.fd; off_t off = 0; if (!evlist) return 0; - maps = overwrite ? evlist->overwrite_mmap : evlist->mmap; + nr_mmaps = thread->nr_mmaps; + maps = overwrite ? thread->overwrite_maps : thread->maps; + if (!maps) return 0; @@ -1131,9 +1469,9 @@ static int record__mmap_read_evlist(struct record *rec, struct evlist *evlist, if (record__aio_enabled(rec)) off = record__aio_get_pos(trace_fd); - for (i = 0; i < evlist->core.nr_mmaps; i++) { + for (i = 0; i < nr_mmaps; i++) { u64 flush = 0; - struct mmap *map = &maps[i]; + struct mmap *map = maps[i]; if (map->core.base) { record__adjust_affinity(rec, map); @@ -1175,8 +1513,12 @@ static int record__mmap_read_evlist(struct record *rec, struct evlist *evlist, /* * Mark the round finished in case we wrote * at least one event. + * + * No need for round events in directory mode, + * because per-cpu maps and files have data + * sorted by kernel. */ - if (bytes_written != rec->bytes_written) + if (!record__threads_enabled(rec) && bytes_written != rec->bytes_written) rc = record__write(rec, NULL, &finished_round_event, sizeof(finished_round_event)); if (overwrite) @@ -1196,6 +1538,77 @@ static int record__mmap_read_all(struct record *rec, bool synch) return record__mmap_read_evlist(rec, rec->evlist, true, synch); } +static void record__thread_munmap_filtered(struct fdarray *fda, int fd, + void *arg __maybe_unused) +{ + struct perf_mmap *map = fda->priv[fd].ptr; + + if (map) + perf_mmap__put(map); +} + +static void *record__thread(void *arg) +{ + enum thread_msg msg = THREAD_MSG__READY; + bool terminate = false; + struct fdarray *pollfd; + int err, ctlfd_pos; + + thread = arg; + thread->tid = gettid(); + + err = write(thread->pipes.ack[1], &msg, sizeof(msg)); + if (err == -1) + pr_warning("threads[%d]: failed to notify on start: %s\n", + thread->tid, strerror(errno)); + + pr_debug("threads[%d]: started on cpu%d\n", thread->tid, sched_getcpu()); + + pollfd = &thread->pollfd; + ctlfd_pos = thread->ctlfd_pos; + + for (;;) { + unsigned long long hits = thread->samples; + + if (record__mmap_read_all(thread->rec, false) < 0 || terminate) + break; + + if (hits == thread->samples) { + + err = fdarray__poll(pollfd, -1); + /* + * Propagate error, only if there's any. Ignore positive + * number of returned events and interrupt error. + */ + if (err > 0 || (err < 0 && errno == EINTR)) + err = 0; + thread->waking++; + + if (fdarray__filter(pollfd, POLLERR | POLLHUP, + record__thread_munmap_filtered, NULL) == 0) + break; + } + + if (pollfd->entries[ctlfd_pos].revents & POLLHUP) { + terminate = true; + close(thread->pipes.msg[0]); + thread->pipes.msg[0] = -1; + pollfd->entries[ctlfd_pos].fd = -1; + pollfd->entries[ctlfd_pos].events = 0; + } + + pollfd->entries[ctlfd_pos].revents = 0; + } + record__mmap_read_all(thread->rec, true); + + err = write(thread->pipes.ack[1], &msg, sizeof(msg)); + if (err == -1) + pr_warning("threads[%d]: failed to notify on termination: %s\n", + thread->tid, strerror(errno)); + + return NULL; +} + static void record__init_features(struct record *rec) { struct perf_session *session = rec->session; @@ -1222,7 +1635,9 @@ static void record__init_features(struct record *rec) if (!rec->opts.use_clockid) perf_header__clear_feat(&session->header, HEADER_CLOCK_DATA); - perf_header__clear_feat(&session->header, HEADER_DIR_FORMAT); + if (!record__threads_enabled(rec)) + perf_header__clear_feat(&session->header, HEADER_DIR_FORMAT); + if (!record__comp_enabled(rec)) perf_header__clear_feat(&session->header, HEADER_COMPRESSED); @@ -1232,6 +1647,7 @@ static void record__init_features(struct record *rec) static void record__finish_output(struct record *rec) { + int i; struct perf_data *data = &rec->data; int fd = perf_data__fd(data); @@ -1240,6 +1656,10 @@ record__finish_output(struct record *rec) rec->session->header.data_size += rec->bytes_written; data->file.size = lseek(perf_data__fd(data), 0, SEEK_CUR); + if (record__threads_enabled(rec)) { + for (i = 0; i < data->dir.nr; i++) + data->dir.files[i].size = lseek(data->dir.files[i].fd, 0, SEEK_CUR); + } if (!rec->no_buildid) { process_buildids(rec); @@ -1619,11 +2039,129 @@ static void record__uniquify_name(struct record *rec) } } +static int record__terminate_thread(struct record_thread *thread_data) +{ + int err; + enum thread_msg ack = THREAD_MSG__UNDEFINED; + pid_t tid = thread_data->tid; + + close(thread_data->pipes.msg[1]); + thread_data->pipes.msg[1] = -1; + err = read(thread_data->pipes.ack[0], &ack, sizeof(ack)); + if (err > 0) + pr_debug2("threads[%d]: sent %s\n", tid, thread_msg_tags[ack]); + else + pr_warning("threads[%d]: failed to receive termination notification from %d\n", + thread->tid, tid); + + return 0; +} + +static int record__start_threads(struct record *rec) +{ + int t, tt, err, ret = 0, nr_threads = rec->nr_threads; + struct record_thread *thread_data = rec->thread_data; + sigset_t full, mask; + pthread_t handle; + pthread_attr_t attrs; + + thread = &thread_data[0]; + + if (!record__threads_enabled(rec)) + return 0; + + sigfillset(&full); + if (sigprocmask(SIG_SETMASK, &full, &mask)) { + pr_err("Failed to block signals on threads start: %s\n", strerror(errno)); + return -1; + } + + pthread_attr_init(&attrs); + pthread_attr_setdetachstate(&attrs, PTHREAD_CREATE_DETACHED); + + for (t = 1; t < nr_threads; t++) { + enum thread_msg msg = THREAD_MSG__UNDEFINED; + +#ifdef HAVE_PTHREAD_ATTR_SETAFFINITY_NP + pthread_attr_setaffinity_np(&attrs, + MMAP_CPU_MASK_BYTES(&(thread_data[t].mask->affinity)), + (cpu_set_t *)(thread_data[t].mask->affinity.bits)); +#endif + if (pthread_create(&handle, &attrs, record__thread, &thread_data[t])) { + for (tt = 1; tt < t; tt++) + record__terminate_thread(&thread_data[t]); + pr_err("Failed to start threads: %s\n", strerror(errno)); + ret = -1; + goto out_err; + } + + err = read(thread_data[t].pipes.ack[0], &msg, sizeof(msg)); + if (err > 0) + pr_debug2("threads[%d]: sent %s\n", rec->thread_data[t].tid, + thread_msg_tags[msg]); + else + pr_warning("threads[%d]: failed to receive start notification from %d\n", + thread->tid, rec->thread_data[t].tid); + } + + sched_setaffinity(0, MMAP_CPU_MASK_BYTES(&thread->mask->affinity), + (cpu_set_t *)thread->mask->affinity.bits); + + pr_debug("threads[%d]: started on cpu%d\n", thread->tid, sched_getcpu()); + +out_err: + pthread_attr_destroy(&attrs); + + if (sigprocmask(SIG_SETMASK, &mask, NULL)) { + pr_err("Failed to unblock signals on threads start: %s\n", strerror(errno)); + ret = -1; + } + + return ret; +} + +static int record__stop_threads(struct record *rec) +{ + int t; + struct record_thread *thread_data = rec->thread_data; + + for (t = 1; t < rec->nr_threads; t++) + record__terminate_thread(&thread_data[t]); + + for (t = 0; t < rec->nr_threads; t++) { + rec->samples += thread_data[t].samples; + if (!record__threads_enabled(rec)) + continue; + rec->session->bytes_transferred += thread_data[t].bytes_transferred; + rec->session->bytes_compressed += thread_data[t].bytes_compressed; + pr_debug("threads[%d]: samples=%lld, wakes=%ld, ", thread_data[t].tid, + thread_data[t].samples, thread_data[t].waking); + if (thread_data[t].bytes_transferred && thread_data[t].bytes_compressed) + pr_debug("transferred=%" PRIu64 ", compressed=%" PRIu64 "\n", + thread_data[t].bytes_transferred, thread_data[t].bytes_compressed); + else + pr_debug("written=%" PRIu64 "\n", thread_data[t].bytes_written); + } + + return 0; +} + +static unsigned long record__waking(struct record *rec) +{ + int t; + unsigned long waking = 0; + struct record_thread *thread_data = rec->thread_data; + + for (t = 0; t < rec->nr_threads; t++) + waking += thread_data[t].waking; + + return waking; +} + static int __cmd_record(struct record *rec, int argc, const char **argv) { int err; int status = 0; - unsigned long waking = 0; const bool forks = argc > 0; struct perf_tool *tool = &rec->tool; struct record_opts *opts = &rec->opts; @@ -1668,6 +2206,17 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) return PTR_ERR(session); } + if (record__threads_enabled(rec)) { + if (perf_data__is_pipe(&rec->data)) { + pr_err("Parallel trace streaming is not available in pipe mode.\n"); + return -1; + } + if (rec->opts.full_auxtrace) { + pr_err("Parallel trace streaming is not available in AUX area tracing mode.\n"); + return -1; + } + } + fd = perf_data__fd(data); rec->session = session; @@ -1727,7 +2276,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) if (record__open(rec) != 0) { err = -1; - goto out_child; + goto out_free_threads; } session->header.env.comp_mmap_len = session->evlist->core.mmap_len; @@ -1735,7 +2284,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) err = record__kcore_copy(&session->machines.host, data); if (err) { pr_err("ERROR: Failed to copy kcore\n"); - goto out_child; + goto out_free_threads; } } @@ -1746,7 +2295,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) bpf__strerror_apply_obj_config(err, errbuf, sizeof(errbuf)); pr_err("ERROR: Apply config to BPF failed: %s\n", errbuf); - goto out_child; + goto out_free_threads; } /* @@ -1764,11 +2313,11 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) if (data->is_pipe) { err = perf_header__write_pipe(fd); if (err < 0) - goto out_child; + goto out_free_threads; } else { err = perf_session__write_header(session, rec->evlist, fd, false); if (err < 0) - goto out_child; + goto out_free_threads; } err = -1; @@ -1776,16 +2325,16 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) && !perf_header__has_feat(&session->header, HEADER_BUILD_ID)) { pr_err("Couldn't generate buildids. " "Use --no-buildid to profile anyway.\n"); - goto out_child; + goto out_free_threads; } err = record__setup_sb_evlist(rec); if (err) - goto out_child; + goto out_free_threads; err = record__synthesize(rec, false); if (err < 0) - goto out_child; + goto out_free_threads; if (rec->realtime_prio) { struct sched_param param; @@ -1794,10 +2343,13 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) if (sched_setscheduler(0, SCHED_FIFO, ¶m)) { pr_err("Could not set realtime priority.\n"); err = -1; - goto out_child; + goto out_free_threads; } } + if (record__start_threads(rec)) + goto out_free_threads; + /* * When perf is starting the traced process, all the events * (apart from group members) have enable_on_exec=1 set, @@ -1855,9 +2407,6 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) evlist__start_workload(rec->evlist); } - if (evlist__initialize_ctlfd(rec->evlist, opts->ctl_fd, opts->ctl_fd_ack)) - goto out_child; - if (opts->initial_delay) { pr_info(EVLIST_DISABLED_MSG); if (opts->initial_delay > 0) { @@ -1871,7 +2420,7 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) trigger_ready(&switch_output_trigger); perf_hooks__invoke_record_start(); for (;;) { - unsigned long long hits = rec->samples; + unsigned long long hits = thread->samples; /* * rec->evlist->bkw_mmap_state is possible to be @@ -1925,8 +2474,8 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) if (!quiet) fprintf(stderr, "[ perf record: dump data: Woken up %ld times ]\n", - waking); - waking = 0; + record__waking(rec)); + thread->waking = 0; fd = record__switch_output(rec, false); if (fd < 0) { pr_err("Failed to switch to new file\n"); @@ -1940,20 +2489,24 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) alarm(rec->switch_output.time); } - if (hits == rec->samples) { + if (hits == thread->samples) { if (done || draining) break; - err = evlist__poll(rec->evlist, -1); + err = fdarray__poll(&thread->pollfd, -1); /* * Propagate error, only if there's any. Ignore positive * number of returned events and interrupt error. */ if (err > 0 || (err < 0 && errno == EINTR)) err = 0; - waking++; + thread->waking++; - if (evlist__filter_pollfd(rec->evlist, POLLERR | POLLHUP) == 0) + if (fdarray__filter(&thread->pollfd, POLLERR | POLLHUP, + record__thread_munmap_filtered, NULL) == 0) draining = true; + + evlist__ctlfd_update(rec->evlist, + &thread->pollfd.entries[thread->ctlfd_pos]); } if (evlist__ctlfd_process(rec->evlist, &cmd) > 0) { @@ -2007,14 +2560,18 @@ static int __cmd_record(struct record *rec, int argc, const char **argv) } if (!quiet) - fprintf(stderr, "[ perf record: Woken up %ld times to write data ]\n", waking); + fprintf(stderr, "[ perf record: Woken up %ld times to write data ]\n", + record__waking(rec)); if (target__none(&rec->opts.target)) record__synthesize_workload(rec, true); out_child: - evlist__finalize_ctlfd(rec->evlist); + record__stop_threads(rec); record__mmap_read_all(rec, true); +out_free_threads: + record__free_thread_data(rec); + evlist__finalize_ctlfd(rec->evlist); record__aio_mmap_read_sync(rec); if (rec->session->bytes_transferred && rec->session->bytes_compressed) { @@ -2204,6 +2761,78 @@ static int record__parse_affinity(const struct option *opt, const char *str, int return 0; } +static int record__mmap_cpu_mask_alloc(struct mmap_cpu_mask *mask, int nr_bits) +{ + mask->nbits = nr_bits; + mask->bits = bitmap_zalloc(mask->nbits); + if (!mask->bits) + return -ENOMEM; + + return 0; +} + +static void record__mmap_cpu_mask_free(struct mmap_cpu_mask *mask) +{ + bitmap_free(mask->bits); + mask->nbits = 0; +} + +static int record__thread_mask_alloc(struct thread_mask *mask, int nr_bits) +{ + int ret; + + ret = record__mmap_cpu_mask_alloc(&mask->maps, nr_bits); + if (ret) { + mask->affinity.bits = NULL; + return ret; + } + + ret = record__mmap_cpu_mask_alloc(&mask->affinity, nr_bits); + if (ret) { + record__mmap_cpu_mask_free(&mask->maps); + mask->maps.bits = NULL; + } + + return ret; +} + +static void record__thread_mask_free(struct thread_mask *mask) +{ + record__mmap_cpu_mask_free(&mask->maps); + record__mmap_cpu_mask_free(&mask->affinity); +} + +static int record__parse_threads(const struct option *opt, const char *str, int unset) +{ + int s; + struct record_opts *opts = opt->value; + + if (unset || !str || !strlen(str)) { + opts->threads_spec = THREAD_SPEC__CPU; + } else { + for (s = 1; s < THREAD_SPEC__MAX; s++) { + if (s == THREAD_SPEC__USER) { + opts->threads_user_spec = strdup(str); + if (!opts->threads_user_spec) + return -ENOMEM; + opts->threads_spec = THREAD_SPEC__USER; + break; + } + if (!strncasecmp(str, thread_spec_tags[s], strlen(thread_spec_tags[s]))) { + opts->threads_spec = s; + break; + } + } + } + + if (opts->threads_spec == THREAD_SPEC__USER) + pr_debug("threads_spec: %s\n", opts->threads_user_spec); + else + pr_debug("threads_spec: %s\n", thread_spec_tags[opts->threads_spec]); + + return 0; +} + static int parse_output_max_size(const struct option *opt, const char *str, int unset) { @@ -2328,12 +2957,22 @@ static int switch_output_setup(struct record *rec) * --switch-output=signal, as we'll send a SIGUSR2 from the side band * thread to its parent. */ - if (rec->switch_output_event_set) + if (rec->switch_output_event_set) { + if (record__threads_enabled(rec)) { + pr_warning("WARNING: --switch-output-event option is not available in parallel streaming mode.\n"); + return 0; + } goto do_signal; + } if (!s->set) return 0; + if (record__threads_enabled(rec)) { + pr_warning("WARNING: --switch-output option is not available in parallel streaming mode.\n"); + return 0; + } + if (!strcmp(s->str, "signal")) { do_signal: s->signal = true; @@ -2652,8 +3291,8 @@ static struct option __record_options[] = { "Set affinity mask of trace reading thread to NUMA node cpu mask or cpu of processed mmap buffer", record__parse_affinity), #ifdef HAVE_ZSTD_SUPPORT - OPT_CALLBACK_OPTARG('z', "compression-level", &record.opts, &comp_level_default, - "n", "Compressed records using specified level (default: 1 - fastest compression, 22 - greatest compression)", + OPT_CALLBACK_OPTARG('z', "compression-level", &record.opts, &comp_level_default, "n", + "Compress records using specified level (default: 1 - fastest compression, 22 - greatest compression)", record__parse_comp_level), #endif OPT_CALLBACK(0, "max-size", &record.output_max_size, @@ -2678,11 +3317,392 @@ static struct option __record_options[] = { &record.debuginfod.set, "debuginfod urls", "Enable debuginfod data retrieval from DEBUGINFOD_URLS or specified urls", "system"), + OPT_CALLBACK_OPTARG(0, "threads", &record.opts, NULL, "spec", + "write collected trace data into several data files using parallel threads", + record__parse_threads), OPT_END() }; struct option *record_options = __record_options; +static void record__mmap_cpu_mask_init(struct mmap_cpu_mask *mask, struct perf_cpu_map *cpus) +{ + int c; + + for (c = 0; c < cpus->nr; c++) + set_bit(cpus->map[c].cpu, mask->bits); +} + +static int record__mmap_cpu_mask_init_spec(struct mmap_cpu_mask *mask, const char *mask_spec) +{ + struct perf_cpu_map *cpus; + + cpus = perf_cpu_map__new(mask_spec); + if (!cpus) + return -ENOMEM; + + bitmap_zero(mask->bits, mask->nbits); + record__mmap_cpu_mask_init(mask, cpus); + perf_cpu_map__put(cpus); + + return 0; +} + +static void record__free_thread_masks(struct record *rec, int nr_threads) +{ + int t; + + if (rec->thread_masks) + for (t = 0; t < nr_threads; t++) + record__thread_mask_free(&rec->thread_masks[t]); + + zfree(&rec->thread_masks); +} + +static int record__alloc_thread_masks(struct record *rec, int nr_threads, int nr_bits) +{ + int t, ret; + + rec->thread_masks = zalloc(nr_threads * sizeof(*(rec->thread_masks))); + if (!rec->thread_masks) { + pr_err("Failed to allocate thread masks\n"); + return -ENOMEM; + } + + for (t = 0; t < nr_threads; t++) { + ret = record__thread_mask_alloc(&rec->thread_masks[t], nr_bits); + if (ret) { + pr_err("Failed to allocate thread masks[%d]\n", t); + goto out_free; + } + } + + return 0; + +out_free: + record__free_thread_masks(rec, nr_threads); + + return ret; +} + +static int record__init_thread_cpu_masks(struct record *rec, struct perf_cpu_map *cpus) +{ + int t, ret, nr_cpus = perf_cpu_map__nr(cpus); + + ret = record__alloc_thread_masks(rec, nr_cpus, cpu__max_cpu().cpu); + if (ret) + return ret; + + rec->nr_threads = nr_cpus; + pr_debug("nr_threads: %d\n", rec->nr_threads); + + for (t = 0; t < rec->nr_threads; t++) { + set_bit(cpus->map[t].cpu, rec->thread_masks[t].maps.bits); + set_bit(cpus->map[t].cpu, rec->thread_masks[t].affinity.bits); + if (verbose) { + pr_debug("thread_masks[%d]: ", t); + mmap_cpu_mask__scnprintf(&rec->thread_masks[t].maps, "maps"); + pr_debug("thread_masks[%d]: ", t); + mmap_cpu_mask__scnprintf(&rec->thread_masks[t].affinity, "affinity"); + } + } + + return 0; +} + +static int record__init_thread_masks_spec(struct record *rec, struct perf_cpu_map *cpus, + const char **maps_spec, const char **affinity_spec, + u32 nr_spec) +{ + u32 s; + int ret = 0, t = 0; + struct mmap_cpu_mask cpus_mask; + struct thread_mask thread_mask, full_mask, *thread_masks; + + ret = record__mmap_cpu_mask_alloc(&cpus_mask, cpu__max_cpu().cpu); + if (ret) { + pr_err("Failed to allocate CPUs mask\n"); + return ret; + } + record__mmap_cpu_mask_init(&cpus_mask, cpus); + + ret = record__thread_mask_alloc(&full_mask, cpu__max_cpu().cpu); + if (ret) { + pr_err("Failed to allocate full mask\n"); + goto out_free_cpu_mask; + } + + ret = record__thread_mask_alloc(&thread_mask, cpu__max_cpu().cpu); + if (ret) { + pr_err("Failed to allocate thread mask\n"); + goto out_free_full_and_cpu_masks; + } + + for (s = 0; s < nr_spec; s++) { + ret = record__mmap_cpu_mask_init_spec(&thread_mask.maps, maps_spec[s]); + if (ret) { + pr_err("Failed to initialize maps thread mask\n"); + goto out_free; + } + ret = record__mmap_cpu_mask_init_spec(&thread_mask.affinity, affinity_spec[s]); + if (ret) { + pr_err("Failed to initialize affinity thread mask\n"); + goto out_free; + } + + /* ignore invalid CPUs but do not allow empty masks */ + if (!bitmap_and(thread_mask.maps.bits, thread_mask.maps.bits, + cpus_mask.bits, thread_mask.maps.nbits)) { + pr_err("Empty maps mask: %s\n", maps_spec[s]); + ret = -EINVAL; + goto out_free; + } + if (!bitmap_and(thread_mask.affinity.bits, thread_mask.affinity.bits, + cpus_mask.bits, thread_mask.affinity.nbits)) { + pr_err("Empty affinity mask: %s\n", affinity_spec[s]); + ret = -EINVAL; + goto out_free; + } + + /* do not allow intersection with other masks (full_mask) */ + if (bitmap_intersects(thread_mask.maps.bits, full_mask.maps.bits, + thread_mask.maps.nbits)) { + pr_err("Intersecting maps mask: %s\n", maps_spec[s]); + ret = -EINVAL; + goto out_free; + } + if (bitmap_intersects(thread_mask.affinity.bits, full_mask.affinity.bits, + thread_mask.affinity.nbits)) { + pr_err("Intersecting affinity mask: %s\n", affinity_spec[s]); + ret = -EINVAL; + goto out_free; + } + + bitmap_or(full_mask.maps.bits, full_mask.maps.bits, + thread_mask.maps.bits, full_mask.maps.nbits); + bitmap_or(full_mask.affinity.bits, full_mask.affinity.bits, + thread_mask.affinity.bits, full_mask.maps.nbits); + + thread_masks = realloc(rec->thread_masks, (t + 1) * sizeof(struct thread_mask)); + if (!thread_masks) { + pr_err("Failed to reallocate thread masks\n"); + ret = -ENOMEM; + goto out_free; + } + rec->thread_masks = thread_masks; + rec->thread_masks[t] = thread_mask; + if (verbose) { + pr_debug("thread_masks[%d]: ", t); + mmap_cpu_mask__scnprintf(&rec->thread_masks[t].maps, "maps"); + pr_debug("thread_masks[%d]: ", t); + mmap_cpu_mask__scnprintf(&rec->thread_masks[t].affinity, "affinity"); + } + t++; + ret = record__thread_mask_alloc(&thread_mask, cpu__max_cpu().cpu); + if (ret) { + pr_err("Failed to allocate thread mask\n"); + goto out_free_full_and_cpu_masks; + } + } + rec->nr_threads = t; + pr_debug("nr_threads: %d\n", rec->nr_threads); + if (!rec->nr_threads) + ret = -EINVAL; + +out_free: + record__thread_mask_free(&thread_mask); +out_free_full_and_cpu_masks: + record__thread_mask_free(&full_mask); +out_free_cpu_mask: + record__mmap_cpu_mask_free(&cpus_mask); + + return ret; +} + +static int record__init_thread_core_masks(struct record *rec, struct perf_cpu_map *cpus) +{ + int ret; + struct cpu_topology *topo; + + topo = cpu_topology__new(); + if (!topo) { + pr_err("Failed to allocate CPU topology\n"); + return -ENOMEM; + } + + ret = record__init_thread_masks_spec(rec, cpus, topo->core_cpus_list, + topo->core_cpus_list, topo->core_cpus_lists); + cpu_topology__delete(topo); + + return ret; +} + +static int record__init_thread_package_masks(struct record *rec, struct perf_cpu_map *cpus) +{ + int ret; + struct cpu_topology *topo; + + topo = cpu_topology__new(); + if (!topo) { + pr_err("Failed to allocate CPU topology\n"); + return -ENOMEM; + } + + ret = record__init_thread_masks_spec(rec, cpus, topo->package_cpus_list, + topo->package_cpus_list, topo->package_cpus_lists); + cpu_topology__delete(topo); + + return ret; +} + +static int record__init_thread_numa_masks(struct record *rec, struct perf_cpu_map *cpus) +{ + u32 s; + int ret; + const char **spec; + struct numa_topology *topo; + + topo = numa_topology__new(); + if (!topo) { + pr_err("Failed to allocate NUMA topology\n"); + return -ENOMEM; + } + + spec = zalloc(topo->nr * sizeof(char *)); + if (!spec) { + pr_err("Failed to allocate NUMA spec\n"); + ret = -ENOMEM; + goto out_delete_topo; + } + for (s = 0; s < topo->nr; s++) + spec[s] = topo->nodes[s].cpus; + + ret = record__init_thread_masks_spec(rec, cpus, spec, spec, topo->nr); + + zfree(&spec); + +out_delete_topo: + numa_topology__delete(topo); + + return ret; +} + +static int record__init_thread_user_masks(struct record *rec, struct perf_cpu_map *cpus) +{ + int t, ret; + u32 s, nr_spec = 0; + char **maps_spec = NULL, **affinity_spec = NULL, **tmp_spec; + char *user_spec, *spec, *spec_ptr, *mask, *mask_ptr, *dup_mask = NULL; + + for (t = 0, user_spec = (char *)rec->opts.threads_user_spec; ; t++, user_spec = NULL) { + spec = strtok_r(user_spec, ":", &spec_ptr); + if (spec == NULL) + break; + pr_debug2("threads_spec[%d]: %s\n", t, spec); + mask = strtok_r(spec, "/", &mask_ptr); + if (mask == NULL) + break; + pr_debug2(" maps mask: %s\n", mask); + tmp_spec = realloc(maps_spec, (nr_spec + 1) * sizeof(char *)); + if (!tmp_spec) { + pr_err("Failed to reallocate maps spec\n"); + ret = -ENOMEM; + goto out_free; + } + maps_spec = tmp_spec; + maps_spec[nr_spec] = dup_mask = strdup(mask); + if (!maps_spec[nr_spec]) { + pr_err("Failed to allocate maps spec[%d]\n", nr_spec); + ret = -ENOMEM; + goto out_free; + } + mask = strtok_r(NULL, "/", &mask_ptr); + if (mask == NULL) { + pr_err("Invalid thread maps or affinity specs\n"); + ret = -EINVAL; + goto out_free; + } + pr_debug2(" affinity mask: %s\n", mask); + tmp_spec = realloc(affinity_spec, (nr_spec + 1) * sizeof(char *)); + if (!tmp_spec) { + pr_err("Failed to reallocate affinity spec\n"); + ret = -ENOMEM; + goto out_free; + } + affinity_spec = tmp_spec; + affinity_spec[nr_spec] = strdup(mask); + if (!affinity_spec[nr_spec]) { + pr_err("Failed to allocate affinity spec[%d]\n", nr_spec); + ret = -ENOMEM; + goto out_free; + } + dup_mask = NULL; + nr_spec++; + } + + ret = record__init_thread_masks_spec(rec, cpus, (const char **)maps_spec, + (const char **)affinity_spec, nr_spec); + +out_free: + free(dup_mask); + for (s = 0; s < nr_spec; s++) { + if (maps_spec) + free(maps_spec[s]); + if (affinity_spec) + free(affinity_spec[s]); + } + free(affinity_spec); + free(maps_spec); + + return ret; +} + +static int record__init_thread_default_masks(struct record *rec, struct perf_cpu_map *cpus) +{ + int ret; + + ret = record__alloc_thread_masks(rec, 1, cpu__max_cpu().cpu); + if (ret) + return ret; + + record__mmap_cpu_mask_init(&rec->thread_masks->maps, cpus); + + rec->nr_threads = 1; + + return 0; +} + +static int record__init_thread_masks(struct record *rec) +{ + int ret = 0; + struct perf_cpu_map *cpus = rec->evlist->core.cpus; + + if (!record__threads_enabled(rec)) + return record__init_thread_default_masks(rec, cpus); + + switch (rec->opts.threads_spec) { + case THREAD_SPEC__CPU: + ret = record__init_thread_cpu_masks(rec, cpus); + break; + case THREAD_SPEC__CORE: + ret = record__init_thread_core_masks(rec, cpus); + break; + case THREAD_SPEC__PACKAGE: + ret = record__init_thread_package_masks(rec, cpus); + break; + case THREAD_SPEC__NUMA: + ret = record__init_thread_numa_masks(rec, cpus); + break; + case THREAD_SPEC__USER: + ret = record__init_thread_user_masks(rec, cpus); + break; + default: + break; + } + + return ret; +} + int cmd_record(int argc, const char **argv) { int err; @@ -2764,9 +3784,20 @@ int cmd_record(int argc, const char **argv) goto out_opts; } - if (rec->opts.kcore) + if (rec->opts.kcore || record__threads_enabled(rec)) rec->data.is_dir = true; + if (record__threads_enabled(rec)) { + if (rec->opts.affinity != PERF_AFFINITY_SYS) { + pr_err("--affinity option is mutually exclusive to parallel streaming mode.\n"); + goto out_opts; + } + if (record__aio_enabled(rec)) { + pr_err("Asynchronous streaming mode (--aio) is mutually exclusive to parallel streaming mode.\n"); + goto out_opts; + } + } + if (rec->opts.comp_level != 0) { pr_debug("Compression enabled, disabling build id collection at the end of the session.\n"); rec->no_buildid = true; @@ -2800,6 +3831,11 @@ int cmd_record(int argc, const char **argv) } } + if (rec->timestamp_filename && record__threads_enabled(rec)) { + rec->timestamp_filename = false; + pr_warning("WARNING: --timestamp-filename option is not available in parallel streaming mode.\n"); + } + /* * Allow aliases to facilitate the lookup of symbols for address * filters. Refer to auxtrace_parse_filters(). @@ -2808,17 +3844,6 @@ int cmd_record(int argc, const char **argv) symbol__init(NULL); - if (rec->opts.affinity != PERF_AFFINITY_SYS) { - rec->affinity_mask.nbits = cpu__max_cpu().cpu; - rec->affinity_mask.bits = bitmap_zalloc(rec->affinity_mask.nbits); - if (!rec->affinity_mask.bits) { - pr_err("Failed to allocate thread mask for %zd cpus\n", rec->affinity_mask.nbits); - err = -ENOMEM; - goto out_opts; - } - pr_debug2("thread mask[%zd]: empty\n", rec->affinity_mask.nbits); - } - err = record__auxtrace_init(rec); if (err) goto out; @@ -2948,6 +3973,12 @@ int cmd_record(int argc, const char **argv) goto out; } + err = record__init_thread_masks(rec); + if (err) { + pr_err("Failed to initialize parallel data streaming masks\n"); + goto out; + } + if (rec->opts.nr_cblocks > nr_cblocks_max) rec->opts.nr_cblocks = nr_cblocks_max; pr_debug("nr_cblocks: %d\n", rec->opts.nr_cblocks); @@ -2961,11 +3992,12 @@ int cmd_record(int argc, const char **argv) err = __cmd_record(&record, argc, argv); out: - bitmap_free(rec->affinity_mask.bits); evlist__delete(rec->evlist); symbol__exit(); auxtrace_record__free(rec->itr); out_opts: + record__free_thread_masks(rec, rec->nr_threads); + rec->nr_threads = 0; evlist__close_control(rec->opts.ctl_fd, rec->opts.ctl_fd_ack, &rec->opts.ctl_fd_close); return err; } diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 1dd92d8c9279..1ad75c7ba074 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -71,7 +71,11 @@ struct report { struct perf_tool tool; struct perf_session *session; struct evswitch evswitch; - bool use_tui, use_gtk, use_stdio; +#ifdef HAVE_SLANG_SUPPORT + bool use_tui; +#endif + bool use_gtk; + bool use_stdio; bool show_full_info; bool show_threads; bool inverted_callchain; @@ -1206,7 +1210,9 @@ int cmd_report(int argc, const char **argv) "Show per-thread event counters"), OPT_STRING(0, "pretty", &report.pretty_printing_style, "key", "pretty printing style key: normal raw"), +#ifdef HAVE_SLANG_SUPPORT OPT_BOOLEAN(0, "tui", &report.use_tui, "Use the TUI interface"), +#endif OPT_BOOLEAN(0, "gtk", &report.use_gtk, "Use the GTK2 interface"), OPT_BOOLEAN(0, "stdio", &report.use_stdio, "Use the stdio interface"), @@ -1492,8 +1498,10 @@ repeat: if (report.use_stdio) use_browser = 0; +#ifdef HAVE_SLANG_SUPPORT else if (report.use_tui) use_browser = 1; +#endif else if (report.use_gtk) use_browser = 2; diff --git a/tools/perf/builtin-sched.c b/tools/perf/builtin-sched.c index 72d446de9c60..646bd938927a 100644 --- a/tools/perf/builtin-sched.c +++ b/tools/perf/builtin-sched.c @@ -3561,7 +3561,7 @@ int cmd_sched(int argc, const char **argv) if (!strcmp(argv[0], "script")) return cmd_script(argc, argv); - if (!strncmp(argv[0], "rec", 3)) { + if (strlen(argv[0]) > 2 && strstarts("record", argv[0])) { return __cmd_record(argc, argv); } else if (!strncmp(argv[0], "lat", 3)) { sched.tp_handler = &lat_ops; @@ -3581,7 +3581,7 @@ int cmd_sched(int argc, const char **argv) sched.tp_handler = &map_ops; setup_sorting(&sched, latency_options, latency_usage); return perf_sched__map(&sched); - } else if (!strncmp(argv[0], "rep", 3)) { + } else if (strlen(argv[0]) > 2 && strstarts("replay", argv[0])) { sched.tp_handler = &replay_ops; if (argc) { argc = parse_options(argc, argv, replay_options, replay_usage, 0); diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index fa478ddcd18a..a2f117936188 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -124,6 +124,7 @@ enum perf_output_field { PERF_OUTPUT_DATA_PAGE_SIZE = 1ULL << 33, PERF_OUTPUT_CODE_PAGE_SIZE = 1ULL << 34, PERF_OUTPUT_INS_LAT = 1ULL << 35, + PERF_OUTPUT_BRSTACKINSNLEN = 1ULL << 36, }; struct perf_script { @@ -191,6 +192,7 @@ struct output_option { {.str = "data_page_size", .field = PERF_OUTPUT_DATA_PAGE_SIZE}, {.str = "code_page_size", .field = PERF_OUTPUT_CODE_PAGE_SIZE}, {.str = "ins_lat", .field = PERF_OUTPUT_INS_LAT}, + {.str = "brstackinsnlen", .field = PERF_OUTPUT_BRSTACKINSNLEN}, }; enum { @@ -488,7 +490,7 @@ static int evsel__check_attr(struct evsel *evsel, struct perf_session *session) "selected. Hence, no address to lookup the source line number.\n"); return -EINVAL; } - if (PRINT_FIELD(BRSTACKINSN) && !allow_user_set && + if ((PRINT_FIELD(BRSTACKINSN) || PRINT_FIELD(BRSTACKINSNLEN)) && !allow_user_set && !(evlist__combined_branch_type(session->evlist) & PERF_SAMPLE_BRANCH_ANY)) { pr_err("Display of branch stack assembler requested, but non all-branch filter set\n" "Hint: run 'perf record -b ...'\n"); @@ -857,6 +859,16 @@ mispred_str(struct branch_entry *br) return br->flags.predicted ? 'P' : 'M'; } +static int print_bstack_flags(FILE *fp, struct branch_entry *br) +{ + return fprintf(fp, "/%c/%c/%c/%d/%s ", + mispred_str(br), + br->flags.in_tx ? 'X' : '-', + br->flags.abort ? 'A' : '-', + br->flags.cycles, + br->flags.type ? branch_type_name(br->flags.type) : "-"); +} + static int perf_sample__fprintf_brstack(struct perf_sample *sample, struct thread *thread, struct perf_event_attr *attr, FILE *fp) @@ -895,11 +907,7 @@ static int perf_sample__fprintf_brstack(struct perf_sample *sample, printed += fprintf(fp, ")"); } - printed += fprintf(fp, "/%c/%c/%c/%d ", - mispred_str(entries + i), - entries[i].flags.in_tx ? 'X' : '-', - entries[i].flags.abort ? 'A' : '-', - entries[i].flags.cycles); + printed += print_bstack_flags(fp, entries + i); } return printed; @@ -941,11 +949,7 @@ static int perf_sample__fprintf_brstacksym(struct perf_sample *sample, printed += map__fprintf_dsoname(alt.map, fp); printed += fprintf(fp, ")"); } - printed += fprintf(fp, "/%c/%c/%c/%d ", - mispred_str(entries + i), - entries[i].flags.in_tx ? 'X' : '-', - entries[i].flags.abort ? 'A' : '-', - entries[i].flags.cycles); + printed += print_bstack_flags(fp, entries + i); } return printed; @@ -991,11 +995,7 @@ static int perf_sample__fprintf_brstackoff(struct perf_sample *sample, printed += map__fprintf_dsoname(alt.map, fp); printed += fprintf(fp, ")"); } - printed += fprintf(fp, "/%c/%c/%c/%d ", - mispred_str(entries + i), - entries[i].flags.in_tx ? 'X' : '-', - entries[i].flags.abort ? 'A' : '-', - entries[i].flags.cycles); + printed += print_bstack_flags(fp, entries + i); } return printed; @@ -1122,10 +1122,17 @@ static int print_srccode(struct thread *thread, u8 cpumode, uint64_t addr) static int ip__fprintf_jump(uint64_t ip, struct branch_entry *en, struct perf_insn *x, u8 *inbuf, int len, - int insn, FILE *fp, int *total_cycles) + int insn, FILE *fp, int *total_cycles, + struct perf_event_attr *attr) { - int printed = fprintf(fp, "\t%016" PRIx64 "\t%-30s\t#%s%s%s%s", ip, - dump_insn(x, ip, inbuf, len, NULL), + int ilen = 0; + int printed = fprintf(fp, "\t%016" PRIx64 "\t%-30s\t", ip, + dump_insn(x, ip, inbuf, len, &ilen)); + + if (PRINT_FIELD(BRSTACKINSNLEN)) + printed += fprintf(fp, "ilen: %d\t", ilen); + + printed += fprintf(fp, "#%s%s%s%s", en->flags.predicted ? " PRED" : "", en->flags.mispred ? " MISPRED" : "", en->flags.in_tx ? " INTX" : "", @@ -1211,7 +1218,8 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample, printed += ip__fprintf_sym(entries[nr - 1].from, thread, x.cpumode, x.cpu, &lastsym, attr, fp); printed += ip__fprintf_jump(entries[nr - 1].from, &entries[nr - 1], - &x, buffer, len, 0, fp, &total_cycles); + &x, buffer, len, 0, fp, &total_cycles, + attr); if (PRINT_FIELD(SRCCODE)) printed += print_srccode(thread, x.cpumode, entries[nr - 1].from); } @@ -1242,14 +1250,17 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample, printed += ip__fprintf_sym(ip, thread, x.cpumode, x.cpu, &lastsym, attr, fp); if (ip == end) { printed += ip__fprintf_jump(ip, &entries[i], &x, buffer + off, len - off, ++insn, fp, - &total_cycles); + &total_cycles, attr); if (PRINT_FIELD(SRCCODE)) printed += print_srccode(thread, x.cpumode, ip); break; } else { ilen = 0; - printed += fprintf(fp, "\t%016" PRIx64 "\t%s\n", ip, + printed += fprintf(fp, "\t%016" PRIx64 "\t%s", ip, dump_insn(&x, ip, buffer + off, len - off, &ilen)); + if (PRINT_FIELD(BRSTACKINSNLEN)) + printed += fprintf(fp, "\tilen: %d", ilen); + printed += fprintf(fp, "\n"); if (ilen == 0) break; if (PRINT_FIELD(SRCCODE)) @@ -1292,16 +1303,23 @@ static int perf_sample__fprintf_brstackinsn(struct perf_sample *sample, machine, thread, &x.is64bit, &x.cpumode, false); if (len <= 0) goto out; - printed += fprintf(fp, "\t%016" PRIx64 "\t%s\n", sample->ip, - dump_insn(&x, sample->ip, buffer, len, NULL)); + ilen = 0; + printed += fprintf(fp, "\t%016" PRIx64 "\t%s", sample->ip, + dump_insn(&x, sample->ip, buffer, len, &ilen)); + if (PRINT_FIELD(BRSTACKINSNLEN)) + printed += fprintf(fp, "\tilen: %d", ilen); + printed += fprintf(fp, "\n"); if (PRINT_FIELD(SRCCODE)) print_srccode(thread, x.cpumode, sample->ip); goto out; } for (off = 0; off <= end - start; off += ilen) { ilen = 0; - printed += fprintf(fp, "\t%016" PRIx64 "\t%s\n", start + off, + printed += fprintf(fp, "\t%016" PRIx64 "\t%s", start + off, dump_insn(&x, start + off, buffer + off, len - off, &ilen)); + if (PRINT_FIELD(BRSTACKINSNLEN)) + printed += fprintf(fp, "\tilen: %d", ilen); + printed += fprintf(fp, "\n"); if (ilen == 0) break; if (arch_is_branch(buffer + off, len - off, x.is64bit) && start + off != sample->ip) { @@ -1459,7 +1477,7 @@ static int perf_sample__fprintf_insn(struct perf_sample *sample, for (i = 0; i < sample->insn_len; i++) printed += fprintf(fp, " %02x", (unsigned char)sample->insn[i]); } - if (PRINT_FIELD(BRSTACKINSN)) + if (PRINT_FIELD(BRSTACKINSN) || PRINT_FIELD(BRSTACKINSNLEN)) printed += perf_sample__fprintf_brstackinsn(sample, thread, attr, machine, fp); return printed; @@ -1579,26 +1597,34 @@ static const char *sample_flags_to_name(u32 flags) int perf_sample__sprintf_flags(u32 flags, char *str, size_t sz) { + u32 xf = PERF_IP_FLAG_IN_TX | PERF_IP_FLAG_INTR_DISABLE | + PERF_IP_FLAG_INTR_TOGGLE; const char *chars = PERF_IP_FLAG_CHARS; const size_t n = strlen(PERF_IP_FLAG_CHARS); - bool in_tx = flags & PERF_IP_FLAG_IN_TX; const char *name = NULL; size_t i, pos = 0; + char xs[16] = {0}; - name = sample_flags_to_name(flags & ~PERF_IP_FLAG_IN_TX); + if (flags & xf) + snprintf(xs, sizeof(xs), "(%s%s%s)", + flags & PERF_IP_FLAG_IN_TX ? "x" : "", + flags & PERF_IP_FLAG_INTR_DISABLE ? "D" : "", + flags & PERF_IP_FLAG_INTR_TOGGLE ? "t" : ""); + + name = sample_flags_to_name(flags & ~xf); if (name) - return snprintf(str, sz, "%-15s%4s", name, in_tx ? "(x)" : ""); + return snprintf(str, sz, "%-15s%6s", name, xs); if (flags & PERF_IP_FLAG_TRACE_BEGIN) { - name = sample_flags_to_name(flags & ~(PERF_IP_FLAG_IN_TX | PERF_IP_FLAG_TRACE_BEGIN)); + name = sample_flags_to_name(flags & ~(xf | PERF_IP_FLAG_TRACE_BEGIN)); if (name) - return snprintf(str, sz, "tr strt %-7s%4s", name, in_tx ? "(x)" : ""); + return snprintf(str, sz, "tr strt %-7s%6s", name, xs); } if (flags & PERF_IP_FLAG_TRACE_END) { - name = sample_flags_to_name(flags & ~(PERF_IP_FLAG_IN_TX | PERF_IP_FLAG_TRACE_END)); + name = sample_flags_to_name(flags & ~(xf | PERF_IP_FLAG_TRACE_END)); if (name) - return snprintf(str, sz, "tr end %-7s%4s", name, in_tx ? "(x)" : ""); + return snprintf(str, sz, "tr end %-7s%6s", name, xs); } for (i = 0; i < n; i++, flags >>= 1) { @@ -1620,7 +1646,7 @@ static int perf_sample__fprintf_flags(u32 flags, FILE *fp) char str[SAMPLE_FLAGS_BUF_SIZE]; perf_sample__sprintf_flags(flags, str, sizeof(str)); - return fprintf(fp, " %-19s ", str); + return fprintf(fp, " %-21s ", str); } struct printer_data { @@ -1811,6 +1837,56 @@ static int perf_sample__fprintf_synth_psb(struct perf_sample *sample, FILE *fp) return len + perf_sample__fprintf_pt_spacing(len, fp); } +/* Intel PT Event Trace */ +static int perf_sample__fprintf_synth_evt(struct perf_sample *sample, FILE *fp) +{ + struct perf_synth_intel_evt *data = perf_sample__synth_ptr(sample); + const char *cfe[32] = {NULL, "INTR", "IRET", "SMI", "RSM", "SIPI", + "INIT", "VMENTRY", "VMEXIT", "VMEXIT_INTR", + "SHUTDOWN"}; + const char *evd[64] = {"PFA", "VMXQ", "VMXR"}; + const char *s; + int len, i; + + if (perf_sample__bad_synth_size(sample, *data)) + return 0; + + s = cfe[data->type]; + if (s) { + len = fprintf(fp, " cfe: %s IP: %d vector: %u", + s, data->ip, data->vector); + } else { + len = fprintf(fp, " cfe: %u IP: %d vector: %u", + data->type, data->ip, data->vector); + } + for (i = 0; i < data->evd_cnt; i++) { + unsigned int et = data->evd[i].evd_type & 0x3f; + + s = evd[et]; + if (s) { + len += fprintf(fp, " %s: %#" PRIx64, + s, data->evd[i].payload); + } else { + len += fprintf(fp, " EVD_%u: %#" PRIx64, + et, data->evd[i].payload); + } + } + return len + perf_sample__fprintf_pt_spacing(len, fp); +} + +static int perf_sample__fprintf_synth_iflag_chg(struct perf_sample *sample, FILE *fp) +{ + struct perf_synth_intel_iflag_chg *data = perf_sample__synth_ptr(sample); + int len; + + if (perf_sample__bad_synth_size(sample, *data)) + return 0; + + len = fprintf(fp, " IFLAG: %d->%d %s branch", !data->iflag, data->iflag, + data->via_branch ? "via" : "non"); + return len + perf_sample__fprintf_pt_spacing(len, fp); +} + static int perf_sample__fprintf_synth(struct perf_sample *sample, struct evsel *evsel, FILE *fp) { @@ -1829,6 +1905,10 @@ static int perf_sample__fprintf_synth(struct perf_sample *sample, return perf_sample__fprintf_synth_cbr(sample, fp); case PERF_SYNTH_INTEL_PSB: return perf_sample__fprintf_synth_psb(sample, fp); + case PERF_SYNTH_INTEL_EVT: + return perf_sample__fprintf_synth_evt(sample, fp); + case PERF_SYNTH_INTEL_IFLAG_CHG: + return perf_sample__fprintf_synth_iflag_chg(sample, fp); default: break; } @@ -3716,7 +3796,7 @@ int cmd_script(int argc, const char **argv) "Valid types: hw,sw,trace,raw,synth. " "Fields: comm,tid,pid,time,cpu,event,trace,ip,sym,dso," "addr,symoff,srcline,period,iregs,uregs,brstack," - "brstacksym,flags,bpf-output,brstackinsn,brstackoff," + "brstacksym,flags,bpf-output,brstackinsn,brstackinsnlen,brstackoff," "callindent,insn,insnlen,synth,phys_addr,metric,misc,ipc,tod," "data_page_size,code_page_size,ins_lat", parse_output_fields), @@ -3842,13 +3922,13 @@ int cmd_script(int argc, const char **argv) if (symbol__validate_sym_arguments()) return -1; - if (argc > 1 && !strncmp(argv[0], "rec", strlen("rec"))) { + if (argc > 1 && strlen(argv[0]) > 2 && strstarts("record", argv[0])) { rec_script_path = get_script_path(argv[1], RECORD_SUFFIX); if (!rec_script_path) return cmd_record(argc, argv); } - if (argc > 1 && !strncmp(argv[0], "rep", strlen("rep"))) { + if (argc > 1 && strlen(argv[0]) > 2 && strstarts("report", argv[0])) { rep_script_path = get_script_path(argv[1], REPORT_SUFFIX); if (!rep_script_path) { fprintf(stderr, diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c index 3f98689dd687..4ee40de698a4 100644 --- a/tools/perf/builtin-stat.c +++ b/tools/perf/builtin-stat.c @@ -955,10 +955,10 @@ try_again_reset: * Enable counters and exec the command: */ if (forks) { - evlist__start_workload(evsel_list); err = enable_counters(); if (err) return -1; + evlist__start_workload(evsel_list); t0 = rdclock(); clock_gettime(CLOCK_MONOTONIC, &ref_time); @@ -2271,11 +2271,11 @@ int cmd_stat(int argc, const char **argv) } else stat_config.csv_sep = DEFAULT_SEPARATOR; - if (argc && !strncmp(argv[0], "rec", 3)) { + if (argc && strlen(argv[0]) > 2 && strstarts("record", argv[0])) { argc = __cmd_record(argc, argv); if (argc < 0) return -1; - } else if (argc && !strncmp(argv[0], "rep", 3)) + } else if (argc && strlen(argv[0]) > 2 && strstarts("report", argv[0])) return __cmd_report(argc, argv); interval = stat_config.interval; diff --git a/tools/perf/builtin-timechart.c b/tools/perf/builtin-timechart.c index 43bf4d67edb0..afce731cec16 100644 --- a/tools/perf/builtin-timechart.c +++ b/tools/perf/builtin-timechart.c @@ -35,6 +35,7 @@ #include "util/tool.h" #include "util/data.h" #include "util/debug.h" +#include "util/string2.h" #include #ifdef LACKS_OPEN_MEMSTREAM_PROTOTYPE @@ -1983,7 +1984,7 @@ int cmd_timechart(int argc, const char **argv) return -1; } - if (argc && !strncmp(argv[0], "rec", 3)) { + if (argc && strlen(argv[0]) > 2 && strstarts("record", argv[0])) { argc = parse_options(argc, argv, timechart_record_options, timechart_record_usage, PARSE_OPT_STOP_AT_NON_OPTION); diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index 1fc390f136dd..9b08e44a31d9 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -746,7 +746,6 @@ static void perf_event__process_sample(struct perf_tool *tool, { struct perf_top *top = container_of(tool, struct perf_top, tool); struct addr_location al; - int err; if (!machine && perf_guest) { static struct intlist *seen; @@ -839,8 +838,7 @@ static void perf_event__process_sample(struct perf_tool *tool, pthread_mutex_lock(&hists->lock); - err = hist_entry_iter__add(&iter, &al, top->max_stack, top); - if (err < 0) + if (hist_entry_iter__add(&iter, &al, top->max_stack, top) < 0) pr_err("Problem incrementing symbol period, skipping event\n"); pthread_mutex_unlock(&hists->lock); @@ -888,7 +886,7 @@ static void perf_top__mmap_read_idx(struct perf_top *top, int idx) if (ret && ret != -1) break; - ret = ordered_events__queue(top->qe.in, event, last_timestamp, 0); + ret = ordered_events__queue(top->qe.in, event, last_timestamp, 0, NULL); if (ret) break; @@ -1486,7 +1484,9 @@ int cmd_top(int argc, const char **argv) "display this many functions"), OPT_BOOLEAN('U', "hide_user_symbols", &top.hide_user_symbols, "hide user symbols"), +#ifdef HAVE_SLANG_SUPPORT OPT_BOOLEAN(0, "tui", &top.use_tui, "Use the TUI interface"), +#endif OPT_BOOLEAN(0, "stdio", &top.use_stdio, "Use the stdio interface"), OPT_INCR('v', "verbose", &verbose, "be more verbose (show counter open errors, etc)"), @@ -1667,8 +1667,10 @@ int cmd_top(int argc, const char **argv) if (top.use_stdio) use_browser = 0; +#ifdef HAVE_SLANG_SUPPORT else if (top.use_tui) use_browser = 1; +#endif setup_browser(false); diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c index 52b137a184a6..897fc504918b 100644 --- a/tools/perf/builtin-trace.c +++ b/tools/perf/builtin-trace.c @@ -3789,7 +3789,7 @@ static int trace__deliver_event(struct trace *trace, union perf_event *event) if (err && err != -1) return err; - err = ordered_events__queue(&trace->oe.data, event, trace->oe.last, 0); + err = ordered_events__queue(&trace->oe.data, event, trace->oe.last, 0, NULL); if (err) return err; diff --git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh index 30ecf3a0f68b..6ee44b18c6b5 100755 --- a/tools/perf/check-headers.sh +++ b/tools/perf/check-headers.sh @@ -146,6 +146,7 @@ done check arch/x86/lib/memcpy_64.S '-I "^EXPORT_SYMBOL" -I "^#include " -I"^SYM_FUNC_START\(_LOCAL\)*(memcpy_\(erms\|orig\))"' check arch/x86/lib/memset_64.S '-I "^EXPORT_SYMBOL" -I "^#include " -I"^SYM_FUNC_START\(_LOCAL\)*(memset_\(erms\|orig\))"' check arch/x86/include/asm/amd-ibs.h '-I "^#include [<\"]\(asm/\)*msr-index.h"' +check arch/arm64/include/asm/cputype.h '-I "^#include [<\"]\(asm/\)*sysreg.h"' check include/uapi/asm-generic/mman.h '-I "^#include <\(uapi/\)*asm-generic/mman-common\(-tools\)*.h>"' check include/uapi/linux/mman.h '-I "^#include <\(uapi/\)*asm/mman.h>"' check include/linux/build_bug.h '-I "^#\(ifndef\|endif\)\( \/\/\)* static_assert$"' diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json new file mode 100644 index 000000000000..7bcddec8a84f --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/uncore-cpa.json @@ -0,0 +1,81 @@ +[ + { + "ConfigCode": "0x00", + "EventName": "cpa_cycles", + "BriefDescription": "count of CPA cycles", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x61", + "EventName": "cpa_p1_wr_dat", + "BriefDescription": "Number of write ops transmitted by the P1 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x62", + "EventName": "cpa_p1_rd_dat", + "BriefDescription": "Number of read ops transmitted by the P1 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x3", + "EventName": "cpa_p1_rd_dat_64b", + "BriefDescription": "Number of read ops transmitted by the P1 port which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x4", + "EventName": "cpa_p1_rd_dat_32b", + "BriefDescription": "Number of read ops transmitted by the P1 port which size is 32 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0xE1", + "EventName": "cpa_p0_wr_dat", + "BriefDescription": "Number of write ops transmitted by the P0 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0xE2", + "EventName": "cpa_p0_rd_dat", + "BriefDescription": "Number of read ops transmitted by the P0 port", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x83", + "EventName": "cpa_p0_rd_dat_64b", + "BriefDescription": "Number of read ops transmitted by the P0 port which size is 64 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "ConfigCode": "0x84", + "EventName": "cpa_p0_rd_dat_32b", + "BriefDescription": "Number of read ops transmitted by the P0 port which size is 32 bytes", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "MetricExpr": "(cpa_p1_wr_dat * 64 + cpa_p1_rd_dat_64b * 64 + cpa_p1_rd_dat_32b * 32) / cpa_cycles", + "BriefDescription": "Average bandwidth of CPA Port 1", + "MetricGroup": "CPA", + "MetricName": "cpa_p1_avg_bw", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + }, + { + "MetricExpr": "(cpa_p0_wr_dat * 64 + cpa_p0_rd_dat_64b * 64 + cpa_p0_rd_dat_32b * 32) / cpa_cycles", + "BriefDescription": "Average bandwidth of CPA Port 0", + "MetricGroup": "CPA", + "MetricName": "cpa_p0_avg_bw", + "Compat": "0x00000030", + "Unit": "hisi_sicl,cpa" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlake/cache.json b/tools/perf/pmu-events/arch/x86/alderlake/cache.json new file mode 100644 index 000000000000..b83ed129c454 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/cache.json @@ -0,0 +1,1140 @@ +[ + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x38", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x20", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x8", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or tlb miss which hit in the last level cache or other core with HITE/F/M.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x10", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of load ops retired that hit in DRAM.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x80", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x04", + "EventName": "MEM_SCHEDULER_BLOCK.ALL", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x7", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x04", + "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x04", + "EventName": "MEM_SCHEDULER_BLOCK.RSV", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x04", + "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of load uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x81", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of store uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x82", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "3", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts all the retired split loads.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x41", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x6", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ICACHE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x20", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.L2_STALL", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.L2_STALLS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of L1D misses that are outstanding", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache lines filling L2", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "L2_LINES_IN.ALL", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x1f", + "Unit": "cpu_core" + }, + { + "BriefDescription": "All L2 requests.[This event is alias to L2_RQSTS.REFERENCES]", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.ALL", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xff", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x3f", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 code requests", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xe4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Demand Data Read requests", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xe1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Demand requests that miss L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x27", + "Unit": "cpu_core" + }, + { + "BriefDescription": "RFO requests to L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xe2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xc4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x24", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xc1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Demand Data Read miss L2, no rejects", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x21", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x3f", + "Unit": "cpu_core" + }, + { + "BriefDescription": "All L2 requests.[This event is alias to L2_REQUEST.ALL]", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xff", + "Unit": "cpu_core" + }, + { + "BriefDescription": "RFO requests that hit L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xc2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "RFO requests that miss L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x22", + "Unit": "cpu_core" + }, + { + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_HIT", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xc8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x28", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x41", + "Unit": "cpu_core" + }, + { + "BriefDescription": "All retired load instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x81", + "Unit": "cpu_core" + }, + { + "BriefDescription": "All retired store instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x82", + "Unit": "cpu_core" + }, + { + "BriefDescription": "All retired memory instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x83", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions with locked access.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "UMask": "0x21", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x41", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired store instructions that split across a cacheline boundary.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x42", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions that miss the STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x11", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired store instructions that miss the STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x12", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Completed demand load uops that miss the L1 d-cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0xfd", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd4", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100007", + "UMask": "0x40", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100021", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "50021", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "MEM_STORE_RETIRED.L2_HIT", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired memory uops for any access", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe5", + "EventName": "MEM_UOP_RETIRED.ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x3", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x80", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DATA_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.T0", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x4", + "Unit": "cpu_core" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json b/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json new file mode 100644 index 000000000000..310c2a8f3e6b --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json @@ -0,0 +1,158 @@ +[ + { + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.FPDIV", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "UMask": "0x8", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb0", + "EventName": "ARITH.FPDIV_ACTIVE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts all microcode FP assists.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.FP", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.SSE_AVX_MIX", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "FP_ARITH_DISPATCHED.PORT_0", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "FP_ARITH_DISPATCHED.PORT_1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "FP_ARITH_DISPATCHED.PORT_5", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json new file mode 100644 index 000000000000..908588f63314 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json @@ -0,0 +1,491 @@ +[ + { + "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x3", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of instruction cache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "DECODE.LCP", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x600106", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "MSRIndex": "0x3F7", + "MSRValue": "0x608006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "MSRIndex": "0x3F7", + "MSRValue": "0x601006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "MSRIndex": "0x3F7", + "MSRValue": "0x600206", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "MSRIndex": "0x3F7", + "MSRValue": "0x610006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "MSRIndex": "0x3F7", + "MSRValue": "0x602006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "MSRIndex": "0x3F7", + "MSRValue": "0x600406", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "MSRIndex": "0x3F7", + "MSRValue": "0x620006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "MSRIndex": "0x3F7", + "MSRValue": "0x604006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "MSRIndex": "0x3F7", + "MSRValue": "0x600806", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "MSRIndex": "0x3F7", + "MSRValue": "0x17", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE_DATA.STALLS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "500009", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "ICACHE_TAG.STALLS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_OK", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_OK", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of switches from DSB or MITE to the MS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops delivered to IDQ while MS is busy", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/alderlake/memory.json b/tools/perf/pmu-events/arch/x86/alderlake/memory.json new file mode 100644 index 000000000000..1d4d1ebe2a74 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/memory.json @@ -0,0 +1,318 @@ +[ + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.ANY_AT_RET", + "SampleAfterValue": "1000003", + "UMask": "0xff", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "LD_HEAD.L1_BOUND_AT_RET", + "SampleAfterValue": "1000003", + "UMask": "0xf4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases when load subsequently retires when load subsequently retires.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.OTHER_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0xc0", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk when load subsequently retires.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.PGWALK_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0xa0", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match when load subsequently retires.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.ST_ADDR_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x84", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x6", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x47", + "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x47", + "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x3", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0x47", + "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x5", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "9", + "EventCode": "0x47", + "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x9", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "CollectPEBSRecord": "2", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility.", + "CollectPEBSRecord": "2", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", + "PEBS": "2", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/alderlake/other.json b/tools/perf/pmu-events/arch/x86/alderlake/other.json new file mode 100644 index 000000000000..dc810f093fb0 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/other.json @@ -0,0 +1,146 @@ +[ + { + "BriefDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x1f", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.HARDWARE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.PAGE_FAULT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "CORE_POWER.LICENSE_1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "CORE_POWER.LICENSE_2", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "CORE_POWER.LICENSE_3", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x2d", + "EventName": "XQ.FULL_CYCLES", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json new file mode 100644 index 000000000000..de2c6e0ef654 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json @@ -0,0 +1,1721 @@ +[ + { + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf9", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and Interrupt call and return.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xbf", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of near CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf9", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "33", + "EventName": "CPU_CLK_UNHALTED.CORE", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "34", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "UMask": "0x3", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "33", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of instructions retired. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "32", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x8", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machines clears due to memory renaming.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MRN_NUKE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x80", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x20", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SLOW", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x6f", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots not consumed due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing uops from the UROM until a specified older uop retires.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x75", + "EventName": "SERIALIZATION.NON_C01_MS_SCB", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x3", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REGISTER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x20", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x40", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x10", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x40", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.CISC", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.DECODE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x8d", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x72", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ITLB", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x10", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.OTHER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x80", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of consumed retirement slots.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the total number of uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of integer divide uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "UMask": "0x10", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.MS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.X87", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event ARITH.DIV_ACTIVE", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb0", + "EventName": "ARITH.DIVIDER_ACTIVE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x9", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb0", + "EventName": "ARITH.DIV_ACTIVE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x9", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb0", + "EventName": "ARITH.FP_DIVIDER_ACTIVE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb0", + "EventName": "ARITH.INT_DIVIDER_ACTIVE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "All branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Conditional branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x11", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Taken conditional branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Far branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "UMask": "0x40", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x80", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Direct and indirect near call instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Return instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "All mispredicted branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x11", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Mispredicted indirect CALL retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100007", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "25003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.PAUSE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x40", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.PAUSE_INST", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x40", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CollectPEBSRecord": "2", + "Counter": "34", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "SampleAfterValue": "2000003", + "UMask": "0x3", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state", + "CollectPEBSRecord": "2", + "Counter": "33", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "8", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "16", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "12", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0xc", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x5", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total execution stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x21", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x40", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instruction decoders utilized in a cycle", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x75", + "EventName": "INST_DECODED.DECODERS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "32", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.MACRO_FUSED", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.NOP", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Precise instruction retired with PEBS precise-distribution", + "CollectPEBSRecord": "2", + "Counter": "32", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "1", + "PEBScounters": "32", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.REP_ITERATION", + "PEBScounters": "1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xad", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "UMask": "0x80", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xad", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "500009", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xad", + "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "MSRIndex": "0x3F7", + "MSRValue": "0x7", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x40", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TMA slots where uops got dropped", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xad", + "EventName": "INT_MISC.UOP_DROPPING", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.128BIT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x13", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.256BIT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0xac", + "Unit": "cpu_core" + }, + { + "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.ADD_128", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x3", + "Unit": "cpu_core" + }, + { + "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.ADD_256", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0xc", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.MUL_256", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x80", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.SHUFFLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x40", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.VNNI_128", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.VNNI_256", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x88", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x82", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xa8", + "EventName": "LSD.CYCLES_ACTIVE", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xa8", + "EventName": "LSD.CYCLES_OK", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe0", + "EventName": "MISC2_RETIRED.LFENCE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "400009", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SB", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SCOREBOARD", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculations.", + "CollectPEBSRecord": "2", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BAD_SPEC_SLOTS", + "SampleAfterValue": "10000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "CollectPEBSRecord": "2", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "SampleAfterValue": "10000003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "35", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "SampleAfterValue": "10000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "10000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x76", + "EventName": "UOPS_DECODED.DEC0_UOPS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops executed on port 0", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_0", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops executed on port 1", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops executed on ports 2, 3 and 10", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_2_3_10", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops executed on ports 4 and 9", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops executed on ports 5 and 11", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_5_11", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops executed on port 6", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_6", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x40", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops executed on ports 7 and 8", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x80", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.STALLS", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.THREAD", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Counts the number of x87 uops dispatched.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.X87", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Uops that RAT issues to RS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xae", + "EventName": "UOPS_ISSUED.ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles with retired uop(s).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.HEAVY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, + { + "BriefDescription": "TBD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.MS", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "TakenAlone": "1", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Retirement slots used.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.STALLS", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UOPS_RETIRED.STALLS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json new file mode 100644 index 000000000000..d82d6f62a6fb --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json @@ -0,0 +1,222 @@ +[ + { + "BriefDescription": "Number of clocks", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 read request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_M_VC0_REQUESTS_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 write request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_M_VC0_REQUESTS_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 read request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_VC1_REQUESTS_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 write request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_M_VC1_REQUESTS_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read prefetch request from IA", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x0A", + "EventName": "UNC_M_PREFETCH_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Any Rank at Hot state", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M_DRAM_THERMAL_HOT", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Any Rank at Warm state", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1A", + "EventName": "UNC_M_DRAM_THERMAL_WARM", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming read request page status is Page Hit", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M_DRAM_PAGE_HIT_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming read request page status is Page Empty", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming read request page status is Page Miss", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1E", + "EventName": "UNC_M_DRAM_PAGE_MISS_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming write request page status is Page Hit", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M_DRAM_PAGE_HIT_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming write request page status is Page Empty", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming write request page status is Page Miss", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M_DRAM_PAGE_MISS_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS command sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_M_CAS_COUNT_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write CAS command sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M_CAS_COUNT_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command for a read request sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M_ACT_COUNT_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command for a write request sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M_ACT_COUNT_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_M_ACT_COUNT_TOTAL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PRE command sent to DRAM for a read/write request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M_PRE_COUNT_IDLE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels)", + "CounterType": "FREERUN", + "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels)", + "Counter": "3", + "CounterType": "FREERUN", + "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", + "Counter": "1", + "CounterType": "FREERUN", + "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", + "Counter": "4", + "CounterType": "FREERUN", + "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "Unit": "iMC" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json new file mode 100644 index 000000000000..50de82c29944 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json @@ -0,0 +1,40 @@ +[ + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", + "Counter": "Fixed", + "CounterType": "PGMABLE", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "Unit": "CLOCK" + }, + { + "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of requests allocated in Coherency Tracker", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json new file mode 100644 index 000000000000..1cc39aa032e1 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json @@ -0,0 +1,258 @@ +[ + { + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xe", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "UMask": "0xe", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss when load subsequently retires.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.DTLB_MISS_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x90", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0xe", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0xe", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Page walks completed due to a demand data store to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.STLB_HIT", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x20", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x10", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0xe", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x4", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "100003", + "UMask": "0x10", + "Unit": "cpu_core" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf/pmu-events/arch/x86/bonnell/cache.json index ffab90c5891c..71653bfe7093 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/cache.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json @@ -1,746 +1,746 @@ [ { - "EventCode": "0x21", + "BriefDescription": "L1 Data Cacheable reads and writes", "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_ADS.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Cycles L2 address bus is in use." - }, - { - "EventCode": "0x22", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_DBUS_BUSY.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Cycles the L2 cache data bus is busy." - }, - { - "EventCode": "0x23", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_DBUS_BUSY_RD.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Cycles the L2 transfers data to the core." - }, - { - "EventCode": "0x24", - "Counter": "0,1", - "UMask": "0x70", - "EventName": "L2_LINES_IN.SELF.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache misses." - }, - { - "EventCode": "0x24", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_LINES_IN.SELF.DEMAND", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache misses." - }, - { - "EventCode": "0x24", - "Counter": "0,1", - "UMask": "0x50", - "EventName": "L2_LINES_IN.SELF.PREFETCH", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache misses." - }, - { - "EventCode": "0x25", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_M_LINES_IN.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache line modifications." - }, - { - "EventCode": "0x26", - "Counter": "0,1", - "UMask": "0x70", - "EventName": "L2_LINES_OUT.SELF.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache lines evicted." - }, - { - "EventCode": "0x26", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_LINES_OUT.SELF.DEMAND", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache lines evicted." - }, - { - "EventCode": "0x26", - "Counter": "0,1", - "UMask": "0x50", - "EventName": "L2_LINES_OUT.SELF.PREFETCH", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache lines evicted." - }, - { - "EventCode": "0x27", - "Counter": "0,1", - "UMask": "0x70", - "EventName": "L2_M_LINES_OUT.SELF.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "Modified lines evicted from the L2 cache" - }, - { - "EventCode": "0x27", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_M_LINES_OUT.SELF.DEMAND", - "SampleAfterValue": "200000", - "BriefDescription": "Modified lines evicted from the L2 cache" - }, - { - "EventCode": "0x27", - "Counter": "0,1", - "UMask": "0x50", - "EventName": "L2_M_LINES_OUT.SELF.PREFETCH", - "SampleAfterValue": "200000", - "BriefDescription": "Modified lines evicted from the L2 cache" - }, - { - "EventCode": "0x28", - "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_IFETCH.SELF.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" - }, - { - "EventCode": "0x28", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_IFETCH.SELF.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" - }, - { - "EventCode": "0x28", - "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_IFETCH.SELF.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" - }, - { - "EventCode": "0x28", - "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_IFETCH.SELF.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" - }, - { - "EventCode": "0x28", - "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_IFETCH.SELF.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cacheable instruction fetch requests" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x74", - "EventName": "L2_LD.SELF.ANY.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x71", - "EventName": "L2_LD.SELF.ANY.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x78", - "EventName": "L2_LD.SELF.ANY.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x72", - "EventName": "L2_LD.SELF.ANY.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x7f", - "EventName": "L2_LD.SELF.ANY.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_LD.SELF.DEMAND.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_LD.SELF.DEMAND.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_LD.SELF.DEMAND.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_LD.SELF.DEMAND.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_LD.SELF.DEMAND.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x54", - "EventName": "L2_LD.SELF.PREFETCH.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x51", - "EventName": "L2_LD.SELF.PREFETCH.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x58", - "EventName": "L2_LD.SELF.PREFETCH.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x52", - "EventName": "L2_LD.SELF.PREFETCH.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x29", - "Counter": "0,1", - "UMask": "0x5f", - "EventName": "L2_LD.SELF.PREFETCH.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache reads" - }, - { - "EventCode": "0x2A", - "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_ST.SELF.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" - }, - { - "EventCode": "0x2A", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_ST.SELF.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" - }, - { - "EventCode": "0x2A", - "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_ST.SELF.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" - }, - { - "EventCode": "0x2A", - "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_ST.SELF.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" - }, - { - "EventCode": "0x2A", - "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_ST.SELF.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 store requests" - }, - { - "EventCode": "0x2B", - "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_LOCK.SELF.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" - }, - { - "EventCode": "0x2B", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_LOCK.SELF.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" - }, - { - "EventCode": "0x2B", - "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_LOCK.SELF.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" - }, - { - "EventCode": "0x2B", - "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_LOCK.SELF.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" - }, - { - "EventCode": "0x2B", - "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_LOCK.SELF.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 locked accesses" - }, - { - "EventCode": "0x2C", - "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_DATA_RQSTS.SELF.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" - }, - { - "EventCode": "0x2C", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_DATA_RQSTS.SELF.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" - }, - { - "EventCode": "0x2C", - "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_DATA_RQSTS.SELF.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" - }, - { - "EventCode": "0x2C", - "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_DATA_RQSTS.SELF.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" - }, - { - "EventCode": "0x2C", - "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_DATA_RQSTS.SELF.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "All data requests from the L1 data cache" - }, - { - "EventCode": "0x2D", - "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_LD_IFETCH.SELF.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and data caches" - }, - { - "EventCode": "0x2D", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_LD_IFETCH.SELF.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and data caches" - }, - { - "EventCode": "0x2D", - "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_LD_IFETCH.SELF.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and data caches" - }, - { - "EventCode": "0x2D", - "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_LD_IFETCH.SELF.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and data caches" - }, - { - "EventCode": "0x2D", - "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_LD_IFETCH.SELF.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "All read requests from L1 instruction and data caches" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x74", - "EventName": "L2_RQSTS.SELF.ANY.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x71", - "EventName": "L2_RQSTS.SELF.ANY.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x78", - "EventName": "L2_RQSTS.SELF.ANY.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x72", - "EventName": "L2_RQSTS.SELF.ANY.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x7f", - "EventName": "L2_RQSTS.SELF.ANY.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x54", - "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x51", - "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x58", - "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x52", - "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x5f", - "EventName": "L2_RQSTS.SELF.PREFETCH.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache requests" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache demand requests from this core that missed the L2" - }, - { - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_RQSTS.SELF.DEMAND.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "L2 cache demand requests from this core" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x74", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x71", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x78", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x72", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x7f", - "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x44", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x48", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x42", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x54", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x51", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x58", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x52", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x30", - "Counter": "0,1", - "UMask": "0x5f", - "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI", - "SampleAfterValue": "200000", - "BriefDescription": "Rejected L2 cache requests" - }, - { - "EventCode": "0x32", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "L2_NO_REQ.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Cycles no L2 cache requests are pending" - }, - { "EventCode": "0x40", - "Counter": "0,1", - "UMask": "0xa1", - "EventName": "L1D_CACHE.LD", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 Cacheable Data Reads" - }, - { - "EventCode": "0x40", - "Counter": "0,1", - "UMask": "0xa2", - "EventName": "L1D_CACHE.ST", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 Cacheable Data Writes" - }, - { - "EventCode": "0x40", - "Counter": "0,1", - "UMask": "0x83", - "EventName": "L1D_CACHE.ALL_REF", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 Data reads and writes" - }, - { - "EventCode": "0x40", - "Counter": "0,1", - "UMask": "0xa3", "EventName": "L1D_CACHE.ALL_CACHE_REF", "SampleAfterValue": "2000000", - "BriefDescription": "L1 Data Cacheable reads and writes" + "UMask": "0xa3" }, { - "EventCode": "0x40", + "BriefDescription": "L1 Data reads and writes", "Counter": "0,1", - "UMask": "0x8", - "EventName": "L1D_CACHE.REPL", - "SampleAfterValue": "200000", - "BriefDescription": "L1 Data line replacements" + "EventCode": "0x40", + "EventName": "L1D_CACHE.ALL_REF", + "SampleAfterValue": "2000000", + "UMask": "0x83" }, { - "EventCode": "0x40", + "BriefDescription": "Modified cache lines evicted from the L1 data cache", "Counter": "0,1", - "UMask": "0x48", - "EventName": "L1D_CACHE.REPLM", - "SampleAfterValue": "200000", - "BriefDescription": "Modified cache lines allocated in the L1 data cache" - }, - { "EventCode": "0x40", - "Counter": "0,1", - "UMask": "0x10", "EventName": "L1D_CACHE.EVICT", "SampleAfterValue": "200000", - "BriefDescription": "Modified cache lines evicted from the L1 data cache" + "UMask": "0x10" }, { - "EventCode": "0xCB", + "BriefDescription": "L1 Cacheable Data Reads", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x40", + "EventName": "L1D_CACHE.LD", + "SampleAfterValue": "2000000", + "UMask": "0xa1" + }, + { + "BriefDescription": "L1 Data line replacements", + "Counter": "0,1", + "EventCode": "0x40", + "EventName": "L1D_CACHE.REPL", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "Modified cache lines allocated in the L1 data cache", + "Counter": "0,1", + "EventCode": "0x40", + "EventName": "L1D_CACHE.REPLM", + "SampleAfterValue": "200000", + "UMask": "0x48" + }, + { + "BriefDescription": "L1 Cacheable Data Writes", + "Counter": "0,1", + "EventCode": "0x40", + "EventName": "L1D_CACHE.ST", + "SampleAfterValue": "2000000", + "UMask": "0xa2" + }, + { + "BriefDescription": "Cycles L2 address bus is in use.", + "Counter": "0,1", + "EventCode": "0x21", + "EventName": "L2_ADS.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x44" + }, + { + "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x41" + }, + { + "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.MESI", + "SampleAfterValue": "200000", + "UMask": "0x4f" + }, + { + "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x48" + }, + { + "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", + "EventCode": "0x2C", + "EventName": "L2_DATA_RQSTS.SELF.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x42" + }, + { + "BriefDescription": "Cycles the L2 cache data bus is busy.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "L2_DBUS_BUSY.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles the L2 transfers data to the core.", + "Counter": "0,1", + "EventCode": "0x23", + "EventName": "L2_DBUS_BUSY_RD.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "L2_IFETCH.SELF.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x44" + }, + { + "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "L2_IFETCH.SELF.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x41" + }, + { + "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "L2_IFETCH.SELF.MESI", + "SampleAfterValue": "200000", + "UMask": "0x4f" + }, + { + "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "L2_IFETCH.SELF.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x48" + }, + { + "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", + "EventCode": "0x28", + "EventName": "L2_IFETCH.SELF.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x42" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.ANY.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x74" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.ANY.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x71" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.ANY.MESI", + "SampleAfterValue": "200000", + "UMask": "0x7f" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.ANY.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x78" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.ANY.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x72" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x44" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x41" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.DEMAND.MESI", + "SampleAfterValue": "200000", + "UMask": "0x4f" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x48" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x42" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x54" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x51" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.PREFETCH.MESI", + "SampleAfterValue": "200000", + "UMask": "0x5f" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x58" + }, + { + "BriefDescription": "L2 cache reads", + "Counter": "0,1", + "EventCode": "0x29", + "EventName": "L2_LD.SELF.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x52" + }, + { + "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x44" + }, + { + "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x41" + }, + { + "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.MESI", + "SampleAfterValue": "200000", + "UMask": "0x4f" + }, + { + "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x48" + }, + { + "BriefDescription": "All read requests from L1 instruction and data caches", + "Counter": "0,1", + "EventCode": "0x2D", + "EventName": "L2_LD_IFETCH.SELF.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x42" + }, + { + "BriefDescription": "L2 cache misses.", + "Counter": "0,1", + "EventCode": "0x24", + "EventName": "L2_LINES_IN.SELF.ANY", + "SampleAfterValue": "200000", + "UMask": "0x70" + }, + { + "BriefDescription": "L2 cache misses.", + "Counter": "0,1", + "EventCode": "0x24", + "EventName": "L2_LINES_IN.SELF.DEMAND", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "L2 cache misses.", + "Counter": "0,1", + "EventCode": "0x24", + "EventName": "L2_LINES_IN.SELF.PREFETCH", + "SampleAfterValue": "200000", + "UMask": "0x50" + }, + { + "BriefDescription": "L2 cache lines evicted.", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.SELF.ANY", + "SampleAfterValue": "200000", + "UMask": "0x70" + }, + { + "BriefDescription": "L2 cache lines evicted.", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.SELF.DEMAND", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "L2 cache lines evicted.", + "Counter": "0,1", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.SELF.PREFETCH", + "SampleAfterValue": "200000", + "UMask": "0x50" + }, + { + "BriefDescription": "L2 locked accesses", + "Counter": "0,1", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x44" + }, + { + "BriefDescription": "L2 locked accesses", + "Counter": "0,1", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x41" + }, + { + "BriefDescription": "L2 locked accesses", + "Counter": "0,1", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.MESI", + "SampleAfterValue": "200000", + "UMask": "0x4f" + }, + { + "BriefDescription": "L2 locked accesses", + "Counter": "0,1", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x48" + }, + { + "BriefDescription": "L2 locked accesses", + "Counter": "0,1", + "EventCode": "0x2B", + "EventName": "L2_LOCK.SELF.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x42" + }, + { + "BriefDescription": "L2 cache line modifications.", + "Counter": "0,1", + "EventCode": "0x25", + "EventName": "L2_M_LINES_IN.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Modified lines evicted from the L2 cache", + "Counter": "0,1", + "EventCode": "0x27", + "EventName": "L2_M_LINES_OUT.SELF.ANY", + "SampleAfterValue": "200000", + "UMask": "0x70" + }, + { + "BriefDescription": "Modified lines evicted from the L2 cache", + "Counter": "0,1", + "EventCode": "0x27", + "EventName": "L2_M_LINES_OUT.SELF.DEMAND", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Modified lines evicted from the L2 cache", + "Counter": "0,1", + "EventCode": "0x27", + "EventName": "L2_M_LINES_OUT.SELF.PREFETCH", + "SampleAfterValue": "200000", + "UMask": "0x50" + }, + { + "BriefDescription": "Cycles no L2 cache requests are pending", + "Counter": "0,1", + "EventCode": "0x32", + "EventName": "L2_NO_REQ.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x74" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x71" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI", + "SampleAfterValue": "200000", + "UMask": "0x7f" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x78" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x72" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x44" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x41" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI", + "SampleAfterValue": "200000", + "UMask": "0x4f" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x48" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x42" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x54" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x51" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI", + "SampleAfterValue": "200000", + "UMask": "0x5f" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x58" + }, + { + "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", + "EventCode": "0x30", + "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x52" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x74" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x71" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.MESI", + "SampleAfterValue": "200000", + "UMask": "0x7f" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x78" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.ANY.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x72" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x44" + }, + { + "BriefDescription": "L2 cache demand requests from this core that missed the L2", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x41" + }, + { + "BriefDescription": "L2 cache demand requests from this core", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.MESI", + "SampleAfterValue": "200000", + "UMask": "0x4f" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x48" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x42" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x54" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x51" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.MESI", + "SampleAfterValue": "200000", + "UMask": "0x5f" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x58" + }, + { + "BriefDescription": "L2 cache requests", + "Counter": "0,1", + "EventCode": "0x2E", + "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x52" + }, + { + "BriefDescription": "L2 store requests", + "Counter": "0,1", + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.E_STATE", + "SampleAfterValue": "200000", + "UMask": "0x44" + }, + { + "BriefDescription": "L2 store requests", + "Counter": "0,1", + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.I_STATE", + "SampleAfterValue": "200000", + "UMask": "0x41" + }, + { + "BriefDescription": "L2 store requests", + "Counter": "0,1", + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.MESI", + "SampleAfterValue": "200000", + "UMask": "0x4f" + }, + { + "BriefDescription": "L2 store requests", + "Counter": "0,1", + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x48" + }, + { + "BriefDescription": "L2 store requests", + "Counter": "0,1", + "EventCode": "0x2A", + "EventName": "L2_ST.SELF.S_STATE", + "SampleAfterValue": "200000", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired loads that hit the L2 cache (precise event).", + "Counter": "0,1", + "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (precise event)." + "UMask": "0x1" }, { - "EventCode": "0xCB", + "BriefDescription": "Retired loads that miss the L2 cache", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_MISS", "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the L2 cache" + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json index f0e090cdb9f0..f8055ff47f19 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json @@ -1,261 +1,261 @@ [ { - "EventCode": "0x10", + "BriefDescription": "Floating point assists for retired operations.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "X87_COMP_OPS_EXE.ANY.S", - "SampleAfterValue": "2000000", - "BriefDescription": "Floating point computational micro-ops executed." - }, - { - "PEBS": "2", - "EventCode": "0x10", - "Counter": "0,1", - "UMask": "0x81", - "EventName": "X87_COMP_OPS_EXE.ANY.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "Floating point computational micro-ops retired." - }, - { - "EventCode": "0x10", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "X87_COMP_OPS_EXE.FXCH.S", - "SampleAfterValue": "2000000", - "BriefDescription": "FXCH uops executed." - }, - { - "PEBS": "2", - "EventCode": "0x10", - "Counter": "0,1", - "UMask": "0x82", - "EventName": "X87_COMP_OPS_EXE.FXCH.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "FXCH uops retired." - }, - { "EventCode": "0x11", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "FP_ASSIST.S", - "SampleAfterValue": "10000", - "BriefDescription": "Floating point assists." - }, - { - "EventCode": "0x11", - "Counter": "0,1", - "UMask": "0x81", "EventName": "FP_ASSIST.AR", "SampleAfterValue": "10000", - "BriefDescription": "Floating point assists for retired operations." + "UMask": "0x81" }, { - "EventCode": "0xB0", + "BriefDescription": "Floating point assists.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "SIMD_UOPS_EXEC.S", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD micro-ops executed (excluding stores)." + "EventCode": "0x11", + "EventName": "FP_ASSIST.S", + "SampleAfterValue": "10000", + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xB0", + "BriefDescription": "SIMD assists invoked.", "Counter": "0,1", - "UMask": "0x80", - "EventName": "SIMD_UOPS_EXEC.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD micro-ops retired (excluding stores)." - }, - { - "EventCode": "0xB1", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "SIMD_SAT_UOP_EXEC.S", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD saturated arithmetic micro-ops executed." - }, - { - "EventCode": "0xB1", - "Counter": "0,1", - "UMask": "0x80", - "EventName": "SIMD_SAT_UOP_EXEC.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD saturated arithmetic micro-ops retired." - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed multiply micro-ops executed" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x81", - "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed multiply micro-ops retired" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed shift micro-ops executed" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x82", - "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed shift micro-ops retired" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x4", - "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed micro-ops executed" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x84", - "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed micro-ops retired" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD unpacked micro-ops executed" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x88", - "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD unpacked micro-ops retired" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed logical micro-ops executed" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x90", - "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed logical micro-ops retired" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed arithmetic micro-ops executed" - }, - { - "EventCode": "0xB3", - "Counter": "0,1", - "UMask": "0xa0", - "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "SIMD packed arithmetic micro-ops retired" - }, - { - "EventCode": "0xC7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions." - }, - { - "EventCode": "0xC7", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions." - }, - { - "EventCode": "0xC7", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions." - }, - { - "EventCode": "0xC7", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "SIMD_INST_RETIRED.VECTOR", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions." - }, - { - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions." - }, - { - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions." - }, - { - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions." - }, - { "EventCode": "0xCD", - "Counter": "0,1", - "UMask": "0x0", "EventName": "SIMD_ASSIST", "SampleAfterValue": "100000", - "BriefDescription": "SIMD assists invoked." + "UMask": "0x0" }, { - "EventCode": "0xCE", + "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.", "Counter": "0,1", - "UMask": "0x0", + "EventCode": "0xCA", + "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.", + "Counter": "0,1", + "EventCode": "0xCA", + "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.", + "Counter": "0,1", + "EventCode": "0xCA", + "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "SIMD Instructions retired.", + "Counter": "0,1", + "EventCode": "0xCE", "EventName": "SIMD_INSTR_RETIRED", "SampleAfterValue": "2000000", - "BriefDescription": "SIMD Instructions retired." + "UMask": "0x0" }, { - "EventCode": "0xCF", + "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.", "Counter": "0,1", - "UMask": "0x0", + "EventCode": "0xC7", + "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.", + "Counter": "0,1", + "EventCode": "0xC7", + "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.", + "Counter": "0,1", + "EventCode": "0xC7", + "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.", + "Counter": "0,1", + "EventCode": "0xC7", + "EventName": "SIMD_INST_RETIRED.VECTOR", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Saturated arithmetic instructions retired.", + "Counter": "0,1", + "EventCode": "0xCF", "EventName": "SIMD_SAT_INSTR_RETIRED", "SampleAfterValue": "2000000", - "BriefDescription": "Saturated arithmetic instructions retired." + "UMask": "0x0" + }, + { + "BriefDescription": "SIMD saturated arithmetic micro-ops retired.", + "Counter": "0,1", + "EventCode": "0xB1", + "EventName": "SIMD_SAT_UOP_EXEC.AR", + "SampleAfterValue": "2000000", + "UMask": "0x80" + }, + { + "BriefDescription": "SIMD saturated arithmetic micro-ops executed.", + "Counter": "0,1", + "EventCode": "0xB1", + "EventName": "SIMD_SAT_UOP_EXEC.S", + "SampleAfterValue": "2000000", + "UMask": "0x0" + }, + { + "BriefDescription": "SIMD micro-ops retired (excluding stores).", + "Counter": "0,1", + "EventCode": "0xB0", + "EventName": "SIMD_UOPS_EXEC.AR", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x80" + }, + { + "BriefDescription": "SIMD micro-ops executed (excluding stores).", + "Counter": "0,1", + "EventCode": "0xB0", + "EventName": "SIMD_UOPS_EXEC.S", + "SampleAfterValue": "2000000", + "UMask": "0x0" + }, + { + "BriefDescription": "SIMD packed arithmetic micro-ops retired", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", + "SampleAfterValue": "2000000", + "UMask": "0xa0" + }, + { + "BriefDescription": "SIMD packed arithmetic micro-ops executed", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", + "SampleAfterValue": "2000000", + "UMask": "0x20" + }, + { + "BriefDescription": "SIMD packed logical micro-ops retired", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR", + "SampleAfterValue": "2000000", + "UMask": "0x90" + }, + { + "BriefDescription": "SIMD packed logical micro-ops executed", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "SIMD packed multiply micro-ops retired", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR", + "SampleAfterValue": "2000000", + "UMask": "0x81" + }, + { + "BriefDescription": "SIMD packed multiply micro-ops executed", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "SIMD packed micro-ops retired", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR", + "SampleAfterValue": "2000000", + "UMask": "0x84" + }, + { + "BriefDescription": "SIMD packed micro-ops executed", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "SIMD packed shift micro-ops retired", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR", + "SampleAfterValue": "2000000", + "UMask": "0x82" + }, + { + "BriefDescription": "SIMD packed shift micro-ops executed", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "SIMD unpacked micro-ops retired", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR", + "SampleAfterValue": "2000000", + "UMask": "0x88" + }, + { + "BriefDescription": "SIMD unpacked micro-ops executed", + "Counter": "0,1", + "EventCode": "0xB3", + "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "Floating point computational micro-ops retired.", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "X87_COMP_OPS_EXE.ANY.AR", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x81" + }, + { + "BriefDescription": "Floating point computational micro-ops executed.", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "X87_COMP_OPS_EXE.ANY.S", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "FXCH uops retired.", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "X87_COMP_OPS_EXE.FXCH.AR", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x82" + }, + { + "BriefDescription": "FXCH uops executed.", + "Counter": "0,1", + "EventCode": "0x10", + "EventName": "X87_COMP_OPS_EXE.FXCH.S", + "SampleAfterValue": "2000000", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json index ef69540ab61d..e852eb2cc878 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json @@ -1,83 +1,91 @@ [ { - "EventCode": "0x80", + "BriefDescription": "BACLEARS asserted.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "ICACHE.ACCESSES", - "SampleAfterValue": "200000", - "BriefDescription": "Instruction fetches." + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "Cycles during which instruction fetches are stalled.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Icache hit" - }, - { - "EventCode": "0x80", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200000", - "BriefDescription": "Icache miss" - }, - { "EventCode": "0x86", - "Counter": "0,1", - "UMask": "0x1", "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles during which instruction fetches are stalled." + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Decode stall due to IQ full", "Counter": "0,1", - "UMask": "0x1", - "EventName": "DECODE_STALL.PFB_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Decode stall due to PFB empty" - }, - { "EventCode": "0x87", - "Counter": "0,1", - "UMask": "0x2", "EventName": "DECODE_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Decode stall due to IQ full" + "UMask": "0x2" }, { - "EventCode": "0xAA", + "BriefDescription": "Decode stall due to PFB empty", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MACRO_INSTS.NON_CISC_DECODED", + "EventCode": "0x87", + "EventName": "DECODE_STALL.PFB_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Non-CISC nacro instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xAA", + "BriefDescription": "Instruction fetches.", "Counter": "0,1", - "UMask": "0x2", - "EventName": "MACRO_INSTS.CISC_DECODED", - "SampleAfterValue": "2000000", - "BriefDescription": "CISC macro instructions decoded" + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "SampleAfterValue": "200000", + "UMask": "0x3" }, { - "EventCode": "0xAA", + "BriefDescription": "Icache hit", "Counter": "0,1", - "UMask": "0x3", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "Icache miss", + "Counter": "0,1", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "All Instructions decoded", + "Counter": "0,1", + "EventCode": "0xAA", "EventName": "MACRO_INSTS.ALL_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "All Instructions decoded" + "UMask": "0x3" }, { - "EventCode": "0xA9", + "BriefDescription": "CISC macro instructions decoded", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xAA", + "EventName": "MACRO_INSTS.CISC_DECODED", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Non-CISC nacro instructions decoded", + "Counter": "0,1", + "EventCode": "0xAA", + "EventName": "MACRO_INSTS.NON_CISC_DECODED", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", + "Counter": "0,1", + "CounterMask": "1", + "EventCode": "0xA9", "EventName": "UOPS.MS_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", - "CounterMask": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json index 3ae843b20c8a..2aa4c41f528e 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json @@ -1,154 +1,154 @@ [ { - "EventCode": "0x5", + "BriefDescription": "Nonzero segbase 1 bubble", "Counter": "0,1", - "UMask": "0xf", - "EventName": "MISALIGN_MEM_REF.SPLIT", - "SampleAfterValue": "200000", - "BriefDescription": "Memory references that cross an 8-byte boundary." - }, - { "EventCode": "0x5", - "Counter": "0,1", - "UMask": "0x9", - "EventName": "MISALIGN_MEM_REF.LD_SPLIT", - "SampleAfterValue": "200000", - "BriefDescription": "Load splits" - }, - { - "EventCode": "0x5", - "Counter": "0,1", - "UMask": "0xa", - "EventName": "MISALIGN_MEM_REF.ST_SPLIT", - "SampleAfterValue": "200000", - "BriefDescription": "Store splits" - }, - { - "EventCode": "0x5", - "Counter": "0,1", - "UMask": "0x8f", - "EventName": "MISALIGN_MEM_REF.SPLIT.AR", - "SampleAfterValue": "200000", - "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)" - }, - { - "EventCode": "0x5", - "Counter": "0,1", - "UMask": "0x89", - "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR", - "SampleAfterValue": "200000", - "BriefDescription": "Load splits (At Retirement)" - }, - { - "EventCode": "0x5", - "Counter": "0,1", - "UMask": "0x8a", - "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR", - "SampleAfterValue": "200000", - "BriefDescription": "Store splits (Ar Retirement)" - }, - { - "EventCode": "0x5", - "Counter": "0,1", - "UMask": "0x8c", - "EventName": "MISALIGN_MEM_REF.RMW_SPLIT", - "SampleAfterValue": "200000", - "BriefDescription": "ld-op-st splits" - }, - { - "EventCode": "0x5", - "Counter": "0,1", - "UMask": "0x97", "EventName": "MISALIGN_MEM_REF.BUBBLE", "SampleAfterValue": "200000", - "BriefDescription": "Nonzero segbase 1 bubble" + "UMask": "0x97" }, { - "EventCode": "0x5", + "BriefDescription": "Nonzero segbase load 1 bubble", "Counter": "0,1", - "UMask": "0x91", + "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.LD_BUBBLE", "SampleAfterValue": "200000", - "BriefDescription": "Nonzero segbase load 1 bubble" + "UMask": "0x91" }, { - "EventCode": "0x5", + "BriefDescription": "Load splits", "Counter": "0,1", - "UMask": "0x92", - "EventName": "MISALIGN_MEM_REF.ST_BUBBLE", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.LD_SPLIT", "SampleAfterValue": "200000", - "BriefDescription": "Nonzero segbase store 1 bubble" + "UMask": "0x9" }, { - "EventCode": "0x5", + "BriefDescription": "Load splits (At Retirement)", "Counter": "0,1", - "UMask": "0x94", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR", + "SampleAfterValue": "200000", + "UMask": "0x89" + }, + { + "BriefDescription": "Nonzero segbase ld-op-st 1 bubble", + "Counter": "0,1", + "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE", "SampleAfterValue": "200000", - "BriefDescription": "Nonzero segbase ld-op-st 1 bubble" + "UMask": "0x94" }, { - "EventCode": "0x7", + "BriefDescription": "ld-op-st splits", "Counter": "0,1", - "UMask": "0x81", - "EventName": "PREFETCH.PREFETCHT0", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.RMW_SPLIT", "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed." + "UMask": "0x8c" }, { - "EventCode": "0x7", + "BriefDescription": "Memory references that cross an 8-byte boundary.", "Counter": "0,1", - "UMask": "0x82", - "EventName": "PREFETCH.PREFETCHT1", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.SPLIT", "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed." + "UMask": "0xf" }, { - "EventCode": "0x7", + "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)", "Counter": "0,1", - "UMask": "0x84", - "EventName": "PREFETCH.PREFETCHT2", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.SPLIT.AR", "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed." + "UMask": "0x8f" }, { - "EventCode": "0x7", + "BriefDescription": "Nonzero segbase store 1 bubble", "Counter": "0,1", - "UMask": "0x86", - "EventName": "PREFETCH.SW_L2", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.ST_BUBBLE", "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed" + "UMask": "0x92" }, { - "EventCode": "0x7", + "BriefDescription": "Store splits", "Counter": "0,1", - "UMask": "0x88", - "EventName": "PREFETCH.PREFETCHNTA", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.ST_SPLIT", "SampleAfterValue": "200000", - "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed" + "UMask": "0xa" }, { - "EventCode": "0x7", + "BriefDescription": "Store splits (Ar Retirement)", "Counter": "0,1", - "UMask": "0x10", + "EventCode": "0x5", + "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR", + "SampleAfterValue": "200000", + "UMask": "0x8a" + }, + { + "BriefDescription": "L1 hardware prefetch request", + "Counter": "0,1", + "EventCode": "0x7", "EventName": "PREFETCH.HW_PREFETCH", "SampleAfterValue": "2000000", - "BriefDescription": "L1 hardware prefetch request" + "UMask": "0x10" }, { - "EventCode": "0x7", + "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed", "Counter": "0,1", - "UMask": "0xf", + "EventCode": "0x7", + "EventName": "PREFETCH.PREFETCHNTA", + "SampleAfterValue": "200000", + "UMask": "0x88" + }, + { + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.", + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "PREFETCH.PREFETCHT0", + "SampleAfterValue": "200000", + "UMask": "0x81" + }, + { + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.", + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "PREFETCH.PREFETCHT1", + "SampleAfterValue": "200000", + "UMask": "0x82" + }, + { + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.", + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "PREFETCH.PREFETCHT2", + "SampleAfterValue": "200000", + "UMask": "0x84" + }, + { + "BriefDescription": "Any Software prefetch", + "Counter": "0,1", + "EventCode": "0x7", "EventName": "PREFETCH.SOFTWARE_PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "Any Software prefetch" + "UMask": "0xf" }, { - "EventCode": "0x7", + "BriefDescription": "Any Software prefetch", "Counter": "0,1", - "UMask": "0x8f", + "EventCode": "0x7", "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR", "SampleAfterValue": "200000", - "BriefDescription": "Any Software prefetch" + "UMask": "0x8f" + }, + { + "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed", + "Counter": "0,1", + "EventCode": "0x7", + "EventName": "PREFETCH.SW_L2", + "SampleAfterValue": "200000", + "UMask": "0x86" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf/pmu-events/arch/x86/bonnell/other.json index 4bc1c582d1cd..114c062e7e96 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/other.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json @@ -1,450 +1,450 @@ [ { - "EventCode": "0x6", + "BriefDescription": "Bus queue is empty.", "Counter": "0,1", - "UMask": "0x80", - "EventName": "SEGMENT_REG_LOADS.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "Number of segment register loads." - }, - { - "EventCode": "0x9", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "DISPATCH_BLOCKED.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason" - }, - { - "EventCode": "0x3A", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "EIST_TRANS", - "SampleAfterValue": "200000", - "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions" - }, - { - "EventCode": "0x3B", - "Counter": "0,1", - "UMask": "0xc0", - "EventName": "THERMAL_TRIP", - "SampleAfterValue": "200000", - "BriefDescription": "Number of thermal trips" - }, - { - "EventCode": "0x60", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Outstanding cacheable data read bus requests duration." - }, - { - "EventCode": "0x60", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_REQUEST_OUTSTANDING.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Outstanding cacheable data read bus requests duration." - }, - { - "EventCode": "0x61", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "BUS_BNR_DRV.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Number of Bus Not Ready signals asserted." - }, - { - "EventCode": "0x61", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "BUS_BNR_DRV.THIS_AGENT", - "SampleAfterValue": "200000", - "BriefDescription": "Number of Bus Not Ready signals asserted." - }, - { - "EventCode": "0x62", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when data is sent on the bus." - }, - { - "EventCode": "0x62", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT", - "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when data is sent on the bus." - }, - { - "EventCode": "0x63", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when a LOCK signal is asserted." - }, - { - "EventCode": "0x63", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_LOCK_CLOCKS.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when a LOCK signal is asserted." - }, - { - "EventCode": "0x64", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_DATA_RCV.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles while processor receives data." - }, - { - "EventCode": "0x65", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_BRD.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Burst read bus transactions." - }, - { - "EventCode": "0x65", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_BRD.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Burst read bus transactions." - }, - { - "EventCode": "0x66", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_RFO.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "RFO bus transactions." - }, - { - "EventCode": "0x66", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_RFO.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "RFO bus transactions." - }, - { - "EventCode": "0x67", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_WB.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Explicit writeback bus transactions." - }, - { - "EventCode": "0x67", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_WB.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Explicit writeback bus transactions." - }, - { - "EventCode": "0x68", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Instruction-fetch bus transactions." - }, - { - "EventCode": "0x68", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_IFETCH.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Instruction-fetch bus transactions." - }, - { - "EventCode": "0x69", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_INVAL.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Invalidate bus transactions." - }, - { - "EventCode": "0x69", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_INVAL.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Invalidate bus transactions." - }, - { - "EventCode": "0x6A", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_PWR.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Partial write bus transaction." - }, - { - "EventCode": "0x6A", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_PWR.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Partial write bus transaction." - }, - { - "EventCode": "0x6B", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_P.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Partial bus transactions." - }, - { - "EventCode": "0x6B", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_P.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Partial bus transactions." - }, - { - "EventCode": "0x6C", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_IO.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "IO bus transactions." - }, - { - "EventCode": "0x6C", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_IO.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "IO bus transactions." - }, - { - "EventCode": "0x6D", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_DEF.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Deferred bus transactions." - }, - { - "EventCode": "0x6D", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_DEF.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Deferred bus transactions." - }, - { - "EventCode": "0x6E", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_BURST.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Burst (full cache-line) bus transactions." - }, - { - "EventCode": "0x6E", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_BURST.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Burst (full cache-line) bus transactions." - }, - { - "EventCode": "0x6F", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_MEM.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "Memory bus transactions." - }, - { - "EventCode": "0x6F", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_MEM.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "Memory bus transactions." - }, - { - "EventCode": "0x70", - "Counter": "0,1", - "UMask": "0xe0", - "EventName": "BUS_TRANS_ANY.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "All bus transactions." - }, - { - "EventCode": "0x70", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "BUS_TRANS_ANY.SELF", - "SampleAfterValue": "200000", - "BriefDescription": "All bus transactions." - }, - { - "EventCode": "0x77", - "Counter": "0,1", - "UMask": "0xb", - "EventName": "EXT_SNOOP.THIS_AGENT.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." - }, - { - "EventCode": "0x77", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." - }, - { - "EventCode": "0x77", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "EXT_SNOOP.THIS_AGENT.HIT", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." - }, - { - "EventCode": "0x77", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "EXT_SNOOP.THIS_AGENT.HITM", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." - }, - { - "EventCode": "0x77", - "Counter": "0,1", - "UMask": "0x2b", - "EventName": "EXT_SNOOP.ALL_AGENTS.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." - }, - { - "EventCode": "0x77", - "Counter": "0,1", - "UMask": "0x21", - "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." - }, - { - "EventCode": "0x77", - "Counter": "0,1", - "UMask": "0x22", - "EventName": "EXT_SNOOP.ALL_AGENTS.HIT", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." - }, - { - "EventCode": "0x77", - "Counter": "0,1", - "UMask": "0x28", - "EventName": "EXT_SNOOP.ALL_AGENTS.HITM", - "SampleAfterValue": "200000", - "BriefDescription": "External snoops." - }, - { - "EventCode": "0x7A", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "BUS_HIT_DRV.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "HIT signal asserted." - }, - { - "EventCode": "0x7A", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "BUS_HIT_DRV.THIS_AGENT", - "SampleAfterValue": "200000", - "BriefDescription": "HIT signal asserted." - }, - { - "EventCode": "0x7B", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "BUS_HITM_DRV.ALL_AGENTS", - "SampleAfterValue": "200000", - "BriefDescription": "HITM signal asserted." - }, - { - "EventCode": "0x7B", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "BUS_HITM_DRV.THIS_AGENT", - "SampleAfterValue": "200000", - "BriefDescription": "HITM signal asserted." - }, - { "EventCode": "0x7D", - "Counter": "0,1", - "UMask": "0x40", "EventName": "BUSQ_EMPTY.SELF", "SampleAfterValue": "200000", - "BriefDescription": "Bus queue is empty." + "UMask": "0x40" }, { - "EventCode": "0x7E", + "BriefDescription": "Number of Bus Not Ready signals asserted.", "Counter": "0,1", - "UMask": "0xe0", - "EventName": "SNOOP_STALL_DRV.ALL_AGENTS", + "EventCode": "0x61", + "EventName": "BUS_BNR_DRV.ALL_AGENTS", "SampleAfterValue": "200000", - "BriefDescription": "Bus stalled for snoops." + "UMask": "0x20" }, { - "EventCode": "0x7E", + "BriefDescription": "Number of Bus Not Ready signals asserted.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "SNOOP_STALL_DRV.SELF", + "EventCode": "0x61", + "EventName": "BUS_BNR_DRV.THIS_AGENT", "SampleAfterValue": "200000", - "BriefDescription": "Bus stalled for snoops." + "UMask": "0x0" }, { + "BriefDescription": "Bus cycles while processor receives data.", + "Counter": "0,1", + "EventCode": "0x64", + "EventName": "BUS_DATA_RCV.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Bus cycles when data is sent on the bus.", + "Counter": "0,1", + "EventCode": "0x62", + "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Bus cycles when data is sent on the bus.", + "Counter": "0,1", + "EventCode": "0x62", + "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT", + "SampleAfterValue": "200000", + "UMask": "0x0" + }, + { + "BriefDescription": "HITM signal asserted.", + "Counter": "0,1", + "EventCode": "0x7B", + "EventName": "BUS_HITM_DRV.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "HITM signal asserted.", + "Counter": "0,1", + "EventCode": "0x7B", + "EventName": "BUS_HITM_DRV.THIS_AGENT", + "SampleAfterValue": "200000", + "UMask": "0x0" + }, + { + "BriefDescription": "HIT signal asserted.", + "Counter": "0,1", + "EventCode": "0x7A", + "EventName": "BUS_HIT_DRV.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "HIT signal asserted.", + "Counter": "0,1", + "EventCode": "0x7A", + "EventName": "BUS_HIT_DRV.THIS_AGENT", + "SampleAfterValue": "200000", + "UMask": "0x0" + }, + { + "BriefDescription": "IO requests waiting in the bus queue.", + "Counter": "0,1", "EventCode": "0x7F", - "Counter": "0,1", - "UMask": "0x40", "EventName": "BUS_IO_WAIT.SELF", "SampleAfterValue": "200000", - "BriefDescription": "IO requests waiting in the bus queue." + "UMask": "0x40" }, { - "EventCode": "0xC6", + "BriefDescription": "Bus cycles when a LOCK signal is asserted.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", + "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Bus cycles when a LOCK signal is asserted.", + "Counter": "0,1", + "EventCode": "0x63", + "EventName": "BUS_LOCK_CLOCKS.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Outstanding cacheable data read bus requests duration.", + "Counter": "0,1", + "EventCode": "0x60", + "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Outstanding cacheable data read bus requests duration.", + "Counter": "0,1", + "EventCode": "0x60", + "EventName": "BUS_REQUEST_OUTSTANDING.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "All bus transactions.", + "Counter": "0,1", + "EventCode": "0x70", + "EventName": "BUS_TRANS_ANY.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "All bus transactions.", + "Counter": "0,1", + "EventCode": "0x70", + "EventName": "BUS_TRANS_ANY.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Burst read bus transactions.", + "Counter": "0,1", + "EventCode": "0x65", + "EventName": "BUS_TRANS_BRD.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Burst read bus transactions.", + "Counter": "0,1", + "EventCode": "0x65", + "EventName": "BUS_TRANS_BRD.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Burst (full cache-line) bus transactions.", + "Counter": "0,1", + "EventCode": "0x6E", + "EventName": "BUS_TRANS_BURST.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Burst (full cache-line) bus transactions.", + "Counter": "0,1", + "EventCode": "0x6E", + "EventName": "BUS_TRANS_BURST.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Deferred bus transactions.", + "Counter": "0,1", + "EventCode": "0x6D", + "EventName": "BUS_TRANS_DEF.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Deferred bus transactions.", + "Counter": "0,1", + "EventCode": "0x6D", + "EventName": "BUS_TRANS_DEF.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Instruction-fetch bus transactions.", + "Counter": "0,1", + "EventCode": "0x68", + "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Instruction-fetch bus transactions.", + "Counter": "0,1", + "EventCode": "0x68", + "EventName": "BUS_TRANS_IFETCH.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Invalidate bus transactions.", + "Counter": "0,1", + "EventCode": "0x69", + "EventName": "BUS_TRANS_INVAL.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Invalidate bus transactions.", + "Counter": "0,1", + "EventCode": "0x69", + "EventName": "BUS_TRANS_INVAL.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "IO bus transactions.", + "Counter": "0,1", + "EventCode": "0x6C", + "EventName": "BUS_TRANS_IO.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "IO bus transactions.", + "Counter": "0,1", + "EventCode": "0x6C", + "EventName": "BUS_TRANS_IO.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Memory bus transactions.", + "Counter": "0,1", + "EventCode": "0x6F", + "EventName": "BUS_TRANS_MEM.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Memory bus transactions.", + "Counter": "0,1", + "EventCode": "0x6F", + "EventName": "BUS_TRANS_MEM.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Partial bus transactions.", + "Counter": "0,1", + "EventCode": "0x6B", + "EventName": "BUS_TRANS_P.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Partial bus transactions.", + "Counter": "0,1", + "EventCode": "0x6B", + "EventName": "BUS_TRANS_P.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Partial write bus transaction.", + "Counter": "0,1", + "EventCode": "0x6A", + "EventName": "BUS_TRANS_PWR.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Partial write bus transaction.", + "Counter": "0,1", + "EventCode": "0x6A", + "EventName": "BUS_TRANS_PWR.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "RFO bus transactions.", + "Counter": "0,1", + "EventCode": "0x66", + "EventName": "BUS_TRANS_RFO.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "RFO bus transactions.", + "Counter": "0,1", + "EventCode": "0x66", + "EventName": "BUS_TRANS_RFO.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Explicit writeback bus transactions.", + "Counter": "0,1", + "EventCode": "0x67", + "EventName": "BUS_TRANS_WB.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Explicit writeback bus transactions.", + "Counter": "0,1", + "EventCode": "0x67", + "EventName": "BUS_TRANS_WB.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles during which interrupts are disabled.", + "Counter": "0,1", + "EventCode": "0xC6", "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles during which interrupts are disabled." + "UMask": "0x1" }, { - "EventCode": "0xC6", + "BriefDescription": "Cycles during which interrupts are pending and disabled.", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xC6", "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles during which interrupts are pending and disabled." + "UMask": "0x2" }, { - "EventCode": "0xC8", + "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason", "Counter": "0,1", - "UMask": "0x0", + "EventCode": "0x9", + "EventName": "DISPATCH_BLOCKED.ANY", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions", + "Counter": "0,1", + "EventCode": "0x3A", + "EventName": "EIST_TRANS", + "SampleAfterValue": "200000", + "UMask": "0x0" + }, + { + "BriefDescription": "External snoops.", + "Counter": "0,1", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.ALL_AGENTS.ANY", + "SampleAfterValue": "200000", + "UMask": "0x2b" + }, + { + "BriefDescription": "External snoops.", + "Counter": "0,1", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN", + "SampleAfterValue": "200000", + "UMask": "0x21" + }, + { + "BriefDescription": "External snoops.", + "Counter": "0,1", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.ALL_AGENTS.HIT", + "SampleAfterValue": "200000", + "UMask": "0x22" + }, + { + "BriefDescription": "External snoops.", + "Counter": "0,1", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.ALL_AGENTS.HITM", + "SampleAfterValue": "200000", + "UMask": "0x28" + }, + { + "BriefDescription": "External snoops.", + "Counter": "0,1", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.THIS_AGENT.ANY", + "SampleAfterValue": "200000", + "UMask": "0xb" + }, + { + "BriefDescription": "External snoops.", + "Counter": "0,1", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "External snoops.", + "Counter": "0,1", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.THIS_AGENT.HIT", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "External snoops.", + "Counter": "0,1", + "EventCode": "0x77", + "EventName": "EXT_SNOOP.THIS_AGENT.HITM", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "Hardware interrupts received.", + "Counter": "0,1", + "EventCode": "0xC8", "EventName": "HW_INT_RCV", "SampleAfterValue": "200000", - "BriefDescription": "Hardware interrupts received." + "UMask": "0x0" + }, + { + "BriefDescription": "Number of segment register loads.", + "Counter": "0,1", + "EventCode": "0x6", + "EventName": "SEGMENT_REG_LOADS.ANY", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "Bus stalled for snoops.", + "Counter": "0,1", + "EventCode": "0x7E", + "EventName": "SNOOP_STALL_DRV.ALL_AGENTS", + "SampleAfterValue": "200000", + "UMask": "0xe0" + }, + { + "BriefDescription": "Bus stalled for snoops.", + "Counter": "0,1", + "EventCode": "0x7E", + "EventName": "SNOOP_STALL_DRV.SELF", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of thermal trips", + "Counter": "0,1", + "EventCode": "0x3B", + "EventName": "THERMAL_TRIP", + "SampleAfterValue": "200000", + "UMask": "0xc0" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json index 09c6de13de20..896b738e59b6 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json @@ -1,364 +1,356 @@ [ { - "EventCode": "0x2", + "BriefDescription": "Bogus branches", "Counter": "0,1", - "UMask": "0x83", - "EventName": "STORE_FORWARDS.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "All store forwards" - }, - { - "EventCode": "0x2", - "Counter": "0,1", - "UMask": "0x81", - "EventName": "STORE_FORWARDS.GOOD", - "SampleAfterValue": "200000", - "BriefDescription": "Good store forwards" - }, - { - "EventCode": "0x3", - "Counter": "0,1", - "UMask": "0x7f", - "EventName": "REISSUE.ANY", - "SampleAfterValue": "200000", - "BriefDescription": "Micro-op reissues for any cause" - }, - { - "EventCode": "0x3", - "Counter": "0,1", - "UMask": "0xff", - "EventName": "REISSUE.ANY.AR", - "SampleAfterValue": "200000", - "BriefDescription": "Micro-op reissues for any cause (At Retirement)" - }, - { - "EventCode": "0x12", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "MUL.S", - "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed." - }, - { - "EventCode": "0x12", - "Counter": "0,1", - "UMask": "0x81", - "EventName": "MUL.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations retired" - }, - { - "EventCode": "0x13", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "DIV.S", - "SampleAfterValue": "2000000", - "BriefDescription": "Divide operations executed." - }, - { - "EventCode": "0x13", - "Counter": "0,1", - "UMask": "0x81", - "EventName": "DIV.AR", - "SampleAfterValue": "2000000", - "BriefDescription": "Divide operations retired" - }, - { - "EventCode": "0x14", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "CYCLES_DIV_BUSY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy." - }, - { - "EventCode": "0x3C", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.CORE_P", - "SampleAfterValue": "2000000", - "BriefDescription": "Core cycles when core is not halted" - }, - { - "EventCode": "0x3C", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.BUS", - "SampleAfterValue": "200000", - "BriefDescription": "Bus cycles when core is not halted" - }, - { - "EventCode": "0xA", - "Counter": "Fixed counter 2", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.CORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Core cycles when core is not halted" - }, - { - "EventCode": "0xA", - "Counter": "Fixed counter 3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.REF", - "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when core is not halted." - }, - { - "EventCode": "0x88", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "BR_INST_TYPE_RETIRED.COND", - "SampleAfterValue": "2000000", - "BriefDescription": "All macro conditional branch instructions." - }, - { - "EventCode": "0x88", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "BR_INST_TYPE_RETIRED.UNCOND", - "SampleAfterValue": "2000000", - "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects" - }, - { - "EventCode": "0x88", - "Counter": "0,1", - "UMask": "0x4", - "EventName": "BR_INST_TYPE_RETIRED.IND", - "SampleAfterValue": "2000000", - "BriefDescription": "All indirect branches that are not calls." - }, - { - "EventCode": "0x88", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "BR_INST_TYPE_RETIRED.RET", - "SampleAfterValue": "2000000", - "BriefDescription": "All indirect branches that have a return mnemonic" - }, - { - "EventCode": "0x88", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL", - "SampleAfterValue": "2000000", - "BriefDescription": "All non-indirect calls" - }, - { - "EventCode": "0x88", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "BR_INST_TYPE_RETIRED.IND_CALL", - "SampleAfterValue": "2000000", - "BriefDescription": "All indirect calls, including both register and memory indirect." - }, - { - "EventCode": "0x88", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN", - "SampleAfterValue": "2000000", - "BriefDescription": "Only taken macro conditional branch instructions" - }, - { - "EventCode": "0x89", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "BR_MISSP_TYPE_RETIRED.COND", - "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted cond branch instructions retired" - }, - { - "EventCode": "0x89", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "BR_MISSP_TYPE_RETIRED.IND", - "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted ind branches that are not calls" - }, - { - "EventCode": "0x89", - "Counter": "0,1", - "UMask": "0x4", - "EventName": "BR_MISSP_TYPE_RETIRED.RETURN", - "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted return branches" - }, - { - "EventCode": "0x89", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL", - "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect." - }, - { - "EventCode": "0x89", - "Counter": "0,1", - "UMask": "0x11", - "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN", - "SampleAfterValue": "200000", - "BriefDescription": "Mispredicted and taken cond branch instructions retired" - }, - { - "PEBS": "2", - "EventCode": "0xC0", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (precise event)." - }, - { - "EventCode": "0xA", - "Counter": "Fixed counter 1", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired." - }, - { - "EventCode": "0xC2", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "Micro-ops retired." - }, - { - "EventCode": "0xC2", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.STALLED_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no micro-ops retired." - }, - { - "EventCode": "0xC2", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.STALLS", - "SampleAfterValue": "2000000", - "BriefDescription": "Periods no micro-ops retired." - }, - { - "EventCode": "0xC3", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "200000", - "BriefDescription": "Self-Modifying Code detected." - }, - { - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ANY", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired branch instructions." - }, - { - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired branch instructions that were predicted not-taken." - }, - { - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN", - "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions that were mispredicted not-taken." - }, - { - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.PRED_TAKEN", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired branch instructions that were predicted taken." - }, - { - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.MISPRED_TAKEN", - "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions that were mispredicted taken." - }, - { - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xc", - "EventName": "BR_INST_RETIRED.TAKEN", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired taken branch instructions." - }, - { - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xf", - "EventName": "BR_INST_RETIRED.ANY1", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired branch instructions." - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.MISPRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired mispredicted branch instructions (precise event)." - }, - { - "EventCode": "0xDC", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "RESOURCE_STALLS.DIV_BUSY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles issue is stalled due to div busy." - }, - { - "EventCode": "0xE0", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "BR_INST_DECODED", - "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" - }, - { "EventCode": "0xE4", - "Counter": "0,1", - "UMask": "0x1", "EventName": "BOGUS_BR", "SampleAfterValue": "2000000", - "BriefDescription": "Bogus branches" + "UMask": "0x1" }, { - "EventCode": "0xE6", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1", - "UMask": "0x1", - "EventName": "BACLEARS.ANY", + "EventCode": "0xE0", + "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEARS asserted." + "UMask": "0x1" }, { - "EventCode": "0x3", + "BriefDescription": "Retired branch instructions.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "UMask": "0x0" + }, + { + "BriefDescription": "Retired branch instructions.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ANY1", + "SampleAfterValue": "2000000", + "UMask": "0xf" + }, + { + "BriefDescription": "Retired mispredicted branch instructions (precise event).", + "Counter": "0,1", + "EventCode": "0xC5", + "EventName": "BR_INST_RETIRED.MISPRED", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x0" + }, + { + "BriefDescription": "Retired branch instructions that were mispredicted not-taken.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired branch instructions that were mispredicted taken.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.MISPRED_TAKEN", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired branch instructions that were predicted not-taken.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired branch instructions that were predicted taken.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.PRED_TAKEN", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired taken branch instructions.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN", + "SampleAfterValue": "2000000", + "UMask": "0xc" + }, + { + "BriefDescription": "All macro conditional branch instructions.", + "Counter": "0,1", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.COND", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Only taken macro conditional branch instructions", + "Counter": "0,1", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN", + "SampleAfterValue": "2000000", + "UMask": "0x41" + }, + { + "BriefDescription": "All non-indirect calls", + "Counter": "0,1", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "All indirect branches that are not calls.", + "Counter": "0,1", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.IND", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "All indirect calls, including both register and memory indirect.", + "Counter": "0,1", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.IND_CALL", + "SampleAfterValue": "2000000", + "UMask": "0x20" + }, + { + "BriefDescription": "All indirect branches that have a return mnemonic", + "Counter": "0,1", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.RET", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects", + "Counter": "0,1", + "EventCode": "0x88", + "EventName": "BR_INST_TYPE_RETIRED.UNCOND", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Mispredicted cond branch instructions retired", + "Counter": "0,1", + "EventCode": "0x89", + "EventName": "BR_MISSP_TYPE_RETIRED.COND", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "Mispredicted and taken cond branch instructions retired", + "Counter": "0,1", + "EventCode": "0x89", + "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN", + "SampleAfterValue": "200000", + "UMask": "0x11" + }, + { + "BriefDescription": "Mispredicted ind branches that are not calls", + "Counter": "0,1", + "EventCode": "0x89", + "EventName": "BR_MISSP_TYPE_RETIRED.IND", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.", + "Counter": "0,1", + "EventCode": "0x89", + "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "Mispredicted return branches", + "Counter": "0,1", + "EventCode": "0x89", + "EventName": "BR_MISSP_TYPE_RETIRED.RETURN", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Bus cycles when core is not halted", + "Counter": "0,1", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.BUS", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when core is not halted", + "Counter": "Fixed counter 2", + "EventCode": "0xA", + "EventName": "CPU_CLK_UNHALTED.CORE", + "SampleAfterValue": "2000000", + "UMask": "0x0" + }, + { + "BriefDescription": "Core cycles when core is not halted", + "Counter": "0,1", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "SampleAfterValue": "2000000", + "UMask": "0x0" + }, + { + "BriefDescription": "Reference cycles when core is not halted.", + "Counter": "Fixed counter 3", + "EventCode": "0xA", + "EventName": "CPU_CLK_UNHALTED.REF", + "SampleAfterValue": "2000000", + "UMask": "0x0" + }, + { + "BriefDescription": "Cycles the divider is busy.", + "Counter": "0,1", + "EventCode": "0x14", + "EventName": "CYCLES_DIV_BUSY", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Divide operations retired", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "DIV.AR", + "SampleAfterValue": "2000000", + "UMask": "0x81" + }, + { + "BriefDescription": "Divide operations executed.", + "Counter": "0,1", + "EventCode": "0x13", + "EventName": "DIV.S", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired.", + "Counter": "Fixed counter 1", + "EventCode": "0xA", + "EventName": "INST_RETIRED.ANY", + "SampleAfterValue": "2000000", + "UMask": "0x0" + }, + { + "BriefDescription": "Instructions retired (precise event).", + "Counter": "0,1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x0" + }, + { + "BriefDescription": "Self-Modifying Code detected.", + "Counter": "0,1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "Multiply operations retired", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "MUL.AR", + "SampleAfterValue": "2000000", + "UMask": "0x81" + }, + { + "BriefDescription": "Multiply operations executed.", + "Counter": "0,1", + "EventCode": "0x12", + "EventName": "MUL.S", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Micro-op reissues for any cause", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "REISSUE.ANY", + "SampleAfterValue": "200000", + "UMask": "0x7f" + }, + { + "BriefDescription": "Micro-op reissues for any cause (At Retirement)", + "Counter": "0,1", + "EventCode": "0x3", + "EventName": "REISSUE.ANY.AR", + "SampleAfterValue": "200000", + "UMask": "0xff" + }, + { + "BriefDescription": "Micro-op reissues on a store-load collision", + "Counter": "0,1", + "EventCode": "0x3", "EventName": "REISSUE.OVERLAP_STORE", "SampleAfterValue": "200000", - "BriefDescription": "Micro-op reissues on a store-load collision" + "UMask": "0x1" }, { - "EventCode": "0x3", + "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)", "Counter": "0,1", - "UMask": "0x81", + "EventCode": "0x3", "EventName": "REISSUE.OVERLAP_STORE.AR", "SampleAfterValue": "200000", - "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)" + "UMask": "0x81" + }, + { + "BriefDescription": "Cycles issue is stalled due to div busy.", + "Counter": "0,1", + "EventCode": "0xDC", + "EventName": "RESOURCE_STALLS.DIV_BUSY", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "All store forwards", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "STORE_FORWARDS.ANY", + "SampleAfterValue": "200000", + "UMask": "0x83" + }, + { + "BriefDescription": "Good store forwards", + "Counter": "0,1", + "EventCode": "0x2", + "EventName": "STORE_FORWARDS.GOOD", + "SampleAfterValue": "200000", + "UMask": "0x81" + }, + { + "BriefDescription": "Micro-ops retired.", + "Counter": "0,1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ANY", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles no micro-ops retired.", + "Counter": "0,1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALLED_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Periods no micro-ops retired.", + "Counter": "0,1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALLS", + "SampleAfterValue": "2000000", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json index 7bb817588721..c2363b8e61b4 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json @@ -1,124 +1,124 @@ [ { - "EventCode": "0x8", + "BriefDescription": "Memory accesses that missed the DTLB.", "Counter": "0,1", - "UMask": "0x7", + "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS", "SampleAfterValue": "200000", - "BriefDescription": "Memory accesses that missed the DTLB." + "UMask": "0x7" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB misses due to load operations.", "Counter": "0,1", - "UMask": "0x5", + "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses due to load operations." + "UMask": "0x5" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB misses due to store operations.", "Counter": "0,1", - "UMask": "0x9", - "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", - "SampleAfterValue": "200000", - "BriefDescription": "L0 DTLB misses due to load operations." - }, - { "EventCode": "0x8", - "Counter": "0,1", - "UMask": "0x6", "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses due to store operations." + "UMask": "0x6" }, { - "EventCode": "0x8", + "BriefDescription": "L0 DTLB misses due to load operations.", "Counter": "0,1", - "UMask": "0xa", + "EventCode": "0x8", + "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", + "SampleAfterValue": "200000", + "UMask": "0x9" + }, + { + "BriefDescription": "L0 DTLB misses due to store operations", + "Counter": "0,1", + "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST", "SampleAfterValue": "200000", - "BriefDescription": "L0 DTLB misses due to store operations" + "UMask": "0xa" }, { - "EventCode": "0xC", + "BriefDescription": "ITLB flushes.", "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.WALKS", - "SampleAfterValue": "200000", - "BriefDescription": "Number of page-walks executed." - }, - { - "EventCode": "0xC", - "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Duration of page-walks in core cycles" - }, - { - "EventCode": "0xC", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_WALKS", - "SampleAfterValue": "200000", - "BriefDescription": "Number of D-side only page walks" - }, - { - "EventCode": "0xC", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Duration of D-side only page walks" - }, - { - "EventCode": "0xC", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_WALKS", - "SampleAfterValue": "200000", - "BriefDescription": "Number of I-Side page walks" - }, - { - "EventCode": "0xC", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Duration of I-Side page walks" - }, - { "EventCode": "0x82", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "ITLB.HIT", - "SampleAfterValue": "200000", - "BriefDescription": "ITLB hits." - }, - { - "EventCode": "0x82", - "Counter": "0,1", - "UMask": "0x4", "EventName": "ITLB.FLUSH", "SampleAfterValue": "200000", - "BriefDescription": "ITLB flushes." + "UMask": "0x4" }, { - "PEBS": "2", + "BriefDescription": "ITLB hits.", + "Counter": "0,1", "EventCode": "0x82", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "ITLB.MISSES", + "EventName": "ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "ITLB misses." + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xCB", + "BriefDescription": "ITLB misses.", "Counter": "0,1", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "EventCode": "0x82", + "EventName": "ITLB.MISSES", + "PEBS": "2", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (precise event)." + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (precise event).", + "Counter": "0,1", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Duration of page-walks in core cycles", + "Counter": "0,1", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x3" + }, + { + "BriefDescription": "Duration of D-side only page walks", + "Counter": "0,1", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of D-side only page walks", + "Counter": "0,1", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "SampleAfterValue": "200000", + "UMask": "0x1" + }, + { + "BriefDescription": "Duration of I-Side page walks", + "Counter": "0,1", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of I-Side page walks", + "Counter": "0,1", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of page-walks executed.", + "Counter": "0,1", + "EventCode": "0xC", + "EventName": "PAGE_WALKS.WALKS", + "SampleAfterValue": "200000", + "UMask": "0x3" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json index 8cdc7c13dc2a..91d23341eabd 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json @@ -1,196 +1,170 @@ [ { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Instructions per Store (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * (4 * cycles) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts_SMT", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", "MetricName": "Branch_Misprediction_Cost_SMT" }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -200,87 +174,196 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpFLOP" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Memory_Bound;Memory_BW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -291,22 +374,46 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, + { + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/cache.json b/tools/perf/pmu-events/arch/x86/broadwell/cache.json index 7938bf5689ab..890412f02e06 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/cache.json @@ -1,3399 +1,3410 @@ [ { - "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", - "EventCode": "0x24", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read miss L2, no rejects", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x22", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x27", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Demand requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.L2_PF_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 prefetch requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "EventName": "L2_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "All requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "L2_RQSTS.L2_PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 prefetch requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xe1", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xe2", - "EventName": "L2_RQSTS.ALL_RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the total number of L2 code requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xe4", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xe7", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", - "SampleAfterValue": "200003", - "BriefDescription": "Demand requests to L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xf8", - "EventName": "L2_RQSTS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "L2_RQSTS.REFERENCES", - "SampleAfterValue": "200003", - "BriefDescription": "All L2 requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x50", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests missed L3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests that refer to L3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "2" - }, - { "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L1D_PEND_MISS.FB_FULL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "UMask": "0x2" + }, + { + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", - "EventCode": "0x51", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", + "BriefDescription": "Not rejected writebacks that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM76", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", - "EventCode": "0x63", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", - "EventCode": "0xb2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB7, 0xBB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100003", - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "L1_Hit_Indication": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x21", - "Errata": "BDM35", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "L1_Hit_Indication": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "L1_Hit_Indication": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM35", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "Errata": "BDM100, BDE70", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", - "SampleAfterValue": "100007", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM100", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.", - "EventCode": "0xD3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDE70, BDM100", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x50" }, { - "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts L1D writebacks that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts L2 fill requests that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts L2 writebacks that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", - "SampleAfterValue": "100003", "BriefDescription": "L2 cache lines filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "UMask": "0x5", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "This event counts the number of split locks in the super queue.", - "EventCode": "0xf4", + "BriefDescription": "L2 code requests", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts demand data reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand data writes (RFOs) have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand data writes (RFOs)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs)", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand data writes (RFOs)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs)", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand data writes (RFOs)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs)", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand data writes (RFOs)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs)", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand data writes (RFOs)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs)", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand data writes (RFOs)", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs)", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand code reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020004", - "Counter": "0,1,2,3", - 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"Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "This event counts the total number of L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020200", + "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0xe1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020200", + "BriefDescription": "Demand requests that miss L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "UMask": "0x27" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020200", + "BriefDescription": "Demand requests to L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xe7" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0200", + "BriefDescription": "Requests from L2 hardware prefetchers", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", + "SampleAfterValue": "200003", + "UMask": "0xf8" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0200", + "BriefDescription": "RFO requests to L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "UMask": "0xe2" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0200", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0200", + "BriefDescription": "L2 cache misses when fetching instructions.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "UMask": "0x24" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0200", + "BriefDescription": "Demand Data Read requests that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0200", + "BriefDescription": "Demand Data Read miss L2, no rejects", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0x21" }, { - "PublicDescription": "Counts any other requests have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000018000", + "BriefDescription": "L2 prefetch requests that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080028000", + "BriefDescription": "L2 prefetch requests that miss L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x30" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100028000", + "BriefDescription": "All requests that miss L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x3f" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200028000", + "BriefDescription": "All L2 requests.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400028000", + "BriefDescription": "RFO requests that hit L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000028000", + "BriefDescription": "RFO requests that miss L2 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "UMask": "0x22" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80028000", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C8000", + "BriefDescription": "Transactions accessing L2 pipe", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", + "SampleAfterValue": "200003", + "UMask": "0x80" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C8000", + "BriefDescription": "L2 cache accesses when fetching instructions", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C8000", + "BriefDescription": "Demand Data Read requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C8000", + "BriefDescription": "L1D writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "This event counts L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C8000", + "BriefDescription": "L2 fill requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "This event counts L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" }, { - "PublicDescription": "Counts any other requests", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C8000", + "BriefDescription": "L2 writebacks that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any other requests", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "This event counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" }, { - "PublicDescription": "Counts all prefetch data reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010090", + "BriefDescription": "RFO requests that access L2 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020090", + "BriefDescription": "Cycles when L1D is locked", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020090", + "BriefDescription": "Core-originated cacheable demand requests missed L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020090", + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4f" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020090", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020090", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020090", + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0090", + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0090", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDE70, BDM100", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0090", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0090", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0090", + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PublicDescription": "Counts all prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0090", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were hits in the mid-level (L2) cache.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PublicDescription": "Counts prefetch RFOs have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010120", + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", + "SampleAfterValue": "50021", + "UMask": "0x10" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020120", + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "50021", + "UMask": "0x4" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020120", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100, BDE70", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x20" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020120", + "BriefDescription": "All retired load uops.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020120", + "BriefDescription": "All retired store uops.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020120", + "BriefDescription": "Retired load uops with locked access.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts load uops with locked access retired to the architected path.", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020120", + "BriefDescription": "Retired load uops that split across a cacheline boundary.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0120", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x42" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0120", + "BriefDescription": "Retired load uops that miss the STLB.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0120", + "BriefDescription": "Retired store uops that miss the STLB.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0120", + "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0120", + "BriefDescription": "Any memory transaction that reached the SQ.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "PublicDescription": "Counts prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0120", + "BriefDescription": "Cacheable and noncachaeble code read requests", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PublicDescription": "Counts all prefetch code reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010240", + "BriefDescription": "Demand Data Read requests sent to uncore", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020240", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020240", + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020240", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020240", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020240", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020240", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0240", + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0240", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0240", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0240", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts all prefetch code reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0240", + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch code reads", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0240", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", + "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", "BriefDescription": "Counts all demand & prefetch data reads have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020091", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads have any response type.", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100020091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0200020091", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0400020091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000020091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F80020091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00803C0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01003C0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x02003C0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0091", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6, 0x1a7", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs have any response type.", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0000010122", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads have any response type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020240", + "Offcore": "1", + "PublicDescription": "Counts all prefetch code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads have any response type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010090", + "Offcore": "1", + "PublicDescription": "Counts all prefetch data reads have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0090", + "Offcore": "1", + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0090", + "Offcore": "1", + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0090", + "Offcore": "1", + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0090", + "Offcore": "1", + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0090", + "Offcore": "1", + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": 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"EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020090", + "Offcore": "1", + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020090", + "Offcore": "1", + "PublicDescription": "Counts all prefetch data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch RFOs have any response type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010120", + "Offcore": "1", + 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"CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020120", + "Offcore": "1", + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020120", + "Offcore": "1", + "PublicDescription": "Counts prefetch RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts all demand & prefetch RFOs have any response type.", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch RFOs", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0080020122", "Counter": "0,1,2,3", - "UMask": "0x1", - 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writes (RFOs) have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs)", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs)", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + 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"SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0040", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0040", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": 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"Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs have any response type.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02003C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00803C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01003C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80020100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400020100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200020100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080020100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100020100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "PublicDescription": "This event counts the number of split locks in the super queue.", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json index 15291239c128..9ad37dddb354 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json @@ -1,172 +1,193 @@ [ { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", - "EventCode": "0xC1", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM30", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "Errata": "BDM30", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from legacy SSE to AVX-256 when penalty applicable (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x8", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x15", - "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", - "SampleAfterValue": "2000006", - "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xc7", - "Counter": "0,1,2,3", - "UMask": "0x20", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x2a", - "EventName": "FP_ARITH_INST_RETIRED.SINGLE", - "SampleAfterValue": "2000005", - "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "UMask": "0x15" }, { - "EventCode": "0xC7", + "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x3c", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.PACKED", "SampleAfterValue": "2000004", - "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3c" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", - "EventCode": "0xCA", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "output - Numeric Overflow, Numeric Underflow, Inexact Result (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", - "EventCode": "0xCA", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.X87_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "input - Invalid Operation, Denormal Operand, SNaN Operand (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", - "EventCode": "0xCA", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "SSE* FP micro-code assist when output value is invalid. (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts any input SSE* floating-point (FP) assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", - "EventCode": "0xCA", + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Any input SSE* FP Assist - (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SINGLE", + "SampleAfterValue": "2000005", + "UMask": "0x2a" }, { - "PEBS": "1", - "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. Uses PEBS.", - "EventCode": "0xCA", + "BriefDescription": "Cycles with any input/output SSE or FP assist", "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any FP_ASSIST umask was incrementing (Precise Event)", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "SampleAfterValue": "100003", + "UMask": "0x1e" + }, + { + "BriefDescription": "Number of SIMD FP assists due to input values", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SIMD FP assists due to Output values", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", + "SampleAfterValue": "2000003", + "UMask": "0x3" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json index aa4a5d762f21..f0bcb945ff76 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json @@ -1,286 +1,295 @@ [ { - "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", + "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x18" }, { - "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x18" }, { - "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x24" }, { - "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x24" }, { - "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", - "EventCode": "0x79", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "Counter": "0,1,2,3", - "UMask": "0x30", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", "EventName": "IDQ.MS_SWITCHES", "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x3c", - "EventName": "IDQ.MITE_ALL_UOPS", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x30" }, { - "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFDATA_STALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding \u201c4 \u2013 x\u201d when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "SampleAfterValue": "2000003", "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "CounterHTOff": "0,1,2,3" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0\u20132 cycles.", - "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/memory.json b/tools/perf/pmu-events/arch/x86/broadwell/memory.json index b6b5247d3d5a..f4eebecf371f 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/memory.json @@ -1,3045 +1,3053 @@ [ { - "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", - "EventCode": "0x05", + "BriefDescription": "Number of times HLE abort was triggered", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX line had a cache conflict.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_MEM.ABORT_CONFLICT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX line had a cache conflict", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times we could not allocate Lock Buffer.", - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times we could not allocate Lock Buffer", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_EXEC.MISC2", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_EXEC.MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RTM region detected inside HLE.", - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_EXEC.MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "HLE_RETIRED.START", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times HLE commit succeeded.", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "HLE_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times HLE commit succeeded", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "Number of times HLE abort was triggered (PEBS).", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "HLE_RETIRED.ABORTED", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times HLE abort was triggered (PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "HLE_RETIRED.ABORTED_MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "HLE_RETIRED.ABORTED_MISC2", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "HLE_RETIRED.ABORTED_MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times HLE caused a fault.", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "HLE_RETIRED.ABORTED_MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "HLE_RETIRED.ABORTED_MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RTM_RETIRED.START", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of times RTM commit succeeded.", - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RTM_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times RTM commit succeeded", - "CounterHTOff": "0,1,2,3" - }, - { "PEBS": "1", - "PublicDescription": "Number of times RTM abort was triggered (PEBS).", - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RTM_RETIRED.ABORTED", + "PublicDescription": "Number of times HLE abort was triggered.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times RTM abort was triggered (PEBS)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", - "EventCode": "0xc9", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RTM_RETIRED.ABORTED_MISC1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", - "EventCode": "0xc9", + "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RTM_RETIRED.ABORTED_MISC2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", - "EventCode": "0xc9", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "RTM_RETIRED.ABORTED_MISC3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "PublicDescription": "Number of times a RTM caused a fault.", - "EventCode": "0xc9", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "RTM_RETIRED.ABORTED_MISC4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times HLE caused a fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", - "EventCode": "0xc9", + "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "RTM_RETIRED.ABORTED_MISC5", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above four.", - "EventCode": "0xCD", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", + "BriefDescription": "Number of times HLE commit succeeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", "SampleAfterValue": "100003", - "BriefDescription": "Randomly selected loads with latency value being above 4", - "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above eight.", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Randomly selected loads with latency value being above 128", "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Randomly selected loads with latency value being above 8", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 16.", - "EventCode": "0xCD", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Randomly selected loads with latency value being above 16", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 32.", - "EventCode": "0xCD", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100007", - "BriefDescription": "Randomly selected loads with latency value being above 32", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 64.", - "EventCode": "0xCD", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x1", - "Errata": "BDM100, BDM35", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Randomly selected loads with latency value being above 64", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 128.", - "EventCode": "0xCD", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 128.", "SampleAfterValue": "1009", - "BriefDescription": "Randomly selected loads with latency value being above 128", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 256.", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Randomly selected loads with latency value being above 16", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 16.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 256", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 256.", "SampleAfterValue": "503", - "BriefDescription": "Randomly selected loads with latency value being above 256", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads with latency value being above 512.", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Randomly selected loads with latency value being above 32", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 32.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 4", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above four.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 512", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 512.", "SampleAfterValue": "101", - "BriefDescription": "Randomly selected loads with latency value being above 512", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 64", + "Counter": "3", + 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"EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x013C000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0404000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0204000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0084000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0104000100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times RTM abort was triggered", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered .", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "PublicDescription": "Number of times a RTM caused a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times a TSX line had a cache conflict", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times we could not allocate Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/other.json b/tools/perf/pmu-events/arch/x86/broadwell/other.json index 4f829c5febbe..4b360fe96698 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/other.json @@ -1,44 +1,44 @@ [ { - "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", - "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPL_CYCLES.RING0", - "SampleAfterValue": "2000003", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", - "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "CPL_CYCLES.RING0_TRANS", - "SampleAfterValue": "100007", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", + "EdgeDetect": "1", "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPL_CYCLES.RING123", - "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventName": "CPL_CYCLES.RING0_TRANS", + "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", - "EventCode": "0x63", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json index bb25574b8d21..18d21b94a4b9 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json @@ -1,1429 +1,1380 @@ [ { - "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt state", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial compare", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles when divider is busy executing divide operations", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", - "EventCode": "0x3C", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3c", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", - "EventCode": "0x4c", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", - "EventCode": "0x4C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", - "EventCode": "0x5E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", - "SampleAfterValue": "200003", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts not taken macro-conditional branch instructions.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts taken speculative and retired direct near calls.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", - "EventCode": "0xA0", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", - "SampleAfterValue": "2000003", - "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 6", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are exectuted in port 6.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 6", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 7", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 7.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 7", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts resource-related stall cycles.", - "EventCode": "0xa2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "SampleAfterValue": "2000003", - "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "SampleAfterValue": "2000003", - "BriefDescription": "Total execution stalls.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "CounterMask": "8", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "CounterMask": "8", - "CounterHTOff": "2" - }, - { - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "CounterMask": "12", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "CounterMask": "12", - "CounterHTOff": "2" - }, - { - "PublicDescription": "Number of Uops delivered by the LSD.", - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of uops to be executed per-thread each cycle.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of uops executed from any thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of uops executed on the core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "Errata": "BDM61", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "Errata": "BDM11, BDM55", - "EventName": "INST_RETIRED.PREC_DIST", - "SampleAfterValue": "2000003", - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "CounterHTOff": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", - "SampleAfterValue": "2000003", - "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Actually retired uops. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts cycles without actually retired uops.", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles no executable uops retired (Precise Event)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to PEBS uops retired event.", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles using always true condition applied to PEBS uops retired event.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.", - "EventCode": "0xC2", + "BriefDescription": "Speculative and retired macro-conditional branches", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", - "EventCode": "0xC3", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "EventCode": "0xC3", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", - "EventCode": "0xC3", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", - "EventCode": "0xC3", + "BriefDescription": "Speculative and retired indirect return branches.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0xc8" }, { - "PublicDescription": "This event counts all (macro) branch instructions retired.", - "EventCode": "0xC4", + "BriefDescription": "Not taken macro-conditional branches", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired macro-conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Taken speculative and retired direct near calls", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0x90" + }, + { + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired indirect calls", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" + }, + { "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).", + "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "BDW98", "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", - "EventCode": "0xC4", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDW98", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.", "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts not taken branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Counts all not taken macro branch instructions retired. (Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts far branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x40", - "Errata": "BDW98", "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "This event counts far branch instructions retired.", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of far branch instructions retired.(Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", - "EventCode": "0xC5", + "BriefDescription": "Direct and indirect near call instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "PublicDescription": "This event counts both direct and indirect near call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" }, { + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect macro near call instructions retired (captured in ring 3).", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "This event counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "This event counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "This event counts not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" + }, + { + "BriefDescription": "All mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted conditional branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_MISP_RETIRED.RET", - "SampleAfterValue": "100007", - "BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).", - "EventCode": "0xC5", + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", "SampleAfterValue": "400009", - "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", - "EventCode": "0xCC", + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "EventCode": "0xe6", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "SampleAfterValue": "2000003" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM61", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "BDM11, BDM55", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", + "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "This event counts resource-related stall cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually retired uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json index 2a015e4c7e21..818a8b132c08 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json @@ -1,388 +1,388 @@ [ { - "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", "BriefDescription": "Load misses in all DTLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "SampleAfterValue": "2000003", - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0xe", - "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "EventCode": "0x08", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x10", - "Errata": "BDM69", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", - "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", - "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x60", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", - "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", - "EventCode": "0x49", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", - "EventCode": "0x49", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", - "EventCode": "0x49", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", "Counter": "0,1,2,3", - "UMask": "0x8", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0x49", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "UMask": "0xe", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "EventCode": "0x49", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", - "SampleAfterValue": "100003", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x60", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", - "EventCode": "0x4F", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "EPT.WALK_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "BDM69", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", - "EventCode": "0x85", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "BDM69", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", - "EventCode": "0x85", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", "Counter": "0,1,2,3", - "UMask": "0x4", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "BDM69", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x85", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", "Counter": "0,1,2,3", - "UMask": "0xe", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "EventCode": "0x85", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "EventName": "ITLB_MISSES.WALK_DURATION", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", "SampleAfterValue": "100003", - "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x85", + "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "ITLB_MISSES.STLB_HIT_2M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", + "EventName": "EPT.WALK_CYCLES", + "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", "Counter": "0,1,2,3", - "UMask": "0x60", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", - "EventCode": "0xAE", + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "UMask": "0x40" }, { - "EventCode": "0xBC", + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", "Counter": "0,1,2,3", - "UMask": "0x11", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of DTLB page walker hits in the L1+FB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L1+FB.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in the L2.", "Counter": "0,1,2,3", - "UMask": "0x12", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", "Counter": "0,1,2,3", - "UMask": "0x14", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L3", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of DTLB page walker hits in Memory.", "Counter": "0,1,2,3", - "UMask": "0x18", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in Memory.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in the L1+FB.", "Counter": "0,1,2,3", - "UMask": "0x21", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L1+FB.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in the L2.", "Counter": "0,1,2,3", - "UMask": "0x22", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x22" }, { - "EventCode": "0xBC", + "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", "Counter": "0,1,2,3", - "UMask": "0x24", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L3", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", - "EventCode": "0xBD", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TLB_FLUSH.DTLB_THREAD", - "SampleAfterValue": "100007", "BriefDescription": "DTLB flush attempts of the thread-specific entries", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", - "EventCode": "0xBD", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TLB_FLUSH.STLB_ANY", - "SampleAfterValue": "100007", "BriefDescription": "STLB flush attempts", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", + "SampleAfterValue": "100007", + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json index 16fd8a7490fc..73b6865a769d 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json @@ -1,104 +1,369 @@ [ { - "BriefDescription": "Instructions Per Cycle (per logical thread)", + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Frontend_Bound", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Frontend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Bad_Speculation", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Bad_Speculation_SMT", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", + "MetricGroup": "TopdownL1", + "MetricName": "Backend_Bound", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Backend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Retiring", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided." + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Retiring_SMT", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely consumed by program instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "Frontend", - "MetricName": "IFetch_Line_Utilization" + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )", - "MetricGroup": "DSB; Frontend_Bandwidth", - "MetricName": "DSB_Coverage" - }, - { - "BriefDescription": "Cycles Per Instruction (threaded)", - "MetricExpr": "1 / INST_RETIRED.ANY / cycles", - "MetricGroup": "Pipeline;Summary", + "BriefDescription": "Cycles Per Instruction (per Logical Processor)", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { - "BriefDescription": "Per-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTune.", + "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots", - "MetricExpr": "4*( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", + "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles", - "MetricGroup": "SMT", + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", + "MetricName": "CoreIPC_SMT" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", + "MetricName": "FLOPc" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", + "MetricName": "FLOPc_SMT" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", - "MetricExpr": "UOPS_EXECUTED.THREAD / ( cpu@uops_executed.core\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "MetricGroup": "Pipeline;Ports_Utilization", + "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "BriefDescription": "Average Branch Address Clear Cost (fraction of cycles)", - "MetricExpr": "2* ( RS_EVENTS.EMPTY_CYCLES - ICACHE.IFDATA_STALL - ( 14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7* ITLB_MISSES.WALK_COMPLETED ) ) / RS_EVENTS.EMPTY_END", - "MetricGroup": "Unknown_Branches", - "MetricName": "BAClear_Cost" + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "Core actual clocks when any thread is active on the physical core", - "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" }, { - "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss)", - "MetricExpr": "L1D_PEND_MISS.PENDING / ( cpu@l1d_pend_miss.pending_cycles\\,any\\=1@ / 2) if #SMT_on else L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Memory_Bound;Memory_BW", + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpFLOP" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, + { + "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L1D_Cache_Fill_BW" + }, + { + "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L2_Cache_Fill_BW" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "L3_Cache_Fill_BW" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI" + }, + { + "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;Backend;CacheMisses", + "MetricName": "L2MPKI" + }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses;Offcore", + "MetricName": "L2MPKI_All" + }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_All" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L3MPKI" + }, { "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7*(DTLB_STORE_MISSES.WALK_COMPLETED+DTLB_LOAD_MISSES.WALK_COMPLETED+ITLB_MISSES.WALK_COMPLETED)) / ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles", - "MetricGroup": "TLB", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", "MetricName": "Page_Walks_Utilization" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( 1*( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2* FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4*( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8* FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -108,17 +373,53 @@ "MetricName": "Turbo_Utilization" }, { - "BriefDescription": "Fraction of cycles where both hardware threads were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", + "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "MetricName": "DRAM_BW_Use" + }, + { + "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "1000000000 * ( cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@ ) / ( cbox_0@event\\=0x0@ / duration_time )", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "MEM_Read_Latency" + }, + { + "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", + "MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "MEM_Parallel_Reads" + }, + { + "BriefDescription": "Socket actual clocks when any core is active on that socket", + "MetricExpr": "cbox_0@event\\=0x0@", + "MetricGroup": "SoC", + "MetricName": "Socket_CLKS" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json index bf243fe2a0ec..0f4de912d099 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json @@ -1,809 +1,809 @@ [ { - "EventCode": "0x24", - "UMask": "0x21", - "BriefDescription": "Demand Data Read miss L2, no rejects", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x22", - "BriefDescription": "RFO requests that miss L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x24", - "BriefDescription": "L2 cache misses when fetching instructions.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x27", - "BriefDescription": "Demand requests that miss L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x30", - "BriefDescription": "L2 prefetch requests that miss L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_MISS", - "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x3f", - "BriefDescription": "All requests that miss L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x41", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x42", - "BriefDescription": "RFO requests that hit L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x44", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x50", - "BriefDescription": "L2 prefetch requests that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_HIT", - "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe1", - "BriefDescription": "Demand Data Read requests", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe2", - "BriefDescription": "RFO requests to L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_RFO", - "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe4", - "BriefDescription": "L2 code requests", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PublicDescription": "This event counts the total number of L2 code requests.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe7", - "BriefDescription": "Demand requests to L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xf8", - "BriefDescription": "Requests from L2 hardware prefetchers", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_PF", - "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xff", - "BriefDescription": "All L2 requests.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.REFERENCES", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "UMask": "0x50", - "BriefDescription": "Not rejected writebacks that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", - "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "UMask": "0x41", - "BriefDescription": "Core-originated cacheable demand requests missed L3", - "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "UMask": "0x4f", - "BriefDescription": "Core-originated cacheable demand requests that refer to L3", - "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "L1D miss oustandings duration in cycles", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING", - "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x2", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", - "Counter": "0,1,2,3", - "EventName": "L1D_PEND_MISS.FB_FULL", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x51", - "UMask": "0x1", "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "CounterMask": "6", - "Errata": "BDM76", + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x2", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x63", - "UMask": "0x2", - "BriefDescription": "Cycles when L1D is locked", + "BriefDescription": "Not rejected writebacks that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests sent to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x2", - "BriefDescription": "Cacheable and noncachaeble code read requests", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x4", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x8", - "BriefDescription": "Demand and prefetch data reads", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb2", - "UMask": "0x1", - "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x11", - "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x12", - "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", - "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x21", - "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "Errata": "BDM35", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x41", - "BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x42", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x81", - "BriefDescription": "All retired load uops. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x82", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", - "SampleAfterValue": "2000003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x1", - "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x2", - "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "Errata": "BDM35", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x4", - "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", - "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x8", - "BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x10", - "BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", - "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x20", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", - "Errata": "BDM100, BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x40", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x1", - "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x2", - "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x8", - "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "Errata": "BDM100", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x1", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "Errata": "BDE70, BDM100", - "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x4", - "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x10", - "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x20", - "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xF0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x50" }, { - "EventCode": "0xF0", - "UMask": "0x2", - "BriefDescription": "RFO requests that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.RFO", - "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x4", - "BriefDescription": "L2 cache accesses when fetching instructions", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.CODE_RD", - "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x8", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_PF", - "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x10", - "BriefDescription": "L1D writebacks that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L1D_WB", - "PublicDescription": "This event counts L1D writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x20", - "BriefDescription": "L2 fill requests that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_FILL", - "PublicDescription": "This event counts L2 fill requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x40", - "BriefDescription": "L2 writebacks that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_WB", - "PublicDescription": "This event counts L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x80", - "BriefDescription": "Transactions accessing L2 pipe", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_REQUESTS", - "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x1", - "BriefDescription": "L2 cache lines in I state filling L2", - "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.I", - "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x2", - "BriefDescription": "L2 cache lines in S state filling L2", - "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.S", - "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x4", - "BriefDescription": "L2 cache lines in E state filling L2", - "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.E", - "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x7", "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x7" + }, + { + "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xF2", - "UMask": "0x5", "BriefDescription": "Clean L2 cache lines evicted by demand.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "This event counts the total number of L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0xe1" + }, + { + "BriefDescription": "Demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "UMask": "0x27" + }, + { + "BriefDescription": "Demand requests to L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xe7" + }, + { + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", + "SampleAfterValue": "200003", + "UMask": "0xf8" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "UMask": "0xe2" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x44" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "UMask": "0x24" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "SampleAfterValue": "200003", + "UMask": "0x50" + }, + { + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x30" + }, + { + "BriefDescription": "All requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x3f" + }, + { + "BriefDescription": "All L2 requests.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "UMask": "0x42" + }, + { + "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "UMask": "0x22" + }, + { + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "This event counts L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "This event counts L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "This event counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "SampleAfterValue": "100003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDE70, BDM100", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", + "SampleAfterValue": "50021", + "UMask": "0x10" + }, + { + "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100, BDE70", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x20" + }, + { + "BriefDescription": "All retired load uops. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "SampleAfterValue": "2000003", + "UMask": "0x81" + }, + { + "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "SampleAfterValue": "2000003", + "UMask": "0x82" + }, + { + "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.", + "SampleAfterValue": "100007", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "SampleAfterValue": "100003", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cacheable and noncachaeble code read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xf4", - "UMask": "0x10", "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "This event counts the number of split locks in the super queue.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json index d7b9d9c9c518..fdf5dc40b835 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json @@ -1,165 +1,193 @@ [ { - "EventCode": "0xC1", - "UMask": "0x8", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", - "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "UMask": "0x10", - "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", - "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC7", - "UMask": "0x1", - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC7", - "UMask": "0x2", - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC7", - "UMask": "0x3", - "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC7", - "UMask": "0x4", "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC7", - "UMask": "0x8", "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xC7", - "UMask": "0x10", "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xC7", - "UMask": "0x15", - "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", - "SampleAfterValue": "2000006", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc7", - "UMask": "0x20", "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xC7", - "UMask": "0x2a", - "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SINGLE", - "SampleAfterValue": "2000005", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "UMask": "0x15" }, { - "EventCode": "0xC7", - "UMask": "0x3c", "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.PACKED", "SampleAfterValue": "2000004", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3c" }, { - "EventCode": "0xCA", - "UMask": "0x2", - "BriefDescription": "Number of X87 assists due to output value.", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_OUTPUT", - "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "EventCode": "0xCA", - "UMask": "0x4", - "BriefDescription": "Number of X87 assists due to input value.", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_INPUT", - "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xCA", - "UMask": "0x8", - "BriefDescription": "Number of SIMD FP assists due to Output values", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SINGLE", + "SampleAfterValue": "2000005", + "UMask": "0x2a" + }, + { + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xCA", - "UMask": "0x10", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "SampleAfterValue": "100003", + "UMask": "0x1e" + }, + { "BriefDescription": "Number of SIMD FP assists due to input values", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xCA", - "UMask": "0x1e", - "BriefDescription": "Cycles with any input/output SSE or FP assist", + "BriefDescription": "Number of SIMD FP assists due to Output values", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.ANY", - "CounterMask": "1", - "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", + "SampleAfterValue": "2000003", + "UMask": "0x3" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json index 72781e1e3362..f0bcb945ff76 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json @@ -1,286 +1,295 @@ [ { - "EventCode": "0x79", - "UMask": "0x2", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "EventName": "IDQ.EMPTY", - "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_UOPS", - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_UOPS", - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_UOPS", - "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_OCCUR", - "CounterMask": "1", - "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x20", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering any Uop", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_SWITCHES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x3c", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_ALL_UOPS", - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "UMask": "0x1", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", - "Counter": "0,1,2,3", - "EventName": "ICACHE.HIT", - "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "UMask": "0x2", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", - "Counter": "0,1,2,3", - "EventName": "ICACHE.MISSES", - "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "UMask": "0x4", - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", - "Counter": "0,1,2,3", - "EventName": "ICACHE.IFDATA_STALL", - "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "CounterMask": "4", - "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", - "CounterMask": "3", - "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xAB", - "UMask": "0x2", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" + }, + { + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", + "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json index e44f73c24ac8..604059e7eb58 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json @@ -1,432 +1,432 @@ [ { - "EventCode": "0x05", - "UMask": "0x1", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOADS", - "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "UMask": "0x2", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORES", - "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x1", - "BriefDescription": "Number of times a TSX line had a cache conflict", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Number of times a TSX line had a cache conflict.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x2", - "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x4", - "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x8", - "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x10", - "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x20", - "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x40", - "BriefDescription": "Number of times we could not allocate Lock Buffer", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PublicDescription": "Number of times we could not allocate Lock Buffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x1", - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x2", - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC2", - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x4", - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC3", - "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x8", - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC4", - "PublicDescription": "RTM region detected inside HLE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x10", - "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x2", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.START", - "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x2", - "BriefDescription": "Number of times HLE commit succeeded", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.COMMIT", - "PublicDescription": "Number of times HLE commit succeeded.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x4", "BriefDescription": "Number of times HLE abort was triggered (PEBS)", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", "PublicDescription": "Number of times HLE abort was triggered (PEBS).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xc8", - "UMask": "0x8", "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xc8", - "UMask": "0x10", "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xc8", - "UMask": "0x20", "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xc8", - "UMask": "0x40", "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times HLE caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xc8", - "UMask": "0x80", "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0xc9", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "BriefDescription": "Number of times HLE commit succeeded", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x2", - "BriefDescription": "Number of times RTM commit succeeded", + "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.COMMIT", - "PublicDescription": "Number of times RTM commit succeeded.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Loads with latency value being above 128", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 128.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 16", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 16.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 256", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 256.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 32", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 32.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 4", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above four.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 512", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 512.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 64", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above 64.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 8", + "Counter": "3", + "CounterHTOff": "3", + "Errata": "BDM100, BDM35", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "This event counts loads with latency value being above eight.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x4", "BriefDescription": "Number of times RTM abort was triggered (PEBS)", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", "PublicDescription": "Number of times RTM abort was triggered (PEBS).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xc9", - "UMask": "0x8", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xc9", - "UMask": "0x10", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xc9", - "UMask": "0x20", "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xc9", - "UMask": "0x40", "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times a RTM caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "EventCode": "0xc9", - "UMask": "0x80", "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 4", - "PEBS": "2", - "MSRValue": "0x4", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above four.", - "TakenAlone": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "3" + "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 8", - "PEBS": "2", - "MSRValue": "0x8", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above eight.", - "TakenAlone": "1", - "SampleAfterValue": "50021", - "CounterHTOff": "3" + "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 16", - "PEBS": "2", - "MSRValue": "0x10", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 16.", - "TakenAlone": "1", - "SampleAfterValue": "20011", - "CounterHTOff": "3" + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 32", - "PEBS": "2", - "MSRValue": "0x20", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 32.", - "TakenAlone": "1", - "SampleAfterValue": "100007", - "CounterHTOff": "3" + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 64", - "PEBS": "2", - "MSRValue": "0x40", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 64.", - "TakenAlone": "1", - "SampleAfterValue": "2003", - "CounterHTOff": "3" + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 128", - "PEBS": "2", - "MSRValue": "0x80", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 128.", - "TakenAlone": "1", - "SampleAfterValue": "1009", - "CounterHTOff": "3" + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 256", - "PEBS": "2", - "MSRValue": "0x100", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 256.", - "TakenAlone": "1", - "SampleAfterValue": "503", - "CounterHTOff": "3" + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Loads with latency value being above 512", - "PEBS": "2", - "MSRValue": "0x200", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "This event counts loads with latency value being above 512.", - "TakenAlone": "1", - "SampleAfterValue": "101", - "CounterHTOff": "3" + "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times a TSX line had a cache conflict", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times we could not allocate Lock Buffer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/other.json b/tools/perf/pmu-events/arch/x86/broadwellde/other.json index 4475249ea9da..4b360fe96698 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/other.json @@ -1,44 +1,44 @@ [ { - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EdgeDetect": "1", - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", "Counter": "0,1,2,3", - "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", - "UMask": "0x2", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", - "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json index e2f0540625a2..7580b8af0d13 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json @@ -1,1423 +1,1381 @@ [ { - "UMask": "0x1", - "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "EventName": "INST_RETIRED.ANY", - "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 0" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when the thread is not in halt state", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x3", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "Counter": "Fixed counter 2", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 2" - }, - { - "EventCode": "0x03", - "UMask": "0x2", - "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "UMask": "0x8", - "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x07", - "UMask": "0x1", - "BriefDescription": "False dependencies in MOB due to partial compare", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "CounterMask": "1", - "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x8", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x0E", - "UMask": "0x10", - "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "UMask": "0x20", - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "UMask": "0x40", - "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x14", - "UMask": "0x1", "BriefDescription": "Cycles when divider is busy executing divide operations", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", "EventName": "ARITH.FPU_DIV_ACTIVE", "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Thread cycles when thread is not in halt state", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3c", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x3C", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4c", - "UMask": "0x1", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", - "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.SW_PF", - "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4C", - "UMask": "0x2", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", - "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.HW_PF", - "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x1", - "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x2", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x4", - "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x8", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "Invert": "1", - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_END", - "CounterMask": "1", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x87", - "UMask": "0x1", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "Counter": "0,1,2,3", - "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x41", - "BriefDescription": "Not taken macro-conditional branches", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken macro-conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired macro-conditional branches", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x82", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x90", - "BriefDescription": "Taken speculative and retired direct near calls", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and retired direct near calls.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired indirect calls", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired macro-conditional branches", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc2", - "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc4", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc8", - "BriefDescription": "Speculative and retired indirect return branches.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xd0", - "BriefDescription": "Speculative and retired direct near calls", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xff", "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x89", - "UMask": "0x41", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Speculative and retired macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc1" }, { - "EventCode": "0x89", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc2" }, { - "EventCode": "0x89", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xd0" }, { - "EventCode": "0x89", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x89", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "BriefDescription": "Speculative and retired indirect return branches.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc8" }, { - "EventCode": "0x89", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Not taken macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken macro-conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x89", - "UMask": "0xc4", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "BriefDescription": "Taken speculative and retired macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x89", - "UMask": "0xff", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x82" }, { - "EventCode": "0xA0", - "UMask": "0x3", - "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", + "BriefDescription": "Taken speculative and retired direct near calls", "Counter": "0,1,2,3", - "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", - "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in port 0", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in port 0", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in port 1", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per core when uops are exectuted in port 1.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in port 1", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per core when uops are dispatched to port 2.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in port 3", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per core when uops are dispatched to port 3.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in port 3", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per core when uops are exectuted in port 4.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in port 5", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per core when uops are exectuted in port 5.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in port 5", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in port 6", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per core when uops are exectuted in port 6.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in port 6", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in port 7", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per core when uops are dispatched to port 7.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in port 7", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x1", - "BriefDescription": "Resource-related stall cycles", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ANY", - "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x4", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.RS", - "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x8", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.SB", - "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x10", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ROB", - "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "CounterMask": "1", - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "CounterMask": "2", - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "CounterMask": "4", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "Total execution stalls.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "CounterMask": "5", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "CounterMask": "5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "CounterMask": "6", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "CounterMask": "6", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "CounterMask": "8", - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "CounterMask": "8", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "CounterMask": "12", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "CounterMask": "12", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Number of Uops delivered by the LSD.", - "Counter": "0,1,2,3", - "EventName": "LSD.UOPS", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_4_UOPS", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_ACTIVE", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.THREAD", - "PublicDescription": "Number of uops to be executed per-thread each cycle.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "CounterMask": "3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x2", - "BriefDescription": "Number of uops executed on the core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE", - "PublicDescription": "Number of uops executed from any thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "CounterMask": "3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "UMask": "0x0", - "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "Errata": "BDM61", - "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "UMask": "0x1", - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "PEBS": "2", - "Counter": "1", - "EventName": "INST_RETIRED.PREC_DIST", - "Errata": "BDM11, BDM55", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", - "SampleAfterValue": "2000003", - "CounterHTOff": "1" - }, - { - "EventCode": "0xC0", - "UMask": "0x2", - "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", - "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.X87", - "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "UMask": "0x40", - "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", - "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Actually retired uops. (Precise Event - PEBS)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.ALL", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles without actually retired uops.", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles without actually retired uops.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 10 actually retired uops.", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "CounterMask": "10", - "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC2", - "UMask": "0x2", - "BriefDescription": "Retirement slots used. (Precise Event - PEBS)", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.CYCLES", - "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.COUNT", - "CounterMask": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x4", - "BriefDescription": "Self-modifying code (SMC) detected.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x20", - "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MASKMOV", - "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x0", "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all (macro) branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "400009" }, { - "EventCode": "0xC4", - "UMask": "0x1", - "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x4", "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", - "PEBS": "2", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "CounterHTOff": "0,1,2,3", "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC4", - "UMask": "0x8", - "BriefDescription": "Return instructions retired. (Precise Event - PEBS)", - "PEBS": "1", + "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "This event counts far branch instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3).", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts return instructions retired.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { + "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC4", - "UMask": "0x10", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "PublicDescription": "This event counts not taken branch instructions retired.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xC4", - "UMask": "0x20", - "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS)", - "PEBS": "1", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0xC4", - "UMask": "0x40", - "BriefDescription": "Far branch instructions retired.", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "Errata": "BDW98", - "PublicDescription": "This event counts far branch instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0xC5", - "UMask": "0x0", "BriefDescription": "All mispredicted macro branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "400009" }, { - "EventCode": "0xC5", - "UMask": "0x1", - "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC5", - "UMask": "0x4", "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", - "PEBS": "2", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC5", - "UMask": "0x8", - "BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)", - "PEBS": "1", + "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS)", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.RET", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x20", "BriefDescription": "number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS).", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" + }, + { + "BriefDescription": "This event counts the number of mispredicted ret instructions retired.(Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "SampleAfterValue": "2000003" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM61", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "BDM11, BDM55", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", + "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "This event counts resource-related stall cycles. Reasons for stalls can be as follows:\n - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots)\n - *any* u-arch structure got empty (like INT/SIMD FreeLists)\n - FPU control word (FPCW), MXCSR\nand others. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xCC", - "UMask": "0x20", "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xe6", - "UMask": "0x1f", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", "Counter": "0,1,2,3", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Actually retired uops. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used. (Precise Event - PEBS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually retired uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json index 7d79c707c6d1..818a8b132c08 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json @@ -1,388 +1,388 @@ [ { - "EventCode": "0x08", - "UMask": "0x1", "BriefDescription": "Load misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x08", - "UMask": "0x2", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x4", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x8", - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0xe", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "Errata": "BDM69", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x20", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x40", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x60", "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x49", - "UMask": "0x1", - "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0x49", - "UMask": "0x2", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0x49", - "UMask": "0x4", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x49", - "UMask": "0x8", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0x49", - "UMask": "0xe", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x49", - "UMask": "0x10", "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0x49", - "UMask": "0x20", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", - "UMask": "0x40", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0x60", "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" + }, + { + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0x4F", - "UMask": "0x10", "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x85", - "UMask": "0x1", - "BriefDescription": "Misses at all ITLB levels that cause page walks", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x2", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x4", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x8", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0xe", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "Errata": "BDM69", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_DURATION", - "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x20", - "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_4K", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x40", - "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_2M", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x60", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xAE", - "UMask": "0x1", "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" + }, + { + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xBC", - "UMask": "0x11", "BriefDescription": "Number of DTLB page walker hits in the L1+FB.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xBC", - "UMask": "0x12", "BriefDescription": "Number of DTLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xBC", - "UMask": "0x14", "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "EventCode": "0xBC", - "UMask": "0x18", "BriefDescription": "Number of DTLB page walker hits in Memory.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "EventCode": "0xBC", - "UMask": "0x21", "BriefDescription": "Number of ITLB page walker hits in the L1+FB.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xBC", - "UMask": "0x22", "BriefDescription": "Number of ITLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x22" }, { - "EventCode": "0xBC", - "UMask": "0x24", "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "EventCode": "0xBD", - "UMask": "0x1", "BriefDescription": "DTLB flush attempts of the thread-specific entries", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", - "UMask": "0x20", "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json index 1eb0415fa11a..b055947c0afe 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json @@ -1,196 +1,170 @@ [ { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Instructions per Store (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * (4 * cycles) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", "MetricName": "Branch_Misprediction_Cost" }, { - "BriefDescription": "Branch Misprediction Cost: Fraction of TopDown slots wasted per non-speculative branch misprediction (jeclear)", - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts_SMT", + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", "MetricName": "Branch_Misprediction_Cost_SMT" }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -200,87 +174,196 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpFLOP" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Memory_Bound;Memory_BW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * cycles )", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) )", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -291,40 +374,52 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "1000000000 * ( cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@ ) / ( cbox_0@event\\=0x0@ / duration_time )", - "MetricGroup": "Memory_Lat", - "MetricName": "DRAM_Read_Latency" + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@", - "MetricGroup": "Memory_BW", - "MetricName": "DRAM_Parallel_Reads" + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "MEM_Parallel_Reads" }, { "BriefDescription": "Socket actual clocks when any core is active on that socket", "MetricExpr": "cbox_0@event\\=0x0@", - "MetricGroup": "", + "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json index 75a3098d5775..127abe08362f 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json @@ -1,966 +1,976 @@ [ { - "EventCode": "0x24", - "UMask": "0x21", - "BriefDescription": "Demand Data Read miss L2, no rejects", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x22", - "BriefDescription": "RFO requests that miss L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x24", - "BriefDescription": "L2 cache misses when fetching instructions.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x27", - "BriefDescription": "Demand requests that miss L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x30", - "BriefDescription": "L2 prefetch requests that miss L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_MISS", - "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x3f", - "BriefDescription": "All requests that miss L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.MISS", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xc1", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xc2", - "BriefDescription": "RFO requests that hit L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xc4", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xd0", - "BriefDescription": "L2 prefetch requests that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_HIT", - "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe1", - "BriefDescription": "Demand Data Read requests", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe2", - "BriefDescription": "RFO requests to L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_RFO", - "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe4", - "BriefDescription": "L2 code requests", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PublicDescription": "This event counts the total number of L2 code requests.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe7", - "BriefDescription": "Demand requests to L2 cache.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xf8", - "BriefDescription": "Requests from L2 hardware prefetchers", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_PF", - "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xff", - "BriefDescription": "All L2 requests.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.REFERENCES", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "UMask": "0x50", - "BriefDescription": "Not rejected writebacks that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", - "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "UMask": "0x41", - "BriefDescription": "Core-originated cacheable demand requests missed L3", - "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "UMask": "0x4f", - "BriefDescription": "Core-originated cacheable demand requests that refer to L3", - "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "L1D miss oustandings duration in cycles", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING", - "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x2", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", - "Counter": "0,1,2,3", - "EventName": "L1D_PEND_MISS.FB_FULL", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x51", - "UMask": "0x1", "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "CounterMask": "6", - "Errata": "BDM76", + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x2", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PublicDescription": "This event counts duration of L1D miss outstanding in cycles.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "Errata": "BDM76", - "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "Errata": "BDM76", - "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x63", - "UMask": "0x2", - "BriefDescription": "Cycles when L1D is locked", + "BriefDescription": "Not rejected writebacks that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests sent to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x2", - "BriefDescription": "Cacheable and noncachaeble code read requests", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x4", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x8", - "BriefDescription": "Demand and prefetch data reads", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb2", - "UMask": "0x1", - "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x11", - "BriefDescription": "Retired load uops that miss the STLB.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x12", - "BriefDescription": "Retired store uops that miss the STLB.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", - "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x21", - "BriefDescription": "Retired load uops with locked access.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "Errata": "BDM35", - "PublicDescription": "This event counts load uops with locked access retired to the architected path.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x41", - "BriefDescription": "Retired load uops that split across a cacheline boundary.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x42", - "BriefDescription": "Retired store uops that split across a cacheline boundary.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "SampleAfterValue": "100003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x81", - "BriefDescription": "All retired load uops.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x82", - "BriefDescription": "All retired store uops.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", - "SampleAfterValue": "2000003", - "L1_Hit_Indication": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x1", - "BriefDescription": "Retired load uops with L1 cache hits as data sources.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "PublicDescription": "This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x2", - "BriefDescription": "Retired load uops with L2 cache hits as data sources.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "Errata": "BDM35", - "PublicDescription": "This event counts retired load uops which data sources were hits in the mid-level (L2) cache.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", - "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x8", - "BriefDescription": "Retired load uops misses in L1 cache as data sources.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "PublicDescription": "This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x10", - "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "PublicDescription": "This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", - "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x20", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", - "Errata": "BDM100, BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x40", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "PublicDescription": "This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x1", - "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x2", - "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x8", - "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "Errata": "BDM100", - "PublicDescription": "This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x1", - "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "Errata": "BDE70, BDM100", - "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x4", - "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x10", - "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x20", - "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", - "Errata": "BDE70", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xF0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "This event counts the number of WB requests that hit L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x50" }, { - "EventCode": "0xF0", - "UMask": "0x2", - "BriefDescription": "RFO requests that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.RFO", - "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x4", - "BriefDescription": "L2 cache accesses when fetching instructions", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.CODE_RD", - "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x8", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_PF", - "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x10", - "BriefDescription": "L1D writebacks that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L1D_WB", - "PublicDescription": "This event counts L1D writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x20", - "BriefDescription": "L2 fill requests that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_FILL", - "PublicDescription": "This event counts L2 fill requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x40", - "BriefDescription": "L2 writebacks that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_WB", - "PublicDescription": "This event counts L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "UMask": "0x80", - "BriefDescription": "Transactions accessing L2 pipe", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_REQUESTS", - "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x1", - "BriefDescription": "L2 cache lines in I state filling L2", - "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.I", - "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x2", - "BriefDescription": "L2 cache lines in S state filling L2", - "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.S", - "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x4", - "BriefDescription": "L2 cache lines in E state filling L2", - "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.E", - "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x7", "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x7" + }, + { + "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xF2", - "UMask": "0x5", "BriefDescription": "Clean L2 cache lines evicted by demand.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "This event counts the total number of L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0xe1" + }, + { + "BriefDescription": "Demand requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "SampleAfterValue": "200003", + "UMask": "0x27" + }, + { + "BriefDescription": "Demand requests to L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xe7" + }, + { + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", + "SampleAfterValue": "200003", + "UMask": "0xf8" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "UMask": "0xe2" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "UMask": "0x24" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", + "SampleAfterValue": "200003", + "UMask": "0xd0" + }, + { + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x30" + }, + { + "BriefDescription": "All requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x3f" + }, + { + "BriefDescription": "All L2 requests.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "UMask": "0xc2" + }, + { + "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "UMask": "0x22" + }, + { + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "This event counts L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "This event counts L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "This event counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", + "SampleAfterValue": "100003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDE70, BDM100", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI).", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDE70", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were hits in the mid-level (L2) cache.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.", + "SampleAfterValue": "50021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM100, BDE70", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x20" + }, + { + "BriefDescription": "All retired load uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.", + "SampleAfterValue": "2000003", + "UMask": "0x81" + }, + { + "BriefDescription": "All retired store uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This event counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event counts AVX-256bit load/store double-pump memory uops as a single uop at retirement.", + "SampleAfterValue": "2000003", + "UMask": "0x82" + }, + { + "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "BDM35", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts load uops with locked access retired to the architected path.", + "SampleAfterValue": "100007", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "SampleAfterValue": "100003", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Cacheable and noncachaeble code read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM76", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C07F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C07F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all requests hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C8FFF", + "Offcore": "1", + "PublicDescription": "Counts all requests hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xf4", - "UMask": "0x10", "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "This event counts the number of split locks in the super queue.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests hit in the L3", - "MSRValue": "0x3F803C8FFF", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C07F7", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C07F7", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0244", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0122", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0122", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0091", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0091", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", - "MSRValue": "0x3F803C0200", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", - "MSRValue": "0x3F803C0100", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0002", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3", - "MSRValue": "0x3F803C0002", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json index ba0e0c4e74eb..9ad37dddb354 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json @@ -1,165 +1,193 @@ [ { - "EventCode": "0xC1", - "UMask": "0x8", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", - "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "UMask": "0x10", - "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", - "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "Errata": "BDM30", - "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC7", - "UMask": "0x1", - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC7", - "UMask": "0x2", - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC7", - "UMask": "0x3", - "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single precision?)", - "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC7", - "UMask": "0x4", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC7", - "UMask": "0x8", - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xC7", - "UMask": "0x10", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xC7", - "UMask": "0x15", - "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", - "SampleAfterValue": "2000006", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xc7", - "UMask": "0x20", - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", - "Counter": "0,1,2,3", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xC7", - "UMask": "0x2a", - "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ARITH_INST_RETIRED.SINGLE", - "SampleAfterValue": "2000005", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", + "SampleAfterValue": "2000006", + "UMask": "0x15" }, { - "EventCode": "0xC7", - "UMask": "0x3c", - "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. (RSQRT for single-precision?)", + "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.PACKED", "SampleAfterValue": "2000004", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3c" }, { - "EventCode": "0xCA", - "UMask": "0x2", - "BriefDescription": "Number of X87 assists due to output value.", + "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation operation. Applies to SSE* and AVX* scalar double and single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_OUTPUT", - "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "EventCode": "0xCA", - "UMask": "0x4", - "BriefDescription": "Number of X87 assists due to input value.", + "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_INPUT", - "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xCA", - "UMask": "0x8", - "BriefDescription": "Number of SIMD FP assists due to Output values", + "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { + "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SINGLE", + "SampleAfterValue": "2000005", + "UMask": "0x2a" + }, + { + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xCA", - "UMask": "0x10", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "SampleAfterValue": "100003", + "UMask": "0x1e" + }, + { "BriefDescription": "Number of SIMD FP assists due to input values", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xCA", - "UMask": "0x1e", - "BriefDescription": "Cycles with any input/output SSE or FP assist", + "BriefDescription": "Number of SIMD FP assists due to Output values", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.ANY", - "CounterMask": "1", - "PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM30", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xA0", + "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", + "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", + "SampleAfterValue": "2000003", + "UMask": "0x3" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json index 72781e1e3362..f0bcb945ff76 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json @@ -1,286 +1,295 @@ [ { - "EventCode": "0x79", - "UMask": "0x2", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "EventName": "IDQ.EMPTY", - "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_UOPS", - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_UOPS", - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_UOPS", - "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_OCCUR", - "CounterMask": "1", - "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x20", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering any Uop", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_SWITCHES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x3c", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_ALL_UOPS", - "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "UMask": "0x1", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", - "Counter": "0,1,2,3", - "EventName": "ICACHE.HIT", - "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "UMask": "0x2", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", - "Counter": "0,1,2,3", - "EventName": "ICACHE.MISSES", - "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "UMask": "0x4", - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", - "Counter": "0,1,2,3", - "EventName": "ICACHE.IFDATA_STALL", - "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "CounterMask": "4", - "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", - "CounterMask": "3", - "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xAB", - "UMask": "0x2", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" + }, + { + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", + "PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json index ecb413bb67ca..cce993b197e3 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json @@ -1,679 +1,687 @@ [ { - "EventCode": "0x05", - "UMask": "0x1", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOADS", - "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "UMask": "0x2", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORES", - "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x1", - "BriefDescription": "Number of times a TSX line had a cache conflict", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Number of times a TSX line had a cache conflict.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x2", - "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x4", - "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x8", - "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x10", - "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x20", - "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x40", - "BriefDescription": "Number of times we could not allocate Lock Buffer", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PublicDescription": "Number of times we could not allocate Lock Buffer.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x1", - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x2", - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC2", - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x4", - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC3", - "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x8", - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC4", - "PublicDescription": "RTM region detected inside HLE.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x10", - "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x2", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.START", - "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x2", - "BriefDescription": "Number of times HLE commit succeeded", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.COMMIT", - "PublicDescription": "Number of times HLE commit succeeded.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x4", "BriefDescription": "Number of times HLE abort was triggered", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", "PublicDescription": "Number of times HLE abort was triggered.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xc8", - "UMask": "0x8", "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xc8", - "UMask": "0x10", "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xc8", - "UMask": "0x20", "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation caused an HLE abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xc8", - "UMask": "0x40", "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times HLE caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xc8", - "UMask": "0x80", "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0xc9", - "UMask": "0x1", - "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", + "BriefDescription": "Number of times HLE commit succeeded", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x2", - "BriefDescription": "Number of times RTM commit succeeded", + "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.COMMIT", - "PublicDescription": "Number of times RTM commit succeeded.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 128", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 128.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 16", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 16.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 256", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 256.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 32", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 32.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 4", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above four.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 512", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 512.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 64", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above 64.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 8", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "BDM100, BDM35", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads with latency value being above eight.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0604000244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0604000091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x063BC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x087FC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch)miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x06040007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch)miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x063BC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x087FC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all requests miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC08FFF", + "Offcore": "1", + "PublicDescription": "Counts all requests miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0604000122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x4", "BriefDescription": "Number of times RTM abort was triggered", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", "PublicDescription": "Number of times RTM abort was triggered .", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xc9", - "UMask": "0x8", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xc9", - "UMask": "0x10", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xc9", - "UMask": "0x20", "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation caused an RTM abort.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xc9", - "UMask": "0x40", "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times a RTM caused a fault.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "EventCode": "0xc9", - "UMask": "0x80", "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 4", - "PEBS": "2", - "MSRValue": "0x4", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above four.", - "TakenAlone": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 8", - "PEBS": "2", - "MSRValue": "0x8", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above eight.", - "TakenAlone": "1", - "SampleAfterValue": "50021", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 16", - "PEBS": "2", - "MSRValue": "0x10", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 16.", - "TakenAlone": "1", - "SampleAfterValue": "20011", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 32", - "PEBS": "2", - "MSRValue": "0x20", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 32.", - "TakenAlone": "1", - "SampleAfterValue": "100007", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 64", - "PEBS": "2", - "MSRValue": "0x40", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 64.", - "TakenAlone": "1", - "SampleAfterValue": "2003", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 128", - "PEBS": "2", - "MSRValue": "0x80", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 128.", - "TakenAlone": "1", - "SampleAfterValue": "1009", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 256", - "PEBS": "2", - "MSRValue": "0x100", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 256.", - "TakenAlone": "1", - "SampleAfterValue": "503", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 512", - "PEBS": "2", - "MSRValue": "0x200", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "Errata": "BDM100, BDM35", - "PublicDescription": "Counts randomly selected loads with latency value being above 512.", - "TakenAlone": "1", - "SampleAfterValue": "101", - "CounterHTOff": "3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests miss in the L3", - "MSRValue": "0x3FBFC08FFF", + "BriefDescription": "Number of times RTM commit succeeded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x087FC007F7", + "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC007F7", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063BC007F7", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", - "MSRValue": "0x06040007F7", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", - "MSRValue": "0x3FBFC007F7", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", - "MSRValue": "0x0604000244", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", - "MSRValue": "0x3FBFC00244", + "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", - "MSRValue": "0x0604000122", + "BriefDescription": "Number of times a TSX line had a cache conflict", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", - "MSRValue": "0x3FBFC00122", + "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x087FC00091", + "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00091", + "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063BC00091", + "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", - "MSRValue": "0x0604000091", + "BriefDescription": "Number of times we could not allocate Lock Buffer", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", - "MSRValue": "0x3FBFC00091", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", - "MSRValue": "0x3FBFC00200", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", - "MSRValue": "0x3FBFC00100", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00002", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", - "MSRValue": "0x3FBFC00002", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PublicDescription": "Number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/other.json b/tools/perf/pmu-events/arch/x86/broadwellx/other.json index 4475249ea9da..4b360fe96698 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/other.json @@ -1,44 +1,44 @@ [ { - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EdgeDetect": "1", - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", "Counter": "0,1,2,3", - "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", - "UMask": "0x2", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", - "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json index c2f6932a5817..18d21b94a4b9 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json @@ -1,1423 +1,1380 @@ [ { - "UMask": "0x1", - "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "EventName": "INST_RETIRED.ANY", - "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 0" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when the thread is not in halt state", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x3", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "Counter": "Fixed counter 2", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 2" - }, - { - "EventCode": "0x03", - "UMask": "0x2", - "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "UMask": "0x8", - "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x07", - "UMask": "0x1", - "BriefDescription": "False dependencies in MOB due to partial compare", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "CounterMask": "1", - "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x8", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x0E", - "UMask": "0x10", - "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "UMask": "0x20", - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "UMask": "0x40", - "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x14", - "UMask": "0x1", "BriefDescription": "Cycles when divider is busy executing divide operations", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", "EventName": "ARITH.FPU_DIV_ACTIVE", "PublicDescription": "This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Thread cycles when thread is not in halt state", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3c", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x3C", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4c", - "UMask": "0x1", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", - "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.SW_PF", - "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4C", - "UMask": "0x2", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", - "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.HW_PF", - "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x1", - "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x2", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x4", - "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x8", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "Invert": "1", - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_END", - "CounterMask": "1", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x87", - "UMask": "0x1", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "Counter": "0,1,2,3", - "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x41", - "BriefDescription": "Not taken macro-conditional branches", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken macro-conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired macro-conditional branches", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x82", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x90", - "BriefDescription": "Taken speculative and retired direct near calls", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and retired direct near calls.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired indirect calls", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired macro-conditional branches", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc2", - "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc4", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc8", - "BriefDescription": "Speculative and retired indirect return branches.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xd0", - "BriefDescription": "Speculative and retired direct near calls", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xff", "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken speculative and retired branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x89", - "UMask": "0x41", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Speculative and retired macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc1" }, { - "EventCode": "0x89", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc2" }, { - "EventCode": "0x89", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts both taken and not taken speculative and retired direct near calls.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xd0" }, { - "EventCode": "0x89", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x89", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "BriefDescription": "Speculative and retired indirect return branches.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc8" }, { - "EventCode": "0x89", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Not taken macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken macro-conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x89", - "UMask": "0xc4", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "BriefDescription": "Taken speculative and retired macro-conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x89", - "UMask": "0xff", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x82" }, { - "EventCode": "0xA0", - "UMask": "0x3", - "BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports", + "BriefDescription": "Taken speculative and retired direct near calls", "Counter": "0,1,2,3", - "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", - "PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in port 0", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired indirect branches excluding calls and return branches.", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "This event counts taken speculative and retired indirect calls including both register and memory indirect.", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in port 0", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "This event counts taken speculative and retired indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in port 1", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per core when uops are exectuted in port 1.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in port 1", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per core when uops are dispatched to port 2.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in port 3", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per core when uops are dispatched to port 3.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in port 3", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per core when uops are exectuted in port 4.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in port 5", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per core when uops are exectuted in port 5.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in port 5", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in port 6", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per core when uops are exectuted in port 6.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in port 6", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in port 7", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per core when uops are dispatched to port 7.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in port 7", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xa2", - "UMask": "0x1", - "BriefDescription": "Resource-related stall cycles", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ANY", - "PublicDescription": "This event counts resource-related stall cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x4", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.RS", - "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x8", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.SB", - "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x10", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ROB", - "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "CounterMask": "1", - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "CounterMask": "2", - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "CounterMask": "4", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "Total execution stalls.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "CounterMask": "5", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "CounterMask": "5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "CounterMask": "6", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "CounterMask": "6", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "CounterMask": "8", - "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "CounterMask": "8", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "CounterMask": "12", - "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "CounterMask": "12", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Number of Uops delivered by the LSD.", - "Counter": "0,1,2,3", - "EventName": "LSD.UOPS", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_4_UOPS", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_ACTIVE", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.THREAD", - "PublicDescription": "Number of uops to be executed per-thread each cycle.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "CounterMask": "3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x2", - "BriefDescription": "Number of uops executed on the core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE", - "PublicDescription": "Number of uops executed from any thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "CounterMask": "2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "CounterMask": "3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "UMask": "0x0", - "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "Errata": "BDM61", - "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "UMask": "0x1", - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "PEBS": "2", - "Counter": "1", - "EventName": "INST_RETIRED.PREC_DIST", - "Errata": "BDM11, BDM55", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", - "SampleAfterValue": "2000003", - "CounterHTOff": "1" - }, - { - "EventCode": "0xC0", - "UMask": "0x2", - "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", - "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.X87", - "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "UMask": "0x40", - "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", - "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Actually retired uops.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.ALL", - "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles without actually retired uops.", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles without actually retired uops.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 10 actually retired uops.", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "CounterMask": "10", - "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC2", - "UMask": "0x2", - "BriefDescription": "Retirement slots used.", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "PublicDescription": "This event counts the number of retirement slots used.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.CYCLES", - "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.COUNT", - "CounterMask": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x4", - "BriefDescription": "Self-modifying code (SMC) detected.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x20", - "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MASKMOV", - "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x0", "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all (macro) branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "400009" }, { - "EventCode": "0xC4", - "UMask": "0x1", - "BriefDescription": "Conditional branch instructions retired.", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "PublicDescription": "This event counts conditional branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect near call instructions retired.", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PublicDescription": "This event counts both direct and indirect near call instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "PublicDescription": "This event counts both direct and indirect macro near call instructions retired (captured in ring 3).", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x4", "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS)", - "PEBS": "2", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "CounterHTOff": "0,1,2,3", "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC4", - "UMask": "0x8", - "BriefDescription": "Return instructions retired.", - "PEBS": "1", + "BriefDescription": "Conditional branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDW98", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "This event counts far branch instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Direct and indirect near call instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect near call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect macro near call instructions retired (captured in ring 3).", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", "PublicDescription": "This event counts return instructions retired.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { + "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC4", - "UMask": "0x10", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "This event counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { "BriefDescription": "Not taken branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "PublicDescription": "This event counts not taken branch instructions retired.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xC4", - "UMask": "0x20", - "BriefDescription": "Taken branch instructions retired.", - "PEBS": "1", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PublicDescription": "This event counts taken branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0xC4", - "UMask": "0x40", - "BriefDescription": "Far branch instructions retired.", + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "Errata": "BDW98", - "PublicDescription": "This event counts far branch instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts both taken and not taken mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "This event counts not taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "This event counts taken speculative and retired mispredicted macro conditional branch instructions.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0xC5", - "UMask": "0x0", "BriefDescription": "All mispredicted macro branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all mispredicted macro branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "400009" }, { - "EventCode": "0xC5", - "UMask": "0x1", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC5", - "UMask": "0x4", "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", - "PEBS": "2", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC5", - "UMask": "0x8", - "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", - "PEBS": "1", + "BriefDescription": "Mispredicted conditional branch instructions retired.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.RET", - "PublicDescription": "This event counts mispredicted return instructions retired.", - "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" }, { - "EventCode": "0xC5", - "UMask": "0x20", "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", "PublicDescription": "Number of near branch instructions retired that were mispredicted and taken.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" + }, + { + "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "SampleAfterValue": "2000003" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM61", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "BDM11, BDM55", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts instructions retired.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions:", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "PublicDescription": "This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", + "PublicDescription": "This event counts both thread-specific (TS) and all-thread (AT) nukes.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "This event counts resource-related stall cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "PublicDescription": "This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "PublicDescription": "This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xCC", - "UMask": "0x20", "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xe6", - "UMask": "0x1f", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", "Counter": "0,1,2,3", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are exectuted in port 6.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually retired uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json index 7d79c707c6d1..818a8b132c08 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json @@ -1,388 +1,388 @@ [ { - "EventCode": "0x08", - "UMask": "0x1", "BriefDescription": "Load misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x08", - "UMask": "0x2", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x4", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x8", - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0xe", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "Errata": "BDM69", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x20", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x40", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x60", "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x49", - "UMask": "0x1", - "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "SampleAfterValue": "2000003", + "UMask": "0x40" }, { - "EventCode": "0x49", - "UMask": "0x2", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "EventCode": "0x49", - "UMask": "0x4", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x49", - "UMask": "0x8", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0x49", - "UMask": "0xe", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "EventCode": "0x49", - "UMask": "0x10", "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "BDM69", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0x49", - "UMask": "0x20", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", - "UMask": "0x40", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0x60", "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" + }, + { + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0x4F", - "UMask": "0x10", "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x85", - "UMask": "0x1", - "BriefDescription": "Misses at all ITLB levels that cause page walks", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x2", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x4", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x8", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", - "Errata": "BDM69", - "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0xe", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "Errata": "BDM69", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_DURATION", - "Errata": "BDM69", - "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x20", - "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_4K", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x40", - "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_2M", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x60", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xAE", - "UMask": "0x1", "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" + }, + { + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "BDM69", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xBC", - "UMask": "0x11", "BriefDescription": "Number of DTLB page walker hits in the L1+FB.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xBC", - "UMask": "0x12", "BriefDescription": "Number of DTLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xBC", - "UMask": "0x14", "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "EventCode": "0xBC", - "UMask": "0x18", "BriefDescription": "Number of DTLB page walker hits in Memory.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "EventCode": "0xBC", - "UMask": "0x21", "BriefDescription": "Number of ITLB page walker hits in the L1+FB.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xBC", - "UMask": "0x22", "BriefDescription": "Number of ITLB page walker hits in the L2.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x22" }, { - "EventCode": "0xBC", - "UMask": "0x24", "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "BDM69, BDM98", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "EventCode": "0xBD", - "UMask": "0x1", "BriefDescription": "DTLB flush attempts of the thread-specific entries", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", - "UMask": "0x20", "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", "SampleAfterValue": "100007", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json index ffafb9f284d2..aa906a7fa520 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json @@ -314,6 +314,19 @@ "SampleAfterValue": "2000003", "UMask": "0x82" }, + { + "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "SampleAfterValue": "2000003", + "UMask": "0x83" + }, { "BriefDescription": "Retired load instructions with locked access.", "Counter": "0,1,2,3", @@ -358,6 +371,7 @@ "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x11" }, @@ -370,6 +384,7 @@ "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", "L1_Hit_Indication": "1", "PEBS": "1", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x12" }, @@ -587,6 +602,6558 @@ "SampleAfterValue": "100003", "UMask": "0x80" }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100491", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100490", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100120", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C07F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C07F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C07F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C07F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C07F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C07F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C07F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C07F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F800807F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10000807F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8000807F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4000807F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000807F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000807F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800807F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F802007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8002007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4002007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F800407F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10000407F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8000407F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4000407F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000407F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000407F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800407F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F801007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8001007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801007F7", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100122", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80208000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000208000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800208000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400208000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100208000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200208000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80208000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100010", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100020", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100080", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8007C0100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803C0100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80080100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800080100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80200100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000200100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800200100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400200100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100200100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200200100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80200100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80040100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800040100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F80100100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800100100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100100", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Demand and prefetch data reads", "Counter": "0,1,2,3", @@ -759,7 +7326,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010491", + "MSRValue": "0x10491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -801,7 +7368,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0491", + "MSRValue": "0x8003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -815,7 +7382,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0491", + "MSRValue": "0x4003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -829,7 +7396,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0491", + "MSRValue": "0x1003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -843,7 +7410,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0491", + "MSRValue": "0x8007C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -857,7 +7424,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0491", + "MSRValue": "0x2003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -871,7 +7438,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0491", + "MSRValue": "0x803C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -913,7 +7480,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080491", + "MSRValue": "0x800080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -927,7 +7494,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080491", + "MSRValue": "0x400080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -941,7 +7508,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080491", + "MSRValue": "0x100080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -955,7 +7522,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080491", + "MSRValue": "0x200080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -969,7 +7536,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080491", + "MSRValue": "0x80080491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1011,7 +7578,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200491", + "MSRValue": "0x800200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1025,7 +7592,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200491", + "MSRValue": "0x400200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1039,7 +7606,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200491", + "MSRValue": "0x100200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1053,7 +7620,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200491", + "MSRValue": "0x200200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1067,7 +7634,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200491", + "MSRValue": "0x80200491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1109,7 +7676,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040491", + "MSRValue": "0x800040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1123,7 +7690,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040491", + "MSRValue": "0x400040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1137,7 +7704,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040491", + "MSRValue": "0x100040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1151,7 +7718,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040491", + "MSRValue": "0x200040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1165,7 +7732,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040491", + "MSRValue": "0x80040491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1207,7 +7774,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100491", + "MSRValue": "0x800100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1221,7 +7788,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100491", + "MSRValue": "0x400100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1235,7 +7802,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100491", + "MSRValue": "0x100100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1249,7 +7816,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100491", + "MSRValue": "0x200100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1263,7 +7830,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100491", + "MSRValue": "0x80100491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1291,7 +7858,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400491", + "MSRValue": "0x80400491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1305,7 +7872,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400491", + "MSRValue": "0x100400491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1347,7 +7914,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020491", + "MSRValue": "0x800020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1361,7 +7928,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020491", + "MSRValue": "0x400020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1375,7 +7942,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020491", + "MSRValue": "0x100020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1389,7 +7956,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020491", + "MSRValue": "0x200020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1403,7 +7970,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020491", + "MSRValue": "0x80020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1417,7 +7984,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010490", + "MSRValue": "0x10490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1459,7 +8026,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0490", + "MSRValue": "0x8003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1473,7 +8040,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0490", + "MSRValue": "0x4003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1487,7 +8054,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0490", + "MSRValue": "0x1003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1501,7 +8068,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0490", + "MSRValue": "0x8007C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1515,7 +8082,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0490", + "MSRValue": "0x2003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1529,7 +8096,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0490", + "MSRValue": "0x803C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1571,7 +8138,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080490", + "MSRValue": "0x800080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1585,7 +8152,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080490", + "MSRValue": "0x400080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1599,7 +8166,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080490", + "MSRValue": "0x100080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1613,7 +8180,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080490", + "MSRValue": "0x200080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1627,7 +8194,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080490", + "MSRValue": "0x80080490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1669,7 +8236,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200490", + "MSRValue": "0x800200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1683,7 +8250,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200490", + "MSRValue": "0x400200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1697,7 +8264,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200490", + "MSRValue": "0x100200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1711,7 +8278,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200490", + "MSRValue": "0x200200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1725,7 +8292,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200490", + "MSRValue": "0x80200490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1767,7 +8334,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040490", + "MSRValue": "0x800040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1781,7 +8348,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040490", + "MSRValue": "0x400040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1795,7 +8362,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040490", + "MSRValue": "0x100040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1809,7 +8376,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040490", + "MSRValue": "0x200040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1823,7 +8390,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040490", + "MSRValue": "0x80040490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1865,7 +8432,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100490", + "MSRValue": "0x800100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1879,7 +8446,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100490", + "MSRValue": "0x400100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1893,7 +8460,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100490", + "MSRValue": "0x100100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1907,7 +8474,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100490", + "MSRValue": "0x200100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1921,7 +8488,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100490", + "MSRValue": "0x80100490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1949,7 +8516,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400490", + "MSRValue": "0x80400490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1963,7 +8530,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400490", + "MSRValue": "0x100400490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2005,7 +8572,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020490", + "MSRValue": "0x800020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2019,7 +8586,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020490", + "MSRValue": "0x400020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2033,7 +8600,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020490", + "MSRValue": "0x100020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2047,7 +8614,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020490", + "MSRValue": "0x200020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2061,7 +8628,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020490", + "MSRValue": "0x80020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2075,7 +8642,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010120", + "MSRValue": "0x10120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2117,7 +8684,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0120", + "MSRValue": "0x8003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2131,7 +8698,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0120", + "MSRValue": "0x4003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2145,7 +8712,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", + "MSRValue": "0x1003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2159,7 +8726,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0120", + "MSRValue": "0x8007C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2173,7 +8740,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0120", + "MSRValue": "0x2003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2187,7 +8754,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0120", + "MSRValue": "0x803C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2229,7 +8796,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080120", + "MSRValue": "0x800080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2243,7 +8810,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080120", + "MSRValue": "0x400080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2257,7 +8824,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080120", + "MSRValue": "0x100080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2271,7 +8838,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080120", + "MSRValue": "0x200080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2285,7 +8852,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080120", + "MSRValue": "0x80080120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2327,7 +8894,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200120", + "MSRValue": "0x800200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2341,7 +8908,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200120", + "MSRValue": "0x400200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2355,7 +8922,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200120", + "MSRValue": "0x100200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2369,7 +8936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200120", + "MSRValue": "0x200200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2383,7 +8950,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200120", + "MSRValue": "0x80200120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2425,7 +8992,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040120", + "MSRValue": "0x800040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2439,7 +9006,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040120", + "MSRValue": "0x400040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2453,7 +9020,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040120", + "MSRValue": "0x100040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2467,7 +9034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040120", + "MSRValue": "0x200040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2481,7 +9048,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040120", + "MSRValue": "0x80040120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2523,7 +9090,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100120", + "MSRValue": "0x800100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2537,7 +9104,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100120", + "MSRValue": "0x400100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2551,7 +9118,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100120", + "MSRValue": "0x100100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2565,7 +9132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100120", + "MSRValue": "0x200100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2579,7 +9146,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100120", + "MSRValue": "0x80100120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2607,7 +9174,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400120", + "MSRValue": "0x80400120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2621,7 +9188,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400120", + "MSRValue": "0x100400120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2663,7 +9230,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020120", + "MSRValue": "0x800020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2677,7 +9244,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020120", + "MSRValue": "0x400020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2691,7 +9258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020120", + "MSRValue": "0x100020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2705,7 +9272,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020120", + "MSRValue": "0x200020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2719,7 +9286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020120", + "MSRValue": "0x80020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2733,7 +9300,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00000107F7", + "MSRValue": "0x107F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2775,7 +9342,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C07F7", + "MSRValue": "0x8003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2789,7 +9356,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C07F7", + "MSRValue": "0x4003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2803,7 +9370,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C07F7", + "MSRValue": "0x1003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2817,7 +9384,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C07F7", + "MSRValue": "0x8007C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2831,7 +9398,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C07F7", + "MSRValue": "0x2003C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2845,7 +9412,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C07F7", + "MSRValue": "0x803C07F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2887,7 +9454,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000807F7", + "MSRValue": "0x8000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2901,7 +9468,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000807F7", + "MSRValue": "0x4000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2915,7 +9482,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000807F7", + "MSRValue": "0x1000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2929,7 +9496,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000807F7", + "MSRValue": "0x2000807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2943,7 +9510,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800807F7", + "MSRValue": "0x800807F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2985,7 +9552,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08002007F7", + "MSRValue": "0x8002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2999,7 +9566,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04002007F7", + "MSRValue": "0x4002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3013,7 +9580,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01002007F7", + "MSRValue": "0x1002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3027,7 +9594,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02002007F7", + "MSRValue": "0x2002007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3041,7 +9608,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00802007F7", + "MSRValue": "0x802007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3083,7 +9650,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000407F7", + "MSRValue": "0x8000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3097,7 +9664,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000407F7", + "MSRValue": "0x4000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3111,7 +9678,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000407F7", + "MSRValue": "0x1000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3125,7 +9692,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000407F7", + "MSRValue": "0x2000407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3139,7 +9706,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800407F7", + "MSRValue": "0x800407F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3181,7 +9748,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08001007F7", + "MSRValue": "0x8001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3195,7 +9762,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001007F7", + "MSRValue": "0x4001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3209,7 +9776,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001007F7", + "MSRValue": "0x1001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3223,7 +9790,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001007F7", + "MSRValue": "0x2001007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3237,7 +9804,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801007F7", + "MSRValue": "0x801007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3265,7 +9832,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00804007F7", + "MSRValue": "0x804007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3279,7 +9846,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01004007F7", + "MSRValue": "0x1004007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3321,7 +9888,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000207F7", + "MSRValue": "0x8000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3335,7 +9902,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000207F7", + "MSRValue": "0x4000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3349,7 +9916,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000207F7", + "MSRValue": "0x1000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3363,7 +9930,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000207F7", + "MSRValue": "0x2000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3377,7 +9944,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800207F7", + "MSRValue": "0x800207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3391,7 +9958,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010122", + "MSRValue": "0x10122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3433,7 +10000,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0122", + "MSRValue": "0x8003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3447,7 +10014,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0122", + "MSRValue": "0x4003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3461,7 +10028,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", + "MSRValue": "0x1003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3475,7 +10042,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0122", + "MSRValue": "0x8007C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3489,7 +10056,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0122", + "MSRValue": "0x2003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3503,7 +10070,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0122", + "MSRValue": "0x803C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3545,7 +10112,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080122", + "MSRValue": "0x800080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3559,7 +10126,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080122", + "MSRValue": "0x400080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3573,7 +10140,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080122", + "MSRValue": "0x100080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3587,7 +10154,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080122", + "MSRValue": "0x200080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3601,7 +10168,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080122", + "MSRValue": "0x80080122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3643,7 +10210,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200122", + "MSRValue": "0x800200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3657,7 +10224,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200122", + "MSRValue": "0x400200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3671,7 +10238,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200122", + "MSRValue": "0x100200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3685,7 +10252,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200122", + "MSRValue": "0x200200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3699,7 +10266,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200122", + "MSRValue": "0x80200122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3741,7 +10308,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040122", + "MSRValue": "0x800040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3755,7 +10322,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040122", + "MSRValue": "0x400040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3769,7 +10336,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040122", + "MSRValue": "0x100040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3783,7 +10350,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040122", + "MSRValue": "0x200040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3797,7 +10364,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040122", + "MSRValue": "0x80040122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3839,7 +10406,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100122", + "MSRValue": "0x800100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3853,7 +10420,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100122", + "MSRValue": "0x400100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3867,7 +10434,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100122", + "MSRValue": "0x100100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3881,7 +10448,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100122", + "MSRValue": "0x200100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3895,7 +10462,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100122", + "MSRValue": "0x80100122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3923,7 +10490,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400122", + "MSRValue": "0x80400122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3937,7 +10504,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400122", + "MSRValue": "0x100400122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3979,7 +10546,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020122", + "MSRValue": "0x800020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3993,7 +10560,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020122", + "MSRValue": "0x400020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4007,7 +10574,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020122", + "MSRValue": "0x100020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4021,7 +10588,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020122", + "MSRValue": "0x200020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4035,7 +10602,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020122", + "MSRValue": "0x80020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4049,7 +10616,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", + "MSRValue": "0x10004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4091,7 +10658,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0004", + "MSRValue": "0x8003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4105,7 +10672,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x4003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4119,7 +10686,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", + "MSRValue": "0x1003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4133,7 +10700,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0004", + "MSRValue": "0x8007C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4147,7 +10714,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0004", + "MSRValue": "0x2003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4161,7 +10728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0004", + "MSRValue": "0x803C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4203,7 +10770,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080004", + "MSRValue": "0x800080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4217,7 +10784,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080004", + "MSRValue": "0x400080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4231,7 +10798,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080004", + "MSRValue": "0x100080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4245,7 +10812,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080004", + "MSRValue": "0x200080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4259,7 +10826,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080004", + "MSRValue": "0x80080004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4301,7 +10868,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200004", + "MSRValue": "0x800200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4315,7 +10882,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200004", + "MSRValue": "0x400200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4329,7 +10896,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200004", + "MSRValue": "0x100200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4343,7 +10910,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200004", + "MSRValue": "0x200200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4357,7 +10924,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200004", + "MSRValue": "0x80200004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4399,7 +10966,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040004", + "MSRValue": "0x800040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4413,7 +10980,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040004", + "MSRValue": "0x400040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4427,7 +10994,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040004", + "MSRValue": "0x100040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4441,7 +11008,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040004", + "MSRValue": "0x200040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4455,7 +11022,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040004", + "MSRValue": "0x80040004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4497,7 +11064,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100004", + "MSRValue": "0x800100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4511,7 +11078,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100004", + "MSRValue": "0x400100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4525,7 +11092,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100004", + "MSRValue": "0x100100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4539,7 +11106,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100004", + "MSRValue": "0x200100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4553,7 +11120,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100004", + "MSRValue": "0x80100004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4581,7 +11148,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400004", + "MSRValue": "0x80400004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4595,7 +11162,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400004", + "MSRValue": "0x100400004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4637,7 +11204,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020004", + "MSRValue": "0x800020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4651,7 +11218,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020004", + "MSRValue": "0x400020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4665,7 +11232,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020004", + "MSRValue": "0x100020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4679,7 +11246,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020004", + "MSRValue": "0x200020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4693,7 +11260,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020004", + "MSRValue": "0x80020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4707,7 +11274,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x10001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4749,7 +11316,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0001", + "MSRValue": "0x8003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4763,7 +11330,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x4003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4777,7 +11344,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", + "MSRValue": "0x1003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4791,7 +11358,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0001", + "MSRValue": "0x8007C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4805,7 +11372,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0001", + "MSRValue": "0x2003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4819,7 +11386,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0001", + "MSRValue": "0x803C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4861,7 +11428,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080001", + "MSRValue": "0x800080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4875,7 +11442,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080001", + "MSRValue": "0x400080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4889,7 +11456,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080001", + "MSRValue": "0x100080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4903,7 +11470,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080001", + "MSRValue": "0x200080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4917,7 +11484,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080001", + "MSRValue": "0x80080001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4959,7 +11526,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200001", + "MSRValue": "0x800200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4973,7 +11540,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200001", + "MSRValue": "0x400200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4987,7 +11554,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200001", + "MSRValue": "0x100200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5001,7 +11568,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200001", + "MSRValue": "0x200200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5015,7 +11582,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200001", + "MSRValue": "0x80200001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5057,7 +11624,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040001", + "MSRValue": "0x800040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5071,7 +11638,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040001", + "MSRValue": "0x400040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5085,7 +11652,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040001", + "MSRValue": "0x100040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5099,7 +11666,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040001", + "MSRValue": "0x200040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5113,7 +11680,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040001", + "MSRValue": "0x80040001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5155,7 +11722,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100001", + "MSRValue": "0x800100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5169,7 +11736,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100001", + "MSRValue": "0x400100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5183,7 +11750,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100001", + "MSRValue": "0x100100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5197,7 +11764,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100001", + "MSRValue": "0x200100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5211,7 +11778,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100001", + "MSRValue": "0x80100001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5239,7 +11806,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400001", + "MSRValue": "0x80400001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5253,7 +11820,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400001", + "MSRValue": "0x100400001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5295,7 +11862,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020001", + "MSRValue": "0x800020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5309,7 +11876,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020001", + "MSRValue": "0x400020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5323,7 +11890,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020001", + "MSRValue": "0x100020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5337,7 +11904,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020001", + "MSRValue": "0x200020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5351,7 +11918,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020001", + "MSRValue": "0x80020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5365,7 +11932,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x10002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5407,7 +11974,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0002", + "MSRValue": "0x8003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5421,7 +11988,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x4003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5435,7 +12002,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", + "MSRValue": "0x1003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5449,7 +12016,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0002", + "MSRValue": "0x8007C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5463,7 +12030,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0002", + "MSRValue": "0x2003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5477,7 +12044,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0002", + "MSRValue": "0x803C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5519,7 +12086,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080002", + "MSRValue": "0x800080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5533,7 +12100,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080002", + "MSRValue": "0x400080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5547,7 +12114,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080002", + "MSRValue": "0x100080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5561,7 +12128,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080002", + "MSRValue": "0x200080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5575,7 +12142,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080002", + "MSRValue": "0x80080002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5617,7 +12184,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200002", + "MSRValue": "0x800200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5631,7 +12198,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200002", + "MSRValue": "0x400200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5645,7 +12212,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200002", + "MSRValue": "0x100200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5659,7 +12226,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200002", + "MSRValue": "0x200200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5673,7 +12240,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200002", + "MSRValue": "0x80200002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5715,7 +12282,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040002", + "MSRValue": "0x800040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5729,7 +12296,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040002", + "MSRValue": "0x400040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5743,7 +12310,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040002", + "MSRValue": "0x100040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5757,7 +12324,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040002", + "MSRValue": "0x200040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5771,7 +12338,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040002", + "MSRValue": "0x80040002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5813,7 +12380,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100002", + "MSRValue": "0x800100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5827,7 +12394,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100002", + "MSRValue": "0x400100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5841,7 +12408,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100002", + "MSRValue": "0x100100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5855,7 +12422,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100002", + "MSRValue": "0x200100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5869,7 +12436,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100002", + "MSRValue": "0x80100002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5897,7 +12464,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400002", + "MSRValue": "0x80400002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5911,7 +12478,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400002", + "MSRValue": "0x100400002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5953,7 +12520,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020002", + "MSRValue": "0x800020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5967,7 +12534,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020002", + "MSRValue": "0x400020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5981,7 +12548,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020002", + "MSRValue": "0x100020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5995,7 +12562,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020002", + "MSRValue": "0x200020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6009,7 +12576,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020002", + "MSRValue": "0x80020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6023,7 +12590,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", + "MSRValue": "0x18000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6065,7 +12632,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C8000", + "MSRValue": "0x8003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6079,7 +12646,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C8000", + "MSRValue": "0x4003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6093,7 +12660,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", + "MSRValue": "0x1003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6107,7 +12674,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C8000", + "MSRValue": "0x8007C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6121,7 +12688,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C8000", + "MSRValue": "0x2003C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6135,7 +12702,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C8000", + "MSRValue": "0x803C8000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6177,7 +12744,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800088000", + "MSRValue": "0x800088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6191,7 +12758,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400088000", + "MSRValue": "0x400088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6205,7 +12772,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100088000", + "MSRValue": "0x100088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6219,7 +12786,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200088000", + "MSRValue": "0x200088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6233,7 +12800,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080088000", + "MSRValue": "0x80088000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6275,7 +12842,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800208000", + "MSRValue": "0x800208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6289,7 +12856,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400208000", + "MSRValue": "0x400208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6303,7 +12870,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100208000", + "MSRValue": "0x100208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6317,7 +12884,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200208000", + "MSRValue": "0x200208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6331,7 +12898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080208000", + "MSRValue": "0x80208000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6373,7 +12940,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800048000", + "MSRValue": "0x800048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6387,7 +12954,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400048000", + "MSRValue": "0x400048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6401,7 +12968,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100048000", + "MSRValue": "0x100048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6415,7 +12982,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200048000", + "MSRValue": "0x200048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6429,7 +12996,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080048000", + "MSRValue": "0x80048000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6471,7 +13038,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800108000", + "MSRValue": "0x800108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6485,7 +13052,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400108000", + "MSRValue": "0x400108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6499,7 +13066,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100108000", + "MSRValue": "0x100108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6513,7 +13080,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200108000", + "MSRValue": "0x200108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6527,7 +13094,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080108000", + "MSRValue": "0x80108000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6555,7 +13122,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080408000", + "MSRValue": "0x80408000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6569,7 +13136,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100408000", + "MSRValue": "0x100408000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6611,7 +13178,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800028000", + "MSRValue": "0x800028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6625,7 +13192,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400028000", + "MSRValue": "0x400028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6639,7 +13206,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100028000", + "MSRValue": "0x100028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6653,7 +13220,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200028000", + "MSRValue": "0x200028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6667,7 +13234,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080028000", + "MSRValue": "0x80028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6681,7 +13248,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010400", + "MSRValue": "0x10400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6723,7 +13290,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0400", + "MSRValue": "0x8003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6737,7 +13304,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0400", + "MSRValue": "0x4003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6751,7 +13318,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", + "MSRValue": "0x1003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6765,7 +13332,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0400", + "MSRValue": "0x8007C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6779,7 +13346,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0400", + "MSRValue": "0x2003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6793,7 +13360,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0400", + "MSRValue": "0x803C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6835,7 +13402,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080400", + "MSRValue": "0x800080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6849,7 +13416,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080400", + "MSRValue": "0x400080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6863,7 +13430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080400", + "MSRValue": "0x100080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6877,7 +13444,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080400", + "MSRValue": "0x200080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6891,7 +13458,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080400", + "MSRValue": "0x80080400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6933,7 +13500,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200400", + "MSRValue": "0x800200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6947,7 +13514,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200400", + "MSRValue": "0x400200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6961,7 +13528,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200400", + "MSRValue": "0x100200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6975,7 +13542,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200400", + "MSRValue": "0x200200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6989,7 +13556,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200400", + "MSRValue": "0x80200400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7031,7 +13598,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040400", + "MSRValue": "0x800040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7045,7 +13612,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040400", + "MSRValue": "0x400040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7059,7 +13626,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040400", + "MSRValue": "0x100040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7073,7 +13640,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040400", + "MSRValue": "0x200040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7087,7 +13654,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040400", + "MSRValue": "0x80040400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7129,7 +13696,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100400", + "MSRValue": "0x800100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7143,7 +13710,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100400", + "MSRValue": "0x400100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7157,7 +13724,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100400", + "MSRValue": "0x100100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7171,7 +13738,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100400", + "MSRValue": "0x200100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7185,7 +13752,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100400", + "MSRValue": "0x80100400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7213,7 +13780,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400400", + "MSRValue": "0x80400400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7227,7 +13794,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400400", + "MSRValue": "0x100400400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7269,7 +13836,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020400", + "MSRValue": "0x800020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7283,7 +13850,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020400", + "MSRValue": "0x400020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7297,7 +13864,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020400", + "MSRValue": "0x100020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7311,7 +13878,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020400", + "MSRValue": "0x200020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7325,7 +13892,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020400", + "MSRValue": "0x80020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7339,7 +13906,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", + "MSRValue": "0x10010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7381,7 +13948,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0010", + "MSRValue": "0x8003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7395,7 +13962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", + "MSRValue": "0x4003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7409,7 +13976,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", + "MSRValue": "0x1003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7423,7 +13990,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0010", + "MSRValue": "0x8007C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7437,7 +14004,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0010", + "MSRValue": "0x2003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7451,7 +14018,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0010", + "MSRValue": "0x803C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7493,7 +14060,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080010", + "MSRValue": "0x800080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7507,7 +14074,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080010", + "MSRValue": "0x400080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7521,7 +14088,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080010", + "MSRValue": "0x100080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7535,7 +14102,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080010", + "MSRValue": "0x200080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7549,7 +14116,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080010", + "MSRValue": "0x80080010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7591,7 +14158,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200010", + "MSRValue": "0x800200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7605,7 +14172,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200010", + "MSRValue": "0x400200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7619,7 +14186,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200010", + "MSRValue": "0x100200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7633,7 +14200,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200010", + "MSRValue": "0x200200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7647,7 +14214,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200010", + "MSRValue": "0x80200010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7689,7 +14256,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040010", + "MSRValue": "0x800040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7703,7 +14270,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040010", + "MSRValue": "0x400040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7717,7 +14284,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040010", + "MSRValue": "0x100040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7731,7 +14298,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040010", + "MSRValue": "0x200040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7745,7 +14312,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040010", + "MSRValue": "0x80040010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7787,7 +14354,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100010", + "MSRValue": "0x800100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7801,7 +14368,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100010", + "MSRValue": "0x400100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7815,7 +14382,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100010", + "MSRValue": "0x100100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7829,7 +14396,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100010", + "MSRValue": "0x200100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7843,7 +14410,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100010", + "MSRValue": "0x80100010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7871,7 +14438,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400010", + "MSRValue": "0x80400010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7885,7 +14452,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400010", + "MSRValue": "0x100400010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7927,7 +14494,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020010", + "MSRValue": "0x800020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7941,7 +14508,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020010", + "MSRValue": "0x400020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7955,7 +14522,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020010", + "MSRValue": "0x100020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7969,7 +14536,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020010", + "MSRValue": "0x200020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7983,7 +14550,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020010", + "MSRValue": "0x80020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7997,7 +14564,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", + "MSRValue": "0x10020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8039,7 +14606,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0020", + "MSRValue": "0x8003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8053,7 +14620,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", + "MSRValue": "0x4003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8067,7 +14634,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", + "MSRValue": "0x1003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8081,7 +14648,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0020", + "MSRValue": "0x8007C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8095,7 +14662,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0020", + "MSRValue": "0x2003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8109,7 +14676,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0020", + "MSRValue": "0x803C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8151,7 +14718,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080020", + "MSRValue": "0x800080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8165,7 +14732,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080020", + "MSRValue": "0x400080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8179,7 +14746,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080020", + "MSRValue": "0x100080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8193,7 +14760,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080020", + "MSRValue": "0x200080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8207,7 +14774,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080020", + "MSRValue": "0x80080020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8249,7 +14816,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200020", + "MSRValue": "0x800200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8263,7 +14830,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200020", + "MSRValue": "0x400200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8277,7 +14844,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200020", + "MSRValue": "0x100200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8291,7 +14858,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200020", + "MSRValue": "0x200200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8305,7 +14872,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200020", + "MSRValue": "0x80200020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8347,7 +14914,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040020", + "MSRValue": "0x800040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8361,7 +14928,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040020", + "MSRValue": "0x400040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8375,7 +14942,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040020", + "MSRValue": "0x100040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8389,7 +14956,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040020", + "MSRValue": "0x200040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8403,7 +14970,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040020", + "MSRValue": "0x80040020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8445,7 +15012,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100020", + "MSRValue": "0x800100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8459,7 +15026,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100020", + "MSRValue": "0x400100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8473,7 +15040,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100020", + "MSRValue": "0x100100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8487,7 +15054,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100020", + "MSRValue": "0x200100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8501,7 +15068,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100020", + "MSRValue": "0x80100020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8529,7 +15096,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400020", + "MSRValue": "0x80400020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8543,7 +15110,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400020", + "MSRValue": "0x100400020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8585,7 +15152,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020020", + "MSRValue": "0x800020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8599,7 +15166,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020020", + "MSRValue": "0x400020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8613,7 +15180,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020020", + "MSRValue": "0x100020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8627,7 +15194,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020020", + "MSRValue": "0x200020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8641,7 +15208,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020020", + "MSRValue": "0x80020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8655,7 +15222,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010080", + "MSRValue": "0x10080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8697,7 +15264,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0080", + "MSRValue": "0x8003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8711,7 +15278,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0080", + "MSRValue": "0x4003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8725,7 +15292,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", + "MSRValue": "0x1003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8739,7 +15306,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0080", + "MSRValue": "0x8007C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8753,7 +15320,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0080", + "MSRValue": "0x2003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8767,7 +15334,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0080", + "MSRValue": "0x803C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8809,7 +15376,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080080", + "MSRValue": "0x800080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8823,7 +15390,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080080", + "MSRValue": "0x400080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8837,7 +15404,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080080", + "MSRValue": "0x100080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8851,7 +15418,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080080", + "MSRValue": "0x200080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8865,7 +15432,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080080", + "MSRValue": "0x80080080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8907,7 +15474,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200080", + "MSRValue": "0x800200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8921,7 +15488,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200080", + "MSRValue": "0x400200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8935,7 +15502,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200080", + "MSRValue": "0x100200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8949,7 +15516,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200080", + "MSRValue": "0x200200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8963,7 +15530,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200080", + "MSRValue": "0x80200080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9005,7 +15572,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040080", + "MSRValue": "0x800040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9019,7 +15586,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040080", + "MSRValue": "0x400040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9033,7 +15600,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040080", + "MSRValue": "0x100040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9047,7 +15614,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040080", + "MSRValue": "0x200040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9061,7 +15628,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040080", + "MSRValue": "0x80040080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9103,7 +15670,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100080", + "MSRValue": "0x800100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9117,7 +15684,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100080", + "MSRValue": "0x400100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9131,7 +15698,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100080", + "MSRValue": "0x100100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9145,7 +15712,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100080", + "MSRValue": "0x200100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9159,7 +15726,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100080", + "MSRValue": "0x80100080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9187,7 +15754,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400080", + "MSRValue": "0x80400080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9201,7 +15768,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400080", + "MSRValue": "0x100400080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9243,7 +15810,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020080", + "MSRValue": "0x800020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9257,7 +15824,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020080", + "MSRValue": "0x400020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9271,7 +15838,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020080", + "MSRValue": "0x100020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9285,7 +15852,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020080", + "MSRValue": "0x200020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9299,7 +15866,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020080", + "MSRValue": "0x80020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9313,7 +15880,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010100", + "MSRValue": "0x10100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9355,7 +15922,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0100", + "MSRValue": "0x8003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9369,7 +15936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0100", + "MSRValue": "0x4003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9383,7 +15950,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", + "MSRValue": "0x1003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9397,7 +15964,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0100", + "MSRValue": "0x8007C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9411,7 +15978,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0100", + "MSRValue": "0x2003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9425,7 +15992,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0100", + "MSRValue": "0x803C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9467,7 +16034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080100", + "MSRValue": "0x800080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9481,7 +16048,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080100", + "MSRValue": "0x400080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9495,7 +16062,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080100", + "MSRValue": "0x100080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9509,7 +16076,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080100", + "MSRValue": "0x200080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9523,7 +16090,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080100", + "MSRValue": "0x80080100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9565,7 +16132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200100", + "MSRValue": "0x800200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9579,7 +16146,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200100", + "MSRValue": "0x400200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9593,7 +16160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200100", + "MSRValue": "0x100200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9607,7 +16174,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200100", + "MSRValue": "0x200200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9621,7 +16188,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200100", + "MSRValue": "0x80200100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9663,7 +16230,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040100", + "MSRValue": "0x800040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9677,7 +16244,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040100", + "MSRValue": "0x400040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9691,7 +16258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040100", + "MSRValue": "0x100040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9705,7 +16272,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040100", + "MSRValue": "0x200040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9719,7 +16286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040100", + "MSRValue": "0x80040100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9761,7 +16328,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100100", + "MSRValue": "0x800100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9775,7 +16342,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100100", + "MSRValue": "0x400100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9789,7 +16356,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100100", + "MSRValue": "0x100100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9803,7 +16370,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100100", + "MSRValue": "0x200100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9817,7 +16384,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100100", + "MSRValue": "0x80100100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9845,7 +16412,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400100", + "MSRValue": "0x80400100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9859,7 +16426,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400100", + "MSRValue": "0x100400100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9901,7 +16468,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020100", + "MSRValue": "0x800020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9915,7 +16482,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020100", + "MSRValue": "0x400020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9929,7 +16496,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020100", + "MSRValue": "0x100020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9943,7 +16510,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020100", + "MSRValue": "0x200020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9957,7 +16524,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020100", + "MSRValue": "0x80020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9972,5 +16539,41 @@ "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", "SampleAfterValue": "100003", "UMask": "0x10" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "SampleAfterValue": "2000003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index 5d6b2e6fcb7b..5a1631448b46 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -1,26 +1,167 @@ [ + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Frontend_Bound", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Frontend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Bad_Speculation", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Bad_Speculation_SMT", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Backend_Bound", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Backend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Retiring", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Retiring_SMT", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "Mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts_SMT", + "MetricName": "Mispredictions_SMT" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (OFFCORE_REQUESTS_BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "Memory_Bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore_SMT", + "MetricName": "Memory_Bandwidth_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore", + "MetricName": "Memory_Latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) - ( ( ( 1 - ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) / ( ( 19 * (MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + 10 * ( (MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + (MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) ) ) + ( 25 * ( MEM_LOAD_RETIRED.LOCAL_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) + 33 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) ) ) ) ) ) ) * (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) if ( 1000000 * ( MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM + MEM_LOAD_RETIRED.LOCAL_PMM ) > MEM_LOAD_RETIRED.L1_MISS ) else 0 ) ) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore_SMT", + "MetricName": "Memory_Latency_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Memory_Data_TLBs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB;_SMT", + "MetricName": "Memory_Data_TLBs_SMT" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "Ret_SMT", + "MetricName": "Branching_Overhead_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB_SMT", + "MetricName": "Big_Code_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "Instruction_Fetch_BW" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "Fed;FetchBW;Frontend_SMT", + "MetricName": "Instruction_Fetch_BW_SMT" + }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;FetchBW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { @@ -30,39 +171,84 @@ "MetricName": "CLKS" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", + "MetricName": "SLOTS_SMT" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Flops", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", - "MetricGroup": "Flops_SMT", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Pipeline;PortsUtil", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" + }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -86,128 +272,255 @@ { "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;InsType", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, { "BriefDescription": "Branch instructions per taken branch. ", "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", - "MetricGroup": "Flops;FpArith;InsType", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, { "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, { "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "LSD", + "MetricGroup": "Fed;LSD", "MetricName": "LSD_Coverage" }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;FetchBW", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "DSB_Misses_Cost" + }, + { + "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "DSBmiss;Fed_SMT", + "MetricName": "DSB_Misses_Cost_SMT" + }, + { + "BriefDescription": "Number of Instructions per non-speculative DSB miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", - "MetricGroup": "MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "MemoryBound;MemoryBW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CORE_CLKS )", - "MetricGroup": "MemoryTLB", - "MetricName": "Page_Walks_Utilization" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", - "MetricGroup": "MemoryBW;Offcore", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Offcore", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructions for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", "MetricExpr": "1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_Silent_PKI" }, { "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_NonSilent_PKI" }, { @@ -225,7 +538,7 @@ { "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time", - "MetricGroup": "Flops;HPC", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -234,6 +547,48 @@ "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License0_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License1_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License2_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions. SMT version; use when SMT is enabled and measuring per logical CPU." + }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", @@ -246,52 +601,64 @@ "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "HPC;MemoryBW;SoC", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "1000000000 * ( cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x35\\,umask\\=0x21\\,config\\=0x40433@ ) / ( cha_0@event\\=0x0@ / duration_time )", - "MetricGroup": "MemoryLat;SoC", + "MetricGroup": "Mem;MemoryLat;SoC", "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433\\,thresh\\=1@", - "MetricGroup": "MemoryBW;SoC", + "MetricGroup": "Mem;MemoryBW;SoC", "MetricName": "MEM_Parallel_Reads" }, { "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", "MetricExpr": "( 1000000000 * ( imc@event\\=0xe0\\,umask\\=0x1@ / imc@event\\=0xe3@ ) / imc_0@event\\=0x0@ )", - "MetricGroup": "MemoryLat;SoC;Server", + "MetricGroup": "Mem;MemoryLat;SoC;Server", "MetricName": "MEM_PMM_Read_Latency" }, + { + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "1000000000 * ( UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS ) / imc_0@event\\=0x0@", + "MetricGroup": "Mem;MemoryLat;SoC;Server", + "MetricName": "MEM_DRAM_Read_Latency" + }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", "MetricExpr": "( ( 64 * imc@event\\=0xe3@ / 1000000000 ) / duration_time )", - "MetricGroup": "MemoryBW;SoC;Server", + "MetricGroup": "Mem;MemoryBW;SoC;Server", "MetricName": "PMM_Read_BW" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", "MetricExpr": "( ( 64 * imc@event\\=0xe7@ / 1000000000 ) / duration_time )", - "MetricGroup": "MemoryBW;SoC;Server", + "MetricGroup": "Mem;MemoryBW;SoC;Server", "MetricName": "PMM_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000000 / duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]", "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 ) * 4 / 1000000000 / duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Read_BW" }, { diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json index ade925d7a68c..41a3d13fc4b2 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json @@ -1,37 +1,41 @@ [ { - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, @@ -41,6 +45,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x40" }, @@ -50,27 +55,60 @@ "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x80" }, { - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x2" }, + { + "BriefDescription": "Intel AVX-512 computational 512-bit packed BFloat16 instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCF", + "EventName": "FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16", + "PublicDescription": "Counts once for each Intel AVX-512 computational 512-bit packed BFloat16 floating-point instruction retired. Applies to the ZMM based VDPBF16PS instruction. Each count represents 64 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Intel AVX-512 computational 128-bit packed BFloat16 instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCF", + "EventName": "FP_ARITH_INST_RETIRED2.256BIT_PACKED_BF16", + "PublicDescription": "Counts once for each Intel AVX-512 computational 128-bit packed BFloat16 floating-point instruction retired. Applies to the XMM based VDPBF16PS instruction. Each count represents 16 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Intel AVX-512 computational 256-bit packed BFloat16 instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCF", + "EventName": "FP_ARITH_INST_RETIRED2.512BIT_PACKED_BF16", + "PublicDescription": "Counts once for each Intel AVX-512 computational 256-bit packed BFloat16 floating-point instruction retired. Applies to the YMM based VDPBF16PS instruction. Each count represents 32 computation operations. This event is only supported on products formerly named Cooper Lake and is not supported on products formerly named Cascade Lake.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, { "BriefDescription": "Cycles with any input/output SSE or FP assist", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json index 078706a50091..ecce4273ae52 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json @@ -30,7 +30,21 @@ "UMask": "0x2" }, { - "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss.", + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", @@ -38,7 +52,7 @@ "MSRIndex": "0x3F7", "MSRValue": "0x11", "PEBS": "1", - "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json b/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json index 7c2adadca87e..ae55c35c2f19 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json @@ -260,7 +260,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000491", + "MSRValue": "0x83C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -273,7 +273,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000491", + "MSRValue": "0x43C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -286,7 +286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000491", + "MSRValue": "0x13C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -312,7 +312,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00491", + "MSRValue": "0x83FC00491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -325,7 +325,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000491", + "MSRValue": "0x23C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -338,7 +338,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000491", + "MSRValue": "0xBC000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -377,7 +377,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000491", + "MSRValue": "0x804000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -390,7 +390,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000491", + "MSRValue": "0x404000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -403,7 +403,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000491", + "MSRValue": "0x104000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -416,7 +416,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000491", + "MSRValue": "0x204000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -429,7 +429,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000491", + "MSRValue": "0x604000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -442,7 +442,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000491", + "MSRValue": "0x84000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -455,7 +455,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800491", + "MSRValue": "0x63B800491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -494,7 +494,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000491", + "MSRValue": "0x810000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -507,7 +507,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000491", + "MSRValue": "0x410000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -520,7 +520,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000491", + "MSRValue": "0x110000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -533,7 +533,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000491", + "MSRValue": "0x210000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -546,7 +546,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000491", + "MSRValue": "0x90000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -585,7 +585,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000490", + "MSRValue": "0x83C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -598,7 +598,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000490", + "MSRValue": "0x43C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -611,7 +611,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000490", + "MSRValue": "0x13C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -637,7 +637,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00490", + "MSRValue": "0x83FC00490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -650,7 +650,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000490", + "MSRValue": "0x23C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -663,7 +663,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000490", + "MSRValue": "0xBC000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -702,7 +702,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000490", + "MSRValue": "0x804000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -715,7 +715,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000490", + "MSRValue": "0x404000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -728,7 +728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000490", + "MSRValue": "0x104000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -741,7 +741,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000490", + "MSRValue": "0x204000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -754,7 +754,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000490", + "MSRValue": "0x604000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -767,7 +767,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000490", + "MSRValue": "0x84000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -780,7 +780,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800490", + "MSRValue": "0x63B800490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -819,7 +819,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000490", + "MSRValue": "0x810000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -832,7 +832,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000490", + "MSRValue": "0x410000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -845,7 +845,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000490", + "MSRValue": "0x110000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -858,7 +858,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000490", + "MSRValue": "0x210000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -871,7 +871,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000490", + "MSRValue": "0x90000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -910,7 +910,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000120", + "MSRValue": "0x83C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -923,7 +923,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000120", + "MSRValue": "0x43C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -936,7 +936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000120", + "MSRValue": "0x13C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -962,7 +962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00120", + "MSRValue": "0x83FC00120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -975,7 +975,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000120", + "MSRValue": "0x23C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -988,7 +988,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000120", + "MSRValue": "0xBC000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1027,7 +1027,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000120", + "MSRValue": "0x804000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1040,7 +1040,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000120", + "MSRValue": "0x404000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1053,7 +1053,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000120", + "MSRValue": "0x104000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1066,7 +1066,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000120", + "MSRValue": "0x204000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1079,7 +1079,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000120", + "MSRValue": "0x604000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1092,7 +1092,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000120", + "MSRValue": "0x84000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1105,7 +1105,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800120", + "MSRValue": "0x63B800120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1144,7 +1144,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000120", + "MSRValue": "0x810000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1157,7 +1157,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000120", + "MSRValue": "0x410000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1170,7 +1170,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000120", + "MSRValue": "0x110000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1183,7 +1183,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000120", + "MSRValue": "0x210000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1196,7 +1196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000120", + "MSRValue": "0x90000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1235,7 +1235,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C0007F7", + "MSRValue": "0x83C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1248,7 +1248,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C0007F7", + "MSRValue": "0x43C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1261,7 +1261,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C0007F7", + "MSRValue": "0x13C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1287,7 +1287,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC007F7", + "MSRValue": "0x83FC007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1300,7 +1300,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C0007F7", + "MSRValue": "0x23C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1313,7 +1313,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC0007F7", + "MSRValue": "0xBC0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1352,7 +1352,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08040007F7", + "MSRValue": "0x8040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1365,7 +1365,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04040007F7", + "MSRValue": "0x4040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1378,7 +1378,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01040007F7", + "MSRValue": "0x1040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1391,7 +1391,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02040007F7", + "MSRValue": "0x2040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1404,7 +1404,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x06040007F7", + "MSRValue": "0x6040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1417,7 +1417,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00840007F7", + "MSRValue": "0x840007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1430,7 +1430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B8007F7", + "MSRValue": "0x63B8007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1469,7 +1469,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08100007F7", + "MSRValue": "0x8100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1482,7 +1482,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04100007F7", + "MSRValue": "0x4100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1495,7 +1495,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01100007F7", + "MSRValue": "0x1100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1508,7 +1508,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02100007F7", + "MSRValue": "0x2100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1521,7 +1521,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00900007F7", + "MSRValue": "0x900007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1560,7 +1560,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000122", + "MSRValue": "0x83C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1573,7 +1573,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000122", + "MSRValue": "0x43C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1586,7 +1586,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000122", + "MSRValue": "0x13C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1612,7 +1612,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00122", + "MSRValue": "0x83FC00122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1625,7 +1625,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000122", + "MSRValue": "0x23C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1638,7 +1638,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000122", + "MSRValue": "0xBC000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1677,7 +1677,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000122", + "MSRValue": "0x804000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1690,7 +1690,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000122", + "MSRValue": "0x404000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1703,7 +1703,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000122", + "MSRValue": "0x104000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1716,7 +1716,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000122", + "MSRValue": "0x204000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1729,7 +1729,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000122", + "MSRValue": "0x604000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1742,7 +1742,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000122", + "MSRValue": "0x84000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1755,7 +1755,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800122", + "MSRValue": "0x63B800122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1794,7 +1794,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000122", + "MSRValue": "0x810000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1807,7 +1807,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000122", + "MSRValue": "0x410000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1820,7 +1820,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000122", + "MSRValue": "0x110000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1833,7 +1833,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000122", + "MSRValue": "0x210000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1846,7 +1846,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000122", + "MSRValue": "0x90000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1885,7 +1885,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000004", + "MSRValue": "0x83C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1898,7 +1898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000004", + "MSRValue": "0x43C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1911,7 +1911,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000004", + "MSRValue": "0x13C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1937,7 +1937,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00004", + "MSRValue": "0x83FC00004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1950,7 +1950,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000004", + "MSRValue": "0x23C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1963,7 +1963,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000004", + "MSRValue": "0xBC000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2002,7 +2002,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000004", + "MSRValue": "0x804000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2015,7 +2015,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000004", + "MSRValue": "0x404000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2028,7 +2028,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000004", + "MSRValue": "0x104000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2041,7 +2041,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000004", + "MSRValue": "0x204000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2054,7 +2054,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000004", + "MSRValue": "0x604000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2067,7 +2067,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000004", + "MSRValue": "0x84000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2080,7 +2080,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800004", + "MSRValue": "0x63B800004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2119,7 +2119,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000004", + "MSRValue": "0x810000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2132,7 +2132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000004", + "MSRValue": "0x410000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2145,7 +2145,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000004", + "MSRValue": "0x110000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2158,7 +2158,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000004", + "MSRValue": "0x210000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2171,7 +2171,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000004", + "MSRValue": "0x90000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2210,7 +2210,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000001", + "MSRValue": "0x83C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2223,7 +2223,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000001", + "MSRValue": "0x43C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2236,7 +2236,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000001", + "MSRValue": "0x13C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2262,7 +2262,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00001", + "MSRValue": "0x83FC00001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2275,7 +2275,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000001", + "MSRValue": "0x23C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2288,7 +2288,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000001", + "MSRValue": "0xBC000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2327,7 +2327,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000001", + "MSRValue": "0x804000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2340,7 +2340,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000001", + "MSRValue": "0x404000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2353,7 +2353,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000001", + "MSRValue": "0x104000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2366,7 +2366,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000001", + "MSRValue": "0x204000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2379,7 +2379,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000001", + "MSRValue": "0x604000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2392,7 +2392,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000001", + "MSRValue": "0x84000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2405,7 +2405,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800001", + "MSRValue": "0x63B800001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2444,7 +2444,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000001", + "MSRValue": "0x810000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2457,7 +2457,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000001", + "MSRValue": "0x410000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2470,7 +2470,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000001", + "MSRValue": "0x110000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2483,7 +2483,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000001", + "MSRValue": "0x210000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2496,7 +2496,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000001", + "MSRValue": "0x90000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2535,7 +2535,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000002", + "MSRValue": "0x83C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2548,7 +2548,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000002", + "MSRValue": "0x43C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2561,7 +2561,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000002", + "MSRValue": "0x13C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2587,7 +2587,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00002", + "MSRValue": "0x83FC00002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2600,7 +2600,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000002", + "MSRValue": "0x23C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2613,7 +2613,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000002", + "MSRValue": "0xBC000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2652,7 +2652,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000002", + "MSRValue": "0x804000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2665,7 +2665,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000002", + "MSRValue": "0x404000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2678,7 +2678,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000002", + "MSRValue": "0x104000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2691,7 +2691,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000002", + "MSRValue": "0x204000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2704,7 +2704,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000002", + "MSRValue": "0x604000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2717,7 +2717,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000002", + "MSRValue": "0x84000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2730,7 +2730,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800002", + "MSRValue": "0x63B800002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2769,7 +2769,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000002", + "MSRValue": "0x810000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2782,7 +2782,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000002", + "MSRValue": "0x410000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2795,7 +2795,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000002", + "MSRValue": "0x110000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2808,7 +2808,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000002", + "MSRValue": "0x210000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2821,7 +2821,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000002", + "MSRValue": "0x90000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2860,7 +2860,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C008000", + "MSRValue": "0x83C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2873,7 +2873,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C008000", + "MSRValue": "0x43C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2886,7 +2886,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C008000", + "MSRValue": "0x13C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2912,7 +2912,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC08000", + "MSRValue": "0x83FC08000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2925,7 +2925,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C008000", + "MSRValue": "0x23C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2938,7 +2938,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC008000", + "MSRValue": "0xBC008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2977,7 +2977,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804008000", + "MSRValue": "0x804008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2990,7 +2990,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404008000", + "MSRValue": "0x404008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3003,7 +3003,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104008000", + "MSRValue": "0x104008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3016,7 +3016,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204008000", + "MSRValue": "0x204008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3029,7 +3029,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604008000", + "MSRValue": "0x604008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3042,7 +3042,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084008000", + "MSRValue": "0x84008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3055,7 +3055,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B808000", + "MSRValue": "0x63B808000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3094,7 +3094,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810008000", + "MSRValue": "0x810008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3107,7 +3107,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410008000", + "MSRValue": "0x410008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3120,7 +3120,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110008000", + "MSRValue": "0x110008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3133,7 +3133,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210008000", + "MSRValue": "0x210008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3146,7 +3146,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090008000", + "MSRValue": "0x90008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3185,7 +3185,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000400", + "MSRValue": "0x83C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3198,7 +3198,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000400", + "MSRValue": "0x43C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3211,7 +3211,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000400", + "MSRValue": "0x13C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3237,7 +3237,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00400", + "MSRValue": "0x83FC00400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3250,7 +3250,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000400", + "MSRValue": "0x23C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3263,7 +3263,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000400", + "MSRValue": "0xBC000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3302,7 +3302,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000400", + "MSRValue": "0x804000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3315,7 +3315,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000400", + "MSRValue": "0x404000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3328,7 +3328,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000400", + "MSRValue": "0x104000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3341,7 +3341,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000400", + "MSRValue": "0x204000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3354,7 +3354,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000400", + "MSRValue": "0x604000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3367,7 +3367,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000400", + "MSRValue": "0x84000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3380,7 +3380,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800400", + "MSRValue": "0x63B800400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3419,7 +3419,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000400", + "MSRValue": "0x810000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3432,7 +3432,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000400", + "MSRValue": "0x410000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3445,7 +3445,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000400", + "MSRValue": "0x110000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3458,7 +3458,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000400", + "MSRValue": "0x210000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3471,7 +3471,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000400", + "MSRValue": "0x90000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3510,7 +3510,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000010", + "MSRValue": "0x83C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3523,7 +3523,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000010", + "MSRValue": "0x43C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3536,7 +3536,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000010", + "MSRValue": "0x13C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3562,7 +3562,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00010", + "MSRValue": "0x83FC00010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3575,7 +3575,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000010", + "MSRValue": "0x23C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3588,7 +3588,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000010", + "MSRValue": "0xBC000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3627,7 +3627,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000010", + "MSRValue": "0x804000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3640,7 +3640,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000010", + "MSRValue": "0x404000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3653,7 +3653,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000010", + "MSRValue": "0x104000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3666,7 +3666,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000010", + "MSRValue": "0x204000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3679,7 +3679,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000010", + "MSRValue": "0x604000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3692,7 +3692,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000010", + "MSRValue": "0x84000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3705,7 +3705,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800010", + "MSRValue": "0x63B800010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3744,7 +3744,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000010", + "MSRValue": "0x810000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3757,7 +3757,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000010", + "MSRValue": "0x410000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3770,7 +3770,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000010", + "MSRValue": "0x110000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3783,7 +3783,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000010", + "MSRValue": "0x210000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3796,7 +3796,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000010", + "MSRValue": "0x90000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3835,7 +3835,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000020", + "MSRValue": "0x83C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3848,7 +3848,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000020", + "MSRValue": "0x43C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3861,7 +3861,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000020", + "MSRValue": "0x13C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3887,7 +3887,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00020", + "MSRValue": "0x83FC00020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3900,7 +3900,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000020", + "MSRValue": "0x23C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3913,7 +3913,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000020", + "MSRValue": "0xBC000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3952,7 +3952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000020", + "MSRValue": "0x804000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3965,7 +3965,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000020", + "MSRValue": "0x404000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3978,7 +3978,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000020", + "MSRValue": "0x104000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3991,7 +3991,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000020", + "MSRValue": "0x204000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4004,7 +4004,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000020", + "MSRValue": "0x604000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4017,7 +4017,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000020", + "MSRValue": "0x84000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4030,7 +4030,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800020", + "MSRValue": "0x63B800020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4069,7 +4069,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000020", + "MSRValue": "0x810000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4082,7 +4082,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000020", + "MSRValue": "0x410000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4095,7 +4095,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000020", + "MSRValue": "0x110000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4108,7 +4108,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000020", + "MSRValue": "0x210000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4121,7 +4121,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000020", + "MSRValue": "0x90000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4160,7 +4160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000080", + "MSRValue": "0x83C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4173,7 +4173,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000080", + "MSRValue": "0x43C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4186,7 +4186,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000080", + "MSRValue": "0x13C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4212,7 +4212,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00080", + "MSRValue": "0x83FC00080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4225,7 +4225,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000080", + "MSRValue": "0x23C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4238,7 +4238,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000080", + "MSRValue": "0xBC000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4277,7 +4277,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000080", + "MSRValue": "0x804000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4290,7 +4290,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000080", + "MSRValue": "0x404000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4303,7 +4303,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000080", + "MSRValue": "0x104000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4316,7 +4316,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000080", + "MSRValue": "0x204000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4329,7 +4329,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000080", + "MSRValue": "0x604000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4342,7 +4342,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000080", + "MSRValue": "0x84000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4355,7 +4355,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800080", + "MSRValue": "0x63B800080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4394,7 +4394,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000080", + "MSRValue": "0x810000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4407,7 +4407,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000080", + "MSRValue": "0x410000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4420,7 +4420,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000080", + "MSRValue": "0x110000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4433,7 +4433,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000080", + "MSRValue": "0x210000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4446,7 +4446,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000080", + "MSRValue": "0x90000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4485,7 +4485,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000100", + "MSRValue": "0x83C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4498,7 +4498,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000100", + "MSRValue": "0x43C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4511,7 +4511,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000100", + "MSRValue": "0x13C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4537,7 +4537,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00100", + "MSRValue": "0x83FC00100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4550,7 +4550,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000100", + "MSRValue": "0x23C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4563,7 +4563,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000100", + "MSRValue": "0xBC000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4602,7 +4602,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000100", + "MSRValue": "0x804000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4615,7 +4615,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000100", + "MSRValue": "0x404000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4628,7 +4628,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000100", + "MSRValue": "0x104000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4641,7 +4641,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000100", + "MSRValue": "0x204000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4654,7 +4654,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000100", + "MSRValue": "0x604000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4667,7 +4667,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000100", + "MSRValue": "0x84000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4680,7 +4680,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800100", + "MSRValue": "0x63B800100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4719,7 +4719,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000100", + "MSRValue": "0x810000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4732,7 +4732,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000100", + "MSRValue": "0x410000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4745,7 +4745,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000100", + "MSRValue": "0x110000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4758,7 +4758,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000100", + "MSRValue": "0x210000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4771,7 +4771,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000100", + "MSRValue": "0x90000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4852,7 +4852,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000491", + "MSRValue": "0x83C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4866,7 +4866,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000491", + "MSRValue": "0x43C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4880,7 +4880,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000491", + "MSRValue": "0x13C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4908,7 +4908,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00491", + "MSRValue": "0x83FC00491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4922,7 +4922,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000491", + "MSRValue": "0x23C000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4936,7 +4936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000491", + "MSRValue": "0xBC000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4978,7 +4978,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000491", + "MSRValue": "0x804000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4992,7 +4992,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000491", + "MSRValue": "0x404000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5006,7 +5006,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000491", + "MSRValue": "0x104000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5020,7 +5020,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000491", + "MSRValue": "0x204000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5034,7 +5034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000491", + "MSRValue": "0x604000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5048,7 +5048,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000491", + "MSRValue": "0x84000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5062,7 +5062,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800491", + "MSRValue": "0x63B800491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5104,7 +5104,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000491", + "MSRValue": "0x810000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5118,7 +5118,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000491", + "MSRValue": "0x410000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5132,7 +5132,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000491", + "MSRValue": "0x110000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5146,7 +5146,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000491", + "MSRValue": "0x210000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5160,7 +5160,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000491", + "MSRValue": "0x90000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5202,7 +5202,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000490", + "MSRValue": "0x83C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5216,7 +5216,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000490", + "MSRValue": "0x43C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5230,7 +5230,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000490", + "MSRValue": "0x13C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5258,7 +5258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00490", + "MSRValue": "0x83FC00490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5272,7 +5272,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000490", + "MSRValue": "0x23C000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5286,7 +5286,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000490", + "MSRValue": "0xBC000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5328,7 +5328,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000490", + "MSRValue": "0x804000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5342,7 +5342,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000490", + "MSRValue": "0x404000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5356,7 +5356,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000490", + "MSRValue": "0x104000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5370,7 +5370,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000490", + "MSRValue": "0x204000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5384,7 +5384,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000490", + "MSRValue": "0x604000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5398,7 +5398,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000490", + "MSRValue": "0x84000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5412,7 +5412,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800490", + "MSRValue": "0x63B800490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5454,7 +5454,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000490", + "MSRValue": "0x810000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5468,7 +5468,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000490", + "MSRValue": "0x410000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5482,7 +5482,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000490", + "MSRValue": "0x110000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5496,7 +5496,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000490", + "MSRValue": "0x210000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5510,7 +5510,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000490", + "MSRValue": "0x90000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5552,7 +5552,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000120", + "MSRValue": "0x83C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5566,7 +5566,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000120", + "MSRValue": "0x43C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5580,7 +5580,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000120", + "MSRValue": "0x13C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5608,7 +5608,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00120", + "MSRValue": "0x83FC00120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5622,7 +5622,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000120", + "MSRValue": "0x23C000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5636,7 +5636,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000120", + "MSRValue": "0xBC000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5678,7 +5678,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000120", + "MSRValue": "0x804000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5692,7 +5692,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000120", + "MSRValue": "0x404000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5706,7 +5706,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000120", + "MSRValue": "0x104000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5720,7 +5720,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000120", + "MSRValue": "0x204000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5734,7 +5734,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000120", + "MSRValue": "0x604000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5748,7 +5748,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000120", + "MSRValue": "0x84000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5762,7 +5762,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800120", + "MSRValue": "0x63B800120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5804,7 +5804,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000120", + "MSRValue": "0x810000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5818,7 +5818,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000120", + "MSRValue": "0x410000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5832,7 +5832,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000120", + "MSRValue": "0x110000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5846,7 +5846,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000120", + "MSRValue": "0x210000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5860,7 +5860,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000120", + "MSRValue": "0x90000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5902,7 +5902,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C0007F7", + "MSRValue": "0x83C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5916,7 +5916,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C0007F7", + "MSRValue": "0x43C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5930,7 +5930,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C0007F7", + "MSRValue": "0x13C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5958,7 +5958,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC007F7", + "MSRValue": "0x83FC007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5972,7 +5972,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C0007F7", + "MSRValue": "0x23C0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5986,7 +5986,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC0007F7", + "MSRValue": "0xBC0007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6028,7 +6028,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08040007F7", + "MSRValue": "0x8040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6042,7 +6042,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04040007F7", + "MSRValue": "0x4040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6056,7 +6056,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01040007F7", + "MSRValue": "0x1040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6070,7 +6070,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02040007F7", + "MSRValue": "0x2040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6084,7 +6084,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x06040007F7", + "MSRValue": "0x6040007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6098,7 +6098,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00840007F7", + "MSRValue": "0x840007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6112,7 +6112,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B8007F7", + "MSRValue": "0x63B8007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6154,7 +6154,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08100007F7", + "MSRValue": "0x8100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6168,7 +6168,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04100007F7", + "MSRValue": "0x4100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6182,7 +6182,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01100007F7", + "MSRValue": "0x1100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6196,7 +6196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02100007F7", + "MSRValue": "0x2100007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6210,7 +6210,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00900007F7", + "MSRValue": "0x900007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6252,7 +6252,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000122", + "MSRValue": "0x83C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6266,7 +6266,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000122", + "MSRValue": "0x43C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6280,7 +6280,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000122", + "MSRValue": "0x13C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6308,7 +6308,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00122", + "MSRValue": "0x83FC00122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6322,7 +6322,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000122", + "MSRValue": "0x23C000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6336,7 +6336,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000122", + "MSRValue": "0xBC000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6378,7 +6378,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000122", + "MSRValue": "0x804000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6392,7 +6392,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000122", + "MSRValue": "0x404000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6406,7 +6406,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000122", + "MSRValue": "0x104000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6420,7 +6420,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000122", + "MSRValue": "0x204000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6434,7 +6434,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000122", + "MSRValue": "0x604000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6448,7 +6448,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000122", + "MSRValue": "0x84000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6462,7 +6462,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800122", + "MSRValue": "0x63B800122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6504,7 +6504,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000122", + "MSRValue": "0x810000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6518,7 +6518,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000122", + "MSRValue": "0x410000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6532,7 +6532,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000122", + "MSRValue": "0x110000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6546,7 +6546,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000122", + "MSRValue": "0x210000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6560,7 +6560,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000122", + "MSRValue": "0x90000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6602,7 +6602,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000004", + "MSRValue": "0x83C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6616,7 +6616,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000004", + "MSRValue": "0x43C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6630,7 +6630,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000004", + "MSRValue": "0x13C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6658,7 +6658,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00004", + "MSRValue": "0x83FC00004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6672,7 +6672,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000004", + "MSRValue": "0x23C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6686,7 +6686,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000004", + "MSRValue": "0xBC000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6728,7 +6728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000004", + "MSRValue": "0x804000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6742,7 +6742,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000004", + "MSRValue": "0x404000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6756,7 +6756,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000004", + "MSRValue": "0x104000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6770,7 +6770,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000004", + "MSRValue": "0x204000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6784,7 +6784,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000004", + "MSRValue": "0x604000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6798,7 +6798,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000004", + "MSRValue": "0x84000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6812,7 +6812,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800004", + "MSRValue": "0x63B800004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6854,7 +6854,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000004", + "MSRValue": "0x810000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6868,7 +6868,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000004", + "MSRValue": "0x410000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6882,7 +6882,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000004", + "MSRValue": "0x110000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6896,7 +6896,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000004", + "MSRValue": "0x210000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6910,7 +6910,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000004", + "MSRValue": "0x90000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6952,7 +6952,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000001", + "MSRValue": "0x83C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6966,7 +6966,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000001", + "MSRValue": "0x43C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6980,7 +6980,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000001", + "MSRValue": "0x13C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7008,7 +7008,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00001", + "MSRValue": "0x83FC00001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7022,7 +7022,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000001", + "MSRValue": "0x23C000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7036,7 +7036,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000001", + "MSRValue": "0xBC000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7078,7 +7078,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000001", + "MSRValue": "0x804000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7092,7 +7092,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000001", + "MSRValue": "0x404000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7106,7 +7106,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000001", + "MSRValue": "0x104000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7120,7 +7120,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000001", + "MSRValue": "0x204000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7134,7 +7134,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000001", + "MSRValue": "0x604000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7148,7 +7148,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000001", + "MSRValue": "0x84000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7162,7 +7162,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800001", + "MSRValue": "0x63B800001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7204,7 +7204,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000001", + "MSRValue": "0x810000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7218,7 +7218,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000001", + "MSRValue": "0x410000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7232,7 +7232,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000001", + "MSRValue": "0x110000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7246,7 +7246,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000001", + "MSRValue": "0x210000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7260,7 +7260,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000001", + "MSRValue": "0x90000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7302,7 +7302,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000002", + "MSRValue": "0x83C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7316,7 +7316,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000002", + "MSRValue": "0x43C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7330,7 +7330,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000002", + "MSRValue": "0x13C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7358,7 +7358,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00002", + "MSRValue": "0x83FC00002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7372,7 +7372,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000002", + "MSRValue": "0x23C000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7386,7 +7386,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000002", + "MSRValue": "0xBC000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7428,7 +7428,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000002", + "MSRValue": "0x804000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7442,7 +7442,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000002", + "MSRValue": "0x404000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7456,7 +7456,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000002", + "MSRValue": "0x104000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7470,7 +7470,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000002", + "MSRValue": "0x204000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7484,7 +7484,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000002", + "MSRValue": "0x604000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7498,7 +7498,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000002", + "MSRValue": "0x84000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7512,7 +7512,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800002", + "MSRValue": "0x63B800002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7554,7 +7554,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000002", + "MSRValue": "0x810000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7568,7 +7568,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000002", + "MSRValue": "0x410000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7582,7 +7582,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000002", + "MSRValue": "0x110000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7596,7 +7596,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000002", + "MSRValue": "0x210000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7610,7 +7610,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000002", + "MSRValue": "0x90000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7652,7 +7652,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C008000", + "MSRValue": "0x83C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7666,7 +7666,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C008000", + "MSRValue": "0x43C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7680,7 +7680,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C008000", + "MSRValue": "0x13C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7708,7 +7708,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC08000", + "MSRValue": "0x83FC08000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7722,7 +7722,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C008000", + "MSRValue": "0x23C008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7736,7 +7736,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC008000", + "MSRValue": "0xBC008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7778,7 +7778,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804008000", + "MSRValue": "0x804008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7792,7 +7792,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404008000", + "MSRValue": "0x404008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7806,7 +7806,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104008000", + "MSRValue": "0x104008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7820,7 +7820,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204008000", + "MSRValue": "0x204008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7834,7 +7834,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604008000", + "MSRValue": "0x604008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7848,7 +7848,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084008000", + "MSRValue": "0x84008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7862,7 +7862,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B808000", + "MSRValue": "0x63B808000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7904,7 +7904,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810008000", + "MSRValue": "0x810008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7918,7 +7918,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410008000", + "MSRValue": "0x410008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7932,7 +7932,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110008000", + "MSRValue": "0x110008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7946,7 +7946,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210008000", + "MSRValue": "0x210008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7960,7 +7960,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090008000", + "MSRValue": "0x90008000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8002,7 +8002,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000400", + "MSRValue": "0x83C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8016,7 +8016,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000400", + "MSRValue": "0x43C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8030,7 +8030,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000400", + "MSRValue": "0x13C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8058,7 +8058,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00400", + "MSRValue": "0x83FC00400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8072,7 +8072,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000400", + "MSRValue": "0x23C000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8086,7 +8086,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000400", + "MSRValue": "0xBC000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8128,7 +8128,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000400", + "MSRValue": "0x804000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8142,7 +8142,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000400", + "MSRValue": "0x404000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8156,7 +8156,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000400", + "MSRValue": "0x104000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8170,7 +8170,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000400", + "MSRValue": "0x204000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8184,7 +8184,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000400", + "MSRValue": "0x604000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8198,7 +8198,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000400", + "MSRValue": "0x84000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8212,7 +8212,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800400", + "MSRValue": "0x63B800400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8254,7 +8254,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000400", + "MSRValue": "0x810000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8268,7 +8268,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000400", + "MSRValue": "0x410000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8282,7 +8282,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000400", + "MSRValue": "0x110000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8296,7 +8296,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000400", + "MSRValue": "0x210000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8310,7 +8310,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000400", + "MSRValue": "0x90000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8352,7 +8352,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000010", + "MSRValue": "0x83C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8366,7 +8366,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000010", + "MSRValue": "0x43C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8380,7 +8380,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000010", + "MSRValue": "0x13C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8408,7 +8408,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00010", + "MSRValue": "0x83FC00010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8422,7 +8422,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000010", + "MSRValue": "0x23C000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8436,7 +8436,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000010", + "MSRValue": "0xBC000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8478,7 +8478,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000010", + "MSRValue": "0x804000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8492,7 +8492,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000010", + "MSRValue": "0x404000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8506,7 +8506,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000010", + "MSRValue": "0x104000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8520,7 +8520,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000010", + "MSRValue": "0x204000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8534,7 +8534,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000010", + "MSRValue": "0x604000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8548,7 +8548,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000010", + "MSRValue": "0x84000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8562,7 +8562,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800010", + "MSRValue": "0x63B800010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8604,7 +8604,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000010", + "MSRValue": "0x810000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8618,7 +8618,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000010", + "MSRValue": "0x410000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8632,7 +8632,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000010", + "MSRValue": "0x110000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8646,7 +8646,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000010", + "MSRValue": "0x210000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8660,7 +8660,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000010", + "MSRValue": "0x90000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8702,7 +8702,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000020", + "MSRValue": "0x83C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8716,7 +8716,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000020", + "MSRValue": "0x43C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8730,7 +8730,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000020", + "MSRValue": "0x13C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8758,7 +8758,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00020", + "MSRValue": "0x83FC00020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8772,7 +8772,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000020", + "MSRValue": "0x23C000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8786,7 +8786,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000020", + "MSRValue": "0xBC000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8828,7 +8828,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000020", + "MSRValue": "0x804000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8842,7 +8842,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000020", + "MSRValue": "0x404000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8856,7 +8856,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000020", + "MSRValue": "0x104000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8870,7 +8870,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000020", + "MSRValue": "0x204000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8884,7 +8884,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000020", + "MSRValue": "0x604000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8898,7 +8898,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000020", + "MSRValue": "0x84000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8912,7 +8912,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800020", + "MSRValue": "0x63B800020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8954,7 +8954,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000020", + "MSRValue": "0x810000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8968,7 +8968,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000020", + "MSRValue": "0x410000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8982,7 +8982,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000020", + "MSRValue": "0x110000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8996,7 +8996,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000020", + "MSRValue": "0x210000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9010,7 +9010,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000020", + "MSRValue": "0x90000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9052,7 +9052,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000080", + "MSRValue": "0x83C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9066,7 +9066,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000080", + "MSRValue": "0x43C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9080,7 +9080,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000080", + "MSRValue": "0x13C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9108,7 +9108,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00080", + "MSRValue": "0x83FC00080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9122,7 +9122,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000080", + "MSRValue": "0x23C000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9136,7 +9136,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000080", + "MSRValue": "0xBC000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9178,7 +9178,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000080", + "MSRValue": "0x804000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9192,7 +9192,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000080", + "MSRValue": "0x404000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9206,7 +9206,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000080", + "MSRValue": "0x104000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9220,7 +9220,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000080", + "MSRValue": "0x204000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9234,7 +9234,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000080", + "MSRValue": "0x604000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9248,7 +9248,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000080", + "MSRValue": "0x84000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9262,7 +9262,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800080", + "MSRValue": "0x63B800080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9304,7 +9304,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000080", + "MSRValue": "0x810000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9318,7 +9318,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000080", + "MSRValue": "0x410000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9332,7 +9332,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000080", + "MSRValue": "0x110000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9346,7 +9346,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000080", + "MSRValue": "0x210000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9360,7 +9360,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000080", + "MSRValue": "0x90000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9402,7 +9402,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083C000100", + "MSRValue": "0x83C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9416,7 +9416,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C000100", + "MSRValue": "0x43C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9430,7 +9430,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C000100", + "MSRValue": "0x13C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9458,7 +9458,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00100", + "MSRValue": "0x83FC00100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9472,7 +9472,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C000100", + "MSRValue": "0x23C000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9486,7 +9486,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC000100", + "MSRValue": "0xBC000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9528,7 +9528,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0804000100", + "MSRValue": "0x804000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9542,7 +9542,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000100", + "MSRValue": "0x404000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9556,7 +9556,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000100", + "MSRValue": "0x104000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9570,7 +9570,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000100", + "MSRValue": "0x204000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9584,7 +9584,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000100", + "MSRValue": "0x604000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9598,7 +9598,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000100", + "MSRValue": "0x84000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9612,7 +9612,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800100", + "MSRValue": "0x63B800100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9654,7 +9654,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0810000100", + "MSRValue": "0x810000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9668,7 +9668,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0410000100", + "MSRValue": "0x410000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9682,7 +9682,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0110000100", + "MSRValue": "0x110000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9696,7 +9696,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0210000100", + "MSRValue": "0x210000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -9710,7 +9710,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0090000100", + "MSRValue": "0x90000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json index 2f111a22d81f..bb23a91b0127 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json @@ -76,475 +76,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100491", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100491", + "MSRValue": "0x10491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -570,7 +102,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400491", + "MSRValue": "0x80400491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -583,7 +115,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400491", + "MSRValue": "0x100400491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -622,7 +154,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020491", + "MSRValue": "0x800020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -635,7 +167,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020491", + "MSRValue": "0x400020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -648,7 +180,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020491", + "MSRValue": "0x100020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -661,7 +193,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020491", + "MSRValue": "0x200020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -674,7 +206,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020491", + "MSRValue": "0x80020491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -687,475 +219,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100490", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100490", + "MSRValue": "0x10490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1181,7 +245,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400490", + "MSRValue": "0x80400490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1194,7 +258,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400490", + "MSRValue": "0x100400490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1233,7 +297,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020490", + "MSRValue": "0x800020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1246,7 +310,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020490", + "MSRValue": "0x400020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1259,7 +323,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020490", + "MSRValue": "0x100020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1272,7 +336,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020490", + "MSRValue": "0x200020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1285,7 +349,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020490", + "MSRValue": "0x80020490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1298,475 +362,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100120", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100120", + "MSRValue": "0x10120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1792,7 +388,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400120", + "MSRValue": "0x80400120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1805,7 +401,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400120", + "MSRValue": "0x100400120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1844,7 +440,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020120", + "MSRValue": "0x800020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1857,7 +453,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020120", + "MSRValue": "0x400020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1870,7 +466,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020120", + "MSRValue": "0x100020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1883,7 +479,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020120", + "MSRValue": "0x200020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1896,7 +492,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020120", + "MSRValue": "0x80020120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1909,475 +505,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00000107F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C07F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C07F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C07F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C07F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C07F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C07F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C07F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C07F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F800807F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10000807F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000807F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000807F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000807F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000807F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800807F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F802007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10002007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08002007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04002007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01002007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02002007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00802007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F800407F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10000407F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000407F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000407F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000407F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000407F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800407F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F801007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08001007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001007F7", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801007F7", + "MSRValue": "0x107F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2403,7 +531,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00804007F7", + "MSRValue": "0x804007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2416,7 +544,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01004007F7", + "MSRValue": "0x1004007F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2455,7 +583,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08000207F7", + "MSRValue": "0x8000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2468,7 +596,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04000207F7", + "MSRValue": "0x4000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2481,7 +609,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01000207F7", + "MSRValue": "0x1000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2494,7 +622,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02000207F7", + "MSRValue": "0x2000207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2507,7 +635,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00800207F7", + "MSRValue": "0x800207F7", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -2520,475 +648,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100122", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100122", + "MSRValue": "0x10122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3014,7 +674,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400122", + "MSRValue": "0x80400122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3027,7 +687,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400122", + "MSRValue": "0x100400122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3066,7 +726,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020122", + "MSRValue": "0x800020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3079,7 +739,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020122", + "MSRValue": "0x400020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3092,7 +752,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020122", + "MSRValue": "0x100020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3105,7 +765,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020122", + "MSRValue": "0x200020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3118,7 +778,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020122", + "MSRValue": "0x80020122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3131,475 +791,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100004", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100004", + "MSRValue": "0x10004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3625,7 +817,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400004", + "MSRValue": "0x80400004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3638,7 +830,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400004", + "MSRValue": "0x100400004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3677,7 +869,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020004", + "MSRValue": "0x800020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3690,7 +882,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020004", + "MSRValue": "0x400020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3703,7 +895,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020004", + "MSRValue": "0x100020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3716,7 +908,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020004", + "MSRValue": "0x200020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3729,7 +921,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020004", + "MSRValue": "0x80020004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -3742,475 +934,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100001", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100001", + "MSRValue": "0x10001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4236,7 +960,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400001", + "MSRValue": "0x80400001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4249,7 +973,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400001", + "MSRValue": "0x100400001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4288,7 +1012,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020001", + "MSRValue": "0x800020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4301,7 +1025,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020001", + "MSRValue": "0x400020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4314,7 +1038,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020001", + "MSRValue": "0x100020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4327,7 +1051,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020001", + "MSRValue": "0x200020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4340,7 +1064,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020001", + "MSRValue": "0x80020001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4353,475 +1077,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100002", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100002", + "MSRValue": "0x10002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4847,7 +1103,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400002", + "MSRValue": "0x80400002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4860,7 +1116,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400002", + "MSRValue": "0x100400002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4899,7 +1155,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020002", + "MSRValue": "0x800020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4912,7 +1168,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020002", + "MSRValue": "0x400020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4925,7 +1181,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020002", + "MSRValue": "0x100020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4938,7 +1194,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020002", + "MSRValue": "0x200020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4951,7 +1207,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020002", + "MSRValue": "0x80020002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -4964,475 +1220,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.ANY_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C8000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HITM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C8000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C8000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C8000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C8000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C8000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C8000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80088000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000088000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800088000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400088000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100088000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200088000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080088000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80208000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000208000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800208000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400208000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100208000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200208000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080208000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80048000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000048000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800048000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400048000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100048000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200048000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080048000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80108000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000108000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800108000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400108000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100108000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200108000", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080108000", + "MSRValue": "0x18000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5458,7 +1246,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080408000", + "MSRValue": "0x80408000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5471,7 +1259,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100408000", + "MSRValue": "0x100408000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5510,7 +1298,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800028000", + "MSRValue": "0x800028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5523,7 +1311,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400028000", + "MSRValue": "0x400028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5536,7 +1324,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100028000", + "MSRValue": "0x100028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5549,7 +1337,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200028000", + "MSRValue": "0x200028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5562,7 +1350,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080028000", + "MSRValue": "0x80028000", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -5575,475 +1363,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100400", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100400", + "MSRValue": "0x10400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6069,7 +1389,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400400", + "MSRValue": "0x80400400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6082,7 +1402,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400400", + "MSRValue": "0x100400400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6121,7 +1441,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020400", + "MSRValue": "0x800020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6134,7 +1454,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020400", + "MSRValue": "0x400020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6147,7 +1467,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020400", + "MSRValue": "0x100020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6160,7 +1480,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020400", + "MSRValue": "0x200020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6173,7 +1493,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020400", + "MSRValue": "0x80020400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6186,475 +1506,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100010", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts prefetch (that bring data to L2) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100010", + "MSRValue": "0x10010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6680,7 +1532,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400010", + "MSRValue": "0x80400010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6693,7 +1545,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400010", + "MSRValue": "0x100400010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6732,7 +1584,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020010", + "MSRValue": "0x800020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6745,7 +1597,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020010", + "MSRValue": "0x400020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6758,7 +1610,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020010", + "MSRValue": "0x100020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6771,7 +1623,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020010", + "MSRValue": "0x200020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6784,7 +1636,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020010", + "MSRValue": "0x80020010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -6797,475 +1649,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100020", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100020", + "MSRValue": "0x10020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7291,7 +1675,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400020", + "MSRValue": "0x80400020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7304,7 +1688,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400020", + "MSRValue": "0x100400020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7343,7 +1727,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020020", + "MSRValue": "0x800020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7356,7 +1740,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020020", + "MSRValue": "0x400020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7369,7 +1753,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020020", + "MSRValue": "0x100020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7382,7 +1766,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020020", + "MSRValue": "0x200020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7395,7 +1779,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020020", + "MSRValue": "0x80020020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7408,475 +1792,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100080", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100080", + "MSRValue": "0x10080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7902,7 +1818,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400080", + "MSRValue": "0x80400080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7915,7 +1831,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400080", + "MSRValue": "0x100400080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7954,7 +1870,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020080", + "MSRValue": "0x800020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7967,7 +1883,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020080", + "MSRValue": "0x400020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7980,7 +1896,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020080", + "MSRValue": "0x100020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -7993,7 +1909,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020080", + "MSRValue": "0x200020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8006,7 +1922,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020080", + "MSRValue": "0x80020080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8019,475 +1935,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F803C0100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08007C0100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00803C0100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80080100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800080100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80200100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000200100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800200100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400200100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100200100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200200100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080200100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80040100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800040100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F80100100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800100100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100100", - "Offcore": "1", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100100", + "MSRValue": "0x10100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8513,7 +1961,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400100", + "MSRValue": "0x80400100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8526,7 +1974,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400100", + "MSRValue": "0x100400100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8565,7 +2013,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0800020100", + "MSRValue": "0x800020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8578,7 +2026,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020100", + "MSRValue": "0x400020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8591,7 +2039,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020100", + "MSRValue": "0x100020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8604,7 +2052,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020100", + "MSRValue": "0x200020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -8617,46 +2065,10 @@ "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020100", + "MSRValue": "0x80020100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "SampleAfterValue": "2000003", - "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json index ca5748120666..12eabae3e224 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json @@ -435,6 +435,17 @@ "PublicDescription": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", "SampleAfterValue": "2000003" }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, { "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", "Counter": "1", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json index 3be09986ce8b..7f1cf4d8f0fa 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-other.json @@ -558,6 +558,18 @@ "PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.", "Unit": "IIO" }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x0f", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", + "UMask": "0x03", + "Unit": "IIO" + }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", "Counter": "0,1,2,3", @@ -606,6 +618,17 @@ "UMask": "0x03", "Unit": "IIO" }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", + "UMask": "0x0f", + "Unit": "IIO" + }, { "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", "Counter": "2,3", diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json index 627691404155..de55b199ba79 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json @@ -179,246 +179,5 @@ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" - }, - { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.ALL", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", - "SampleAfterValue": "1000003", - "UMask": "0x6" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x4" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x73", - "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.ALL", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.REGISTER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x10" - }, - { - "BriefDescription": "This event is deprecated.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x74", - "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.ALL", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", - "SampleAfterValue": "1000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.CISC", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.DECODE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.ITLB", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", - "SampleAfterValue": "1000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.OTHER", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x80" - }, - { - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x71", - "EventName": "TOPDOWN_FE_BOUND.PREDECODE", - "PDIR_COUNTER": "na", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts the total number of consumed retirement slots.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xc2", - "EventName": "TOPDOWN_RETIRING.ALL", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json index 41e5dfad8f51..31816c6543a8 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json @@ -262,6 +262,247 @@ "PEBScounters": "0,1,2,3", "SampleAfterValue": "20003" }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "SampleAfterValue": "1000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REGISTER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "This event is deprecated.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.CISC", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.DECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ITLB", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.OTHER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the total number of consumed retirement slots.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, { "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).", "CollectPEBSRecord": "2", diff --git a/tools/perf/pmu-events/arch/x86/goldmont/cache.json b/tools/perf/pmu-events/arch/x86/goldmont/cache.json index 52a105666afc..0b887d73b7f3 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/cache.json @@ -1,1305 +1,1303 @@ [ { + "BriefDescription": "Requests rejected by the L2Q", "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", - "EventCode": "0x2E", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache request misses" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache requests" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.", - "EventCode": "0x30", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "L2_REJECT_XQ.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the XQ" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.", "EventCode": "0x31", - "Counter": "0,1,2,3", - "UMask": "0x0", "EventName": "CORE_REJECT_L2Q.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the L2Q" + "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "L1 Cache evictions for dirty data", "CollectPEBSRecord": "1", - "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback.", + "Counter": "0,1,2,3", "EventCode": "0x51", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "DL1.DIRTY_EVICTION", + "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback.", "SampleAfterValue": "200003", - "BriefDescription": "L1 Cache evictions for dirty data" + "UMask": "0x1" }, { + "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.", + "Counter": "0,1,2,3", "EventCode": "0x86", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss." + "UMask": "0x2" }, { + "BriefDescription": "Requests rejected by the XQ", "CollectPEBSRecord": "1", - "EventCode": "0xB7", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ALL", + "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "L2 cache request misses", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "L2 cache requests", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Loads retired that came from DRAM (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PEBS": "2", + "PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PEBS": "2", + "PublicDescription": "Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that hit the L1 data cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that miss the L1 data cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that hit in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Load uops retired that missed L2 (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that miss in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads retired that hit WCB (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "PEBS": "2", + "PublicDescription": "Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Memory uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL", + "PEBS": "2", + "PublicDescription": "Counts the number of memory uops retired that is either a loads or a store or both.", + "SampleAfterValue": "200003", + "UMask": "0x83" + }, + { + "BriefDescription": "Load uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "2", + "PublicDescription": "Counts the number of load uops retired.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Store uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "2", + "PublicDescription": "Counts the number of store uops retired.", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Locked load uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "2", + "PublicDescription": "Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks.", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "PEBS": "2", + "PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.", + "SampleAfterValue": "200003", + "UMask": "0x43" + }, + { + "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "2", + "PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "2", + "PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.", + "SampleAfterValue": "200003", + "UMask": "0x42" + }, + { + "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100007", - "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Locked load uops retired (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "200003", - "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x43", - "EventName": "MEM_UOPS_RETIRED.SPLIT", - "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of load uops retired.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of store uops retired.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of memory uops retired that is either a loads or a store or both.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x83", - "EventName": "MEM_UOPS_RETIRED.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit the L1 data cache.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit in the L2 cache.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss the L1 data cache.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss in the L2 cache.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L2 (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", - "SampleAfterValue": "200003", - "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that hit WCB (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that came from DRAM (Precise event capable)", - "Data_LA": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x36000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "EventCode": "0xB7", - "MSRValue": "0x10000032b7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x04000032b7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x02000032b7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x00000432b7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600003091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000003091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400003091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043091", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000043091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600003091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000003091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400003091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003010", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200003091", + "Offcore": "1", + "PublicDescription": "Counts data reads (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043010", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000043010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000008000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600003010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400008000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000003010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200008000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400003010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000048000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200003010", + "Offcore": "1", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000018000", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00000432b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x36000032b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10000032b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04000032b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x02000032b7", + "Offcore": "1", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000018000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem that have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600004800", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000048000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000044800", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000008000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600004000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400008000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000004000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200008000", + "Offcore": "1", + "PublicDescription": "Counts requests to the uncore subsystem that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400004000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200004000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000044000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_HIT", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000022", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400002000", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "EventCode": "0xB7", - "MSRValue": "0x0200002000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000042000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600001000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000001000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400001000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200001000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000041000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010400", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010400", + "Offcore": "1", + "PublicDescription": "Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests that have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000100", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "EventCode": "0xB7", - "MSRValue": "0x3600000080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040008", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", "MSRIndex": "0x1a6", + "MSRValue": "0x0000040008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", "MSRIndex": "0x1a6", + "MSRValue": "0x3600000008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6", + "MSRValue": "0x1000000008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6", + "MSRValue": "0x0400000008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000004", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6", + "MSRValue": "0x0200000008", + "Offcore": "1", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040004", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000004", + "Offcore": "1", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000002", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "EventCode": "0xB7", - "MSRValue": "0x1000000002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x3600000001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0400000001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040001", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines that hit the L2 cache.", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full cache lines that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000001", + "Offcore": "1", + "PublicDescription": "Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000002", + "Offcore": "1", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that are outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000800", + "Offcore": "1", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000080", + "Offcore": "1", + "PublicDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000044000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600004000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000004000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400004000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200004000", + "Offcore": "1", + "PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000100", + "Offcore": "1", + "PublicDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000042000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600002000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000002000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400002000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200002000", + "Offcore": "1", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000010", + "Offcore": "1", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000040020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600000020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000020", + "Offcore": "1", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000044800", + "Offcore": "1", + "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600004800", + "Offcore": "1", + "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000041000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions that hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3600001000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000001000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400001000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache with a snoop hit in the other processor module, no data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200001000", + "Offcore": "1", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions that true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json new file mode 100644 index 000000000000..bb364a04a75f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json @@ -0,0 +1,33 @@ +[ + { + "BriefDescription": "Cycles the FP divide unit is busy", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.FPDIV", + "PublicDescription": "Counts core cycles the floating point divide unit is busy.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Machine clears due to FP assists", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Floating point divide uops retired. (Precise Event Capable)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.FPDIV", + "PEBS": "2", + "PublicDescription": "Counts the number of floating point divide uops retired.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json index 9ba08518649e..120ff65897c0 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json @@ -1,52 +1,82 @@ [ { + "BriefDescription": "BACLEARs asserted for any branch type", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", + "EventCode": "0xE6", + "EventName": "BACLEARS.ALL", + "PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture" + "UMask": "0x1" }, { + "BriefDescription": "BACLEARs asserted for conditional branch", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", + "EventCode": "0xE6", + "EventName": "BACLEARS.COND", + "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture" + "UMask": "0x10" }, { + "BriefDescription": "BACLEARs asserted for return branch", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "ICACHE.ACCESSES", + "EventCode": "0xE6", + "EventName": "BACLEARS.RETURN", + "PublicDescription": "Counts BACLEARS on return instructions.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture" + "UMask": "0x8" }, { + "BriefDescription": "Decode restrictions due to predicting wrong instruction length", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.", - "EventCode": "0xE7", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MS_DECODED.MS_ENTRY", - "SampleAfterValue": "200003", - "BriefDescription": "MS decode starts" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.", "EventCode": "0xE9", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.", "SampleAfterValue": "200003", - "BriefDescription": "Decode restrictions due to predicting wrong instruction length" + "UMask": "0x1" + }, + { + "BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "MS decode starts", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xE7", + "EventName": "MS_DECODED.MS_ENTRY", + "PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.", + "SampleAfterValue": "200003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/memory.json b/tools/perf/pmu-events/arch/x86/goldmont/memory.json index 197dc76d49dd..6252503f68a1 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/memory.json @@ -1,34 +1,34 @@ [ { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.", - "EventCode": "0x13", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops that split a page (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.", - "EventCode": "0x13", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", - "SampleAfterValue": "200003", - "BriefDescription": "Store uops that split a page (Precise event capable)" - }, - { + "BriefDescription": "Machine clears due to memory ordering issue", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data.", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data.", "SampleAfterValue": "200003", - "BriefDescription": "Machine clears due to memory ordering issue" + "UMask": "0x2" + }, + { + "BriefDescription": "Load uops that split a page (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "PEBS": "2", + "PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Store uops that split a page (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PEBS": "2", + "PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.", + "SampleAfterValue": "200003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/other.json b/tools/perf/pmu-events/arch/x86/goldmont/other.json index 959cadd7cb0e..e4605e636447 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/other.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/other.json @@ -1,82 +1,80 @@ [ { + "BriefDescription": "Cycles code-fetch stalled due to any reason.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x86", "EventName": "FETCH_STALL.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to any reason." + "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.", + "Counter": "0,1,2,3", "EventCode": "0x86", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", + "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss." - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", - "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", - "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", - "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle to recover" + "UMask": "0x1" }, { + "BriefDescription": "Cycles hardware interrupts are masked", "CollectPEBSRecord": "2", - "PublicDescription": "Counts hardware interrupts received by the processor.", - "EventCode": "0xCB", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "HW_INTERRUPTS.RECEIVED", - "SampleAfterValue": "203", - "BriefDescription": "Hardware interrupts received" - }, - { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "HW_INTERRUPTS.MASKED", + "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles hardware interrupts are masked" + "UMask": "0x2" }, { + "BriefDescription": "Cycles pending interrupts are masked", "CollectPEBSRecord": "2", - "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).", - "EventCode": "0xCB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).", "SampleAfterValue": "200003", - "BriefDescription": "Cycles pending interrupts are masked" + "UMask": "0x4" + }, + { + "BriefDescription": "Hardware interrupts received", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.RECEIVED", + "PublicDescription": "Counts hardware interrupts received by the processor.", + "SampleAfterValue": "203", + "UMask": "0x1" + }, + { + "BriefDescription": "Unfilled issue slots per cycle", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", + "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Unfilled issue slots per cycle to recover", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", + "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", + "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.", + "SampleAfterValue": "200003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json index 6342368accf8..cb9155c3836d 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json @@ -1,452 +1,382 @@ [ { - "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Fixed event)" - }, - { - "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted (Fixed event)" - }, - { - "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted (Fixed event)" - }, - { - "PEBS": "2", + "BriefDescription": "Retired branch instructions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS.DATA_UNKNOWN", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "LD_BLOCKS.4K_ALIAS", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.UTLB_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts anytime a load that retires is blocked for any reason.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "LD_BLOCKS.ALL_BLOCK", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked (Precise event capable)" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "200003", - "BriefDescription": "Uops issued to the back end per cycle" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.CORE_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Reference cycles when core is not halted. This event uses a programmable general purpose performance counter.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.", - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "UOPS_NOT_DELIVERED.ANY", - "SampleAfterValue": "200003", - "BriefDescription": "Uops requested but not-delivered to the back-end per cycle" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops which retired.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "UOPS_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops retired (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.MS", - "SampleAfterValue": "2000003", - "BriefDescription": "MS uops retired (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of floating point divide uops retired.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_RETIRED.FPDIV", - "SampleAfterValue": "2000003", - "BriefDescription": "Floating point divide uops retired. (Precise Event Capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of integer divide uops retired.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.IDIV", - "SampleAfterValue": "2000003", - "BriefDescription": "Integer divide uops retired. (Precise Event Capable)" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears for any reason.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "MACHINE_CLEARS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "All machine clears" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel\u00ae architecture processors.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "200003", - "BriefDescription": "Self-Modifying Code detected" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.FP_ASSIST", - "SampleAfterValue": "200003", - "BriefDescription": "Machine clears due to FP assists" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MACHINE_CLEARS.DISAMBIGUATION", - "SampleAfterValue": "200003", - "BriefDescription": "Machine clears due to memory disambiguation" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.", "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x0", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired branch instructions (Precise event capable)" + "PEBS": "2", + "PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.", + "SampleAfterValue": "200003" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x7e", - "EventName": "BR_INST_RETIRED.JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions (Precise event capable)" - }, - { - "PEBS": "2", + "BriefDescription": "Retired taken branch instructions (Precise event capable)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of taken branch instructions retired.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", + "PEBS": "2", + "PublicDescription": "Counts the number of taken branch instructions retired.", "SampleAfterValue": "200003", - "BriefDescription": "Retired taken branch instructions (Precise event capable)" + "UMask": "0x80" }, { - "PEBS": "2", + "BriefDescription": "Retired near call instructions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xbf", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "200003", - "BriefDescription": "Retired far branch instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.", "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xeb", - "EventName": "BR_INST_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near return branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xf7", - "EventName": "BR_INST_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near return instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near CALL branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xf9", "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "2", + "PublicDescription": "Counts near CALL branch instructions retired.", "SampleAfterValue": "200003", - "BriefDescription": "Retired near call instructions (Precise event capable)" + "UMask": "0xf9" }, { - "PEBS": "2", + "BriefDescription": "Retired far branch instructions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect CALL branch instructions retired.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xfb", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "2", + "PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.", + "SampleAfterValue": "200003", + "UMask": "0xbf" + }, + { + "BriefDescription": "Retired near indirect call instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "2", + "PublicDescription": "Counts near indirect CALL branch instructions retired.", "SampleAfterValue": "200003", - "BriefDescription": "Retired near indirect call instructions (Precise event capable)" + "UMask": "0xfb" }, { - "PEBS": "2", + "BriefDescription": "Retired conditional branch instructions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts near relative CALL branch instructions retired.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0xfd", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "2", + "PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "2", + "PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Retired near relative call instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "2", + "PublicDescription": "Counts near relative CALL branch instructions retired.", "SampleAfterValue": "200003", - "BriefDescription": "Retired near relative call instructions (Precise event capable)" + "UMask": "0xfd" }, { - "PEBS": "2", + "BriefDescription": "Retired near return instructions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.", + "Counter": "0,1,2,3", "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "2", + "PublicDescription": "Counts near return branch instructions retired.", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0xfe", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "2", + "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.", "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)" + "UMask": "0xfe" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted branch instructions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions retired including all branch types.", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted branch instructions (Precise event capable)" + "PEBS": "2", + "PublicDescription": "Counts mispredicted branch instructions retired including all branch types.", + "SampleAfterValue": "200003" }, { - "PEBS": "2", + "BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0x7e", - "EventName": "BR_MISP_RETIRED.JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.", "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0xeb", - "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0xf7", - "EventName": "BR_MISP_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near return instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0xfb", "EventName": "BR_MISP_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)" - }, - { "PEBS": "2", + "PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "2", + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0xfe", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "2", + "PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Retired mispredicted near return instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "2", + "PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "2", + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.", "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)" + "UMask": "0xfe" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles if either divide unit is busy.", - "EventCode": "0xCD", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CYCLES_DIV_BUSY.ALL", + "BriefDescription": "Core cycles when core is not halted (Fixed event)", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.CORE", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a divider is busy" + "UMask": "0x2" }, { + "BriefDescription": "Core cycles when core is not halted", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the integer divide unit is busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Reference cycles when core is not halted", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF", + "PublicDescription": "Reference cycles when core is not halted. This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Reference cycles when core is not halted (Fixed event)", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Cycles a divider is busy", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.ALL", + "PublicDescription": "Counts core cycles if either divide unit is busy.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Cycles the integer divide unit is busy", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.IDIV", + "PublicDescription": "Counts core cycles the integer divide unit is busy.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles the integer divide unit is busy" + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the floating point divide unit is busy.", - "EventCode": "0xCD", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLES_DIV_BUSY.FPDIV", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the FP divide unit is busy" + "BriefDescription": "Instructions retired (Fixed event)", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { + "BriefDescription": "Instructions retired (Precise event capable)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.", - "EventCode": "0xE6", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BACLEARS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for any branch type" + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "2", + "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.", + "SampleAfterValue": "2000003" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on return instructions.", - "EventCode": "0xE6", + "BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BACLEARS.RETURN", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", + "PEBS": "2", + "PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.", "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for return branch" + "UMask": "0x4" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.", - "EventCode": "0xE6", + "BriefDescription": "Loads blocked (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BACLEARS.COND", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "PEBS": "2", + "PublicDescription": "Counts anytime a load that retires is blocked for any reason.", "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for conditional branch" + "UMask": "0x10" + }, + { + "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PEBS": "2", + "PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBS": "2", + "PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.UTLB_MISS", + "PEBS": "2", + "PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "All machine clears", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.ALL", + "PublicDescription": "Counts machine clears for any reason.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Machine clears due to memory disambiguation", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Self-Modifying Code detected", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops issued to the back end per cycle", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UOPS_NOT_DELIVERED.ANY", + "PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ANY", + "PEBS": "2", + "PublicDescription": "Counts uops which retired.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Integer divide uops retired. (Precise Event Capable)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "2", + "PublicDescription": "Counts the number of integer divide uops retired.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "MS uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.MS", + "PEBS": "2", + "PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json index 343d66bbd777..d5e89c74a9be 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json @@ -1,78 +1,78 @@ [ { + "BriefDescription": "ITLB misses", "CollectPEBSRecord": "1", - "PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.", - "EventCode": "0x05", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Duration of D-side page-walks in cycles" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Duration of I-side pagewalks in cycles" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "PAGE_WALKS.CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Duration of page-walks in cycles" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.", "EventCode": "0x81", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "ITLB.MISS", + "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.", "SampleAfterValue": "200003", - "BriefDescription": "ITLB misses" + "UMask": "0x4" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that caused a DTLB miss.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired that caused a DTLB miss.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", - "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x13", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", - "SampleAfterValue": "200003", "BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)", - "Data_LA": "1" + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", + "PEBS": "2", + "PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.", + "SampleAfterValue": "200003", + "UMask": "0x13" + }, + { + "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "2", + "PublicDescription": "Counts load uops retired that caused a DTLB miss.", + "SampleAfterValue": "200003", + "UMask": "0x11" + }, + { + "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", + "PEBS": "2", + "PublicDescription": "Counts store uops retired that caused a DTLB miss.", + "SampleAfterValue": "200003", + "UMask": "0x12" + }, + { + "BriefDescription": "Duration of page-walks in cycles", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.CYCLES", + "PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Duration of D-side page-walks in cycles", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Duration of I-side pagewalks in cycles", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.", + "SampleAfterValue": "200003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json index 5a6ac8285ad4..59c039169eb8 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json @@ -1,1467 +1,1465 @@ [ { + "BriefDescription": "Requests rejected by the L2Q", "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", - "EventCode": "0x2E", "Counter": "0,1,2,3", - "UMask": "0x41", - "PEBScounters": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache request misses" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "PEBScounters": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache requests" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.", - "EventCode": "0x30", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "L2_REJECT_XQ.ALL", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the XQ" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.", "EventCode": "0x31", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", "EventName": "CORE_REJECT_L2Q.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Requests rejected by the L2Q" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand and L1 prefetcher requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "L1 Cache evictions for dirty data", "CollectPEBSRecord": "1", - "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback.", - "EventCode": "0x51", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0x51", "EventName": "DL1.REPLACEMENT", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts when a modified (dirty) cache line is evicted from the data L1 cache and needs to be written back to memory. No count will occur if the evicted line is clean, and hence does not require a writeback.", "SampleAfterValue": "200003", - "BriefDescription": "L1 Cache evictions for dirty data" + "UMask": "0x1" }, { + "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", + "EventCode": "0x86", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss." + "UMask": "0x2" }, { + "BriefDescription": "Requests rejected by the XQ", "CollectPEBSRecord": "1", - "EventCode": "0xB7", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ALL", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cacheable requests), L2 misses and L2 write-back victims.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "L2 cache request misses", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory requests originating from the core that miss in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "L2 cache requests", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory requests originating from the core that reference a cache line in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Loads retired that came from DRAM (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts load uops retired that hit the L1 data cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts load uops retired that miss the L1 data cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts load uops retired that hit in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Load uops retired that missed L2 (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts load uops retired that miss in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads retired that hit WCB (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Memory uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of memory uops retired that is either a loads or a store or both.", + "SampleAfterValue": "200003", + "UMask": "0x83" + }, + { + "BriefDescription": "Load uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of load uops retired.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Store uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of store uops retired.", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Locked load uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks.", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.", + "SampleAfterValue": "200003", + "UMask": "0x43" + }, + { + "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.", + "SampleAfterValue": "200003", + "UMask": "0x42" + }, + { + "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE", "PDIR_COUNTER": "na", - "SampleAfterValue": "100007", - "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts locked memory uops retired. This includes regular locks and bus locks. (To specifically count bus locks only, see the Offcore response event.) A locked access is one with a lock prefix, or an exchange to memory. See the SDM for a complete description of which memory load accesses are locks.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x21", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Locked load uops retired (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the data requested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x41", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired where the data requested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x42", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "200003", - "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory uops retired where the data requested spans a 64 byte cache line boundary.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x43", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT", - "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of load uops retired.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x81", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of store uops retired.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x82", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of memory uops retired that is either a loads or a store or both.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x83", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit the L1 data cache.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that hit in the L2 cache.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that hit L2 (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss the L1 data cache.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that miss in the L2 cache.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed L2 (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired where the cache line containing the data was in the modified state of another core or modules cache (HITM). More specifically, this means that when the load address was checked by other caching agents (typically another processor) in the system, one of those caching agents indicated that they had a dirty copy of the data. Loads that obtain a HITM response incur greater latency than most is typical for a load. In addition, since HITM indicates that some other processor had this data in its cache, it implies that the data was shared between processors, or potentially was a lock or semaphore value. This event is useful for locating sharing, false sharing, and contended locks.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", - "SampleAfterValue": "200003", - "BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the data is retrieved from the WCB (or fill buffer), indicating that the load found its data while that data was in the process of being brought into the L1 cache. Typically a load will receive this indication when some other load or prefetch missed the L1 cache and was in the process of retrieving the cache line containing the data, but that process had not yet finished (and written the data back to the cache). For example, consider load X and Y, both referencing the same cache line that is not in the L1 cache. If load X misses cache first, it obtains and WCB (or fill buffer) and begins the process of requesting the data. When load Y requests the data, it will either hit the WCB, or the L1 cache, depending on exactly what time the request to Y occurs.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that hit WCB (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts memory load uops retired where the data is retrieved from DRAM. Event is counted at retirement, so the speculative loads are ignored. A memory load can hit (or miss) the L1 cache, hit (or miss) the L2 cache, hit DRAM, hit in the WCB or receive a HITM response.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Loads retired that came from DRAM (Precise event capable)", - "Data_LA": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000010", - "Counter": "0,1,2,3", - "UMask": "0x1", "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010400", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040400", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000400", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000400", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000400", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000040800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000011000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000041000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200001000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000001000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000001000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000012000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000042000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200002000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000002000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000002000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000014800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000044800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200004800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000004800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000004800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000018000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000048000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200008000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000008000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000008000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000013010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000003010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000003010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000013091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", "BriefDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000013091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000043091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", "BriefDescription": "Counts data reads (demand & prefetch) hit the L2 cache.", - "Offcore": "1" + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000043091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200003091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000003091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", "BriefDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000003091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000003091", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200003091", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { "BriefDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0000010022", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "EventCode": "0xB7", - "MSRValue": "0x0000040022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x0200000022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x1000000022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x4000000022", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", - "PDIR_COUNTER": "na", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000003091", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", - "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x00000132b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", - "PDIR_COUNTER": "na", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000013010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000043010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000003010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200003010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000003010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.", - "Offcore": "1" + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x00000132b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x00000432b7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache.", - "Offcore": "1" + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x00000432b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x02000032b7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.", - "Offcore": "1" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x10000032b7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", - "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100007", "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", - "Offcore": "1" + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x10000032b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { + "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", - "EventCode": "0xB7", - "MSRValue": "0x40000032b7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x02000032b7", + "Offcore": "1", "PDIR_COUNTER": "na", - "MSRIndex": "0x1a6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { "BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x40000032b7", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000018000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts requests to the uncore subsystem hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000048000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000008000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200008000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000008000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000022", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts bus lock and split lock requests hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000400", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000008", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000004", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full cache lines have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full cache lines hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full cache lines true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000001", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000002", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000012000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000042000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000002000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200002000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000002000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000010", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000010020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000040020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000000020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200000020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000020", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000014800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000044800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000004800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200004800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000004800", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000011000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions have any transaction responses from the uncore subsystem. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0000041000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions hit the L2 cache. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x1000001000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6, 0x1a7", + "MSRValue": "0x0200001000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000001000", + "Offcore": "1", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts data cache lines requests by software prefetch instructions outstanding, per cycle, from the time of the L2 miss to when any response is received. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)", + "SampleAfterValue": "100007", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json new file mode 100644 index 000000000000..c1f00c9470f4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json @@ -0,0 +1,38 @@ +[ + { + "BriefDescription": "Cycles the FP divide unit is busy", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.FPDIV", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts core cycles the floating point divide unit is busy.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Machine clears due to FP assists", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.", + "SampleAfterValue": "20003", + "UMask": "0x4" + }, + { + "BriefDescription": "Floating point divide uops retired (Precise Event Capable)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.FPDIV", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of floating point divide uops retired.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json index a7878965ceab..3fdc788a2b20 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json @@ -1,62 +1,98 @@ [ { + "BriefDescription": "BACLEARs asserted for any branch type", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "ICACHE.HIT", + "EventCode": "0xE6", + "EventName": "BACLEARS.ALL", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture" + "UMask": "0x1" }, { + "BriefDescription": "BACLEARs asserted for conditional branch", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "ICACHE.MISSES", + "EventCode": "0xE6", + "EventName": "BACLEARS.COND", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture" + "UMask": "0x10" }, { + "BriefDescription": "BACLEARs asserted for return branch", "CollectPEBSRecord": "1", - "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x3", - "PEBScounters": "0,1,2,3", - "EventName": "ICACHE.ACCESSES", + "EventCode": "0xE6", + "EventName": "BACLEARS.RETURN", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts BACLEARS on return instructions.", "SampleAfterValue": "200003", - "BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture" + "UMask": "0x8" }, { + "BriefDescription": "Decode restrictions due to predicting wrong instruction length", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.", - "EventCode": "0xE7", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "MS_DECODED.MS_ENTRY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "MS decode starts" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.", "EventCode": "0xE9", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the prediction (from the predecode cache) for instruction length is incorrect.", "SampleAfterValue": "200003", - "BriefDescription": "Decode restrictions due to predicting wrong instruction length" + "UMask": "0x1" + }, + { + "BriefDescription": "References per ICache line. This event counts differently than Intel processors based on Silvermont microarchitecture", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.\r\nThis event counts differently than Intel processors based on Silvermont microarchitecture.", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "References per ICache line that are available in the ICache (hit). This event counts differently than Intel processors based on Silvermont microarchitecture", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is in the ICache (hit). The event strives to count on a cache line basis, so that multiple accesses which hit in a single cache line count as one ICACHE.HIT. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "References per ICache line that are not available in the ICache (miss). This event counts differently than Intel processors based on Silvermont microarchitecture", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache. This event counts differently than Intel processors based on Silvermont microarchitecture.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "MS decode starts", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xE7", + "EventName": "MS_DECODED.MS_ENTRY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the Microcode Sequencer (MS) starts a flow of uops from the MSROM. It does not count every time a uop is read from the MSROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort that initiates a flow of uops. The event will count MS startups for uops that are speculative, and subsequently cleared by branch mispredict or a machine clear.", + "SampleAfterValue": "200003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json index 91e0815f3ffb..e26763d16d52 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json @@ -1,38 +1,38 @@ [ { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.", - "EventCode": "0x13", - "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops that split a page (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.", - "EventCode": "0x13", - "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", - "SampleAfterValue": "200003", - "BriefDescription": "Store uops that split a page (Precise event capable)" - }, - { + "BriefDescription": "Machine clears due to memory ordering issue", "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data.", - "EventCode": "0xC3", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data.", "SampleAfterValue": "20003", - "BriefDescription": "Machine clears due to memory ordering issue" + "UMask": "0x2" + }, + { + "BriefDescription": "Load uops that split a page (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts when a memory load of a uop spans a page boundary (a split) is retired.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Store uops that split a page (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts when a memory store of a uop spans a page boundary (a split) is retired.", + "SampleAfterValue": "200003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json index b860374418ab..3378f48cb818 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json @@ -1,98 +1,96 @@ [ { + "BriefDescription": "Cycles code-fetch stalled due to any reason.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", + "EventCode": "0x86", "EventName": "FETCH_STALL.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to any reason." + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss is outstanding.", "CollectPEBSRecord": "1", - "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.", - "EventCode": "0x86", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0x86", "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss is outstanding." - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x0", "PEBScounters": "0,1,2,3", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", - "PDIR_COUNTER": "na", + "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.", "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Unfilled issue slots per cycle to recover" + "UMask": "0x1" }, { + "BriefDescription": "Cycles hardware interrupts are masked", "CollectPEBSRecord": "2", - "PublicDescription": "Counts hardware interrupts received by the processor.", - "EventCode": "0xCB", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "HW_INTERRUPTS.RECEIVED", - "PDIR_COUNTER": "na", - "SampleAfterValue": "203", - "BriefDescription": "Hardware interrupts received" - }, - { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", "EventName": "HW_INTERRUPTS.MASKED", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles hardware interrupts are masked" + "UMask": "0x2" }, { + "BriefDescription": "Cycles pending interrupts are masked", "CollectPEBSRecord": "2", - "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).", - "EventCode": "0xCB", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts core cycles during which there are pending interrupts, but interrupts are masked (EFLAGS.IF = 0).", "SampleAfterValue": "200003", - "BriefDescription": "Cycles pending interrupts are masked" + "UMask": "0x4" + }, + { + "BriefDescription": "Hardware interrupts received", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "HW_INTERRUPTS.RECEIVED", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts hardware interrupts received by the processor.", + "SampleAfterValue": "203", + "UMask": "0x1" + }, + { + "BriefDescription": "Unfilled issue slots per cycle", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend due to either a full resource in the backend (RESOURCE_FULL) or due to the processor recovering from some event (RECOVERY).", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Unfilled issue slots per cycle to recover", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xCA", + "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.", + "SampleAfterValue": "200003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json index e3fa1a0ba71b..8305e2ecf617 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json @@ -1,541 +1,459 @@ [ { + "BriefDescription": "Retired branch instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "PEBScounters": "32", - "EventName": "INST_RETIRED.ANY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Fixed event)" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Retired taken branch instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of taken branch instructions retired.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Retired near call instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts near CALL branch instructions retired.", + "SampleAfterValue": "200003", + "UMask": "0xf9" + }, + { + "BriefDescription": "Retired far branch instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.", + "SampleAfterValue": "200003", + "UMask": "0xbf" + }, + { + "BriefDescription": "Retired near indirect call instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts near indirect CALL branch instructions retired.", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "Retired conditional branch instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Retired near relative call instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts near relative CALL branch instructions retired.", + "SampleAfterValue": "200003", + "UMask": "0xfd" + }, + { + "BriefDescription": "Retired near return instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts near return branch instructions retired.", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Retired mispredicted branch instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts mispredicted branch instructions retired including all branch types.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Retired mispredicted near return instructions (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Core cycles when core is not halted (Fixed event)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.", "Counter": "Fixed counter 1", - "UMask": "0x2", - "PEBScounters": "33", "EventName": "CPU_CLK_UNHALTED.CORE", "PDIR_COUNTER": "na", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.", "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted (Fixed event)" + "UMask": "0x2" }, { + "BriefDescription": "Core cycles when core is not halted", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "PEBScounters": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted (Fixed event)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.", - "EventCode": "0x03", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.DATA_UNKNOWN", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.4K_ALIAS", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.UTLB_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts anytime a load that retires is blocked for any reason.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", - "EventName": "LD_BLOCKS.ALL_BLOCK", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked (Precise event capable)" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Uops issued to the back end per cycle" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.", "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Reference cycles when core is not halted", "CollectPEBSRecord": "1", - "PublicDescription": "Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.", - "EventCode": "0x3C", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.", "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted" + "UMask": "0x1" }, { + "BriefDescription": "Reference cycles when core is not halted (Fixed event)", "CollectPEBSRecord": "1", - "PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.", - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "UOPS_NOT_DELIVERED.ANY", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Uops requested but not-delivered to the back-end per cycle" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.", "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired (Precise event capable)" + "UMask": "0x3" }, { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.PREC_DIST", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops which retired.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.ANY", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops retired (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.MS", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "MS uops retired (Precise event capable)" - }, - { - "PEBS": "2", + "BriefDescription": "Cycles a divider is busy", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of floating point divide uops retired.", - "EventCode": "0xC2", "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.FPDIV", - "SampleAfterValue": "2000003", - "BriefDescription": "Floating point divide uops retired (Precise Event Capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of integer divide uops retired.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", - "EventName": "UOPS_RETIRED.IDIV", - "SampleAfterValue": "2000003", - "BriefDescription": "Integer divide uops retired (Precise Event Capable)" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears for any reason.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.ALL", - "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "All machine clears" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel\u00ae architecture processors.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", - "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Self-Modifying Code detected" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to floating point (FP) operations needing assists. For instance, if the result was a floating point denormal, the hardware clears the pipeline and reissues uops to produce the correct IEEE compliant denormal result.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.FP_ASSIST", - "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machine clears due to FP assists" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.DISAMBIGUATION", - "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machine clears due to memory disambiguation" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x20", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.PAGE_FAULT", - "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Machines clear due to a page fault" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired branch instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x7e", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of taken branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x80", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired taken branch instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xbf", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "200003", - "BriefDescription": "Retired far branch instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xeb", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near return branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xf7", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near return instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near CALL branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xf9", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near call instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near indirect CALL branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xfb", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near indirect call instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts near relative CALL branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xfd", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.REL_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired near relative call instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0xfe", - "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions retired including all branch types.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted branch instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x7e", - "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0xeb", - "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0xf7", - "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near return instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0xfb", - "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0xfe", - "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles if either divide unit is busy.", "EventCode": "0xCD", - "Counter": "0,1,2,3", - "UMask": "0x0", - "PEBScounters": "0,1,2,3", "EventName": "CYCLES_DIV_BUSY.ALL", "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a divider is busy" + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts core cycles if either divide unit is busy.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Cycles the integer divide unit is busy", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the integer divide unit is busy.", - "EventCode": "0xCD", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.IDIV", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts core cycles the integer divide unit is busy.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles the integer divide unit is busy" + "UMask": "0x1" }, { + "BriefDescription": "Instructions retired (Fixed event)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts core cycles the floating point divide unit is busy.", - "EventCode": "0xCD", - "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "CYCLES_DIV_BUSY.FPDIV", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Cycles the FP divide unit is busy" + "PEBS": "2", + "PEBScounters": "32", + "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { + "BriefDescription": "Instructions retired (Precise event capable)", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.", - "EventCode": "0xE6", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BACLEARS.ALL", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for any branch type" + "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.", + "SampleAfterValue": "2000003" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on return instructions.", - "EventCode": "0xE6", + "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", - "EventName": "BACLEARS.RETURN", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for return branch" + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "Counts INST_RETIRED.ANY using the Reduced Skid PEBS feature that reduces the shadow in which events aren't counted allowing for a more unbiased distribution of samples across instructions retired.", + "SampleAfterValue": "2000003" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.", - "EventCode": "0xE6", + "BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", + "PEBS": "2", "PEBScounters": "0,1,2,3", - "EventName": "BACLEARS.COND", - "PDIR_COUNTER": "na", + "PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.", "SampleAfterValue": "200003", - "BriefDescription": "BACLEARs asserted for conditional branch" + "UMask": "0x4" + }, + { + "BriefDescription": "Loads blocked (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts anytime a load that retires is blocked for any reason.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads blocked due to store data not ready (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.UTLB_MISS", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "All machine clears", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts machine clears for any reason.", + "SampleAfterValue": "20003" + }, + { + "BriefDescription": "Machine clears due to memory disambiguation", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts machine clears due to memory disambiguation. Memory disambiguation happens when a load which has been issued conflicts with a previous unretired store in the pipeline whose address was not known at issue time, but is later resolved to be the same as the load address.", + "SampleAfterValue": "20003", + "UMask": "0x8" + }, + { + "BriefDescription": "Machines clear due to a page fault", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times that the machines clears due to a page fault. Covers both I-side and D-side(Loads/Stores) page faults. A page fault occurs when either page is not present, or an access violation", + "SampleAfterValue": "20003", + "UMask": "0x20" + }, + { + "BriefDescription": "Self-Modifying Code detected", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.", + "SampleAfterValue": "20003", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops issued to the back end per cycle", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Uops requested but not-delivered to the back-end per cycle", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "UOPS_NOT_DELIVERED.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ANY", + "PDIR_COUNTER": "na", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops which retired.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Integer divide uops retired (Precise Event Capable)", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of integer divide uops retired.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "MS uops retired (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.MS", + "PDIR_COUNTER": "na", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops retired that are from the complex flows issued by the micro-sequencer (MS). Counts both the uops from a micro-coded instruction, and the uops that might be generated from a micro-coded assist.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json index 0d32fd26ded1..36eaec87eead 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json @@ -1,221 +1,221 @@ [ { + "BriefDescription": "Page walk completed due to a demand load to a 1GB page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a 4K page" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 1GB pages. The page walks can end with or without a page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a 1GB page" + "UMask": "0x8" }, { + "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Page walk completed due to a demand load to a 4K page", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Page walks outstanding due to a demand load every cycle.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand data loads or SW prefetches). Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to a demand load every cycle." + "UMask": "0x10" }, { + "BriefDescription": "Page walk completed due to a demand data store to a 1GB page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data store to a 4K page" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data store to a 1GB page" + "UMask": "0x8" }, { + "BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Page walk completed due to a demand data store to a 4K page", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Page walks outstanding due to a demand data store every cycle.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk occurring due to a demand data store. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to a demand data store every cycle." + "UMask": "0x10" }, { + "BriefDescription": "Page walks outstanding due to walking the EPT every cycle", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks.", - "EventCode": "0x4F", "Counter": "0,1,2,3", - "UMask": "0x10", - "PEBScounters": "0,1,2,3", + "EventCode": "0x4F", "EventName": "EPT.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk only while traversing the Extended Page Table (EPT), and does not count during the rest of the translation. The EPT is used for translating Guest-Physical Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Average cycles per walk can be calculated by dividing the count by number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to walking the EPT every cycle" + "UMask": "0x10" }, { + "BriefDescription": "ITLB misses", "CollectPEBSRecord": "1", - "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.", - "EventCode": "0x81", "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", + "EventCode": "0x81", "EventName": "ITLB.MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.", "SampleAfterValue": "200003", - "BriefDescription": "ITLB misses" + "UMask": "0x4" }, { + "BriefDescription": "Page walk completed due to an instruction fetch in a 1GB page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page" - }, - { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", "EventName": "ITLB_MISSES.WALK_COMPLETED_1GB", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 1GB pages. The page walks can end with or without a page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fetch in a 1GB page" + "UMask": "0x8" }, { + "BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page", "CollectPEBSRecord": "1", - "PublicDescription": "Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Page walks outstanding due to an instruction fetch every cycle.", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts once per cycle for each page walk occurring due to an instruction fetch. Includes cycles spent traversing the Extended Page Table (EPT). Average cycles per walk can be calculated by dividing by the number of walks.", "SampleAfterValue": "200003", - "BriefDescription": "Page walks outstanding due to an instruction fetch every cycle." + "UMask": "0x10" }, { - "CollectPEBSRecord": "1", - "PublicDescription": "Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3.", - "EventCode": "0xBD", + "BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x20", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", + "PEBS": "2", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.", + "SampleAfterValue": "200003", + "UMask": "0x13" + }, + { + "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts load uops retired that caused a DTLB miss.", + "SampleAfterValue": "200003", + "UMask": "0x11" + }, + { + "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", + "PEBS": "2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts store uops retired that caused a DTLB miss.", + "SampleAfterValue": "200003", + "UMask": "0x12" + }, + { + "BriefDescription": "STLB flushes", + "CollectPEBSRecord": "1", + "Counter": "0,1,2,3", + "EventCode": "0xBD", "EventName": "TLB_FLUSHES.STLB_ANY", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts STLB flushes. The TLBs are flushed on instructions like INVLPG and MOV to CR3.", "SampleAfterValue": "20003", - "BriefDescription": "STLB flushes" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts load uops retired that caused a DTLB miss.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x11", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts store uops retired that caused a DTLB miss.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x12", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", - "SampleAfterValue": "200003", - "BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)", - "Data_LA": "1" - }, - { - "PEBS": "2", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts uops retired that had a DTLB miss on load, store or either. Note that when two distinct memory operations to the same page miss the DTLB, only one of them will be recorded as a DTLB miss.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x13", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)", - "Data_LA": "1" + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf/pmu-events/arch/x86/haswell/cache.json index 7fb0ad8d8ca1..91464cfb9615 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json @@ -1,1063 +1,1061 @@ [ { - "PublicDescription": "Demand data read requests that missed L2, no rejects.", - "EventCode": "0x24", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "UMask": "0x21", - "Errata": "HSD78", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read miss L2, no rejects", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x22", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of instruction fetches that missed the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Demand requests that miss L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x27", - "Errata": "HSD78", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Demand requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.L2_PF_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 prefetch requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "All requests that missed L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "Errata": "HSD78", - "EventName": "L2_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "All requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "Errata": "HSD78", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of instruction fetches that hit the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "L2_RQSTS.L2_PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 prefetch requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xe1", - "Errata": "HSD78", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 store RFO requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xe2", - "EventName": "L2_RQSTS.ALL_RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 code requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xe4", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Demand requests to L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xe7", - "Errata": "HSD78", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", - "SampleAfterValue": "200003", - "BriefDescription": "Demand requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 HW prefetcher requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xf8", - "EventName": "L2_RQSTS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "All requests to L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xff", - "Errata": "HSD78", - "EventName": "L2_RQSTS.REFERENCES", - "SampleAfterValue": "200003", - "BriefDescription": "All L2 requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Not rejected writebacks that hit L2 cache.", - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x50", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests missed L3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests that refer to L3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "2" - }, - { "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x48", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L1D_PEND_MISS.FB_FULL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "UMask": "0x2" + }, + { + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", - "EventCode": "0x51", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78, HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78, HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x60", + "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78, HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "Not rejected writebacks that hit L2 cache", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "Not rejected writebacks that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x50" }, { - "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "EventCode": "0x60", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "L2 cache lines in E state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "L2 cache lines in I state filling L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "L2 cache lines in I state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0x60", + "BriefDescription": "L2 cache lines in S state filling L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "HSD62, HSD61", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "L2 cache lines in S state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles in which the L1D is locked.", - "EventCode": "0x63", + "BriefDescription": "Clean L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x5" + }, + { + "BriefDescription": "Dirty L2 cache lines evicted by demand", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x6" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts all L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", + "SampleAfterValue": "200003", + "UMask": "0xe1" + }, + { + "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PublicDescription": "Demand requests that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x27" + }, + { + "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "PublicDescription": "Demand requests to L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xe7" + }, + { + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "SampleAfterValue": "200003", + "UMask": "0xf8" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts all L2 store RFO requests.", + "SampleAfterValue": "200003", + "UMask": "0xe2" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Number of instruction fetches that hit the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Number of instruction fetches that missed the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x24" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "Demand data read requests that missed L2, no rejects.", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", + "SampleAfterValue": "200003", + "UMask": "0xd0" + }, + { + "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", + "SampleAfterValue": "200003", + "UMask": "0x30" + }, + { + "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "PublicDescription": "All requests that missed L2.", + "SampleAfterValue": "200003", + "UMask": "0x3f" + }, + { + "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PublicDescription": "All requests to L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc2" + }, + { + "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x22" + }, + { + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "Transactions accessing L2 pipe.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "RFO requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when L1D is locked", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D is locked.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Demand data read requests sent to uncore.", - "EventCode": "0xB0", + "BriefDescription": "Core-originated cacheable demand requests missed L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "PublicDescription": "Demand code read requests sent to uncore.", - "EventCode": "0xB0", + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4f" }, { - "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", - "EventCode": "0xB0", + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x2" }, { - "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", - "EventCode": "0xB0", + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", + "PublicDescription": "Retired load uops missed L1 cache as data sources.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD76, HSD29, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", + "SampleAfterValue": "50021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "Retired load uops with L3 cache hits as data sources.", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "PEBS": "1", + "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "All retired load uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x81" + }, + { + "BriefDescription": "All retired store uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x82" + }, + { + "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD76, HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { "BriefDescription": "Demand and prefetch data reads", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", + "SampleAfterValue": "100003", + "UMask": "0x8" }, { - "EventCode": "0xb2", + "BriefDescription": "Cacheable and noncachaeble code read requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Demand code read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "SampleAfterValue": "2000003", - "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x11", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (precise Event)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x12", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (precise Event)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "L1_Hit_Indication": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x21", - "Errata": "HSD76, HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with locked access. (precise Event)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.", - "EventCode": "0xD0", + "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x41", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C07F7", + "Offcore": "1", + "PublicDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheline boundary. (precise Event)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.", - "EventCode": "0xD0", + "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x42", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C07F7", + "Offcore": "1", + "PublicDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (precise Event)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "L1_Hit_Indication": "1" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Counts all requests hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x81", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (precise Event)", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts all store uops retired. This is a precise event.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x82", - "Errata": "HSD29, HSM30", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops. (precise Event)", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "L1_Hit_Indication": "1" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD29, HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data sources.", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD76, HSD29, HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C8FFF", + "Offcore": "1", + "PublicDescription": "Counts all requests hit in the L3", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.", - "EventCode": "0xD1", + "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.", - "EventCode": "0xD1", + "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops misses in L1 cache as data sources.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x10", - "Errata": "HSD29, HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops with L2 cache misses as data sources.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x20", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD1", + "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x40", - "Errata": "HSM30", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.", - "EventCode": "0xD2", + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.", - "EventCode": "0xD2", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x4", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0040", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD2", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x8", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0010", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.", - "EventCode": "0xD3", + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD74, HSD29, HSD25, HSM30", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3", - "Data_LA": "1" - }, - { - "PublicDescription": "Demand data read requests that access L2 cache.", - "EventCode": "0xf0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RFO requests that access L2 cache.", - "EventCode": "0xf0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 cache accesses when fetching instructions.", - "EventCode": "0xf0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", - "EventCode": "0xf0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L1D writebacks that access L2 cache.", - "EventCode": "0xf0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 fill requests that access L2 cache.", - "EventCode": "0xf0", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 writebacks that access L2 cache.", - "EventCode": "0xf0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Transactions accessing L2 pipe.", - "EventCode": "0xf0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 cache lines in I state filling L2.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0020", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "L2 cache lines in S state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "L2 cache lines in E state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", - "EventCode": "0xF1", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Clean L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "Split locks in SQ", "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Dirty L2 cache lines evicted by demand.", - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xf4", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all requests hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C8FFF", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all requests hit in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C07F7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C07F7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0244", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3F803C0010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003C0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x04003C0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json index f5a3beaa19fc..55cf5b96464e 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json @@ -1,92 +1,103 @@ [ { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC1", + "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.", "Counter": "0,1,2,3", - "UMask": "0x8", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC6", + "EventName": "AVX_INSTS.ALL", + "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.", + "SampleAfterValue": "2000003", + "UMask": "0x7" + }, + { + "BriefDescription": "Cycles with any input/output SSE or FP assist", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", + "SampleAfterValue": "100003", + "UMask": "0x1e" + }, + { + "BriefDescription": "Number of SIMD FP assists due to input values", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "Number of SIMD FP assists due to input values.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SIMD FP assists due to Output values", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output values.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "Number of X87 FP assists due to input values.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output values.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "HSD56, HSM57", + "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC1", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "HSD56, HSM57", + "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from legacy SSE to AVX-256 when penalty applicable", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.", - "EventCode": "0xC6", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "AVX_INSTS.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "output - Numeric Overflow, Numeric Underflow, Inexact Result", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.X87_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "input - Invalid Operation, Denormal Operand, SNaN Operand", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "SSE* FP micro-code assist when output value is invalid.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Any input SSE* FP Assist", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts any FP_ASSIST umask was incrementing", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/frontend.json b/tools/perf/pmu-events/arch/x86/haswell/frontend.json index c0a5bedcc15c..0c8d5ccf1276 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/haswell/frontend.json @@ -1,294 +1,304 @@ [ { - "PublicDescription": "Counts cycles the IDQ is empty.", - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD135", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of front end re-steers due to BPU misprediction.", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of uops delivered to IDQ from any path.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x3c", - "EventName": "IDQ.MITE_ALL_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.", - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFETCH_STALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFDATA_STALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.", - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis.", - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" + }, + { + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFDATA_STALL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFETCH_STALL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD135", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "Counts cycles the IDQ is empty.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "Number of uops delivered to IDQ from any path.", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json index f57c5f3506c2..3ade2c19533e 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json @@ -1,172 +1,125 @@ [ { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" - }, - { - "BriefDescription": "Instructions per Store (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -176,83 +129,127 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Memory_Bound;Memory_BW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, - { - "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI_All" - }, - { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2HPKI_All" - }, { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Average Frequency Utilization relative nominal frequency", "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", @@ -261,22 +258,46 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, + { + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/haswell/memory.json b/tools/perf/pmu-events/arch/x86/haswell/memory.json index ef13ed88e2ea..8b69493e3726 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/memory.json @@ -1,676 +1,684 @@ [ { - "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_MEM.ABORT_CONFLICT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "TX_EXEC.MISC2", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "TX_EXEC.MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "TX_EXEC.MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "HLE_RETIRED.START", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution started.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "HLE_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution successfully committed.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "HLE_RETIRED.ABORTED", - "SampleAfterValue": "2000003", "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xc8", + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", - "UMask": "0x8", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xc8", + "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xc8", + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xc8", + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.", "Counter": "0,1,2,3", - "UMask": "0x40", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "HSD65", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).", - "EventCode": "0xc8", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "HLE_RETIRED.ABORTED_MISC5", - "SampleAfterValue": "2000003", "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC9", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RTM_RETIRED.START", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution started.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xc9", + "BriefDescription": "Number of times an HLE execution successfully committed.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RTM_RETIRED.COMMIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution successfully committed.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xc9", + "BriefDescription": "Number of times an HLE execution started.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RTM_RETIRED.ABORTED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.START", "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", - "EventCode": "0xc9", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RTM_RETIRED.ABORTED_MISC1", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RTM_RETIRED.ABORTED_MISC2", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "RTM_RETIRED.ABORTED_MISC3", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x40", - "Errata": "HSD65", - "EventName": "RTM_RETIRED.ABORTED_MISC4", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", - "EventCode": "0xc9", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "RTM_RETIRED.ABORTED_MISC5", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", "SampleAfterValue": "100003", - "BriefDescription": "Randomly selected loads with latency value being above 4.", - "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Randomly selected loads with latency value being above 128.", "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Randomly selected loads with latency value being above 8.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Randomly selected loads with latency value being above 16.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100003", - "BriefDescription": "Randomly selected loads with latency value being above 32.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x1", - "Errata": "HSD76, HSD25, HSM26", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Randomly selected loads with latency value being above 64.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", "SampleAfterValue": "1009", - "BriefDescription": "Randomly selected loads with latency value being above 128.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Randomly selected loads with latency value being above 16.", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 256.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "SampleAfterValue": "503", - "BriefDescription": "Randomly selected loads with latency value being above 256.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Randomly selected loads with latency value being above 32.", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 4.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 512.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "SampleAfterValue": "101", - "BriefDescription": "Randomly selected loads with latency value being above 512.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PublicDescription": "Counts all requests miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC08FFF", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all requests miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "BriefDescription": "Randomly selected loads with latency value being above 64.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PublicDescription": "miss the L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x01004007F7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "miss the L3 and the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "BriefDescription": "Randomly selected loads with latency value being above 8.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" }, { - "PublicDescription": "miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC007F7", + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400244", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00244", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00244", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400122", + "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400244", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00200", + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400091", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00100", + "BriefDescription": "miss in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC007F7", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00080", + "BriefDescription": "miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01004007F7", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00040", + "BriefDescription": "Counts all requests miss in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC08FFF", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all requests miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00020", + "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00010", + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400122", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts all demand code reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", "BriefDescription": "Counts all demand code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00004", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400002", + "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400004", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x0100400001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", - "Offcore": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts demand data reads miss in the L3", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC00001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6, 0x1a7", - "SampleAfterValue": "100003", "BriefDescription": "Counts demand data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00001", "Offcore": "1", - "CounterHTOff": "0,1,2,3" + "PublicDescription": "Counts demand data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00040", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00010", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00020", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC1", + "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC2", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC3", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD65", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC5", + "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of times an RTM execution successfully committed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.START", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/other.json b/tools/perf/pmu-events/arch/x86/haswell/other.json index 8a4d898d76c1..4c6b9d34325a 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/other.json +++ b/tools/perf/pmu-events/arch/x86/haswell/other.json @@ -1,43 +1,43 @@ [ { - "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", - "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPL_CYCLES.RING0", - "SampleAfterValue": "2000003", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100003", - "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", - "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPL_CYCLES.RING123", - "SampleAfterValue": "2000003", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", - "EventCode": "0x63", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json index 734d3873729e..a53f28ec9270 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json @@ -1,1343 +1,1305 @@ [ { - "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "Errata": "HSD140, HSD143", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.", - "EventCode": "0x03", + "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.", - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial compare on address.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.", - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "ARITH.DIVIDER_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", - "EventCode": "0x3C", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3c", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", - "EventCode": "0x4c", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", - "EventCode": "0x4c", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.", - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.", - "EventCode": "0x5E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", - "SampleAfterValue": "200003", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).", - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Stall cycles due to IQ is full.", - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x88", + "BriefDescription": "Speculative and retired macro-conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc1", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc1" }, { - "EventCode": "0x88", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", "Counter": "0,1,2,3", - "UMask": "0xc2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc2" }, { - "EventCode": "0x88", + "BriefDescription": "Speculative and retired direct near calls.", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xd0", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xd0" }, { - "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x89", + "BriefDescription": "Speculative and retired indirect return branches.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc8" }, { - "EventCode": "0x89", + "BriefDescription": "Not taken macro-conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired macro-conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x82" }, { - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired direct near calls.", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x90" }, { - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0xc1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired indirect calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0x88" + }, + { + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Branch instructions at retirement.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "Counts the number of conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "Number of far branches retired.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Direct and indirect near call instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "Counts the number of near return instructions retired.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near taken branches retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0xc4", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "PublicDescription": "Counts all near executed branches (not necessarily retired).", - "EventCode": "0x89", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles per core when uops are exectuted in port 0.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles per core when uops are exectuted in port 1.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles per core when uops are exectuted in port 4.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles per core when uops are exectuted in port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 6", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles per core when uops are exectuted in port 6.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are executed in port 6.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 6.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 7", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 7.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are executed in port 7.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles allocation is stalled due to resource related reason.", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD135", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD78", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L2 cache miss loads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with pending memory loads. Set Cmask=2 to count cycle.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending memory loads.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "SampleAfterValue": "2000003", - "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of loads missed L2.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L2 cache misses.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to memory subsystem.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L1 cache miss loads.", - "CounterMask": "8", - "CounterHTOff": "2" - }, - { - "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L1 data cache misses", - "CounterMask": "12", - "CounterHTOff": "2" - }, - { - "PublicDescription": "Number of uops delivered by the LSD.", - "EventCode": "0xa8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 1 uop was executed per-thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 2 uops were executed per-thread", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 3 uops were executed per-thread", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Errata": "HSD144, HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of uops executed on the core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "Errata": "HSD30, HSM31", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of instructions at retirement.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "Errata": "HSD11, HSD140", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "Errata": "HSD140", - "EventName": "INST_RETIRED.PREC_DIST", - "SampleAfterValue": "2000003", - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "CounterHTOff": "1" - }, - { - "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", - "SampleAfterValue": "2000003", - "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Actually retired uops.", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Data_LA": "1" + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles no executable uops retired", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles using always true condition applied to PEBS uops retired event.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC2", - "Invert": "1", + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles no executable uops retired on core", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Branch instructions at retirement.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100003", - "BriefDescription": "Direct and indirect near call instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100003", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100003", - "BriefDescription": "Return instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Counts all not taken macro branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Mispredicted branch instructions at retirement.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", "BriefDescription": "All mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC5", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Mispredicted branch instructions at retirement.", + "SampleAfterValue": "400009" }, { + "BriefDescription": "Mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", "PublicDescription": "This event counts all mispredicted branch instructions retired. This is a precise event.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near branch instructions retired that were taken but mispredicted.", + "SampleAfterValue": "400009", + "UMask": "0x20" }, { - "PublicDescription": "Count cases of saving new LBR records by hardware.", - "EventCode": "0xCC", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of front end re-steers due to BPU misprediction.", - "EventCode": "0xe6", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD78, HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with pending memory loads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Cycles with pending memory loads. Set Cmask=2 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls due to L2 cache misses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "Errata": "HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Number of loads missed L2.", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls due to memory subsystem.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Stall cycles because IQ is full", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "Errata": "HSD140, HSD143", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD11, HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of uops delivered by the LSD.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD135", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Cycles allocation is stalled due to resource related reason.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Count cases of saving new LBR records by hardware.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 6.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json new file mode 100644 index 000000000000..6b0639944d78 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json @@ -0,0 +1,252 @@ +[ + { + "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", + "UMask": "0x86", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", + "UMask": "0x8f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", + "UMask": "0x46", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", + "UMask": "0x4f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", + "UMask": "0x16", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", + "UMask": "0x18", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.", + "UMask": "0x11", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", + "UMask": "0x1f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.", + "UMask": "0x26", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.", + "UMask": "0x2f", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a modified line in some processor core.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", + "UMask": "0x84", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a non-modified line in some processor core.", + "UMask": "0x24", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop misses in some processor core.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", + "UMask": "0x41", + "Unit": "CBO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json new file mode 100644 index 000000000000..8f2ae2891042 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json @@ -0,0 +1,69 @@ +[ + { + "BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)", + "EventCode": "0x83", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All", + "PerPkg": "1", + "PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "Counter": "0,", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "Unit": "NCU" + } +] diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore.json b/tools/perf/pmu-events/arch/x86/haswell/uncore.json deleted file mode 100644 index 3ef5c21fef56..000000000000 --- a/tools/perf/pmu-events/arch/x86/haswell/uncore.json +++ /dev/null @@ -1,374 +0,0 @@ -[ - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x21", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", - "BriefDescription": "An external snoop misses in some processor core.", - "PublicDescription": "An external snoop misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x41", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x81", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", - "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x24", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", - "BriefDescription": "An external snoop hits a non-modified line in some processor core.", - "PublicDescription": "An external snoop hits a non-modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x44", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x84", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", - "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x28", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", - "BriefDescription": "An external snoop hits a modified line in some processor core.", - "PublicDescription": "An external snoop hits a modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x48", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", - "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", - "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x88", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", - "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", - "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x11", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", - "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.", - "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x21", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", - "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.", - "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x41", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", - "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", - "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x81", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", - "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", - "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x18", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", - "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", - "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x28", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", - "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.", - "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x48", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", - "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", - "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x88", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", - "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", - "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x1f", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", - "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", - "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x2f", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", - "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.", - "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x4f", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", - "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", - "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x8f", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", - "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", - "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x86", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", - "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", - "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x46", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", - "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", - "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x16", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", - "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", - "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x26", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", - "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.", - "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", - "PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "BriefDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", - "PublicDescription": "Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x81", - "UMask": "0x20", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "BriefDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", - "PublicDescription": "Number of Writes allocated - any write transactions: full/partials writes and evictions.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x83", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All", - "BriefDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory)", - "PublicDescription": "Each cycle count number of valid entries in Coherency Tracker queue from allocation till deallocation. Aperture requests (snoops) appear as NC decoded internally and become coherent (snoop L3, access memory).", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "iMPH-U", - "EventCode": "0x84", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "BriefDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", - "PublicDescription": "Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "NCU", - "EventCode": "0x0", - "UMask": "0x01", - "EventName": "UNC_CLOCK.SOCKET", - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", - "Counter": "FIXED", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json index 777b500a5c9f..ba3e77a9f9a0 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json @@ -1,484 +1,484 @@ [ { - "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", "BriefDescription": "Load misses in all DTLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", - "EventCode": "0x08", + "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", + "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Number of cache load STLB hits. No page walk.", "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", - "EventCode": "0x08", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x08", + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", "Counter": "0,1,2,3", - "UMask": "0x8", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "2000003", - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", - "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of cache load STLB hits. No page walk.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", "BriefDescription": "Store misses in all DTLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", - "EventCode": "0x49", + "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", + "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x49", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x8", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", - "EventCode": "0x49", + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", - "EventCode": "0x49", + "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x4f", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", - "EventCode": "0x85", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xae", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Misses at all ITLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", - "EventCode": "0x85", + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "ITLB misses that hit STLB. No page walk.", "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x85", + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", "Counter": "0,1,2,3", - "UMask": "0x8", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "PublicDescription": "ITLB misses that hit STLB (2M).", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "PublicDescription": "ITLB misses that hit STLB (4K).", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks in ITLB of any page size.", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Completed page walks in ITLB of any page size.", - "EventCode": "0x85", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "ITLB_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", - "EventCode": "0x85", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "ITLB_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "ITLB misses that hit STLB (4K).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISSES.STLB_HIT_4K", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", "SampleAfterValue": "100003", - "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "ITLB misses that hit STLB (2M).", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "ITLB_MISSES.STLB_HIT_2M", - "SampleAfterValue": "100003", - "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "ITLB misses that hit STLB. No page walk.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "ITLB_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", - "EventCode": "0xae", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100003", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "PAGE_WALKER_LOADS.DTLB_L1", - "SampleAfterValue": "2000003", "BriefDescription": "Number of DTLB page walker hits in the L1+FB", - "CounterHTOff": "0,1,2,3" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L1", + "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", + "SampleAfterValue": "2000003", + "UMask": "0x11" }, { - "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "PAGE_WALKER_LOADS.DTLB_L2", - "SampleAfterValue": "2000003", "BriefDescription": "Number of DTLB page walker hits in the L2", - "CounterHTOff": "0,1,2,3" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L2", + "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", + "SampleAfterValue": "2000003", + "UMask": "0x12" }, { - "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x14", - "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.DTLB_L3", - "SampleAfterValue": "2000003", "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", - "CounterHTOff": "0,1,2,3" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", + "SampleAfterValue": "2000003", + "UMask": "0x14" }, { - "PublicDescription": "Number of DTLB page walker loads from memory.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x18", - "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", - "SampleAfterValue": "2000003", "BriefDescription": "Number of DTLB page walker hits in Memory", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", - "EventCode": "0xBC", "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "PAGE_WALKER_LOADS.ITLB_L1", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L1+FB", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x22", - "EventName": "PAGE_WALKER_LOADS.ITLB_L2", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L2", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x24", + "CounterHTOff": "0,1,2,3", "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "PublicDescription": "Number of DTLB page walker loads from memory.", "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { - "PublicDescription": "Number of ITLB page walker loads from memory.", - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", "Counter": "0,1,2,3", - "UMask": "0x28", - "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in Memory", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x41", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", "Counter": "0,1,2,3", - "UMask": "0x42", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x42" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", "Counter": "0,1,2,3", - "UMask": "0x44", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x44" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", "Counter": "0,1,2,3", - "UMask": "0x48", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x48" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", "Counter": "0,1,2,3", - "UMask": "0x81", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x81" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", "Counter": "0,1,2,3", - "UMask": "0x82", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x82" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", "Counter": "0,1,2,3", - "UMask": "0x84", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x84" }, { - "EventCode": "0xBC", + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", "Counter": "0,1,2,3", - "UMask": "0x88", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x88" }, { - "PublicDescription": "DTLB flush attempts of the thread-specific entries.", - "EventCode": "0xBD", + "BriefDescription": "Number of ITLB page walker hits in the L1+FB", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TLB_FLUSH.DTLB_THREAD", - "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L1", + "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", + "SampleAfterValue": "2000003", + "UMask": "0x21" + }, + { + "BriefDescription": "Number of ITLB page walker hits in the L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L2", + "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", + "SampleAfterValue": "2000003", + "UMask": "0x22" + }, + { + "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Number of ITLB page walker hits in Memory", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", + "PublicDescription": "Number of ITLB page walker loads from memory.", + "SampleAfterValue": "2000003", + "UMask": "0x28" + }, + { "BriefDescription": "DTLB flush attempts of the thread-specific entries", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "DTLB flush attempts of the thread-specific entries.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Count number of STLB flush attempts.", - "EventCode": "0xBD", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TLB_FLUSH.STLB_ANY", - "SampleAfterValue": "100003", "BriefDescription": "STLB flush attempts", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "Count number of STLB flush attempts.", + "SampleAfterValue": "100003", + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/cache.json b/tools/perf/pmu-events/arch/x86/haswellx/cache.json index a9e62d4357af..85eb998dd39e 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/cache.json @@ -1,1097 +1,1097 @@ [ { - "EventCode": "0x24", - "UMask": "0x21", - "BriefDescription": "Demand Data Read miss L2, no rejects", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "Errata": "HSD78", - "PublicDescription": "Demand data read requests that missed L2, no rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x22", - "BriefDescription": "RFO requests that miss L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_MISS", - "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x24", - "BriefDescription": "L2 cache misses when fetching instructions", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "PublicDescription": "Number of instruction fetches that missed the L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x27", - "BriefDescription": "Demand requests that miss L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "Errata": "HSD78", - "PublicDescription": "Demand requests that miss L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x30", - "BriefDescription": "L2 prefetch requests that miss L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_MISS", - "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0x3f", - "BriefDescription": "All requests that miss L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.MISS", - "Errata": "HSD78", - "PublicDescription": "All requests that missed L2.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xc1", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "Errata": "HSD78", - "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xc2", - "BriefDescription": "RFO requests that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.RFO_HIT", - "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xc4", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "PublicDescription": "Number of instruction fetches that hit the L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xd0", - "BriefDescription": "L2 prefetch requests that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.L2_PF_HIT", - "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe1", - "BriefDescription": "Demand Data Read requests", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "Errata": "HSD78", - "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe2", - "BriefDescription": "RFO requests to L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_RFO", - "PublicDescription": "Counts all L2 store RFO requests.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe4", - "BriefDescription": "L2 code requests", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PublicDescription": "Counts all L2 code requests.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xe7", - "BriefDescription": "Demand requests to L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", - "Errata": "HSD78", - "PublicDescription": "Demand requests to L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xf8", - "BriefDescription": "Requests from L2 hardware prefetchers", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.ALL_PF", - "PublicDescription": "Counts all L2 HW prefetcher requests.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "UMask": "0xff", - "BriefDescription": "All L2 requests", - "Counter": "0,1,2,3", - "EventName": "L2_RQSTS.REFERENCES", - "Errata": "HSD78", - "PublicDescription": "All requests to L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "UMask": "0x50", - "BriefDescription": "Not rejected writebacks that hit L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_DEMAND_RQSTS.WB_HIT", - "PublicDescription": "Not rejected writebacks that hit L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "UMask": "0x41", - "BriefDescription": "Core-originated cacheable demand requests missed L3", - "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "UMask": "0x4f", - "BriefDescription": "Core-originated cacheable demand requests that refer to L3", - "Counter": "0,1,2,3", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "L1D miss oustandings duration in cycles", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING", - "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x1", - "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "Counter": "2", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "UMask": "0x2", - "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", - "Counter": "0,1,2,3", - "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x48", - "UMask": "0x2", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", - "Counter": "0,1,2,3", - "EventName": "L1D_PEND_MISS.FB_FULL", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x51", - "UMask": "0x1", "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "Errata": "HSD78, HSD62, HSD61", - "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "Errata": "HSD78, HSD62, HSD61", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x60", - "UMask": "0x1", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "CounterMask": "6", - "Errata": "HSD78, HSD62, HSD61", + "BriefDescription": "L1D miss oustandings duration in cycles", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x2", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "Errata": "HSD62, HSD61", - "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "Errata": "HSD62, HSD61", - "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "Errata": "HSD62, HSD61", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "Errata": "HSD62, HSD61", - "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "Errata": "HSD62, HSD61", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x63", - "UMask": "0x2", - "BriefDescription": "Cycles when L1D is locked", + "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", "Counter": "0,1,2,3", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "PublicDescription": "Cycles in which the L1D is locked.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xB0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests sent to uncore", + "BriefDescription": "Not rejected writebacks that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "Errata": "HSD78", - "PublicDescription": "Demand data read requests sent to uncore.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x2", - "BriefDescription": "Cacheable and noncachaeble code read requests", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "Demand code read requests sent to uncore.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x4", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "UMask": "0x8", - "BriefDescription": "Demand and prefetch data reads", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb2", - "UMask": "0x1", - "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x11", - "BriefDescription": "Retired load uops that miss the STLB.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "Errata": "HSD29, HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x12", - "BriefDescription": "Retired store uops that miss the STLB.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "Errata": "HSD29, HSM30", - "L1_Hit_Indication": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x21", - "BriefDescription": "Retired load uops with locked access.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "Errata": "HSD76, HSD29, HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x41", - "BriefDescription": "Retired load uops that split across a cacheline boundary.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "Errata": "HSD29, HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x42", - "BriefDescription": "Retired store uops that split across a cacheline boundary.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "Errata": "HSD29, HSM30", - "L1_Hit_Indication": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x81", - "BriefDescription": "All retired load uops.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "Errata": "HSD29, HSM30", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD0", - "UMask": "0x82", - "BriefDescription": "All retired store uops.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "Errata": "HSD29, HSM30", - "L1_Hit_Indication": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x1", - "BriefDescription": "Retired load uops with L1 cache hits as data sources.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "Errata": "HSD29, HSM30", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x2", - "BriefDescription": "Retired load uops with L2 cache hits as data sources.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "Errata": "HSD76, HSD29, HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "PublicDescription": "Retired load uops with L3 cache hits as data sources.", - "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x8", - "BriefDescription": "Retired load uops misses in L1 cache as data sources.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "Errata": "HSM30", - "PublicDescription": "Retired load uops missed L1 cache as data sources.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x10", - "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "Errata": "HSD29, HSM30", - "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", - "SampleAfterValue": "50021", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x20", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "UMask": "0x40", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "Errata": "HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x1", - "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x2", - "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x4", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", - "Errata": "HSD29, HSD25, HSM26, HSM30", - "SampleAfterValue": "20011", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "UMask": "0x8", - "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", - "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x1", - "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "Errata": "HSD74, HSD29, HSD25, HSM30", - "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x4", - "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", - "Errata": "HSD29, HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x10", - "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", - "Errata": "HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "UMask": "0x20", - "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", - "Errata": "HSM30", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xf0", - "UMask": "0x1", - "BriefDescription": "Demand Data Read requests that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "PublicDescription": "Demand data read requests that access L2 cache.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_DEMAND_RQSTS.WB_HIT", + "PublicDescription": "Not rejected writebacks that hit L2 cache.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x50" }, { - "EventCode": "0xf0", - "UMask": "0x2", - "BriefDescription": "RFO requests that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.RFO", - "PublicDescription": "RFO requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xf0", - "UMask": "0x4", - "BriefDescription": "L2 cache accesses when fetching instructions", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.CODE_RD", - "PublicDescription": "L2 cache accesses when fetching instructions.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xf0", - "UMask": "0x8", - "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_PF", - "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xf0", - "UMask": "0x10", - "BriefDescription": "L1D writebacks that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L1D_WB", - "PublicDescription": "L1D writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xf0", - "UMask": "0x20", - "BriefDescription": "L2 fill requests that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_FILL", - "PublicDescription": "L2 fill requests that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xf0", - "UMask": "0x40", - "BriefDescription": "L2 writebacks that access L2 cache", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.L2_WB", - "PublicDescription": "L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xf0", - "UMask": "0x80", - "BriefDescription": "Transactions accessing L2 pipe", - "Counter": "0,1,2,3", - "EventName": "L2_TRANS.ALL_REQUESTS", - "PublicDescription": "Transactions accessing L2 pipe.", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x1", - "BriefDescription": "L2 cache lines in I state filling L2", - "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.I", - "PublicDescription": "L2 cache lines in I state filling L2.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x2", - "BriefDescription": "L2 cache lines in S state filling L2", - "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.S", - "PublicDescription": "L2 cache lines in S state filling L2.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x4", - "BriefDescription": "L2 cache lines in E state filling L2", - "Counter": "0,1,2,3", - "EventName": "L2_LINES_IN.E", - "PublicDescription": "L2 cache lines in E state filling L2.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "UMask": "0x7", "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x7" + }, + { + "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "L2 cache lines in E state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "L2 cache lines in I state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "L2 cache lines in S state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0xF2", - "UMask": "0x5", "BriefDescription": "Clean L2 cache lines evicted by demand", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "PublicDescription": "Clean L2 cache lines evicted by demand.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0xF2", - "UMask": "0x6", "BriefDescription": "Dirty L2 cache lines evicted by demand", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "PublicDescription": "Dirty L2 cache lines evicted by demand.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x6" }, { - "EventCode": "0xf4", - "UMask": "0x10", - "BriefDescription": "Split locks in SQ", + "BriefDescription": "L2 code requests", "Counter": "0,1,2,3", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts all L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0001", + "BriefDescription": "Demand Data Read requests", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", + "SampleAfterValue": "200003", + "UMask": "0xe1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0001", + "BriefDescription": "Demand requests that miss L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PublicDescription": "Demand requests that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x27" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0002", + "BriefDescription": "Demand requests to L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "PublicDescription": "Demand requests to L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xe7" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0002", + "BriefDescription": "Requests from L2 hardware prefetchers", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "SampleAfterValue": "200003", + "UMask": "0xf8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0004", + "BriefDescription": "RFO requests to L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts all L2 store RFO requests.", + "SampleAfterValue": "200003", + "UMask": "0xe2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0004", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Number of instruction fetches that hit the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", - "MSRValue": "0x3F803C0010", + "BriefDescription": "L2 cache misses when fetching instructions", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Number of instruction fetches that missed the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x24" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", - "MSRValue": "0x3F803C0020", + "BriefDescription": "Demand Data Read requests that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", - "MSRValue": "0x3F803C0040", + "BriefDescription": "Demand Data Read miss L2, no rejects", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "Demand data read requests that missed L2, no rejects.", + "SampleAfterValue": "200003", + "UMask": "0x21" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", - "MSRValue": "0x3F803C0080", + "BriefDescription": "L2 prefetch requests that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_HIT", + "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", - "MSRValue": "0x3F803C0100", + "BriefDescription": "L2 prefetch requests that miss L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.L2_PF_MISS", + "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", + "SampleAfterValue": "200003", + "UMask": "0x30" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", - "MSRValue": "0x3F803C0200", + "BriefDescription": "All requests that miss L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "PublicDescription": "All requests that missed L2.", + "SampleAfterValue": "200003", + "UMask": "0x3f" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0091", + "BriefDescription": "All L2 requests", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PublicDescription": "All requests to L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0091", + "BriefDescription": "RFO requests that hit L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0122", + "BriefDescription": "RFO requests that miss L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x22" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C0122", + "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "Offcore": "1", + "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "Transactions accessing L2 pipe.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "RFO requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D is locked.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", + "SampleAfterValue": "100003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops misses in L1 cache as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", + "PublicDescription": "Retired load uops missed L1 cache as data sources.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD76, HSD29, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.", + "SampleAfterValue": "50021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load uops which data sources were data hits in L3 without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "Retired load uops with L3 cache hits as data sources.", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", + "PEBS": "1", + "PublicDescription": "Retired load uops missed L3. Excludes unknown data source .", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "All retired load uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x81" + }, + { + "BriefDescription": "All retired store uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x82" + }, + { + "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD76, HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Retired store uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "Errata": "HSD29, HSM30", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cacheable and noncachaeble code read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Demand code read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSM80", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD62, HSD61, HSM63", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "UMask": "0x1", + "EventName": "OFFCORE_RESPONSE", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { "BriefDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C0244", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0244", + "Offcore": "1", "PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "MSRValue": "0x04003C07F7", + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "MSRValue": "0x10003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "MSRValue": "0x10003C07F7", + "BriefDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C07F7", + "Offcore": "1", "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests hit in the L3", - "MSRValue": "0x3F803C8FFF", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C07F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all requests hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C8FFF", + "Offcore": "1", "PublicDescription": "Counts all requests hit in the L3", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x04003C0002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0040", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0010", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0020", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xf4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json index bc08cc1f2f7e..55cf5b96464e 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json @@ -1,83 +1,103 @@ [ { - "EventCode": "0xC1", - "UMask": "0x8", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", - "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "Errata": "HSD56, HSM57", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "UMask": "0x10", - "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", - "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "Errata": "HSD56, HSM57", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC6", - "UMask": "0x7", "BriefDescription": "Approximate counts of AVX & AVX2 256-bit instructions, including non-arithmetic instructions, loads, and stores. May count non-AVX instructions that employ 256-bit operations, including (but not necessarily limited to) rep string instructions that use 256-bit loads and stores for optimized performance, XSAVE* and XRSTOR*, and operations that transition the x87 FPU data registers between x87 and MMX.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC6", "EventName": "AVX_INSTS.ALL", "PublicDescription": "Note that a whole rep string only counts AVX_INST.ALL once.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x7" }, { - "EventCode": "0xCA", - "UMask": "0x2", - "BriefDescription": "Number of X87 assists due to output value.", + "BriefDescription": "Cycles with any input/output SSE or FP assist", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_OUTPUT", - "PublicDescription": "Number of X87 FP assists due to output values.", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1e" }, { - "EventCode": "0xCA", - "UMask": "0x4", - "BriefDescription": "Number of X87 assists due to input value.", - "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.X87_INPUT", - "PublicDescription": "Number of X87 FP assists due to input values.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "UMask": "0x8", - "BriefDescription": "Number of SIMD FP assists due to Output values", - "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "PublicDescription": "Number of SIMD FP assists due to output values.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "UMask": "0x10", "BriefDescription": "Number of SIMD FP assists due to input values", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "Number of SIMD FP assists due to input values.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xCA", - "UMask": "0x1e", - "BriefDescription": "Cycles with any input/output SSE or FP assist", + "BriefDescription": "Number of SIMD FP assists due to Output values", "Counter": "0,1,2,3", - "EventName": "FP_ASSIST.ANY", - "CounterMask": "1", - "PublicDescription": "Cycles with any input/output SSE* or FP assists.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output values.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "Number of X87 FP assists due to input values.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output values.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD56, HSM57", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD56, HSM57", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json index a4d9f1fcf940..0c8d5ccf1276 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json @@ -1,294 +1,304 @@ [ { - "EventCode": "0x79", - "UMask": "0x2", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "EventName": "IDQ.EMPTY", - "Errata": "HSD135", - "PublicDescription": "Counts cycles the IDQ is empty.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of front end re-steers due to BPU misprediction.", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_UOPS", - "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x79", - "UMask": "0x4", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", - "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_CYCLES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_UOPS", - "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x8", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "Counter": "0,1,2,3", - "EventName": "IDQ.DSB_CYCLES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_UOPS", - "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_CYCLES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x10", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_DSB_OCCUR", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x18", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "CounterMask": "1", - "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x20", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "CounterMask": "4", - "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x24", - "BriefDescription": "Cycles MITE is delivering any Uop", - "Counter": "0,1,2,3", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "CounterMask": "1", - "PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_UOPS", - "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "EventCode": "0x79", - "UMask": "0x30", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "Counter": "0,1,2,3", - "EventName": "IDQ.MS_SWITCHES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "UMask": "0x3c", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "EventName": "IDQ.MITE_ALL_UOPS", - "PublicDescription": "Number of uops delivered to IDQ from any path.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "UMask": "0x1", "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x80", - "UMask": "0x2", + "EventName": "ICACHE.IFDATA_STALL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFETCH_STALL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "This event counts Instruction Cache (ICACHE) misses.", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x80", - "UMask": "0x4", - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", "Counter": "0,1,2,3", - "EventName": "ICACHE.IFETCH_STALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" }, { - "EventCode": "0x80", - "UMask": "0x4", - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.", + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", "Counter": "0,1,2,3", - "EventName": "ICACHE.IFDATA_STALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles MITE is delivered at least one uop. Set Cmask = 1.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "HSD135", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "Counts cycles the IDQ is empty.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "Number of uops delivered to IDQ from any path.", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the Front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "This event counts uops delivered by the Front-end with the assistance of the microcode sequencer. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance.", + "SampleAfterValue": "2000003", + "UMask": "0x30" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "CounterHTOff": "0,1,2,3", "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event count the number of undelivered (unallocated) uops from the Front-end to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. The Front-end can allocate up to 4 uops per cycle so this event can increment 0-4 times per cycle depending on the number of unallocated uops. This event is counted on a per-core basis.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "PublicDescription": "This event counts the number cycles during which the Front-end allocated exactly zero uops to the Resource Allocation Table (RAT) while the Back-end of the processor is not stalled. This event is counted on a per-core basis.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", - "CounterMask": "3", - "Errata": "HSD135", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", - "CounterMask": "2", - "Errata": "HSD135", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", - "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", - "CounterMask": "1", - "Errata": "HSD135", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", - "EventCode": "0x9C", - "UMask": "0x1", "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", "Counter": "0,1,2,3", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xAB", - "UMask": "0x2", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", "Counter": "0,1,2,3", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD135", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json index 311a005dc35b..c99734fd907d 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json @@ -1,172 +1,125 @@ [ { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", - "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" - }, - { - "BriefDescription": "Instructions per Store (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -176,83 +129,127 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Memory_Bound;Memory_BW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, - { - "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI_All" - }, - { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2HPKI_All" - }, { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Average Frequency Utilization relative nominal frequency", "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", @@ -261,40 +258,52 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "1000000000 * ( cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@ ) / ( cbox_0@event\\=0x0@ / duration_time )", - "MetricGroup": "Memory_Lat", - "MetricName": "DRAM_Read_Latency" + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@", - "MetricGroup": "Memory_BW", - "MetricName": "DRAM_Parallel_Reads" + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "MEM_Parallel_Reads" }, { "BriefDescription": "Socket actual clocks when any core is active on that socket", "MetricExpr": "cbox_0@event\\=0x0@", - "MetricGroup": "", + "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/memory.json b/tools/perf/pmu-events/arch/x86/haswellx/memory.json index a42d5ce86b6f..6ffb5067f4eb 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/memory.json @@ -1,767 +1,775 @@ [ { - "EventCode": "0x05", - "UMask": "0x1", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.LOADS", - "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "UMask": "0x2", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "Counter": "0,1,2,3", - "EventName": "MISALIGN_MEM_REF.STORES", - "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x1", - "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CONFLICT", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x2", - "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x4", - "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x8", - "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x10", - "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x20", - "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x54", - "UMask": "0x40", - "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", - "Counter": "0,1,2,3", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x1", - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x2", - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x4", - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x8", - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5d", - "UMask": "0x10", - "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", - "Counter": "0,1,2,3", - "EventName": "TX_EXEC.MISC5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x2", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC8", - "UMask": "0x1", - "BriefDescription": "Number of times an HLE execution started.", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.START", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x2", - "BriefDescription": "Number of times an HLE execution successfully committed.", - "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.COMMIT", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc8", - "UMask": "0x4", "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xc8", - "UMask": "0x8", "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xc8", - "UMask": "0x10", "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xc8", - "UMask": "0x20", "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xc8", - "UMask": "0x40", "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type.", "Counter": "0,1,2,3", - "EventName": "HLE_RETIRED.ABORTED_MISC4", + "CounterHTOff": "0,1,2,3,4,5,6,7", "Errata": "HSD65", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MISC4", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xc8", - "UMask": "0x80", "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0xC9", - "UMask": "0x1", - "BriefDescription": "Number of times an RTM execution started.", + "BriefDescription": "Number of times an HLE execution successfully committed.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.START", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xc9", - "UMask": "0x2", - "BriefDescription": "Number of times an RTM execution successfully committed.", + "BriefDescription": "Number of times an HLE execution started.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.COMMIT", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.START", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering machine clears detected. Memory ordering machine clears can result from memory address aliasing or snoops from another hardware thread or core to data inflight in the pipeline. Machine clears can have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 128.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 16.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 256.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 32.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 4.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 512.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 64.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Randomly selected loads with latency value being above 8.", + "Counter": "3", + "CounterHTOff": "3", + "Data_LA": "1", + "Errata": "HSD76, HSD25, HSM26", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "Speculative cache-line split store-address uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400244", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x063F800091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x083FC00091", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x06004007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x063F8007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x083FC007F7", + "Offcore": "1", + "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all requests miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC08FFF", + "Offcore": "1", + "PublicDescription": "Counts all requests miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400122", + "Offcore": "1", + "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400004", + "Offcore": "1", + "PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400001", + "Offcore": "1", + "PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0600400002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103FC00002", + "Offcore": "1", + "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00040", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00010", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00020", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00200", + "Offcore": "1", + "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00080", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00100", + "Offcore": "1", + "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "EventCode": "0xc9", - "UMask": "0x4", "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", - "PEBS": "1", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xc9", - "UMask": "0x8", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xc9", - "UMask": "0x10", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC2", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x10" }, { - "EventCode": "0xc9", - "UMask": "0x20", "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC3", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "EventCode": "0xc9", - "UMask": "0x40", "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type.", "Counter": "0,1,2,3", - "EventName": "RTM_RETIRED.ABORTED_MISC4", + "CounterHTOff": "0,1,2,3", "Errata": "HSD65", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MISC4", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "EventCode": "0xc9", - "UMask": "0x80", "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x80" }, { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 4.", - "PEBS": "2", - "MSRValue": "0x4", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 8.", - "PEBS": "2", - "MSRValue": "0x8", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "50021", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 16.", - "PEBS": "2", - "MSRValue": "0x10", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "20011", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 32.", - "PEBS": "2", - "MSRValue": "0x20", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 64.", - "PEBS": "2", - "MSRValue": "0x40", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "2003", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 128.", - "PEBS": "2", - "MSRValue": "0x80", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "1009", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 256.", - "PEBS": "2", - "MSRValue": "0x100", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "503", - "CounterHTOff": "3" - }, - { - "EventCode": "0xCD", - "UMask": "0x1", - "BriefDescription": "Randomly selected loads with latency value being above 512.", - "PEBS": "2", - "MSRValue": "0x200", - "Counter": "3", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "Errata": "HSD76, HSD25, HSM26", - "TakenAlone": "1", - "SampleAfterValue": "101", - "CounterHTOff": "3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads miss in the L3", - "MSRValue": "0x3FBFC00001", + "BriefDescription": "Number of times an RTM execution successfully committed.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts demand data reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", - "MSRValue": "0x0600400001", + "BriefDescription": "Number of times an RTM execution started.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.START", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3", - "MSRValue": "0x3FBFC00002", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", - "MSRValue": "0x0600400002", + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00002", + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand code reads miss in the L3", - "MSRValue": "0x3FBFC00004", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", - "MSRValue": "0x0600400004", + "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC5", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", - "MSRValue": "0x3FBFC00010", + "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional writes.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", - "MSRValue": "0x3FBFC00020", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", - "MSRValue": "0x3FBFC00040", + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", - "MSRValue": "0x3FBFC00080", + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", - "MSRValue": "0x3FBFC00100", + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "SampleAfterValue": "2000003", + "UMask": "0x20" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", - "MSRValue": "0x3FBFC00200", + "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss in the L3", - "MSRValue": "0x3FBFC00091", + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", - "MSRValue": "0x0600400091", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063F800091", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC00091", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x083FC00091", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3", - "MSRValue": "0x3FBFC00122", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", - "MSRValue": "0x0600400122", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss in the L3", - "MSRValue": "0x3FBFC00244", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", - "MSRValue": "0x0600400244", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", - "MSRValue": "0x3FBFC007F7", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", - "MSRValue": "0x06004007F7", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", - "MSRValue": "0x063F8007F7", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", - "MSRValue": "0x103FC007F7", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", - "MSRValue": "0x083FC007F7", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" - }, - { - "Offcore": "1", - "EventCode": "0xB7, 0xBB", - "UMask": "0x1", - "BriefDescription": "Counts all requests miss in the L3", - "MSRValue": "0x3FBFC08FFF", - "Counter": "0,1,2,3", - "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "PublicDescription": "Counts all requests miss in the L3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/other.json b/tools/perf/pmu-events/arch/x86/haswellx/other.json index 800e65df31bc..4c6b9d34325a 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/other.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/other.json @@ -1,43 +1,43 @@ [ { - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EdgeDetect": "1", - "EventCode": "0x5C", - "UMask": "0x1", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", "Counter": "0,1,2,3", - "EventName": "CPL_CYCLES.RING0_TRANS", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", - "UMask": "0x2", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", - "UMask": "0x1", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json index 26f2888341ee..a53f28ec9270 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json @@ -1,1340 +1,1305 @@ [ { - "UMask": "0x1", - "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "EventName": "INST_RETIRED.ANY", - "Errata": "HSD140, HSD143", - "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 0" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when the thread is not in halt state.", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x2", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 1" - }, - { - "UMask": "0x3", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "Counter": "Fixed counter 2", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.", - "SampleAfterValue": "2000003", - "CounterHTOff": "Fixed counter 2" - }, - { - "EventCode": "0x03", - "UMask": "0x2", - "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "UMask": "0x8", - "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS.NO_SR", - "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x07", - "UMask": "0x1", - "BriefDescription": "False dependencies in MOB due to partial compare on address.", - "Counter": "0,1,2,3", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "CounterMask": "1", - "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "UMask": "0x3", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", - "Counter": "0,1,2,3", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "AnyThread": "1", - "CounterMask": "1", - "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.ANY", - "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", - "EventCode": "0x0E", - "UMask": "0x1", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x0E", - "UMask": "0x10", - "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "UMask": "0x20", - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "UMask": "0x40", - "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", - "Counter": "0,1,2,3", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x14", - "UMask": "0x2", "BriefDescription": "Any uop executed by the Divider. (This includes all divide uops, sqrt, ...)", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", "EventName": "ARITH.DIVIDER_UOPS", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Thread cycles when thread is not in halt state", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x0", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "UMask": "0x1", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "AnyThread": "1", - "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3c", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x3C", - "UMask": "0x2", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4c", - "UMask": "0x1", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", - "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.SW_PF", - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4c", - "UMask": "0x2", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", - "Counter": "0,1,2,3", - "EventName": "LOAD_HIT_PRE.HW_PF", - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x1", - "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x2", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "PublicDescription": "Number of SIMD move elimination candidate uops that were eliminated.", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x4", - "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "UMask": "0x8", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", - "Counter": "0,1,2,3", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "PublicDescription": "Number of SIMD move elimination candidate uops that were not eliminated.", - "SampleAfterValue": "1000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "Invert": "1", - "EventCode": "0x5E", - "UMask": "0x1", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "Counter": "0,1,2,3", - "EventName": "RS_EVENTS.EMPTY_END", - "CounterMask": "1", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x87", - "UMask": "0x1", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "Counter": "0,1,2,3", - "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x87", - "UMask": "0x4", - "BriefDescription": "Stall cycles because IQ is full", - "Counter": "0,1,2,3", - "EventName": "ILD_STALL.IQ_FULL", - "PublicDescription": "Stall cycles due to IQ is full.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x41", - "BriefDescription": "Not taken macro-conditional branches.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired macro-conditional branches.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x82", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0x90", - "BriefDescription": "Taken speculative and retired direct near calls.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired indirect calls.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired macro-conditional branches.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc2", - "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc4", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xc8", - "BriefDescription": "Speculative and retired indirect return branches.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xd0", - "BriefDescription": "Speculative and retired direct near calls.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "UMask": "0xff", "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "Counts all near executed branches (not necessarily retired).", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x89", - "UMask": "0x41", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "BriefDescription": "Speculative and retired macro-conditional branches.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc1" }, { - "EventCode": "0x89", - "UMask": "0x81", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc2" }, { - "EventCode": "0x89", - "UMask": "0x84", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "BriefDescription": "Speculative and retired direct near calls.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xd0" }, { - "EventCode": "0x89", - "UMask": "0x88", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc4" }, { - "EventCode": "0x89", - "UMask": "0xa0", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "BriefDescription": "Speculative and retired indirect return branches.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc8" }, { - "EventCode": "0x89", - "UMask": "0xc1", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "BriefDescription": "Not taken macro-conditional branches.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "EventCode": "0x89", - "UMask": "0xc4", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", + "BriefDescription": "Taken speculative and retired macro-conditional branches.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "EventCode": "0x89", - "UMask": "0xff", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", "Counter": "0,1,2,3", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "SampleAfterValue": "200003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x82" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in port 0", + "BriefDescription": "Taken speculative and retired direct near calls.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0", - "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per core when uops are executed in port 0.", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in port 0.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" }, { - "EventCode": "0xA1", - "UMask": "0x1", - "BriefDescription": "Cycles per thread when uops are executed in port 0.", + "BriefDescription": "Taken speculative and retired indirect calls.", "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in port 1", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1", - "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per core when uops are executed in port 1.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in port 1.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x2", - "BriefDescription": "Cycles per thread when uops are executed in port 1.", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in port 2", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2", - "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per core when uops are dispatched to port 2.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x4", - "BriefDescription": "Cycles per thread when uops are executed in port 2.", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in port 3", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3", - "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per core when uops are dispatched to port 3.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x8", - "BriefDescription": "Cycles per thread when uops are executed in port 3.", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in port 4", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4", - "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per core when uops are executed in port 4.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in port 4.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x10", - "BriefDescription": "Cycles per thread when uops are executed in port 4.", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in port 5", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5", - "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per core when uops are executed in port 5.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in port 5.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x20", - "BriefDescription": "Cycles per thread when uops are executed in port 5.", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in port 6", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6", - "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per core when uops are executed in port 6.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", - "AnyThread": "1", - "PublicDescription": "Cycles per core when uops are exectuted in port 6.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x40", - "BriefDescription": "Cycles per thread when uops are executed in port 6.", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_6", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in port 7", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7", - "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per core when uops are dispatched to port 7.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", - "AnyThread": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "UMask": "0x80", - "BriefDescription": "Cycles per thread when uops are executed in port 7.", - "Counter": "0,1,2,3", - "EventName": "UOPS_DISPATCHED_PORT.PORT_7", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x1", - "BriefDescription": "Resource-related stall cycles", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ANY", - "Errata": "HSD135", - "PublicDescription": "Cycles allocation is stalled due to resource related reason.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x4", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x8", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.SB", - "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "UMask": "0x10", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "Counter": "0,1,2,3", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x1", - "BriefDescription": "Cycles with pending L2 cache miss loads.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "CounterMask": "1", - "Errata": "HSD78", - "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "UMask": "0x2", - "BriefDescription": "Cycles with pending memory loads.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "CounterMask": "2", - "PublicDescription": "Cycles with pending memory loads. Set Cmask=2 to count cycle.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x4", - "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "CounterMask": "4", - "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x5", - "BriefDescription": "Execution stalls due to L2 cache misses.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "CounterMask": "5", - "PublicDescription": "Number of loads missed L2.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x6", - "BriefDescription": "Execution stalls due to memory subsystem.", - "Counter": "0,1,2,3", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "CounterMask": "6", - "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "UMask": "0x8", - "BriefDescription": "Cycles with pending L1 cache miss loads.", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "CounterMask": "8", - "PublicDescription": "Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "UMask": "0xc", - "BriefDescription": "Execution stalls due to L1 data cache misses", - "Counter": "2", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "CounterMask": "12", - "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", - "SampleAfterValue": "2000003", - "CounterHTOff": "2" - }, - { - "EventCode": "0xa8", - "UMask": "0x1", - "BriefDescription": "Number of Uops delivered by the LSD.", - "Counter": "0,1,2,3", - "EventName": "LSD.UOPS", - "PublicDescription": "Number of uops delivered by the LSD.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_ACTIVE", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "UMask": "0x1", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "Counter": "0,1,2,3", - "EventName": "LSD.CYCLES_4_UOPS", - "CounterMask": "4", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "CounterMask": "1", - "Errata": "HSD144, HSD30, HSM31", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 1 uop was executed per-thread", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "CounterMask": "1", - "Errata": "HSD144, HSD30, HSM31", - "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 2 uops were executed per-thread", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "CounterMask": "2", - "Errata": "HSD144, HSD30, HSM31", - "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 3 uops were executed per-thread", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "CounterMask": "3", - "Errata": "HSD144, HSD30, HSM31", - "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x1", - "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", - "CounterMask": "4", - "Errata": "HSD144, HSD30, HSM31", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB1", - "UMask": "0x2", - "BriefDescription": "Number of uops executed on the core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE", - "Errata": "HSD30, HSM31", - "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", - "CounterMask": "1", - "Errata": "HSD30, HSM31", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "CounterMask": "2", - "Errata": "HSD30, HSM31", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "CounterMask": "3", - "Errata": "HSD30, HSM31", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "CounterMask": "4", - "Errata": "HSD30, HSM31", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0xb1", - "UMask": "0x2", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "Counter": "0,1,2,3", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "Errata": "HSD30, HSM31", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "UMask": "0x0", - "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "Errata": "HSD11, HSD140", - "PublicDescription": "Number of instructions at retirement.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "UMask": "0x1", - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "PEBS": "2", - "Counter": "1", - "EventName": "INST_RETIRED.PREC_DIST", - "Errata": "HSD140", - "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", - "SampleAfterValue": "2000003", - "CounterHTOff": "1" - }, - { - "EventCode": "0xC0", - "UMask": "0x2", - "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.", - "Counter": "0,1,2,3", - "EventName": "INST_RETIRED.X87", - "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "UMask": "0x40", - "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", - "Counter": "0,1,2,3", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Actually retired uops.", - "Data_LA": "1", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.ALL", - "PublicDescription": "Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles without actually retired uops.", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles with less than 10 actually retired uops.", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "CounterMask": "10", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "Invert": "1", - "EventCode": "0xC2", - "UMask": "0x1", - "BriefDescription": "Cycles without actually retired uops.", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", - "AnyThread": "1", - "CounterMask": "1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC2", - "UMask": "0x2", - "BriefDescription": "Retirement slots used.", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.CYCLES", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EdgeDetect": "1", - "EventCode": "0xC3", - "UMask": "0x1", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.COUNT", - "CounterMask": "1", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x4", - "BriefDescription": "Self-modifying code (SMC) detected.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC3", - "UMask": "0x20", - "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "Counter": "0,1,2,3", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x0", "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "Branch instructions at retirement.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "400009" }, { - "EventCode": "0xC4", - "UMask": "0x1", - "BriefDescription": "Conditional branch instructions retired.", - "PEBS": "1", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", "PublicDescription": "Counts the number of conditional branch instructions retired.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect near call instructions retired.", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x2", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x4", - "BriefDescription": "All (macro) branch instructions retired.", - "PEBS": "2", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC4", - "UMask": "0x8", - "BriefDescription": "Return instructions retired.", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PublicDescription": "Counts the number of near return instructions retired.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x10", - "BriefDescription": "Not taken branch instructions retired.", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "PublicDescription": "Counts the number of not taken branch instructions retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x20", - "BriefDescription": "Taken branch instructions retired.", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PublicDescription": "Number of near taken branches retired.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "UMask": "0x40", "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PublicDescription": "Number of far branches retired.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" + }, + { + "BriefDescription": "Direct and indirect near call instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "Counts the number of near return instructions retired.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Number of near taken branches retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "UMask": "0x88" }, { - "EventCode": "0xC5", - "UMask": "0x0", "BriefDescription": "All mispredicted macro branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Mispredicted branch instructions at retirement.", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "SampleAfterValue": "400009" }, { - "EventCode": "0xC5", - "UMask": "0x1", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "PEBS": "1", - "Counter": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC5", - "UMask": "0x4", "BriefDescription": "Mispredicted macro branch instructions retired.", - "PEBS": "2", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", "PublicDescription": "This event counts all mispredicted branch instructions retired. This is a precise event.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xC5", - "UMask": "0x20", - "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", - "PEBS": "1", + "BriefDescription": "Mispredicted conditional branch instructions retired.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", "PublicDescription": "Number of near branch instructions retired that were taken but mispredicted.", "SampleAfterValue": "400009", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "PublicDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Cycles with pending L1 data cache miss loads. Set Cmask=8 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD78, HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Cycles with pending L2 miss loads. Set Cmask=2 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with pending memory loads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Cycles with pending memory loads. Set Cmask=2 to count cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls due to L2 cache misses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "Errata": "HSM63, HSM80", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Number of loads missed L2.", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls due to memory subsystem.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", + "PublicDescription": "This event counts cycles during which no instructions were executed in the execution stage of the pipeline and there were memory instructions pending (waiting for data).", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Stall cycles because IQ is full", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "This event counts cycles where the decoder is stalled on an instruction with a length changing prefix (LCP).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "Errata": "HSD140, HSD143", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leaving the programmable counters available for other events. Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD11, HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "HSD140", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "FP operations retired. X87 FP operations that have no exceptions: Counts also flows that have several X87 or flows that use X87 uops in the exception handling.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "This event counts the number of cycles spent waiting for a recovery after an event such as a processor nuke, JEClear, assist, hle/rtm abort etc.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "PublicDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "loads blocked by overlapping with store buffer that cannot be forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. The penalty for blocked store forwarding is that the load must wait for the store to write its value to the cache before it can be issued.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline which can have a performance impact.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of uops delivered by the LSD.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate uops that were eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "PublicDescription": "Number of integer move elimination candidate uops that were not eliminated.", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "PublicDescription": "Number of microcode assists invoked by HW upon uop writeback.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD135", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Cycles allocation is stalled due to resource related reason.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "This event counts cycles during which no instructions were allocated because no Store Buffers (SB) were available.", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xCC", - "UMask": "0x20", "BriefDescription": "Count cases of saving new LBR", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Count cases of saving new LBR records by hardware.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xe6", - "UMask": "0x1f", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", "Counter": "0,1,2,3", - "EventName": "BACLEARS.ANY", - "PublicDescription": "Number of front end re-steers due to BPU misprediction.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "This event counts cycles when the Reservation Station ( RS ) is empty for the thread. The RS is a structure that buffers allocated micro-ops from the Front-end. If there are many cycles when the RS is empty, it may represent an underflow of instructions delivered from the Front-end.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_6", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_7", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "HSD30, HSM31", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "This events counts the cycles where at least one uop was executed. It is counted per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least two uop were executed. It is counted per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "This events counts the cycles where at least three uop were executed. It is counted per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed per-thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "Errata": "HSD144, HSD30, HSM31", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0", + "PublicDescription": "Cycles which a uop is dispatched on port 0 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1", + "PublicDescription": "Cycles which a uop is dispatched on port 1 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2", + "PublicDescription": "Cycles which a uop is dispatched on port 2 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3", + "PublicDescription": "Cycles which a uop is dispatched on port 3 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4", + "PublicDescription": "Cycles which a uop is dispatched on port 4 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5", + "PublicDescription": "Cycles which a uop is dispatched on port 5 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6", + "PublicDescription": "Cycles which a uop is dispatched on port 6 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are executed in port 6.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", + "PublicDescription": "Cycles per core when uops are exectuted in port 6.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are executed in port 7", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7", + "PublicDescription": "Cycles which a uop is dispatched on port 7 in this thread.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 7.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of uops issued by the Front-end of the pipeline to the Back-end. This event is counted at the allocation stage and will count both retired and non-retired uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such uops add delay.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (for example, 2 sources + immediate) regardless of whether it is a result of LEA instruction or not.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "Counts the number of micro-ops retired. Use Cmask=1 and invert to count active cycles or stalled cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 uops or 4 instructions could retire each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json index 168df552b1a8..ba3e77a9f9a0 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json @@ -1,484 +1,484 @@ [ { - "EventCode": "0x08", - "UMask": "0x1", "BriefDescription": "Load misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x08", - "UMask": "0x2", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x4", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x8", - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0xe", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x20", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", - "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x40", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", - "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x60", - "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", - "Counter": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "PublicDescription": "Number of cache load STLB hits. No page walk.", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "UMask": "0x80", "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" + }, + { + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Number of cache load STLB hits. No page walk.", + "SampleAfterValue": "2000003", + "UMask": "0x60" + }, + { + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0x49", - "UMask": "0x1", "BriefDescription": "Store misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", - "UMask": "0x2", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0x4", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0x8", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0xe", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", - "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0x10", - "BriefDescription": "Cycles when PMH is busy with page walks", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0x20", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", - "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0x40", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", - "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0x60", - "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", - "Counter": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "UMask": "0x80", "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x80" }, { - "EventCode": "0x4f", - "UMask": "0x10", - "BriefDescription": "Cycle count for an Extended Page table walk.", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "EventName": "EPT.WALK_CYCLES", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x1", - "BriefDescription": "Misses at all ITLB levels that cause page walks", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x60" }, { - "EventCode": "0x85", - "UMask": "0x2", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", + "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0x85", - "UMask": "0x4", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", + "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0x85", - "UMask": "0x8", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xe" }, { - "EventCode": "0x85", - "UMask": "0xe", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "PublicDescription": "Completed page walks in ITLB of any page size.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "EventCode": "0x85", - "UMask": "0x10", "BriefDescription": "Cycles when PMH is busy with page walks", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_DURATION", - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x85", - "UMask": "0x20", - "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", + "BriefDescription": "Cycle count for an Extended Page table walk.", "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_4K", - "PublicDescription": "ITLB misses that hit STLB (4K).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4f", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "EventCode": "0x85", - "UMask": "0x40", - "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT_2M", - "PublicDescription": "ITLB misses that hit STLB (2M).", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "UMask": "0x60", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", - "Counter": "0,1,2,3", - "EventName": "ITLB_MISSES.STLB_HIT", - "PublicDescription": "ITLB misses that hit STLB. No page walk.", - "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xae", - "UMask": "0x1", "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xae", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" + }, + { + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "ITLB misses that hit STLB. No page walk.", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_2M", + "PublicDescription": "ITLB misses that hit STLB (2M).", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT_4K", + "PublicDescription": "ITLB misses that hit STLB (4K).", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Completed page walks in ITLB of any page size.", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", + "SampleAfterValue": "100003", + "UMask": "0x10" }, { - "EventCode": "0xBC", - "UMask": "0x11", "BriefDescription": "Number of DTLB page walker hits in the L1+FB", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xBC", - "UMask": "0x12", "BriefDescription": "Number of DTLB page walker hits in the L2", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xBC", - "UMask": "0x14", "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_L3", "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x14" }, { - "EventCode": "0xBC", - "UMask": "0x18", "BriefDescription": "Number of DTLB page walker hits in Memory", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", + "CounterHTOff": "0,1,2,3", "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "PublicDescription": "Number of DTLB page walker loads from memory.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x18" }, { + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xBC", - "UMask": "0x21", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", + "SampleAfterValue": "2000003", + "UMask": "0x41" + }, + { + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", + "SampleAfterValue": "2000003", + "UMask": "0x42" + }, + { + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", + "SampleAfterValue": "2000003", + "UMask": "0x44" + }, + { + "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", + "SampleAfterValue": "2000003", + "UMask": "0x48" + }, + { + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", + "SampleAfterValue": "2000003", + "UMask": "0x81" + }, + { + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", + "SampleAfterValue": "2000003", + "UMask": "0x82" + }, + { + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", + "SampleAfterValue": "2000003", + "UMask": "0x84" + }, + { + "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", + "SampleAfterValue": "2000003", + "UMask": "0x88" + }, + { "BriefDescription": "Number of ITLB page walker hits in the L1+FB", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x21" }, { - "EventCode": "0xBC", - "UMask": "0x22", "BriefDescription": "Number of ITLB page walker hits in the L2", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x22" }, { - "EventCode": "0xBC", - "UMask": "0x24", "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", + "CounterHTOff": "0,1,2,3", "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_L3", "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x24" }, { - "EventCode": "0xBC", - "UMask": "0x28", "BriefDescription": "Number of ITLB page walker hits in Memory", "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", + "CounterHTOff": "0,1,2,3", "Errata": "HSD25", + "EventCode": "0xBC", + "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", "PublicDescription": "Number of ITLB page walker loads from memory.", "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" + "UMask": "0x28" }, { - "EventCode": "0xBC", - "UMask": "0x41", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x42", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x44", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x48", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x81", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x82", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x84", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "UMask": "0x88", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", - "Counter": "0,1,2,3", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", - "SampleAfterValue": "2000003", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBD", - "UMask": "0x1", "BriefDescription": "DTLB flush attempts of the thread-specific entries", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "DTLB flush attempts of the thread-specific entries.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", - "UMask": "0x20", "BriefDescription": "STLB flush attempts", "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Count number of STLB flush attempts.", "SampleAfterValue": "100003", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json index 49fe78fb6538..375ce490833c 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json @@ -1,164 +1,4 @@ [ - { - "BriefDescription": "L2 code requests", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of L2 code requests.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xe4" - }, - { - "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", - "SampleAfterValue": "20011", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand requests that miss L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts demand requests that miss L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x27" - }, - { - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xb0", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "RFO requests that hit L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xc2" - }, - { - "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.FB_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", - "SampleAfterValue": "100007", - "UMask": "0x40" - }, - { - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "L2 cache lines filling L2", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xF1", - "EventName": "L2_LINES_IN.ALL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1f" - }, - { - "BriefDescription": "Retired load instructions that split across a cacheline boundary.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", - "SampleAfterValue": "100003", - "UMask": "0x41" - }, - { - "BriefDescription": "Retired load instructions with L3 cache hits as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L3_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", - "SampleAfterValue": "100021", - "UMask": "0x4" - }, - { - "BriefDescription": "Demand Data Read miss L2, no rejects", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x21" - }, - { - "BriefDescription": "L2 cache misses when fetching instructions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 cache misses when fetching instructions.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x24" - }, - { - "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.FB_FULL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x2" - }, { "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", "CollectPEBSRecord": "2", @@ -172,292 +12,17 @@ "UMask": "0x1" }, { - "BriefDescription": "All retired load instructions.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.ALL_LOADS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.", - "SampleAfterValue": "1000003", - "UMask": "0x81" - }, - { - "BriefDescription": "L2 writebacks that access L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xF0", - "EventName": "L2_TRANS.L2_WB", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x40" - }, - { - "BriefDescription": "Demand Data Read requests", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xe1" - }, - { - "BriefDescription": "Demand Data Read transactions pending for off-core. Highly correlated.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xc1" - }, - { - "BriefDescription": "Cycles the superQ cannot take any more entries.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xf4", - "EventName": "SQ_MISC.SQ_FULL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand Data Read requests sent to uncore", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xb0", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions with L1 cache hits as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L1_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", - "SampleAfterValue": "1000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", + "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.L2_STALL", + "EventName": "L1D_PEND_MISS.FB_FULL", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired load instructions with L2 cache hits as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", - "SampleAfterValue": "200003", "UMask": "0x2" }, - { - "BriefDescription": "Retired load instructions with locked access.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.LOCK_LOADS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with locked access.", - "SampleAfterValue": "100007", - "UMask": "0x21" - }, - { - "BriefDescription": "Retired load instructions missed L3 cache as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L3_MISS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", - "SampleAfterValue": "50021", - "UMask": "0x20" - }, - { - "BriefDescription": "All retired store instructions.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.ALL_STORES", - "L1_Hit_Indication": "1", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.", - "SampleAfterValue": "1000003", - "UMask": "0x82" - }, - { - "BriefDescription": "Demand requests to L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts demand requests to L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xe7" - }, - { - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xc4" - }, - { - "BriefDescription": "Demand and prefetch data reads", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Core-originated cacheable demand requests missed L3", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x2e", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "SW prefetch requests that miss L2 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.SWPF_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x28" - }, - { - "BriefDescription": "Retired load instructions missed L1 cache as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L1_MISS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", - "SampleAfterValue": "200003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of L1D misses that are outstanding", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, { "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.", "CollectPEBSRecord": "2", @@ -473,57 +38,137 @@ "UMask": "0x2" }, { - "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", + "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", - "PEBS": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.L2_STALL", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", - "SampleAfterValue": "20011", + "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "SampleAfterValue": "1000003", + "Speculative": "1", "UMask": "0x4" }, { - "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "BriefDescription": "Number of L1D misses that are outstanding", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", - "PEBS": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", - "SampleAfterValue": "20011", + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines filling L2", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1f" + }, + { + "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.NON_SILENT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", + "SampleAfterValue": "200003", + "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", - "PEBS": "1", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.SILENT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", - "SampleAfterValue": "100003", - "UMask": "0x8" + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Retired store instructions that miss the STLB.", + "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", - "L1_Hit_Indication": "1", - "PEBS": "1", + "EventCode": "0xf2", + "EventName": "L2_LINES_OUT.USELESS_HWPF", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired store instructions that true miss the STLB.", - "SampleAfterValue": "100003", - "UMask": "0x12" + "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 code requests", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of L2 code requests.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read requests", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe1" + }, + { + "BriefDescription": "Demand requests that miss L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x27" + }, + { + "BriefDescription": "Demand requests to L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand requests to L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe7" }, { "BriefDescription": "RFO requests to L2 cache", @@ -538,41 +183,191 @@ "UMask": "0xe2" }, { - "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xc4" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts L2 cache misses when fetching instructions.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x24" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xc1" + }, + { + "BriefDescription": "Demand Data Read miss L2, no rejects", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x21" + }, + { + "BriefDescription": "RFO requests that hit L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xc2" + }, + { + "BriefDescription": "RFO requests that miss L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x22" + }, + { + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xc8" + }, + { + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x28" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x41" + }, + { + "BriefDescription": "All retired load instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", - "SampleAfterValue": "100021", - "UMask": "0x10" - }, - { - "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.", + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.", "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x4" + "UMask": "0x81" }, { - "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", + "BriefDescription": "All retired store instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.SILENT", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x1" + "PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.", + "SampleAfterValue": "1000003", + "UMask": "0x82" + }, + { + "BriefDescription": "All retired memory instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "SampleAfterValue": "1000003", + "UMask": "0x83" + }, + { + "BriefDescription": "Retired load instructions with locked access.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with locked access.", + "SampleAfterValue": "100007", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", + "SampleAfterValue": "100003", + "UMask": "0x41" }, { "BriefDescription": "Retired store instructions that split across a cacheline boundary.", @@ -588,18 +383,6 @@ "SampleAfterValue": "100003", "UMask": "0x42" }, - { - "BriefDescription": "SW prefetch requests that hit L2 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.SWPF_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xc8" - }, { "BriefDescription": "Retired load instructions that miss the STLB.", "CollectPEBSRecord": "2", @@ -609,55 +392,919 @@ "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions that true miss the STLB.", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x11" }, { - "BriefDescription": "RFO requests that miss L2 cache", + "BriefDescription": "Retired store instructions that miss the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_MISS", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x22" + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x12" }, { - "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.NON_SILENT", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", - "SampleAfterValue": "200003", - "Speculative": "1", + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "SampleAfterValue": "20011", "UMask": "0x2" }, { - "BriefDescription": "Any memory transaction that reached the SQ.", + "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load instructions missed L1 cache as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", + "SampleAfterValue": "100021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "SampleAfterValue": "100021", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", + "SampleAfterValue": "50021", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C0020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C2380", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C8000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C8000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C8000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1E003C8000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC03C0800", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts memory transactions sent to the uncore.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..", + "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x80" }, { - "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses", + "BriefDescription": "Demand Data Read requests sent to uncore", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xf2", - "EventName": "L2_LINES_OUT.USELESS_HWPF", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache", - "SampleAfterValue": "200003", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles the queue waiting for offcore responses is full.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xf4", + "EventName": "SQ_MISC.SQ_FULL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" } diff --git a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json index 5391c4f6eca3..4347e2d0d090 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json @@ -1,85 +1,4 @@ [ - { - "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x40" - }, - { - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x80" - }, - { - "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x10" - }, { "BriefDescription": "Counts all microcode FP assists.", "CollectPEBSRecord": "2", @@ -91,5 +10,93 @@ "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x2" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/frontend.json b/tools/perf/pmu-events/arch/x86/icelake/frontend.json index 4fa2a4186ee3..b510dd5d80da 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/icelake/frontend.json @@ -11,214 +11,6 @@ "Speculative": "1", "UMask": "0x1" }, - { - "BriefDescription": "Retired Instructions who experienced DSB miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.DSB_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x11", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles MITE is delivering optimal number of Uops", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired Instructions who experienced iTLB true miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.ITLB_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x14", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "5", - "EventCode": "0x9c", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x80", - "EventName": "ICACHE_16B.IFDATA_STALL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", - "MSRIndex": "0x3F7", - "MSRValue": "0x510006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", - "MSRIndex": "0x3F7", - "MSRValue": "0x100206", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "DSB-to-MITE switch true penalty cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xab", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.STLB_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x15", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.MITE_UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", - "MSRIndex": "0x3F7", - "MSRValue": "0x504006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", - "MSRIndex": "0x3F7", - "MSRValue": "0x502006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles MITE is delivering any Uop", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", - "MSRIndex": "0x3F7", - "MSRValue": "0x500206", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", "CollectPEBSRecord": "2", @@ -234,16 +26,76 @@ "UMask": "0x2" }, { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.DSB_UOPS", + "EventCode": "0xab", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", - "SampleAfterValue": "2000003", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x2" + }, + { + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", @@ -260,92 +112,6 @@ "TakenAlone": "1", "UMask": "0x1" }, - { - "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", - "MSRIndex": "0x3F7", - "MSRValue": "0x520006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "Invert": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", - "MSRIndex": "0x3F7", - "MSRValue": "0x501006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", - "MSRIndex": "0x3F7", - "MSRValue": "0x508006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", - "MSRIndex": "0x3F7", - "MSRValue": "0x500806", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, { "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", "CollectPEBSRecord": "2", @@ -361,6 +127,96 @@ "TakenAlone": "1", "UMask": "0x1" }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "MSRIndex": "0x3F7", + "MSRValue": "0x508006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "MSRIndex": "0x3F7", + "MSRValue": "0x501006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "MSRIndex": "0x3F7", + "MSRValue": "0x500206", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "MSRIndex": "0x3F7", + "MSRValue": "0x510006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "MSRIndex": "0x3F7", + "MSRValue": "0x502006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, { "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", "CollectPEBSRecord": "2", @@ -376,6 +232,203 @@ "TakenAlone": "1", "UMask": "0x1" }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "MSRIndex": "0x3F7", + "MSRValue": "0x520006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "MSRIndex": "0x3F7", + "MSRValue": "0x504006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "MSRIndex": "0x3F7", + "MSRValue": "0x500806", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE_16B.IFDATA_STALL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_STALL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_OK", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_OK", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x30" + }, { "BriefDescription": "Number of switches from DSB or MITE to the MS", "CollectPEBSRecord": "2", @@ -390,18 +443,6 @@ "Speculative": "1", "UMask": "0x30" }, - { - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_STALL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x4" - }, { "BriefDescription": "Uops delivered to IDQ while MS is busy", "CollectPEBSRecord": "2", @@ -414,59 +455,6 @@ "Speculative": "1", "UMask": "0x30" }, - { - "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MS_CYCLES_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x30" - }, - { - "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.L1I_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x12", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles DSB is delivering optimal number of Uops", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, { "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", "CollectPEBSRecord": "2", @@ -478,5 +466,32 @@ "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json index 432e45ac6814..4af23c04dc18 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json @@ -1,272 +1,452 @@ [ { - "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS)", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * (( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD) + (10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, + { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricGroup": "Summary", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { - "MetricExpr": "UOPS_RETIRED.SLOTS / INST_RETIRED.ANY", "BriefDescription": "Uops Per Instruction", - "MetricGroup": "Pipeline;Retire", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "BriefDescription": "Instruction per taken branch", - "MetricGroup": "Branches;FetchBW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { - "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricGroup": "Pipeline", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricGroup": "SMT", + "MetricName": "Slots_Utilization" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED", - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", "BriefDescription": "Floating Point Operations Per Cycle", - "MetricGroup": "Flops", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { - "MetricExpr": "UOPS_EXECUTED.THREAD / ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 )", + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting." + }, + { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", - "MetricGroup": "Pipeline;PortsUtil", + "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", - "MetricGroup": "BrMispredicts", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { - "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "CPU_CLK_UNHALTED.DISTRIBUTED", "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, { - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", "MetricGroup": "InsType", "MetricName": "IpLoad" }, { - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", "MetricGroup": "InsType", "MetricName": "IpStore" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricGroup": "Branches;InsType", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricGroup": "Branches", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, { - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { "BriefDescription": "Branch instructions per taken branch. ", - "MetricGroup": "Branches;PGO", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { - "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricGroup": "Flops;FpArith;InsType", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", - "BriefDescription": "Total number of retired Instructions", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, { - "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, + { "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", - "MetricGroup": "LSD", + "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "Fed;LSD", "MetricName": "LSD_Coverage" }, { - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricGroup": "DSB;FetchBW", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", - "MetricGroup": "MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Number of Instructions per non-speculative DSB miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) )", + "MetricGroup": "Bad;Branches", + "MetricName": "Other_Branches" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricGroup": "MemoryBound;MemoryBW", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, { - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricGroup": "MemoryTLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", - "MetricGroup": "MemoryBW", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", - "MetricGroup": "MemoryBW", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricGroup": "MemoryBW", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricGroup": "MemoryBW;Offcore", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricGroup": "CacheMisses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, + { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricGroup": "CacheMisses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { - "MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) / INST_RETIRED.ANY", "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", - "MetricGroup": "CacheMisses;Offcore", + "MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, + { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricGroup": "CacheMisses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, { - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructions for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, { - "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", "MetricGroup": "Summary;Power", "MetricName": "Average_Frequency" }, { - "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time", "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricGroup": "Flops;HPC", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, { - "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." + }, + { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0", "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, { - "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, + { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricGroup": "HPC;MemoryBW;SoC", + "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "MetricGroup": "Branches;OS", "MetricName": "IpFarBranch" }, { - "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C3 residency percent per core", + "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C3_Core_Residency" }, { - "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C6 residency percent per core", + "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Core_Residency" }, { - "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C7 residency percent per core", + "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Core_Residency" }, { - "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C2 residency percent per package", + "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C2_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C3 residency percent per package", + "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C3_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C6 residency percent per package", + "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C7 residency percent per package", + "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" } diff --git a/tools/perf/pmu-events/arch/x86/icelake/memory.json b/tools/perf/pmu-events/arch/x86/icelake/memory.json index 3701bd93a462..f045e1f6a868 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/memory.json +++ b/tools/perf/pmu-events/arch/x86/icelake/memory.json @@ -1,15 +1,27 @@ [ { - "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CONFLICT", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", - "SampleAfterValue": "100003", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" + }, + { + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x6" }, { "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", @@ -23,18 +35,86 @@ "UMask": "0x4" }, { - "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.", + "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_EVENTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_MEM", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an HLE execution successfully committed", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.COMMIT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times HLE commit succeeded.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times an HLE execution started.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc8", + "EventName": "HLE_RETIRED.START", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", "SampleAfterValue": "100003", "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "1009", + "TakenAlone": "1", "UMask": "0x1" }, { @@ -54,105 +134,51 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "503", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.ABORTED_MEM", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "SampleAfterValue": "100003", - "UMask": "0x8" + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x20" - }, - { - "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles where data return is pending for a Demand Data Read request who miss L3 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", + "TakenAlone": "1", "UMask": "0x1" }, { @@ -172,93 +198,45 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution successfully committed", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.COMMIT", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times RTM commit succeeded.", - "SampleAfterValue": "100003", - "UMask": "0x2" + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.ABORTED_EVENTS", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an HLE execution aborted due to unfriendly events (such as interrupts).", - "SampleAfterValue": "100003", - "UMask": "0x80" + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution successfully committed", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.COMMIT", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times HLE commit succeeded.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", - "SampleAfterValue": "100003", - "UMask": "0x40" - }, - { - "BriefDescription": "Number of machine clears due to memory ordering conflicts.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.L3_MISS", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00800", + "MSRValue": "0x3FFFC00004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -267,25 +245,58 @@ "UMask": "0x1" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_READ", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x80" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.", + "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_MISS", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC08000", + "MSRValue": "0x3FFFC00001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00010", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -309,222 +320,58 @@ "UMask": "0x1" }, { - "BriefDescription": "Demand Data Read requests who miss L3 cache", + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC08000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that was not supplied by the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC00800", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Demand Data Read requests who miss L3 cache.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x10" }, { - "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", + "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "2", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", - "SampleAfterValue": "100003", - "UMask": "0x20" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_EVENTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", - "SampleAfterValue": "100003", - "UMask": "0x80" - }, - { - "BriefDescription": "Number of times an HLE execution started.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.START", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times we entered an HLE region. Does not count nested transactions.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "MSRValue": "0x4", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "100003", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "MSRValue": "0x80", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "1009", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "MSRValue": "0x8", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "50021", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "MSRValue": "0x100", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "503", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "6", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x6" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "MSRValue": "0x40", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "2003", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "MSRValue": "0x20", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_MEM", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00400", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFFC00004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" + "UMask": "0x10" }, { "BriefDescription": "Number of times an RTM execution aborted.", @@ -537,6 +384,61 @@ "SampleAfterValue": "100003", "UMask": "0x4" }, + { + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an RTM execution successfully committed", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, { "BriefDescription": "Number of times an RTM execution started.", "CollectPEBSRecord": "2", @@ -549,14 +451,99 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc8", - "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x80" + }, + { + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", + "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x20" }, { @@ -570,5 +557,17 @@ "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" + }, + { + "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times we could not allocate Lock Buffer.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x40" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf/pmu-events/arch/x86/icelake/other.json index a806b00f8616..08f6321025e8 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/other.json +++ b/tools/perf/pmu-events/arch/x86/icelake/other.json @@ -1,834 +1,4 @@ [ - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C8000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184008000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0400", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184008000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C8000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts streaming stores that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010800", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts streaming stores that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000800", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C8000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x18" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts streaming stores that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000800", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0400", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C8000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "35", - "EventName": "TOPDOWN.SLOTS", - "PEBScounters": "35", - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000400", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.OTHER.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000400", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, { "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", "CollectPEBSRecord": "2", @@ -841,210 +11,6 @@ "Speculative": "1", "UMask": "0x7" }, - { - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0010", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x28", - "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0800", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0020", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0004", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L3.L3_HIT.ANY", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC03C2380", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.SLOTS_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1E003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010400", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0184000002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, { "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", "CollectPEBSRecord": "2", @@ -1058,13 +24,37 @@ "UMask": "0x7" }, { - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.", + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x18" + }, + { + "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x28", + "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", + "MSRValue": "0x10004", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", @@ -1073,13 +63,343 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02003C0004", + "MSRValue": "0x184000004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000004", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that have any type of response.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000400", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184008000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184008000", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that have any type of response.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000800", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that DRAM supplied the request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000800", "Offcore": "1", "PEBScounters": "0,1,2,3", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json index 4f4ce309c2f8..573ac7ac8879 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json @@ -1,464 +1,4 @@ [ - { - "BriefDescription": "Mispredicted indirect CALL instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", - "SampleAfterValue": "50021", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of uops executed on the core.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of uops executed from any thread.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of uops executed on port 4 and 9", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_4_9", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.THREAD", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Not taken branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND_NTAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts not taken branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x10" - }, - { - "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "Invert": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.INDIRECT", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", - "SampleAfterValue": "100003", - "UMask": "0x80" - }, - { - "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Number of uops executed on port 2 and 3", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_2_3", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Taken branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x4c", - "EventName": "LOAD_HIT_PREFETCH.SWPF", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of uops executed on port 1", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of Uops delivered by the LSD.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xa8", - "EventName": "LSD.UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of uops executed on port 5", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_5", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x20" - }, - { - "BriefDescription": "Number of uops executed on port 6", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_6", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x40" - }, - { - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0xA8", - "EventName": "LSD.CYCLES_ACTIVE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x40" - }, - { - "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", - "SampleAfterValue": "25003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x87", - "EventName": "ILD_STALL.LCP", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "False dependencies in MOB due to partial compare on address.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x07", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x5e", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles without actually retired uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "Invert": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event counts cycles without actually retired uops.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Far branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts far branch instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x40" - }, - { - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "16", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.ANY", - "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SCOREBOARD", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Increments whenever there is an update to the LBR array.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xcc", - "EventName": "MISC_RETIRED.LBR_INSERTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", - "SampleAfterValue": "100003", - "UMask": "0x20" - }, - { - "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc0", - "EventName": "INST_RETIRED.ANY_P", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003" - }, - { - "BriefDescription": "Counts the number of x87 uops dispatched.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.X87", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of x87 uops executed.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SB", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.NO_SR", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of machine clears (nukes) of any type.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.COUNT", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of machine clears (nukes) of any type.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", - "SampleAfterValue": "50021", - "UMask": "0x20" - }, - { - "BriefDescription": "Return instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts return instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x8" - }, { "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", "CollectPEBSRecord": "2", @@ -473,53 +13,39 @@ "UMask": "0x9" }, { - "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "BriefDescription": "All branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles without actually retired instructions.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xc0", - "EventName": "INST_RETIRED.STALL_CYCLES", - "Invert": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event counts cycles without actually retired instructions.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", - "SampleAfterValue": "50021", - "UMask": "0x10" + "PublicDescription": "Counts all branch instructions retired.", + "SampleAfterValue": "400009" }, { - "BriefDescription": "Core cycles when the thread is not in halt state", + "BriefDescription": "Conditional branch instructions retired.", "CollectPEBSRecord": "2", - "Counter": "33", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PEBScounters": "33", - "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x11" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" }, { "BriefDescription": "Taken conditional branch instructions retired.", @@ -533,6 +59,30 @@ "SampleAfterValue": "400009", "UMask": "0x1" }, + { + "BriefDescription": "Far branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts far branch instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, { "BriefDescription": "Direct and indirect near call instructions retired.", "CollectPEBSRecord": "2", @@ -546,210 +96,112 @@ "UMask": "0x2" }, { - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", - "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.PREC_DIST", - "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Total execution stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "12", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0xc" - }, - { - "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xcc", - "EventName": "MISC_RETIRED.PAUSE_INST", - "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", - "SampleAfterValue": "100003", - "UMask": "0x40" - }, - { - "BriefDescription": "Self-modifying code (SMC) detected.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.SMC", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Uops that RAT issues to RS", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x5" - }, - { - "BriefDescription": "Reference cycles when the core is not in halt state.", - "CollectPEBSRecord": "2", - "Counter": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PEBScounters": "34", - "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x3" - }, - { - "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x0D", - "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x3" - }, - { - "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "8", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x80" - }, - { - "BriefDescription": "Cycles with less than 10 actually retired uops.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "10", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "Invert": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", - "SampleAfterValue": "1000003", - "UMask": "0x2" - }, - { - "BriefDescription": "All branch instructions retired.", + "BriefDescription": "Return instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all branch instructions retired.", - "SampleAfterValue": "400009" + "PublicDescription": "Counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" }, { - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", + "BriefDescription": "Taken branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x5E", - "EventName": "RS_EVENTS.EMPTY_END", - "Invert": "1", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", - "SampleAfterValue": "100003", - "Speculative": "1", + "PublicDescription": "Counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "All mispredicted branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "SampleAfterValue": "50021" + }, + { + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "50021", + "UMask": "0x11" + }, + { + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "SampleAfterValue": "50021", + "UMask": "0x10" + }, + { + "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "SampleAfterValue": "50021", "UMask": "0x1" }, + { + "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "SampleAfterValue": "50021", + "UMask": "0x80" + }, + { + "BriefDescription": "Mispredicted indirect CALL instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.", + "SampleAfterValue": "50021", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "SampleAfterValue": "50021", + "UMask": "0x20" + }, { "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", "CollectPEBSRecord": "2", @@ -774,6 +226,52 @@ "Speculative": "1", "UMask": "0x2" }, + { + "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x3" + }, + { + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", + "SampleAfterValue": "25003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, { "BriefDescription": "Thread cycles when thread is not in halt state", "CollectPEBSRecord": "2", @@ -786,52 +284,330 @@ "Speculative": "1" }, { - "BriefDescription": "Mispredicted conditional branch instructions retired.", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts mispredicted conditional branch instructions retired.", - "SampleAfterValue": "50021", - "UMask": "0x11" + "Counter": "0,1,2,3", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" }, { - "BriefDescription": "Number of uops executed on port 0", + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_0", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.", - "SampleAfterValue": "2000003", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Conditional branch instructions retired.", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND", - "PEBS": "1", + "CounterMask": "16", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts conditional branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x11" + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x10" }, { - "BriefDescription": "Retirement slots used.", + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.SLOTS", + "CounterMask": "20", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x14" + }, + { + "BriefDescription": "Total execution stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the retirement slots used each cycle.", "SampleAfterValue": "2000003", "UMask": "0x2" }, + { + "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles without actually retired instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.STALL_CYCLES", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "This event counts cycles without actually retired instructions.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x0d", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x80" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "TMA slots where uops got dropped", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x0d", + "EventName": "INT_MISC.UOP_DROPPING", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies due to partial compare on address.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, { "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", "CollectPEBSRecord": "2", @@ -846,104 +622,265 @@ "UMask": "0x1" }, { - "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.", + "BriefDescription": "Number of Uops delivered by the LSD.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3c", - "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.PAUSE_INST", + "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SB", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x8" }, { - "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SCOREBOARD", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", - "SampleAfterValue": "2000003", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" }, { - "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "EventCode": "0x5e", + "EventName": "RS_EVENTS.EMPTY_CYCLES", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles where at least 1 uop was executed per-thread", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles where at least 4 uops were executed per-thread", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)", "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.STALL_CYCLES", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UOPS_DECODED.DEC0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Uops exclusively fetched by decoder 0", "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "BriefDescription": "Number of uops executed on port 0", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_0", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of uops executed on port 1", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of uops executed on port 2 and 3", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_2_3", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of uops executed on port 4 and 9", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of uops executed on port 5", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_5", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of uops executed on port 6", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_6", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of uops executed on port 7 and 8", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa1", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of uops executed from any thread.", "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x2" @@ -962,74 +899,207 @@ "UMask": "0x2" }, { - "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.INDIRECT", - "PEBS": "1", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", - "SampleAfterValue": "50021", - "UMask": "0x80" + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "TMA slots where uops got dropped", + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.UOP_DROPPING", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", - "SampleAfterValue": "1000003", + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.THREAD", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of x87 uops dispatched.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.X87", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of x87 uops executed.", + "SampleAfterValue": "2000003", "Speculative": "1", "UMask": "0x10" }, { - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "BriefDescription": "Uops that RAT issues to RS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "20", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x14" - }, - { - "BriefDescription": "Number of uops executed on port 7 and 8", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa1", - "EventName": "UOPS_DISPATCHED.PORT_7_8", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.", + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x80" - }, - { - "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_TAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", - "SampleAfterValue": "50021", "UMask": "0x1" }, { - "BriefDescription": "All mispredicted branch instructions retired.", + "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PEBS": "1", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", - "SampleAfterValue": "50021" + "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Retirement slots used.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the retirement slots used each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "This event counts cycles without actually retired uops.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "10", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "1000003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json index f485f4664ea6..a006fd7f7b18 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json @@ -1,38 +1,14 @@ [ { - "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "TLB_FLUSH.DTLB_THREAD", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", - "SampleAfterValue": "100007", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0xe" - }, - { - "BriefDescription": "STLB flush attempts", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xBD", - "EventName": "TLB_FLUSH.STLB_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", - "SampleAfterValue": "100007", - "Speculative": "1", "UMask": "0x20" }, { @@ -49,16 +25,28 @@ "UMask": "0x10" }, { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0xe" + }, + { + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" }, { "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", @@ -73,16 +61,28 @@ "UMask": "0x2" }, { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x10" + }, + { + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x20" }, { "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", @@ -97,30 +97,6 @@ "Speculative": "1", "UMask": "0x10" }, - { - "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Stores that miss the DTLB and hit the STLB.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x20" - }, { "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", "CollectPEBSRecord": "2", @@ -134,16 +110,16 @@ "UMask": "0xe" }, { - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0xe" + "UMask": "0x4" }, { "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", @@ -157,6 +133,18 @@ "Speculative": "1", "UMask": "0x2" }, + { + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" + }, { "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", "CollectPEBSRecord": "2", @@ -169,30 +157,6 @@ "Speculative": "1", "UMask": "0x20" }, - { - "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_PENDING", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x10" - }, { "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", "CollectPEBSRecord": "2", @@ -207,39 +171,75 @@ "UMask": "0x10" }, { - "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "Speculative": "1", + "UMask": "0xe" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", + "SampleAfterValue": "100007", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "STLB flush attempts", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.STLB_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", + "SampleAfterValue": "100007", + "Speculative": "1", "UMask": "0x20" - }, - { - "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_PENDING", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json index 624762008aaa..3c4da0371df9 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json @@ -1,185 +1,16 @@ [ { - "BriefDescription": "Demand Data Read miss L2, no rejects", + "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x21" - }, - { - "BriefDescription": "RFO requests that miss L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x22" - }, - { - "BriefDescription": "L2 cache misses when fetching instructions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 cache misses when fetching instructions.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x24" - }, - { - "BriefDescription": "Demand requests that miss L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts demand requests that miss L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x27" - }, - { - "BriefDescription": "SW prefetch requests that miss L2 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.SWPF_MISS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0x28" - }, - { - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xc1" - }, - { - "BriefDescription": "RFO requests that hit L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xc2" - }, - { - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xc4" - }, - { - "BriefDescription": "SW prefetch requests that hit L2 cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.SWPF_HIT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xc8" - }, - { - "BriefDescription": "Demand Data Read requests", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xe1" - }, - { - "BriefDescription": "RFO requests to L2 cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_RFO", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xe2" - }, - { - "BriefDescription": "L2 code requests", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of L2 code requests.", - "SampleAfterValue": "200003", - "Speculative": "1", - "UMask": "0xe4" - }, - { - "BriefDescription": "Core-originated cacheable demand requests missed L3", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x2e", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.", + "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, - { - "BriefDescription": "Number of L1D misses that are outstanding", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, { "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.", "CollectPEBSRecord": "2", @@ -219,117 +50,286 @@ "UMask": "0x4" }, { - "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.", + "BriefDescription": "Number of L1D misses that are outstanding", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x51", - "EventName": "L1D.REPLACEMENT", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.", + "BriefDescription": "Cycles with L1D load Misses outstanding.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", "PEBScounters": "0,1,2,3", - "PublicDescription": "For every cycle where the core is waiting on at least 1 outstanding demand RFO request, increments by 1. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "PublicDescription": "Counts duration of L1D miss outstanding in cycles.", "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "For every cycle, increments by the number of outstanding data read requests the core is waiting on.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "For every cycle, increments by the number of outstanding data read requests the core is waiting on. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding demand data read request, increments by 1.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "For every cycle where the core is waiting on at least 1 outstanding data read request, increments by 1. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Demand Data Read requests sent to uncore", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xb0", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", - "SampleAfterValue": "100003", - "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Demand and prefetch data reads", + "BriefDescription": "L2 cache lines filling L2", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x8" + "UMask": "0x1f" }, { - "BriefDescription": "Counts memory transactions sent to the uncore.", + "BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.NON_SILENT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities.", + "SampleAfterValue": "200003", "Speculative": "1", - "UMask": "0x80" + "UMask": "0x2" }, { - "BriefDescription": "Retired load instructions that miss the STLB.", + "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.SILENT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 code requests", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of L2 code requests.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read requests", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe1" + }, + { + "BriefDescription": "Demand requests that miss L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x27" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe2" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xc4" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts L2 cache misses when fetching instructions.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x24" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xc1" + }, + { + "BriefDescription": "Demand Data Read miss L2, no rejects", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x21" + }, + { + "BriefDescription": "RFO requests that hit L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xc2" + }, + { + "BriefDescription": "RFO requests that miss L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x22" + }, + { + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xc8" + }, + { + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_MISS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x28" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x41" + }, + { + "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4f" + }, + { + "BriefDescription": "All retired load instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions that true miss the STLB.", - "SampleAfterValue": "100003", - "UMask": "0x11" + "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.", + "SampleAfterValue": "1000003", + "UMask": "0x81" }, { - "BriefDescription": "Retired store instructions that miss the STLB.", + "BriefDescription": "All retired store instructions.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "EventName": "MEM_INST_RETIRED.ALL_STORES", "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired store instructions that true miss the STLB.", - "SampleAfterValue": "100003", - "UMask": "0x12" + "PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.", + "SampleAfterValue": "1000003", + "UMask": "0x82" + }, + { + "BriefDescription": "All retired memory instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "SampleAfterValue": "1000003", + "UMask": "0x83" }, { "BriefDescription": "Retired load instructions with locked access.", @@ -372,185 +372,31 @@ "UMask": "0x42" }, { - "BriefDescription": "All retired load instructions.", + "BriefDescription": "Retired load instructions that miss the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.ALL_LOADS", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.", - "SampleAfterValue": "1000003", - "UMask": "0x81" + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x11" }, { - "BriefDescription": "All retired store instructions.", + "BriefDescription": "Retired store instructions that miss the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", - "EventName": "MEM_INST_RETIRED.ALL_STORES", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.", - "SampleAfterValue": "1000003", - "UMask": "0x82" - }, - { - "BriefDescription": "Retired load instructions with L1 cache hits as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L1_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", - "SampleAfterValue": "1000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions with L2 cache hits as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", - "SampleAfterValue": "200003", - "UMask": "0x2" - }, - { - "BriefDescription": "Retired load instructions with L3 cache hits as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L3_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", - "SampleAfterValue": "100021", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired load instructions missed L1 cache as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L1_MISS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", - "SampleAfterValue": "200003", - "UMask": "0x8" - }, - { - "BriefDescription": "Retired load instructions missed L2 cache as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L2_MISS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", - "SampleAfterValue": "100021", - "UMask": "0x10" - }, - { - "BriefDescription": "Retired load instructions missed L3 cache as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.L3_MISS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", - "SampleAfterValue": "50021", - "UMask": "0x20" - }, - { - "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.FB_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", - "SampleAfterValue": "100007", - "UMask": "0x40" - }, - { - "BriefDescription": "Retired demand load instructions which missed L3 but serviced from local IXP memory as data sources", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd1", - "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", - "PEBS": "1", - "PEBScounters": "0,1,2,3", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", - "UMask": "0x80" - }, - { - "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", - "SampleAfterValue": "20011", - "UMask": "0x1" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "20011", - "UMask": "0x2" - }, - { - "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", - "SampleAfterValue": "20011", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "20011", - "UMask": "0x4" + "UMask": "0x12" }, { "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3", @@ -566,6 +412,43 @@ "Speculative": "1", "UMask": "0x4" }, + { + "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, { "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required", "CollectPEBSRecord": "2", @@ -579,6 +462,20 @@ "SampleAfterValue": "100003", "UMask": "0x8" }, + { + "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "SampleAfterValue": "20011", + "Speculative": "1", + "UMask": "0x2" + }, { "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram", "CollectPEBSRecord": "2", @@ -604,19 +501,6 @@ "SampleAfterValue": "100007", "UMask": "0x2" }, - { - "BriefDescription": "Retired load instructions whose data sources was remote HITM", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xd3", - "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", - "PEBS": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Retired load instructions whose data sources was remote HITM.", - "SampleAfterValue": "100007", - "UMask": "0x4" - }, { "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache", "CollectPEBSRecord": "2", @@ -631,7 +515,20 @@ "UMask": "0x8" }, { - "BriefDescription": "Retired demand load instructions which missed L3 but serviced from remote IXP memory as data sources", + "BriefDescription": "Retired load instructions whose data sources was remote HITM", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Retired load instructions whose data sources was remote HITM.", + "SampleAfterValue": "100007", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions with remote Intel Optane DC persistent memory as the data source where the data request missed all caches.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "Data_LA": "1", @@ -639,58 +536,610 @@ "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Retired load instructions which data source was serviced from L4", + "PublicDescription": "Counts retired load instructions with remote Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", "SampleAfterValue": "100007", "UMask": "0x10" }, { - "BriefDescription": "L2 writebacks that access L2 cache", + "BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF0", - "EventName": "L2_TRANS.L2_WB", + "Data_LA": "1", + "EventCode": "0xd4", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "Speculative": "1", + "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).", + "SampleAfterValue": "100007", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "SampleAfterValue": "100007", "UMask": "0x40" }, { - "BriefDescription": "L2 cache lines filling L2", + "BriefDescription": "Retired load instructions with L1 cache hits as data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF1", - "EventName": "L2_LINES_IN.ALL", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1f" + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.", + "SampleAfterValue": "1000003", + "UMask": "0x1" }, { - "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.SILENT", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load instructions missed L2 cache as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.", + "SampleAfterValue": "100021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "SampleAfterValue": "100021", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", + "SampleAfterValue": "50021", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired load instructions with local Intel Optane DC persistent memory as the data source where the data request missed all caches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts retired load instructions with local Intel Optane DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80082380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PREFETCHES.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C27F0", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1830000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1030000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x830000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts memory transactions sent to the uncore.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts cacheable and non-cacheable code reads to the core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts both cacheable and non-cacheable code reads to the core.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", + "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x1" }, { - "BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.NON_SILENT", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities.", - "SampleAfterValue": "200003", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with outstanding code read requests pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x2" }, + { + "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "For every cycle, increments by the number of outstanding code read requests pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, { "BriefDescription": "Cycles the queue waiting for offcore responses is full.", "CollectPEBSRecord": "2", @@ -702,5 +1151,53 @@ "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x4" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json index bcedcd985e84..4347e2d0d090 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json @@ -11,26 +11,6 @@ "Speculative": "1", "UMask": "0x2" }, - { - "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "CollectPEBSRecord": "2", @@ -38,6 +18,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x4" }, @@ -48,7 +29,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x8" }, @@ -59,6 +40,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x10" }, @@ -69,6 +51,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x20" }, @@ -79,17 +62,41 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x40" }, { - "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x80" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json index cc59cee1cd57..f217c3211ba2 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json @@ -1,105 +1,296 @@ [ { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.MITE_UOPS", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", + "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x1" }, { - "BriefDescription": "Cycles MITE is delivering optimal number of Uops", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Cycles MITE is delivering any Uop", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.DSB_UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles DSB is delivering optimal number of Uops", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES_ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of switches from DSB or MITE to the MS", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", - "EventCode": "0x79", - "EventName": "IDQ.MS_SWITCHES", + "EventCode": "0xab", + "EventName": "DSB2MITE_SWITCHES.COUNT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x30" + "UMask": "0x2" }, { - "BriefDescription": "Uops delivered to IDQ while MS is busy", + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x79", - "EventName": "IDQ.MS_UOPS", + "EventCode": "0xab", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x30" + "UMask": "0x2" + }, + { + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced iTLB true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x500106", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "MSRIndex": "0x3F7", + "MSRValue": "0x508006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "MSRIndex": "0x3F7", + "MSRValue": "0x501006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "MSRIndex": "0x3F7", + "MSRValue": "0x500206", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "MSRIndex": "0x3F7", + "MSRValue": "0x510006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "MSRIndex": "0x3F7", + "MSRValue": "0x502006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "MSRIndex": "0x3F7", + "MSRValue": "0x500406", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "MSRIndex": "0x3F7", + "MSRValue": "0x520006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "MSRIndex": "0x3F7", + "MSRValue": "0x504006", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "MSRIndex": "0x3F7", + "MSRValue": "0x500806", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", @@ -149,6 +340,108 @@ "Speculative": "1", "UMask": "0x4" }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles DSB is delivering optimal number of Uops", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_OK", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_ANY", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles MITE is delivering optimal number of Uops", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_OK", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of switches from DSB or MITE to the MS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to IDQ while MS is busy", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x30" + }, { "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled", "CollectPEBSRecord": "2", @@ -187,283 +480,5 @@ "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x1" - }, - { - "BriefDescription": "DSB-to-MITE switch true penalty cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xab", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0xab", - "EventName": "DSB2MITE_SWITCHES.COUNT", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Retired Instructions who experienced DSB miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.DSB_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x11", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.L1I_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x12", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.L2_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x13", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired Instructions who experienced iTLB true miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.ITLB_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x14", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.STLB_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x15", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", - "MSRIndex": "0x3F7", - "MSRValue": "0x500206", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", - "MSRIndex": "0x3F7", - "MSRValue": "0x500406", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", - "MSRIndex": "0x3F7", - "MSRValue": "0x500806", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", - "MSRIndex": "0x3F7", - "MSRValue": "0x501006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", - "MSRIndex": "0x3F7", - "MSRValue": "0x502006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", - "MSRIndex": "0x3F7", - "MSRValue": "0x504006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", - "MSRIndex": "0x3F7", - "MSRValue": "0x508006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", - "MSRIndex": "0x3F7", - "MSRValue": "0x510006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", - "MSRIndex": "0x3F7", - "MSRValue": "0x520006", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", - "MSRIndex": "0x3F7", - "MSRValue": "0x100206", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", - "MSRIndex": "0x3F7", - "MSRValue": "0x500106", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xe6", - "EventName": "BACLEARS.ANY", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 14b9a8ab15b9..a737fa40feb0 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -1,26 +1,38 @@ [ + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.COND + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) ) / TOPDOWN.SLOTS)", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * (( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (ICACHE_16B.IFDATA_STALL / CPU_CLK_UNHALTED.THREAD) + (10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(( 5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING ) / TOPDOWN.SLOTS)", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;FetchBW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { @@ -30,27 +42,53 @@ "MetricName": "CLKS" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilized by this Logical Processor", + "MetricExpr": "TOPDOWN.SLOTS / ( TOPDOWN.SLOTS / 2 ) if #SMT_on else 1", + "MetricGroup": "SMT", + "MetricName": "Slots_Utilization" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.DISTRIBUTED", - "MetricGroup": "Flops", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Pipeline;PortsUtil", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -74,122 +112,237 @@ { "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;InsType", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, { "BriefDescription": "Branch instructions per taken branch. ", "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", - "MetricGroup": "Flops;FpArith;InsType", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, { "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, { "BriefDescription": "Fraction of Uops delivered by the LSD (Loop Stream Detector; aka Loop Cache)", "MetricExpr": "LSD.UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "LSD", + "MetricGroup": "Fed;LSD", "MetricName": "LSD_Coverage" }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;FetchBW", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "BriefDescription": "Number of Instructions per non-speculative DSB miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not individually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - ( (BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BRANCHES) + (( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES) + ((BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES) )", + "MetricGroup": "Bad;Branches", + "MetricName": "Other_Branches" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", - "MetricGroup": "MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "MemoryBound;MemoryBW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", - "MetricGroup": "MemoryTLB", - "MetricName": "Page_Walks_Utilization" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", - "MetricGroup": "MemoryBW;Offcore", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", "MetricExpr": "1000 * ( ( OFFCORE_REQUESTS.ALL_DATA_RD - OFFCORE_REQUESTS.DEMAND_DATA_RD ) + L2_RQSTS.ALL_DEMAND_MISS + L2_RQSTS.SWPF_MISS ) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Offcore", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructions for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.DISTRIBUTED )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, { "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", "MetricExpr": "1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_Silent_PKI" }, { "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_NonSilent_PKI" }, { @@ -207,7 +360,7 @@ { "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time", - "MetricGroup": "Flops;HPC", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -216,6 +369,27 @@ "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.DISTRIBUTED", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." + }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_DISTRIBUTED if #SMT_on else 0", @@ -228,52 +402,64 @@ "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "HPC;MemoryBW;SoC", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_INSERTS.IA_MISS_DRD ) / ( cha_0@event\\=0x0@ / duration_time )", - "MetricGroup": "MemoryLat;SoC", + "MetricGroup": "Mem;MemoryLat;SoC", "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / cha@event\\=0x36\\,umask\\=0xC817FE01\\,thresh\\=1@", - "MetricGroup": "MemoryBW;SoC", + "MetricGroup": "Mem;MemoryBW;SoC", "MetricName": "MEM_Parallel_Reads" }, { "BriefDescription": "Average latency of data read request to external 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", "MetricExpr": "( 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM ) / cha_0@event\\=0x0@ )", - "MetricGroup": "MemoryLat;SoC;Server", + "MetricGroup": "Mem;MemoryLat;SoC;Server", "MetricName": "MEM_PMM_Read_Latency" }, + { + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": " 1000000000 * ( UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR ) / cha_0@event\\=0x0@", + "MetricGroup": "Mem;MemoryLat;SoC;Server", + "MetricName": "MEM_DRAM_Read_Latency" + }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [GB / sec]", "MetricExpr": "( ( 64 * imc@event\\=0xe3@ / 1000000000 ) / duration_time )", - "MetricGroup": "MemoryBW;SoC;Server", + "MetricGroup": "Mem;MemoryBW;SoC;Server", "MetricName": "PMM_Read_BW" }, { "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes [GB / sec]", "MetricExpr": "( ( 64 * imc@event\\=0xe7@ / 1000000000 ) / duration_time )", - "MetricGroup": "MemoryBW;SoC;Server", + "MetricGroup": "Mem;MemoryBW;SoC;Server", "MetricName": "PMM_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1000000000 / duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]", "MetricExpr": "( UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSERTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR ) * 64 / 1000000000 / duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Read_BW" }, { @@ -289,10 +475,10 @@ "MetricName": "IpFarBranch" }, { - "BriefDescription": "C1 residency percent per core", - "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100", + "BriefDescription": "C3 residency percent per core", + "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", - "MetricName": "C1_Core_Residency" + "MetricName": "C3_Core_Residency" }, { "BriefDescription": "C6 residency percent per core", @@ -300,16 +486,34 @@ "MetricGroup": "Power", "MetricName": "C6_Core_Residency" }, + { + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency" + }, { "BriefDescription": "C2 residency percent per package", "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C2_Pkg_Residency" }, + { + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency" + }, { "BriefDescription": "C6 residency percent per package", "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Pkg_Residency" + }, + { + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json index d319d448e2aa..c10a1bbc66b1 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json @@ -1,40 +1,510 @@ [ { - "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CONFLICT", + "CounterMask": "6", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", - "SampleAfterValue": "100003", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x6" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", + "BriefDescription": "Number of machine clears due to memory ordering conflicts.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "1009", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "503", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "101", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F04400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94002380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84002380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ITOM.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC08000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F844027F0", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC00477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F04400477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70CC00477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x94000800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000800", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data read requests that miss the L3 cache.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_READ", + "EventCode": "0xb0", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PEBScounters": "0,1,2,3", - "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", "SampleAfterValue": "100003", "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an RTM execution aborted.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times RTM abort was triggered.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "SampleAfterValue": "100003", "UMask": "0x80" }, + { + "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MEM", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an RTM execution successfully committed", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.COMMIT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times RTM commit succeeded.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times an RTM execution started.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc9", + "EventName": "RTM_RETIRED.START", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", "CollectPEBSRecord": "2", @@ -60,232 +530,39 @@ "UMask": "0x4" }, { - "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "6", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_READ", "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x6" - }, - { - "BriefDescription": "Number of machine clears due to memory ordering conflicts.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of times an RTM execution started.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.START", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an RTM execution successfully committed", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.COMMIT", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times RTM commit succeeded.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of times an RTM execution aborted.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times RTM abort was triggered.", - "SampleAfterValue": "100003", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_MEM", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", - "SampleAfterValue": "100003", - "UMask": "0x20" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", - "SampleAfterValue": "100003", - "UMask": "0x40" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED_EVENTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", - "SampleAfterValue": "100003", "UMask": "0x80" }, { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", + "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "MSRValue": "0x4", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", "SampleAfterValue": "100003", - "TakenAlone": "1", - "UMask": "0x1" + "Speculative": "1", + "UMask": "0x2" }, { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "MSRValue": "0x8", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "50021", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "MSRValue": "0x10", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "20011", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "MSRValue": "0x20", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "MSRValue": "0x40", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "2003", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "MSRValue": "0x80", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "1009", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "MSRValue": "0x100", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "503", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "MSRValue": "0x200", - "PEBS": "2", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "101", - "TakenAlone": "1", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", + "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json index ef50d3a3392e..1246b22769da 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json @@ -1,14 +1,15 @@ [ { - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", "CollectPEBSRecord": "2", - "Counter": "35", - "EventName": "TOPDOWN.SLOTS", - "PEBScounters": "35", - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", - "SampleAfterValue": "10000003", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", + "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x7" }, { "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", @@ -47,120 +48,540 @@ "UMask": "0x20" }, { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "BriefDescription": "Hit snoop reply with data, line invalidated.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.I_FWD_FE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this cores caches cache. A single snoop response from the core counts on all hyperthreads of the core.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x20" }, { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "BriefDescription": "HitM snoop reply with data, line invalidated.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.I_FWD_M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this cores caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Hit snoop reply without sending the data, line invalidated.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.I_HIT_FSE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this cores caches. A single snoop response from the core counts on all hyperthreads of the core.", + "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x2" }, { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "BriefDescription": "Line not found snoop reply", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x4" + "UMask": "0x1" }, { - "BriefDescription": "Number of PREFETCHW instructions executed.", + "BriefDescription": "Hit snoop reply with data, line kept in Shared state.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.S_FWD_FE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", - "SampleAfterValue": "100003", + "PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "HitM snoop reply with data, line kept in Shared state", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.S_FWD_M", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core.", + "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x8" }, { - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "BriefDescription": "Hit snoop reply without sending the data, line kept in Shared state.", "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.SLOTS_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", - "SampleAfterValue": "10000003", + "Counter": "0,1,2,3", + "EventCode": "0xef", + "EventName": "CORE_SNOOP_RESPONSE.S_HIT_FSE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x4" }, { - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", - "SampleAfterValue": "10000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc1", - "EventName": "ASSISTS.ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x7" - }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", + "MSRValue": "0x10004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0001", + "MSRValue": "0x73C000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts writes that generate a demand reads for ownership (RFO) request and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", + "MSRValue": "0x104000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by PMM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703C00001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.SNC_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700800001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.LOCAL_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703C00002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.REMOTE_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.SNC_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.SNC_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700800002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000400", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x12380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.HWPF_L3.REMOTE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x90002380", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.ITOM.REMOTE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x90000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC0477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x70C000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700C00477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F33000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x730000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.REMOTE_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.SNC_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708000477", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that (IC) were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.READS_TO_CORE.SNC_PMM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x700800477", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json index 3cc71244e699..068a3d46b443 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json @@ -1,171 +1,4 @@ [ - { - "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.ANY", - "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", - "CollectPEBSRecord": "2", - "Counter": "32", - "EventName": "INST_RETIRED.PREC_DIST", - "PEBS": "1", - "PEBScounters": "32", - "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Core cycles when the thread is not in halt state", - "CollectPEBSRecord": "2", - "Counter": "33", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PEBScounters": "33", - "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Reference cycles when the core is not in halt state.", - "CollectPEBSRecord": "2", - "Counter": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PEBScounters": "34", - "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x3" - }, - { - "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.NO_SR", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "False dependencies due to partial compare on address.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x07", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x0D", - "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x3" - }, - { - "BriefDescription": "TMA slots where uops got dropped", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.UOP_DROPPING", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0d", - "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", - "SampleAfterValue": "500009", - "Speculative": "1", - "UMask": "0x80" - }, - { - "BriefDescription": "Uops that RAT issues to RS", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "Invert": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x0e", - "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, { "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.", "CollectPEBSRecord": "2", @@ -180,28 +13,207 @@ "UMask": "0x9" }, { - "BriefDescription": "Thread cycles when thread is not in halt state", + "BriefDescription": "All branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", - "SampleAfterValue": "2000003", - "Speculative": "1" + "PublicDescription": "Counts all branch instructions retired.", + "SampleAfterValue": "400009" }, { - "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "BriefDescription": "Conditional branch instructions retired.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", + "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", - "SampleAfterValue": "25003", - "Speculative": "1", + "PublicDescription": "Counts conditional branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x11" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { + "BriefDescription": "Taken conditional branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts taken conditional branch instructions retired.", + "SampleAfterValue": "400009", "UMask": "0x1" }, + { + "BriefDescription": "Far branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts far branch instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Direct and indirect near call instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts both direct and indirect near call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "All mispredicted branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "SampleAfterValue": "50021" + }, + { + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "50021", + "UMask": "0x11" + }, + { + "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", + "SampleAfterValue": "50021", + "UMask": "0x10" + }, + { + "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", + "SampleAfterValue": "50021", + "UMask": "0x1" + }, + { + "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "SampleAfterValue": "50021", + "UMask": "0x80" + }, + { + "BriefDescription": "Mispredicted indirect CALL instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect.", + "SampleAfterValue": "50021", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", + "SampleAfterValue": "50021", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, { "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", "CollectPEBSRecord": "2", @@ -226,6 +238,349 @@ "Speculative": "1", "UMask": "0x8" }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x3" + }, + { + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.", + "SampleAfterValue": "25003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.", + "SampleAfterValue": "2000003", + "Speculative": "1" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "16", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "20", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x14" + }, + { + "BriefDescription": "Total execution stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Instruction decoders utilized in a cycle", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "INST_DECODED.DECODERS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x0d", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x80" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "SampleAfterValue": "500009", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "TMA slots where uops got dropped", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x0d", + "EventName": "INT_MISC.UOP_DROPPING", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies due to partial compare on address.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times a load got blocked due to false dependencies due to partial compare on address.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, { "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", "CollectPEBSRecord": "2", @@ -238,6 +593,114 @@ "Speculative": "1", "UMask": "0x1" }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xa8", + "EventName": "LSD.CYCLES_OK", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of machine clears (nukes) of any type.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.PAUSE_INST", + "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SB", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SCOREBOARD", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", "CollectPEBSRecord": "2", @@ -266,14 +729,49 @@ "UMask": "0x1" }, { - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "SampleAfterValue": "10000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x87", - "EventName": "ILD_STALL.LCP", + "EventCode": "0x56", + "EventName": "UOPS_DECODED.DEC0", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", - "SampleAfterValue": "500009", + "PublicDescription": "Uops exclusively fetched by decoder 0", + "SampleAfterValue": "1000003", "Speculative": "1", "UMask": "0x1" }, @@ -362,235 +860,56 @@ "UMask": "0x80" }, { - "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SCOREBOARD", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.SB", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Total execution stalls.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x5" - }, - { - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "8", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "12", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "PEBScounters": "0,1,2,3", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0xc" - }, - { - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "16", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "20", - "EventCode": "0xa3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x14" - }, - { - "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa6", - "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x10" - }, - { - "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.", - "SampleAfterValue": "1000003", - "Speculative": "1", - "UMask": "0x40" - }, - { - "BriefDescription": "Number of Uops delivered by the LSD.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xa8", - "EventName": "LSD.UOPS", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0xA8", - "EventName": "LSD.CYCLES_ACTIVE", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "CounterMask": "5", - "EventCode": "0xa8", - "EventName": "LSD.CYCLES_OK", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xb1", - "EventName": "UOPS_EXECUTED.THREAD", - "PEBScounters": "0,1,2,3,4,5,6,7", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "Invert": "1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x1" + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" }, { "BriefDescription": "Cycles where at least 1 uop was executed per-thread", @@ -645,56 +964,29 @@ "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.THREAD", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.", "SampleAfterValue": "2000003", "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.", - "SampleAfterValue": "2000003", - "Speculative": "1", - "UMask": "0x2" + "UMask": "0x1" }, { "BriefDescription": "Counts the number of x87 uops dispatched.", @@ -709,27 +1001,41 @@ "UMask": "0x10" }, { - "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "BriefDescription": "Uops that RAT issues to RS", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc0", - "EventName": "INST_RETIRED.ANY_P", - "PEBS": "1", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", - "SampleAfterValue": "2000003" + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" }, { - "BriefDescription": "Cycles with less than 10 actually retired uops.", + "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "CounterMask": "10", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", + "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to Mixing Intel AVX and Intel SSE Code section of the Optimization Guide.", + "SampleAfterValue": "100003", + "Speculative": "1", "UMask": "0x2" }, { @@ -744,229 +1050,30 @@ "UMask": "0x2" }, { - "BriefDescription": "Number of machine clears (nukes) of any type.", + "BriefDescription": "Cycles without actually retired uops.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.COUNT", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of machine clears (nukes) of any type.", - "SampleAfterValue": "100003", + "PublicDescription": "This event counts cycles without actually retired uops.", + "SampleAfterValue": "1000003", "Speculative": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Self-modifying code (SMC) detected.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc3", - "EventName": "MACHINE_CLEARS.SMC", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "All branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all branch instructions retired.", - "SampleAfterValue": "400009" - }, - { - "BriefDescription": "Taken conditional branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND_TAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken conditional branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x1" - }, - { - "BriefDescription": "Direct and indirect near call instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts both direct and indirect near call instructions retired.", - "SampleAfterValue": "100007", "UMask": "0x2" }, { - "BriefDescription": "Return instructions retired.", + "BriefDescription": "Cycles with less than 10 actually retired uops.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PEBS": "1", + "CounterMask": "10", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts return instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x8" - }, - { - "BriefDescription": "Not taken branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND_NTAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts not taken branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x10" - }, - { - "BriefDescription": "Conditional branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts conditional branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x11" - }, - { - "BriefDescription": "Taken branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x20" - }, - { - "BriefDescription": "Far branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts far branch instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x40" - }, - { - "BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.INDIRECT", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", - "SampleAfterValue": "100003", - "UMask": "0x80" - }, - { - "BriefDescription": "All mispredicted branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", - "SampleAfterValue": "50021" - }, - { - "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_TAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.", - "SampleAfterValue": "50021", - "UMask": "0x1" - }, - { - "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND_NTAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.", - "SampleAfterValue": "50021", - "UMask": "0x10" - }, - { - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.COND", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts mispredicted conditional branch instructions retired.", - "SampleAfterValue": "50021", - "UMask": "0x11" - }, - { - "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.", - "SampleAfterValue": "50021", - "UMask": "0x20" - }, - { - "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xc5", - "EventName": "BR_MISP_RETIRED.INDIRECT", - "PEBS": "1", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", - "SampleAfterValue": "50021", - "UMask": "0x80" - }, - { - "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xcc", - "EventName": "MISC_RETIRED.PAUSE_INST", - "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.", - "SampleAfterValue": "100003", - "UMask": "0x40" - }, - { - "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xec", - "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.", - "SampleAfterValue": "2000003", - "Speculative": "1", + "PublicDescription": "Counts the number of cycles using always true condition (uops_ret &lt; 16) applied to non PEBS uops retired event.", + "SampleAfterValue": "1000003", "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json index 52f2301582bb..71e052667e50 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-other.json @@ -60,7 +60,7 @@ "Unit": "CHA" }, { - "BriefDescription": "Clockticks of the uncore caching &amp; home agent (CHA)", + "BriefDescription": "Clockticks of the uncore caching and home agent (CHA)", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventName": "UNC_CHA_CLOCKTICKS", @@ -2472,5 +2472,64 @@ "PerPkg": "1", "UMask": "0x27", "Unit": "UPI LL" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to locally HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCD42FF04", + "UMaskExt": "0xCD42FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices to remotely HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCD437F04", + "UMaskExt": "0xCD437F", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to locally HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCC42FF04", + "UMaskExt": "0xCC42FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to remotely HOMed memory", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCC437F04", + "UMaskExt": "0xCC437F", + "Unit": "CHA" + }, + { + "BriefDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x2e", + "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "PublicDescription": "Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode.", + "UMask": "0x01", + "Unit": "M2M" } ] diff --git a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json index 1b9d03039c53..bc43ea855840 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json @@ -1,51 +1,15 @@ [ { - "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0xe" - }, - { - "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x10" + "UMask": "0x20" }, { "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", @@ -61,74 +25,61 @@ "UMask": "0x10" }, { - "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x20" - }, - { - "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0xe" }, { - "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "Speculative": "1", - "UMask": "0x10" + "UMask": "0x8" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", + "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Page walks completed due to a demand data load to a 4K page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x10" @@ -146,62 +97,74 @@ "UMask": "0x20" }, { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "CounterMask": "1", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x2" - }, - { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0x4" - }, - { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "Speculative": "1", - "UMask": "0xe" - }, - { - "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_PENDING", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x10" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "CounterMask": "1", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_ACTIVE", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0xe" + }, + { + "BriefDescription": "Page walks completed due to a demand data store to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Page walks completed due to a demand data store to a 4K page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.", "SampleAfterValue": "100003", "Speculative": "1", "UMask": "0x10" @@ -218,6 +181,67 @@ "Speculative": "1", "UMask": "0x20" }, + { + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0xe" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_PENDING", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x10" + }, { "BriefDescription": "DTLB flush attempts of the thread-specific entries", "CollectPEBSRecord": "2", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json index 5f6cb2abc384..62e9705daa19 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json @@ -1,1102 +1,1102 @@ [ { - "PublicDescription": "Demand Data Read requests that hit L2 cache.", - "EventCode": "0x24", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RFO requests that hit L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 store RFO requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.ALL_RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of instruction fetches that hit the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of instruction fetches that missed the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 code requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PF_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 HW prefetcher requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RFOs that miss cache lines.", - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_STORE_LOCK_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that miss cache lines", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RFOs that hit cache lines in M state.", - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in M state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RFOs that access cache lines in any state.", - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_STORE_LOCK_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that access cache lines in any state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Not rejected writebacks that missed LLC.", - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_L1D_WB_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_L1D_WB_RQSTS.HIT_E", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_L1D_WB_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_L1D_WB_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests missed LLC", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "Counts the number of lines brought into the L1 data cache.", "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles", - "CounterHTOff": "2" + "UMask": "0x1" }, { + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "L1D miss oustandings duration in cycles", "Counter": "2", - "UMask": "0x1", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CounterMask": "1", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "CounterHTOff": "2" - }, - { - "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", "EventCode": "0x48", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.FB_FULL", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of lines brought into the L1 data cache.", - "EventCode": "0x51", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles in which the L1D is locked.", - "EventCode": "0x63", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Demand data read requests sent to uncore.", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Demand code read requests sent to uncore.", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data sources.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data sources.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops with L2 cache misses as data sources.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", - "SampleAfterValue": "100007", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).", - "EventCode": "0xD3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Demand Data Read requests that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf" }, { - "PublicDescription": "RFO requests that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "L2 cache accesses when fetching instructions.", - "EventCode": "0xF0", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", - "EventCode": "0xF0", + "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "PublicDescription": "Not rejected writebacks that missed LLC.", "SampleAfterValue": "200003", - "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "L1D writebacks that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 fill requests that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 writebacks that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Transactions accessing L2 pipe.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 cache lines in I state filling L2.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 cache lines in S state filling L2.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 cache lines in E state filling L2.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 cache lines filling L2.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", - "SampleAfterValue": "100003", "BriefDescription": "L2 cache lines filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "L2 cache lines filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "PublicDescription": "Clean L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "L2 cache lines in E state filling L2.", "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "L2 cache lines in I state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "L2 cache lines in S state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { "BriefDescription": "Clean L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Dirty L2 cache lines evicted by demand.", - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", - "SampleAfterValue": "100003", "BriefDescription": "Dirty L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_OUT.PF_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_LINES_OUT.PF_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Dirty L2 cache lines filling the L2.", - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "L2_LINES_OUT.DIRTY_ALL", - "SampleAfterValue": "100003", "BriefDescription": "Dirty L2 cache lines filling the L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF4", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "PublicDescription": "Dirty L2 cache lines filling the L2.", "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0244", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts all L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0x30" + }, + { + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "SampleAfterValue": "200003", + "UMask": "0xc0" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts all L2 store RFO requests.", + "SampleAfterValue": "200003", + "UMask": "0xc" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Number of instruction fetches that hit the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Number of instruction fetches that missed the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Demand Data Read requests that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "RFO requests that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "RFOs that access cache lines in any state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "PublicDescription": "RFOs that access cache lines in any state.", + "SampleAfterValue": "200003", + "UMask": "0xf" + }, + { + "BriefDescription": "RFOs that hit cache lines in M state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "PublicDescription": "RFOs that hit cache lines in M state.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "RFOs that miss cache lines", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "PublicDescription": "RFOs that miss cache lines.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "Transactions accessing L2 pipe.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "Demand Data Read requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "RFO requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D is locked.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core-originated cacheable demand requests missed LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", + "SampleAfterValue": "100003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops with L2 cache misses as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "SampleAfterValue": "50021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "PEBS": "1", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x20" + }, + { + "BriefDescription": "All retired load uops. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x81" + }, + { + "BriefDescription": "All retired store uops. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x82" + }, + { + "BriefDescription": "Retired load uops with locked access. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cacheable and noncachaeble code read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Demand code read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0244", + "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0091", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all writebacks from the core to the LLC", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x18000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10400", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts non-temporal stores", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand rfo's", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000105B3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000105B3", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010122", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch prefetch RFOs", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000107F7", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0091", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0091", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0091", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000107F7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch prefetch RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all writebacks from the core to the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10008", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data reads that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand rfo's", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts non-temporal stores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json index 950b62c0908e..db8b1c4fceb0 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json @@ -1,151 +1,169 @@ [ { - "PublicDescription": "Counts number of X87 uops executed.", - "EventCode": "0x10", + "BriefDescription": "Cycles with any input/output SSE or FP assist", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_COMP_OPS_EXE.X87", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.", - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.", - "EventCode": "0x11", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_FP_256.PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.", - "EventCode": "0x11", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SIMD_FP_256.PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of assists associated with 256-bit AVX store operations.", - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OTHER_ASSISTS.AVX_STORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", "SampleAfterValue": "100003", - "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1e" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SIMD FP assists due to input values", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "Number of SIMD FP assists due to input values.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SIMD FP assists due to Output values", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output values.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "Number of X87 FP assists due to input values.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output values.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.X87", + "PublicDescription": "Counts number of X87 uops executed.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "PublicDescription": "Number of assists associated with 256-bit AVX store operations.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Number of X87 FP assists due to output values.", - "EventCode": "0xCA", + "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to output value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Number of X87 FP assists due to input values.", - "EventCode": "0xCA", + "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.X87_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to input value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SIMD FP assists due to output values.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to Output values", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SIMD FP assists due to input values.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to input values", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with any input/output SSE* or FP assists.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles with any input/output SSE or FP assist", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json index efaa949ead31..c956a0a51312 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json @@ -1,305 +1,315 @@ [ { - "PublicDescription": "Counts cycles the IDQ is empty.", - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of front end re-steers due to BPU misprediction.", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "PublicDescription": "Number of DSB to MITE switches.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "Cycles DSB to MITE switches caused delay.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "PublicDescription": "DSB Fill encountered > 3 DSB lines.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of uops delivered to IDQ from any path.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x3c", - "EventName": "IDQ.MITE_ALL_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "2000003", "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFETCH_STALL", + "EventName": "ICACHE.HIT", + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", - "EventCode": "0x9C", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFETCH_STALL", + "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0x9C", + "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "Counts cycles the IDQ is empty.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "Number of uops delivered to IDQ from any path.", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of DSB to MITE switches.", - "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DSB2MITE_SWITCHES.COUNT", - "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles DSB to MITE switches caused delay.", - "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "DSB Fill encountered > 3 DSB lines.", - "EventCode": "0xAC", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DSB_FILL.EXCEED_DSB_LINES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json index 28e25447d3ef..87670226f52d 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json @@ -1,184 +1,144 @@ [ { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", - "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Instructions per Store (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -188,87 +148,138 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "1 / ( ((FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD) + ((FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Memory_Bound;Memory_BW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, - { - "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI_All" - }, - { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2HPKI_All" - }, { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -279,22 +290,46 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, + { + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json index a74d54f56192..5f98f7746cf7 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json @@ -1,236 +1,236 @@ [ { - "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", - "EventCode": "0x05", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xBE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "PAGE_WALKS.LLC_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Number of any page walk that had a miss in LLC.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 4.", - "EventCode": "0xCD", - "MSRValue": "0x4", + "BriefDescription": "Loads with latency value being above 128", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100003", - "BriefDescription": "Loads with latency value being above 4", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 8.", + "CounterHTOff": "3", "EventCode": "0xCD", - "MSRValue": "0x8", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Loads with latency value being above 8", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 16.", - "EventCode": "0xCD", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Loads with latency value being above 16", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 32.", - "EventCode": "0xCD", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100007", - "BriefDescription": "Loads with latency value being above 32", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 64.", - "EventCode": "0xCD", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Loads with latency value being above 64", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 128.", - "EventCode": "0xCD", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x1", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 128.", "SampleAfterValue": "1009", - "BriefDescription": "Loads with latency value being above 128", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 256.", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Loads with latency value being above 16", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 16.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 256", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 256.", "SampleAfterValue": "503", - "BriefDescription": "Loads with latency value being above 256", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 512.", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Loads with latency value being above 32", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 32.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 4", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 4.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 512", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Loads with latency value being above 512", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { + "MSRValue": "0x200", "PEBS": "2", - "EventCode": "0xCD", - "Counter": "3", - "UMask": "0x2", - "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", - "PRECISE_STORE": "1", + "PublicDescription": "Loads with latency value being above 512.", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400244", + "BriefDescription": "Loads with latency value being above 64", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 64.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 8", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 8.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", + "PEBS": "2", + "PRECISE_STORE": "1", + "SampleAfterValue": "2000003", + "TakenAlone": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400091", + "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3004003f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3004003f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400004", + "BriefDescription": "Counts LLC replacements", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6004001b3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6004001b3", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts LLC replacements", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of any page walk that had a miss in LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBE", + "EventName": "PAGE_WALKS.LLC_MISS", + "SampleAfterValue": "100003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/other.json b/tools/perf/pmu-events/arch/x86/ivybridge/other.json index 4eb83ee40412..83fe8f79adc6 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/other.json @@ -1,44 +1,44 @@ [ { - "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", - "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPL_CYCLES.RING0", - "SampleAfterValue": "2000003", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", - "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "CPL_CYCLES.RING0_TRANS", - "SampleAfterValue": "100007", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "EdgeDetect": "1", "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPL_CYCLES.RING123", - "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventName": "CPL_CYCLES.RING0_TRANS", + "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", - "EventCode": "0x63", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json index 2a0aad91d83d..2de31c56c2a5 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json @@ -1,1305 +1,1272 @@ [ { - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "False dependencies in MOB due to partial compare on address.", - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial compare on address", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EdgeDetect": "1", - "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of flags-merge uops being allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.", - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when divider is busy executing divide operations", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Divide operations executed.", - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EdgeDetect": "1", - "EventName": "ARITH.FPU_DIV", - "SampleAfterValue": "100003", "BriefDescription": "Divide operations executed", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", - "EventCode": "0x4C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", - "EventCode": "0x4C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles the RS is empty for the thread.", - "EventCode": "0x5E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", - "SampleAfterValue": "200003", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV", + "PublicDescription": "Divide operations executed.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Cycles when divider is busy executing divide operations", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.", "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Stall cycles due to IQ is full.", - "EventCode": "0x87", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Not taken macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "PublicDescription": "Taken speculative and retired macro-conditional branches.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired direct near calls.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired indirect calls.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative and retired macro-conditional branches.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", "BriefDescription": "Speculative and retired macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "Speculative and retired macro-conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.", - "EventCode": "0x88", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc2" }, { - "EventCode": "0x88", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "UMask": "0xc8", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "Speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0xd0" + }, + { + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Speculative and retired indirect return branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc8" }, { - "PublicDescription": "Speculative and retired direct near calls.", + "BriefDescription": "Not taken macro-conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "Not taken macro-conditional branches.", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "BriefDescription": "Taken speculative and retired macro-conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "Taken speculative and retired macro-conditional branches.", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x82" }, { - "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired direct near calls", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired direct near calls.", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x90" }, { - "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired indirect calls.", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa0" }, { - "PublicDescription": "Taken speculative and retired mispredicted indirect calls.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "PublicDescription": "Speculative and retired mispredicted macro conditional branches.", - "EventCode": "0x89", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Branch instructions at retirement.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "Number of far branches retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Direct and indirect near call instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { "BriefDescription": "Speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Mispredicted indirect branches excluding calls and returns.", - "EventCode": "0x89", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xff", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { "BriefDescription": "Speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "Speculative and retired mispredicted macro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 0.", - "EventCode": "0xA1", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect calls", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired mispredicted indirect calls.", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" + }, + { + "BriefDescription": "All mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Mispredicted branch instructions at retirement.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "Mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles per core when uops are dispatched to port 0.", - "EventCode": "0xA1", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 1.", - "EventCode": "0xA1", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles per core when uops are dispatched to port 1.", - "EventCode": "0xA1", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 2.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "BriefDescription": "Core cycles when the thread is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0xc", "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 3.", - "EventCode": "0xA1", + "BriefDescription": "Thread cycles when thread is not in halt state", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x30", "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a Uop is dispatched on port 4.", - "EventCode": "0xA1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Cycles per core when uops are dispatched to port 4.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a Uop is dispatched on port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles per core when uops are dispatched to port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L2 cache miss loads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L2 cache miss load* is outstanding.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending memory loads.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Total execution stalls.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "SampleAfterValue": "2000003", - "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "SampleAfterValue": "2000003", - "BriefDescription": "Total execution stalls.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of loads missed L2.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L2 cache misses.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to memory subsystem.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.", - "EventCode": "0xA3", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L1 cache miss loads.", + "CounterHTOff": "2", "CounterMask": "8", - "CounterHTOff": "2" - }, - { "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "8", - "CounterHTOff": "2" - }, - { - "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L1 data cache misses", - "CounterMask": "12", - "CounterHTOff": "2" + "UMask": "0x8" }, { + "BriefDescription": "Cycles while L2 cache miss load* is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with pending memory loads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Total execution stalls.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "Counter": "2", - "UMask": "0xc", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "12", - "CounterHTOff": "2" + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", + "SampleAfterValue": "2000003", + "UMask": "0xc" }, { - "EventCode": "0xA8", + "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "EventCode": "0xA8", + "BriefDescription": "Execution stalls due to L2 cache misses.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Number of loads missed L2.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "EventCode": "0xA8", + "BriefDescription": "Execution stalls due to memory subsystem.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder", + "UMask": "0x6" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", - "EventCode": "0xB1", + "BriefDescription": "Stall cycles because IQ is full", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.THREAD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000003", - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 1 uop was executed per-thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 2 uops were executed per-thread", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 3 uops were executed per-thread", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 4 uops were executed per-thread", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of uops executed on the core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of instructions at retirement.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "EventName": "INST_RETIRED.PREC_DIST", "SampleAfterValue": "2000003", - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired uops.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 10 actually retired uops.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3" }, { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xC3", + "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare on address", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "False dependencies in MOB due to partial compare on address.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.COUNT", "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of self-modifying-code machine clears detected.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Branch instructions at retirement.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of not taken branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Not taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of far branches retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100007", - "BriefDescription": "Far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Mispredicted branch instructions at retirement.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Count cases of saving new LBR records by hardware.", - "EventCode": "0xCC", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of front end re-steers due to BPU misprediction.", - "EventCode": "0xE6", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "Number of self-modifying-code machine clears detected.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Count cases of saving new LBR records by hardware.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "Cycles the RS is empty for the thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "Cycles which a Uop is dispatched on port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "Cycles which a Uop is dispatched on port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "Cycles which a Uop is dispatched on port 2.", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "AnyThread": "1", + "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "Cycles which a Uop is dispatched on port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "Cycles which a Uop is dispatched on port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "Cycles which a Uop is dispatched on port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of flags-merge uops being allocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json new file mode 100644 index 000000000000..6b0639944d78 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json @@ -0,0 +1,252 @@ +[ + { + "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", + "UMask": "0x86", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", + "UMask": "0x8f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", + "UMask": "0x46", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", + "UMask": "0x4f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", + "UMask": "0x16", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", + "UMask": "0x18", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.", + "UMask": "0x11", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", + "UMask": "0x1f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.", + "UMask": "0x26", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.", + "UMask": "0x2f", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a modified line in some processor core.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", + "UMask": "0x84", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a non-modified line in some processor core.", + "UMask": "0x24", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop misses in some processor core.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", + "UMask": "0x41", + "Unit": "CBO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json new file mode 100644 index 000000000000..6278068908cf --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json @@ -0,0 +1,91 @@ +[ + { + "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", + "EventCode": "0x83", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of requests allocated in Coherency Tracker.", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Number of requests allocated in Coherency Tracker.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "Counter": "0,1", + "CounterMask": "10", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", + "PerPkg": "1", + "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "Counter": "0,1", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of LLC evictions allocated.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", + "PerPkg": "1", + "PublicDescription": "Counts the number of LLC evictions allocated.", + "UMask": "0x80", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "Counter": "Fixed", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "UMask": "0x01", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore.json deleted file mode 100644 index 42c70eed05a2..000000000000 --- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore.json +++ /dev/null @@ -1,314 +0,0 @@ -[ - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x01", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS", - "BriefDescription": "A snoop misses in some processor core.", - "PublicDescription": "A snoop misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x02", - "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL", - "BriefDescription": "A snoop invalidates a non-modified line in some processor core.", - "PublicDescription": "A snoop invalidates a non-modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x04", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT", - "BriefDescription": "A snoop hits a non-modified line in some processor core.", - "PublicDescription": "A snoop hits a non-modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x08", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM", - "BriefDescription": "A snoop hits a modified line in some processor core.", - "PublicDescription": "A snoop hits a modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x10", - "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M", - "BriefDescription": "A snoop invalidates a modified line in some processor core.", - "PublicDescription": "A snoop invalidates a modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x20", - "EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x40", - "EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x80", - "EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x01", - "EventName": "UNC_CBO_CACHE_LOOKUP.M", - "BriefDescription": "LLC lookup request that access cache and found line in M-state.", - "PublicDescription": "LLC lookup request that access cache and found line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x02", - "EventName": "UNC_CBO_CACHE_LOOKUP.E", - "BriefDescription": "LLC lookup request that access cache and found line in E-state.", - "PublicDescription": "LLC lookup request that access cache and found line in E-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x04", - "EventName": "UNC_CBO_CACHE_LOOKUP.S", - "BriefDescription": "LLC lookup request that access cache and found line in S-state.", - "PublicDescription": "LLC lookup request that access cache and found line in S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x08", - "EventName": "UNC_CBO_CACHE_LOOKUP.I", - "BriefDescription": "LLC lookup request that access cache and found line in I-state.", - "PublicDescription": "LLC lookup request that access cache and found line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x10", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER", - "BriefDescription": "Filter on processor core initiated cacheable read requests.", - "PublicDescription": "Filter on processor core initiated cacheable read requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x20", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", - "BriefDescription": "Filter on processor core initiated cacheable write requests.", - "PublicDescription": "Filter on processor core initiated cacheable write requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x40", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", - "BriefDescription": "Filter on external snoop requests.", - "PublicDescription": "Filter on external snoop requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x80", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", - "BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.", - "PublicDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x20", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", - "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x80", - "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", - "BriefDescription": "Counts the number of LLC evictions allocated.", - "PublicDescription": "Counts the number of LLC evictions allocated.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x83", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", - "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", - "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x84", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "BriefDescription": "Number of requests allocated in Coherency Tracker.", - "PublicDescription": "Number of requests allocated in Coherency Tracker.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "Counter": "0,1", - "CounterMask": "1", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", - "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "Counter": "0,1", - "CounterMask": "10", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x0", - "UMask": "0x01", - "EventName": "UNC_CLOCK.SOCKET", - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", - "Counter": "Fixed", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x06", - "EventName": "UNC_CBO_CACHE_LOOKUP.ES", - "BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.", - "PublicDescription": "LLC lookup request that access cache and found line in E-state or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json index f243551b4d12..8cf1549797b0 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json @@ -1,180 +1,180 @@ [ { - "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", - "EventCode": "0x08", + "BriefDescription": "Page walk for a large page completed for Demand load.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x88", "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Page walk for a large page completed for Demand load.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5F", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles PMH is busy with this walk.", - "EventCode": "0x49", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", + "SampleAfterValue": "100003", + "UMask": "0x82" + }, + { + "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x4F", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "Cycles PMH is busy with this walk.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", - "EventCode": "0x5F", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Misses in all ITLB levels that cause page walks.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Misses in all ITLB levels that cause completed page walks.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycle PMH is busy with a walk.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of cache load STLB hits. No page walk.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "ITLB_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", - "EventCode": "0xAE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "DTLB flush attempts of the thread-specific entries.", - "EventCode": "0xBD", + "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TLB_FLUSH.DTLB_THREAD", - "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", + "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all ITLB levels that cause page walks.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "Number of cache load STLB hits. No page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Misses in all ITLB levels that cause completed page walks.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "Cycle PMH is busy with a walk.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { "BriefDescription": "DTLB flush attempts of the thread-specific entries", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "DTLB flush attempts of the thread-specific entries.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "Count number of STLB flush attempts.", - "EventCode": "0xBD", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TLB_FLUSH.STLB_ANY", - "SampleAfterValue": "100007", "BriefDescription": "STLB flush attempts", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "Count number of STLB flush attempts.", + "SampleAfterValue": "100007", + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/cache.json b/tools/perf/pmu-events/arch/x86/ivytown/cache.json index 6dad3ad6b102..9bbf2bc59859 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/cache.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/cache.json @@ -1,1260 +1,1260 @@ [ { - "PublicDescription": "Demand Data Read requests that hit L2 cache.", - "EventCode": "0x24", + "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RFO requests that hit L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 store RFO requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.ALL_RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of instruction fetches that hit the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of instruction fetches that missed the L2 cache.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 code requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PF_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all L2 HW prefetcher requests.", - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RFOs that miss cache lines.", - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_STORE_LOCK_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that miss cache lines", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RFOs that hit cache lines in M state.", - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in M state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "RFOs that access cache lines in any state.", - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_STORE_LOCK_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that access cache lines in any state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Not rejected writebacks that missed LLC.", - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_L1D_WB_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_L1D_WB_RQSTS.HIT_E", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_L1D_WB_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_L1D_WB_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests missed LLC", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "Counts the number of lines brought into the L1 data cache.", "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles", - "CounterHTOff": "2" + "UMask": "0x1" }, { + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "L1D miss oustandings duration in cycles", "Counter": "2", - "UMask": "0x1", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CounterMask": "1", - "CounterHTOff": "2" + "UMask": "0x1" }, { - "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "CounterHTOff": "2" - }, - { - "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", "EventCode": "0x48", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.FB_FULL", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of lines brought into the L1 data cache.", - "EventCode": "0x51", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.ALL", + "SampleAfterValue": "200003", + "UMask": "0xf" }, { - "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", + "SampleAfterValue": "200003", + "UMask": "0x4" }, { - "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "EventCode": "0x60", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "EventCode": "0x60", + "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "PublicDescription": "Not rejected writebacks that missed LLC.", + "SampleAfterValue": "200003", + "UMask": "0x1" }, { - "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "L2 cache lines filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x7" }, { - "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", - "EventCode": "0x60", + "BriefDescription": "L2 cache lines in E state filling L2", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", + "PublicDescription": "L2 cache lines in E state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "L2 cache lines in I state filling L2", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", + "PublicDescription": "L2 cache lines in I state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", - "EventCode": "0x60", + "BriefDescription": "L2 cache lines in S state filling L2", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "PublicDescription": "L2 cache lines in S state filling L2.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", - "EventCode": "0x60", + "BriefDescription": "Clean L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x1" }, { - "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "EventCode": "0x60", + "BriefDescription": "Dirty L2 cache lines evicted by demand", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by demand.", + "SampleAfterValue": "100003", + "UMask": "0x2" }, { - "PublicDescription": "Cycles in which the L1D is locked.", - "EventCode": "0x63", + "BriefDescription": "Dirty L2 cache lines filling the L2", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DIRTY_ALL", + "PublicDescription": "Dirty L2 cache lines filling the L2.", + "SampleAfterValue": "100003", + "UMask": "0xa" + }, + { + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_CLEAN", + "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts all L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0x30" + }, + { + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts all L2 HW prefetcher requests.", + "SampleAfterValue": "200003", + "UMask": "0xc0" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts all L2 store RFO requests.", + "SampleAfterValue": "200003", + "UMask": "0xc" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Number of instruction fetches that hit the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Number of instruction fetches that missed the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Demand Data Read requests that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "RFO requests that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "RFOs that access cache lines in any state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "PublicDescription": "RFOs that access cache lines in any state.", + "SampleAfterValue": "200003", + "UMask": "0xf" + }, + { + "BriefDescription": "RFOs that hit cache lines in M state", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "PublicDescription": "RFOs that hit cache lines in M state.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "RFOs that miss cache lines", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "PublicDescription": "RFOs that miss cache lines.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "PublicDescription": "Transactions accessing L2 pipe.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "PublicDescription": "L2 cache accesses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand Data Read requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "PublicDescription": "Demand Data Read requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "PublicDescription": "L1D writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "PublicDescription": "L2 fill requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "PublicDescription": "RFO requests that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when L1D is locked", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Demand data read requests sent to uncore.", - "EventCode": "0xB0", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Demand code read requests sent to uncore.", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D is locked.", "SampleAfterValue": "2000003", - "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Core-originated cacheable demand requests missed LLC", "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4f" }, { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops. (Precise Event)", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data sources.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data sources.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops with L2 cache misses as data sources.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", - "SampleAfterValue": "100007", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD2", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "EventCode": "0xD3", + "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3" }, { - "EventCode": "0xD3", + "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", "Counter": "0,1,2,3", - "UMask": "0xc", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", - "CounterHTOff": "0,1,2,3" + "UMask": "0xc" }, { - "EventCode": "0xD3", + "BriefDescription": "Data forwarded from remote cache.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", - "SampleAfterValue": "100007", - "BriefDescription": "Remote cache HITM.", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xD3", - "Counter": "0,1,2,3", - "UMask": "0x20", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", "SampleAfterValue": "100007", - "BriefDescription": "Data forwarded from remote cache.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x20" }, { - "PublicDescription": "Demand Data Read requests that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Remote cache HITM.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", + "SampleAfterValue": "100007", + "UMask": "0x10" }, { - "PublicDescription": "RFO requests that access L2 cache.", - "EventCode": "0xF0", + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 cache accesses when fetching instructions.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L1D writebacks that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 fill requests that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 writebacks that access L2 cache.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Transactions accessing L2 pipe.", - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "L2 cache lines in I state filling L2.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "PublicDescription": "L2 cache lines in S state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "L2 cache lines in E state filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "L2 cache lines filling L2.", - "EventCode": "0xF1", + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Clean L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "Retired load uops with L2 cache misses as data sources.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "SampleAfterValue": "50021", + "UMask": "0x10" }, { - "PublicDescription": "Dirty L2 cache lines evicted by demand.", - "EventCode": "0xF2", + "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by demand", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "PEBS": "1", + "SampleAfterValue": "50021", + "UMask": "0x4" }, { - "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", - "EventCode": "0xF2", + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_OUT.PF_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x20" }, { - "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", - "EventCode": "0xF2", + "BriefDescription": "All retired load uops. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_LINES_OUT.PF_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "PublicDescription": "Dirty L2 cache lines filling the L2.", - "EventCode": "0xF2", + "BriefDescription": "All retired store uops. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "L2_LINES_OUT.DIRTY_ALL", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines filling the L2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "EventCode": "0xF4", + "BriefDescription": "Retired load uops with locked access. (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x21" }, { + "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cacheable and noncachaeble code read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Demand code read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Demand data read requests sent to uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0091", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0091", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0090", + "BriefDescription": "Counts all prefetch data reads that hit the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0090", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0090", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0090", + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c03f7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c03f7", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c03f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c03f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10008", + "BriefDescription": "Counts all writebacks from the core to the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10008", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all writebacks from the core to the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0004", + "BriefDescription": "Counts all demand code reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0001", + "BriefDescription": "Counts all demand data reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0001", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0001", + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0002", + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803c8000", + "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803c8000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x23ffc08000", + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x23ffc08000", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0040", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0010", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0200", + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0080", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0080", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10400", + "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10800", + "BriefDescription": "Counts non-temporal stores", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts non-temporal stores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json index 950b62c0908e..db8b1c4fceb0 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json @@ -1,151 +1,169 @@ [ { - "PublicDescription": "Counts number of X87 uops executed.", - "EventCode": "0x10", + "BriefDescription": "Cycles with any input/output SSE or FP assist", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_COMP_OPS_EXE.X87", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.", - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.", - "EventCode": "0x11", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_FP_256.PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.", - "EventCode": "0x11", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SIMD_FP_256.PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of assists associated with 256-bit AVX store operations.", - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OTHER_ASSISTS.AVX_STORE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.ANY", + "PublicDescription": "Cycles with any input/output SSE* or FP assists.", "SampleAfterValue": "100003", - "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1e" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of SIMD FP assists due to input values", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "PublicDescription": "Number of SIMD FP assists due to input values.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SIMD FP assists due to Output values", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "PublicDescription": "Number of SIMD FP assists due to output values.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "PublicDescription": "Number of X87 FP assists due to input values.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "PublicDescription": "Number of X87 FP assists due to output values.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "PublicDescription": "Counts number of SSE* or AVX-128 double precision FP scalar uops executed.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "PublicDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.X87", + "PublicDescription": "Counts number of X87 uops executed.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "PublicDescription": "Number of assists associated with 256-bit AVX store operations.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "PublicDescription": "Number of X87 FP assists due to output values.", - "EventCode": "0xCA", + "BriefDescription": "number of AVX-256 Computational FP double precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to output value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "PublicDescription": "Counts 256-bit packed double-precision floating-point instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { - "PublicDescription": "Number of X87 FP assists due to input values.", - "EventCode": "0xCA", + "BriefDescription": "number of GSSE-256 Computational FP single precision uops issued this cycle", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.X87_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to input value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SIMD FP assists due to output values.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to Output values", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of SIMD FP assists due to input values.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to input values", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with any input/output SSE* or FP assists.", - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x1e", - "EventName": "FP_ASSIST.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles with any input/output SSE or FP assist", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "PublicDescription": "Counts 256-bit packed single-precision floating-point instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json index efaa949ead31..c956a0a51312 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json @@ -1,305 +1,315 @@ [ { - "PublicDescription": "Counts cycles the IDQ is empty.", - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of front end re-steers due to BPU misprediction.", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "PublicDescription": "Number of DSB to MITE switches.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "Cycles DSB to MITE switches caused delay.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "PublicDescription": "DSB Fill encountered > 3 DSB lines.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of uops delivered to IDQ from any path.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x3c", - "EventName": "IDQ.MITE_ALL_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "2000003", "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ICACHE.IFETCH_STALL", + "EventName": "ICACHE.HIT", + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", - "EventCode": "0x9C", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.IFETCH_STALL", + "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0x9C", + "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "PublicDescription": "Counts cycles the IDQ is empty.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "PublicDescription": "Number of uops delivered to IDQ from any path.", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0x9C", + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of DSB to MITE switches.", - "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DSB2MITE_SWITCHES.COUNT", - "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles DSB to MITE switches caused delay.", - "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "DSB Fill encountered > 3 DSB lines.", - "EventCode": "0xAC", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DSB_FILL.EXCEED_DSB_LINES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json index db23db2e98be..8d0ddcbd6c7c 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json @@ -1,184 +1,144 @@ [ { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" - }, - { - "BriefDescription": "Branch instructions per taken branch. ", - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", - "MetricName": "BpTB" - }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", - "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Instructions per Load (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricGroup": "Instruction_Type", - "MetricName": "IpL" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Instructions per Store (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricGroup": "Instruction_Type", - "MetricName": "IpS" - }, - { - "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;Instruction_Type", - "MetricName": "IpB" - }, - { - "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", - "MetricName": "IpCall" - }, - { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" - }, - { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -188,87 +148,138 @@ "MetricName": "CORE_CLKS" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "IpLoad" + }, + { + "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "IpStore" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "IpBranch" + }, + { + "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { + "BriefDescription": "Branch instructions per taken branch. ", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "BpTkBranch" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "1 / ( ((FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE) / UOPS_EXECUTED.THREAD) + ((FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE) / UOPS_EXECUTED.THREAD) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "Memory_Bound;Memory_BW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, - { - "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2MPKI_All" - }, - { - "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", - "MetricName": "L2HPKI_All" - }, { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.LLC_MISS / INST_RETIRED.ANY", - "MetricGroup": "Cache_Misses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -279,28 +290,40 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Socket actual clocks when any core is active on that socket", "MetricExpr": "cbox_0@event\\=0x0@", - "MetricGroup": "", + "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/memory.json b/tools/perf/pmu-events/arch/x86/ivytown/memory.json index 3a7b86af8816..f904140203fe 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/memory.json @@ -1,503 +1,503 @@ [ { - "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", - "EventCode": "0x05", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "100003", - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 4.", - "EventCode": "0xCD", - "MSRValue": "0x4", + "BriefDescription": "Loads with latency value being above 128", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100003", - "BriefDescription": "Loads with latency value being above 4", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 8.", + "CounterHTOff": "3", "EventCode": "0xCD", - "MSRValue": "0x8", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Loads with latency value being above 8", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 16.", - "EventCode": "0xCD", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Loads with latency value being above 16", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 32.", - "EventCode": "0xCD", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100007", - "BriefDescription": "Loads with latency value being above 32", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 64.", - "EventCode": "0xCD", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Loads with latency value being above 64", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 128.", - "EventCode": "0xCD", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x1", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 128.", "SampleAfterValue": "1009", - "BriefDescription": "Loads with latency value being above 128", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 256.", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Loads with latency value being above 16", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 16.", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 256", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 256.", "SampleAfterValue": "503", - "BriefDescription": "Loads with latency value being above 256", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "PublicDescription": "Loads with latency value being above 512.", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Loads with latency value being above 32", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 32.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 4", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 4.", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 512", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Loads with latency value being above 512", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { + "MSRValue": "0x200", "PEBS": "2", - "EventCode": "0xCD", - "Counter": "3", - "UMask": "0x2", - "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", - "PRECISE_STORE": "1", + "PublicDescription": "Loads with latency value being above 512.", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc00244", + "BriefDescription": "Loads with latency value being above 64", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 64.", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 8", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Loads with latency value being above 8.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", + "PEBS": "2", + "PRECISE_STORE": "1", + "SampleAfterValue": "2000003", + "TakenAlone": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc00244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800244", + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f800244", + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f800244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20091", + "BriefDescription": "Counts all demand & prefetch data reads that hits the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that hits the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc203f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc203f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6004003f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6004003f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f8203f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc003f7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc003f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20004", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f8203f7", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400004", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800004", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820004", + "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00001", + "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820004", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20001", + "BriefDescription": "Counts demand data reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400001", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800001", + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820001", + "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00001", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc20002", + "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820001", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc20002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20040", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820010", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20200", + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820010", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20080", + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/other.json b/tools/perf/pmu-events/arch/x86/ivytown/other.json index 4eb83ee40412..83fe8f79adc6 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/other.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/other.json @@ -1,44 +1,44 @@ [ { - "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", - "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPL_CYCLES.RING0", - "SampleAfterValue": "2000003", "BriefDescription": "Unhalted core cycles when the thread is in ring 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING0", + "PublicDescription": "Unhalted core cycles when the thread is in ring 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", - "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "CPL_CYCLES.RING0_TRANS", - "SampleAfterValue": "100007", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", + "EdgeDetect": "1", "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPL_CYCLES.RING123", - "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventName": "CPL_CYCLES.RING0_TRANS", + "PublicDescription": "Number of intervals between processor halts while thread is in ring 0.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", - "EventCode": "0x63", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", + "EventName": "CPL_CYCLES.RING123", + "PublicDescription": "Unhalted core cycles when the thread is not in ring 0.", "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", + "PublicDescription": "Cycles in which the L1D and L2 are locked, due to a UC lock or split lock.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json index 2a0aad91d83d..2de31c56c2a5 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json @@ -1,1305 +1,1272 @@ [ { - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "False dependencies in MOB due to partial compare on address.", - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial compare on address", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EdgeDetect": "1", - "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "UOPS_ISSUED.FLAGS_MERGE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of flags-merge uops being allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_ISSUED.SINGLE_MUL", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.", - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when divider is busy executing divide operations", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Divide operations executed.", - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EdgeDetect": "1", - "EventName": "ARITH.FPU_DIV", - "SampleAfterValue": "100003", "BriefDescription": "Divide operations executed", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", - "EventCode": "0x4C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", - "EventCode": "0x4C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x58", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", - "SampleAfterValue": "1000003", - "BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles the RS is empty for the thread.", - "EventCode": "0x5E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", - "SampleAfterValue": "200003", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV", + "PublicDescription": "Divide operations executed.", + "SampleAfterValue": "100003", + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Cycles when divider is busy executing divide operations", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "PublicDescription": "Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides.", "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Stall cycles due to IQ is full.", - "EventCode": "0x87", + "BriefDescription": "Speculative and retired branches", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Not taken macro-conditional branches.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "PublicDescription": "Taken speculative and retired macro-conditional branches.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired direct near calls.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Taken speculative and retired indirect calls.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative and retired macro-conditional branches.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", "BriefDescription": "Speculative and retired macro-conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "PublicDescription": "Speculative and retired macro-conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.", - "EventCode": "0x88", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "PublicDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc2" }, { - "EventCode": "0x88", + "BriefDescription": "Speculative and retired direct near calls", "Counter": "0,1,2,3", - "UMask": "0xc8", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "PublicDescription": "Speculative and retired direct near calls.", + "SampleAfterValue": "200003", + "UMask": "0xd0" + }, + { + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Speculative and retired indirect return branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xc8" }, { - "PublicDescription": "Speculative and retired direct near calls.", + "BriefDescription": "Not taken macro-conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "Not taken macro-conditional branches.", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x41" }, { - "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "BriefDescription": "Taken speculative and retired macro-conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "Taken speculative and retired macro-conditional branches.", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "PublicDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x82" }, { - "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired direct near calls", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired direct near calls.", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x90" }, { - "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired indirect calls", "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired indirect calls.", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa0" }, { - "PublicDescription": "Taken speculative and retired mispredicted indirect calls.", - "EventCode": "0x89", + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic", "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.", "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "PublicDescription": "Speculative and retired mispredicted macro conditional branches.", - "EventCode": "0x89", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Branch instructions at retirement.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PublicDescription": "Number of far branches retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Direct and indirect near call instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "Counts the number of not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { "BriefDescription": "Speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Mispredicted indirect branches excluding calls and returns.", - "EventCode": "0x89", "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts all near executed branches (not necessarily retired).", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xff", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "PublicDescription": "Counts all near executed branches (not necessarily retired).", "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { "BriefDescription": "Speculative and retired mispredicted macro conditional branches", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "PublicDescription": "Speculative and retired mispredicted macro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 0.", - "EventCode": "0xA1", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "PublicDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "PublicDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "PublicDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect calls", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "PublicDescription": "Taken speculative and retired mispredicted indirect calls.", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "PublicDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "SampleAfterValue": "200003", + "UMask": "0x88" + }, + { + "BriefDescription": "All mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Mispredicted branch instructions at retirement.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "Mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles per core when uops are dispatched to port 0.", - "EventCode": "0xA1", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "PublicDescription": "Increments at the frequency of XCLK (100 MHz) when not halted.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 0", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 1.", - "EventCode": "0xA1", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles per core when uops are dispatched to port 1.", - "EventCode": "0xA1", + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted. (counts at 100 MHz rate)", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 2.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "BriefDescription": "Core cycles when the thread is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0xc", "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "Cycles which a Uop is dispatched on port 3.", - "EventCode": "0xA1", + "BriefDescription": "Thread cycles when thread is not in halt state", "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PublicDescription": "Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x30", "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a Uop is dispatched on port 4.", - "EventCode": "0xA1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "SampleAfterValue": "2000003" }, { - "PublicDescription": "Cycles per core when uops are dispatched to port 4.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles which a Uop is dispatched on port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles per core when uops are dispatched to port 5.", - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 5", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).", - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L2 cache miss loads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L2 cache miss load* is outstanding.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending memory loads.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Total execution stalls.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", - "SampleAfterValue": "2000003", - "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "SampleAfterValue": "2000003", - "BriefDescription": "Total execution stalls.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of loads missed L2.", - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L2 cache misses.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to memory subsystem.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.", - "EventCode": "0xA3", + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", "Counter": "2", - "UMask": "0x8", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with pending L1 cache miss loads.", + "CounterHTOff": "2", "CounterMask": "8", - "CounterHTOff": "2" - }, - { "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x8", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "8", - "CounterHTOff": "2" - }, - { - "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", "EventCode": "0xA3", - "Counter": "2", - "UMask": "0xc", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "PublicDescription": "Cycles with pending L1 cache miss loads. Set AnyThread to count per core.", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls due to L1 data cache misses", - "CounterMask": "12", - "CounterHTOff": "2" + "UMask": "0x8" }, { + "BriefDescription": "Cycles while L2 cache miss load* is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with pending L2 cache miss loads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "PublicDescription": "Cycles with pending L2 miss loads. Set AnyThread to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with pending memory loads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", + "PublicDescription": "Cycles with pending memory loads. Set AnyThread to count per core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event increments by 1 for every cycle where there was no execute for this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", + "PublicDescription": "Total execution stalls.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", "Counter": "2", - "UMask": "0xc", + "CounterHTOff": "2", + "CounterMask": "12", + "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "12", - "CounterHTOff": "2" + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "PublicDescription": "Execution stalls due to L1 data cache miss loads. Set Cmask=0CH.", + "SampleAfterValue": "2000003", + "UMask": "0xc" }, { - "EventCode": "0xA8", + "BriefDescription": "Execution stalls while L2 cache miss load* is outstanding.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "EventCode": "0xA8", + "BriefDescription": "Execution stalls due to L2 cache misses.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "PublicDescription": "Number of loads missed L2.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "EventCode": "0xA8", + "BriefDescription": "Execution stalls due to memory subsystem.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder", + "UMask": "0x6" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", - "EventCode": "0xB1", + "BriefDescription": "Stall cycles because IQ is full", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.THREAD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "PublicDescription": "Stall cycles due to IQ is full.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xB1", - "Invert": "1", + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000003", - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 1 uop was executed per-thread", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 2 uops were executed per-thread", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 3 uops were executed per-thread", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles where at least 4 uops were executed per-thread", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of uops executed on the core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of instructions at retirement.", - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Number of instructions at retirement.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", "PublicDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution.", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "EventName": "INST_RETIRED.PREC_DIST", "SampleAfterValue": "2000003", - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "CounterHTOff": "1" + "UMask": "0x1" }, { - "EventCode": "0xC1", + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", - "SampleAfterValue": "100003", - "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired uops.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 10 actually retired uops.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" + "UMask": "0x3" }, { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3" }, { - "EventCode": "0xC3", + "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Loads blocked by overlapping with store buffer that cannot be forwarded.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare on address", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "False dependencies in MOB due to partial compare on address.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "PublicDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PublicDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.COUNT", "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "Number of self-modifying-code machine clears detected.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Branch instructions at retirement.", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of not taken branch instructions retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Not taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of far branches retired.", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100007", - "BriefDescription": "Far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Mispredicted branch instructions at retirement.", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "number of near branch instructions retired that were mispredicted and taken.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Count cases of saving new LBR records by hardware.", - "EventCode": "0xCC", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of front end re-steers due to BPU misprediction.", - "EventCode": "0xE6", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "Number of self-modifying-code machine clears detected.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of integer Move Elimination candidate uops that were not eliminated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x58", + "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times any microcode assist is invoked by HW upon uop writeback.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Cycles Allocation is stalled due to Resource Related reason.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "Cycles stalled due to no store buffers available (not including draining form sync).", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Count cases of saving new LBR records by hardware.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "Cycles the RS is empty for the thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "PublicDescription": "Cycles which a Uop is dispatched on port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 0", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to port 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "PublicDescription": "Cycles which a Uop is dispatched on port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to port 1.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "PublicDescription": "Cycles which a Uop is dispatched on port 2.", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "AnyThread": "1", + "BriefDescription": "Uops dispatched to port 2, loads and stores per core (speculative and retired).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "PublicDescription": "Cycles which a Uop is dispatched on port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "PublicDescription": "Cycles per core when load or STA uops are dispatched to port 3.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "PublicDescription": "Cycles which a Uop is dispatched on port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 4", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to port 4.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "PublicDescription": "Cycles which a Uop is dispatched on port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 5", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "PublicDescription": "Cycles per core when uops are dispatched to port 5.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts total number of uops to be executed per-core each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "PublicDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "PublicDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "PublicDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "PublicDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "PublicDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed per-thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", + "PublicDescription": "Cycles where at least 4 uops were executed per-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of flags-merge uops being allocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.FLAGS_MERGE", + "PublicDescription": "Number of flags-merge uops allocated. Such uops adds delay.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of Multiply packed/scalar single precision uops allocated", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SINGLE_MUL", + "PublicDescription": "Number of multiply packed/scalar single precision uops allocated.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "PublicDescription": "Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json index 4645e9d3f460..da6a3e09a782 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json @@ -1,198 +1,198 @@ [ { - "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", - "EventCode": "0x08", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x82", "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x82" }, { - "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", - "EventCode": "0x08", + "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x84", "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION", "SampleAfterValue": "2000003", - "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", - "EventCode": "0x08", + "BriefDescription": "Page walk for a large page completed for Demand load.", "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x88", "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Page walk for a large page completed for Demand load.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x88" }, { - "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand loads.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x81" }, { - "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5F", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "Cycles PMH is busy with this walk.", - "EventCode": "0x49", + "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by demand loads.", + "SampleAfterValue": "100003", + "UMask": "0x82" + }, + { + "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "Cycle PMH is busy with a walk due to demand loads.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x84" }, { - "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x4F", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PublicDescription": "Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G).", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "PublicDescription": "Cycles PMH is busy with this walk.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", - "EventCode": "0x5F", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Misses in all ITLB levels that cause page walks.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Misses in all ITLB levels that cause completed page walks.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Cycle PMH is busy with a walk.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of cache load STLB hits. No page walk.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "ITLB_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", - "EventCode": "0xAE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "DTLB flush attempts of the thread-specific entries.", - "EventCode": "0xBD", + "BriefDescription": "Completed page walks in ITLB due to STLB load misses for large pages", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TLB_FLUSH.DTLB_THREAD", - "SampleAfterValue": "100007", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", + "PublicDescription": "Completed page walks in ITLB due to STLB load misses for large pages.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Misses in all ITLB levels that cause page walks.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "Number of cache load STLB hits. No page walk.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Misses in all ITLB levels that cause completed page walks.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "Cycle PMH is busy with a walk.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { "BriefDescription": "DTLB flush attempts of the thread-specific entries", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "DTLB flush attempts of the thread-specific entries.", + "SampleAfterValue": "100007", + "UMask": "0x1" }, { - "PublicDescription": "Count number of STLB flush attempts.", - "EventCode": "0xBD", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TLB_FLUSH.STLB_ANY", - "SampleAfterValue": "100007", "BriefDescription": "STLB flush attempts", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "Count number of STLB flush attempts.", + "SampleAfterValue": "100007", + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/perf/pmu-events/arch/x86/jaketown/cache.json index 52dc6ef40e63..97c7e0ceed18 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json @@ -1,1290 +1,1266 @@ [ { - "PEBS": "1", - "EventCode": "0xD0", + "BriefDescription": "Allocated L1D data cache lines in M state.", "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheline boundary.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cacheline boundary.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts the number of load uops retired", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts the number of store uops retired.", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data sources.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data sources.", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", - "SampleAfterValue": "100007", - "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "100007", - "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xD3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", - "SampleAfterValue": "100007", - "BriefDescription": "Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x51", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x51", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L1D.ALLOCATED_IN_M", "SampleAfterValue": "2000003", - "BriefDescription": "Allocated L1D data cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L1D.EVICTION", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data cache lines in M state evicted due to replacement.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x51", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "L1D.ALL_M_REPLACEMENT", "SampleAfterValue": "2000003", - "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", + "BriefDescription": "L1D data cache lines in M state evicted due to replacement.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.EVICTION", "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles.", - "CounterHTOff": "2" + "UMask": "0x4" }, { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "BriefDescription": "L1D data line replacements.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "2" - }, - { - "EventCode": "0x63", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PF_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_STORE_LOCK_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that miss cache lines.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in E state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_STORE_LOCK_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that access cache lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_L1D_WB_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_L1D_WB_RQSTS.HIT_S", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_L1D_WB_RQSTS.HIT_E", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_L1D_WB_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_L1D_WB_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_IN.E", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", - "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_OUT.DEMAND_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_OUT.DEMAND_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_OUT.PF_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_LINES_OUT.PF_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "L2_LINES_OUT.DIRTY_ALL", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines filling the L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests missed LLC.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.ALL_RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EventCode": "0xBF", - "Counter": "0,1,2,3", - "UMask": "0x5", "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", "SampleAfterValue": "100003", - "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x5" }, { - "EventCode": "0x60", + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L1D_PEND_MISS.FB_FULL", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "UMask": "0x2" + }, + { + "BriefDescription": "L1D miss oustandings duration in cycles.", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0091", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.ALL", + "SampleAfterValue": "200003", + "UMask": "0xf" + }, + { + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_S", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines filling L2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x7" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0091", + "BriefDescription": "L2 cache lines in E state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.E", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0091", + "BriefDescription": "L2 cache lines in I state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.I", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0091", + "BriefDescription": "L2 cache lines in S state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0090", + "BriefDescription": "Clean L2 cache lines evicted by demand.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0090", + "BriefDescription": "Dirty L2 cache lines evicted by demand.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0090", + "BriefDescription": "Dirty L2 cache lines filling the L2.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.DIRTY_ALL", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0xa" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0090", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_CLEAN", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0090", + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_DIRTY", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c03f7", + "BriefDescription": "L2 code requests.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "UMask": "0x30" + }, + { + "BriefDescription": "Demand Data Read requests.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Requests from L2 hardware prefetchers.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "UMask": "0xc0" + }, + { + "BriefDescription": "RFO requests to L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "UMask": "0xc" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "RFOs that access cache lines in any state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "SampleAfterValue": "200003", + "UMask": "0xf" + }, + { + "BriefDescription": "RFOs that hit cache lines in E state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "RFOs that hit cache lines in M state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "RFOs that miss cache lines.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Transactions accessing L2 pipe.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 cache accesses when fetching instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand Data Read requests that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L1D writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 fill requests that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "RFO requests that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when L1D is locked.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core-originated cacheable demand requests missed LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c03f7", + "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4f" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c03f7", + "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.", + "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c03f7", + "BriefDescription": "Data from local DRAM either Snoop not needed or Snoop Miss (RspI)", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Data from remote DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD3", + "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", + "SampleAfterValue": "100007", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x40" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c03f7", + "BriefDescription": "Retired load uops with L1 cache hits as data sources.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops with L2 cache hits as data sources.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10008", + "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required.", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", + "SampleAfterValue": "100007", + "UMask": "0x20" + }, + { + "BriefDescription": "All retired load uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load uops retired", + "SampleAfterValue": "2000003", + "UMask": "0x81" + }, + { + "BriefDescription": "All retired store uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "PublicDescription": "This event counts the number of store uops retired.", + "SampleAfterValue": "2000003", + "UMask": "0x82" + }, + { + "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load uops that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", - "BriefDescription": "Counts all writebacks from the core to the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x41" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0004", + "BriefDescription": "Retired store uops that split across a cacheline boundary.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x42" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0001", + "BriefDescription": "Retired load uops that miss the STLB.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "UMask": "0x11" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0001", + "BriefDescription": "Retired store uops that miss the STLB.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PEBS": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x12" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0001", + "BriefDescription": "Demand and prefetch data reads.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0001", + "BriefDescription": "Cacheable and noncachaeble code read requests.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0001", + "BriefDescription": "Demand Data Read requests sent to uncore.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803c8000", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", - "MSRIndex": "0x1a6,0x1a7", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "SampleAfterValue": "100003", - "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x23ffc08000", + "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0040", + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0010", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0010", + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0010", + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0010", + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0010", + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0200", + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0080", + "BriefDescription": "Counts all demand & prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10400", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts non-temporal stores", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand rfo's", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000105B3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000105B3", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010122", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch prefetch RFOs", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000107F7", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0091", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0091", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0091", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads that hit the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000107F7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo references (demand & prefetch)", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c03f7", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c03f7", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c03f7", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c03f7", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c03f7", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch prefetch RFOs", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all writebacks from the core to the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10008", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data reads that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand rfo's", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803c8000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x23ffc08000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0200", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts non-temporal stores", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Split locks in SQ.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json index 982eda48785e..713878fd062b 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json @@ -1,138 +1,138 @@ [ { - "EventCode": "0xC1", + "BriefDescription": "Cycles with any input/output SSE or FP assist.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OTHER_ASSISTS.AVX_STORE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to output value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.X87_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to input value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to Output values.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to input values.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_COMP_OPS_EXE.X87", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x11", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_FP_256.PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x11", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SIMD_FP_256.PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x1e", "EventName": "FP_ASSIST.ANY", "SampleAfterValue": "100003", - "BriefDescription": "Cycles with any input/output SSE or FP assist.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1e" + }, + { + "BriefDescription": "Number of SIMD FP assists due to input values.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SIMD FP assists due to Output values.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json index 1b7b1dd36c68..4bc0954448d2 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json @@ -1,305 +1,314 @@ [ { - "EventCode": "0x80", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.", - "EventCode": "0x80", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.", - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "DSB2MITE_SWITCHES.COUNT", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.", - "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "SampleAfterValue": "2000003", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { + "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAC", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB_FILL.OTHER_CANCEL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xAC", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DSB_FILL.EXCEED_DSB_LINES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xAC", - "Counter": "0,1,2,3", - "UMask": "0xa", "EventName": "DSB_FILL.ALL_CANCEL", "SampleAfterValue": "2000003", - "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa" }, { - "EventCode": "0x9C", - "Invert": "1", + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x8" }, { - "EventCode": "0x79", + "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", "Counter": "0,1,2,3", - "UMask": "0x3c", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.OTHER_CANCEL", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles MITE is delivering 4 Uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x3c" }, { - "EventCode": "0x79", + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", "Counter": "0,1,2,3", - "UMask": "0x30", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more information.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", "EventName": "IDQ.MS_SWITCHES", "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json index dbb33e00b72a..2800264c12aa 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json @@ -1,142 +1,132 @@ [ { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", - "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" - }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { @@ -145,16 +135,34 @@ "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -165,28 +173,40 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Socket actual clocks when any core is active on that socket", "MetricExpr": "cbox_0@event\\=0x0@", - "MetricGroup": "", + "MetricGroup": "SoC", "MetricName": "Socket_CLKS" }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/perf/pmu-events/arch/x86/jaketown/memory.json index 27e636428f4f..29b70f21a44b 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json @@ -1,422 +1,422 @@ [ { - "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "SampleAfterValue": "100003", "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", "SampleAfterValue": "100003", - "BriefDescription": "Loads with latency value being above 4 .", - "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Loads with latency value being above 128.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Loads with latency value being above 8.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", + "CounterHTOff": "3", "EventCode": "0xCD", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Loads with latency value being above 16.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100007", - "BriefDescription": "Loads with latency value being above 32.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Loads with latency value being above 64.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x1", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", "SampleAfterValue": "1009", - "BriefDescription": "Loads with latency value being above 128.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Loads with latency value being above 16.", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 256.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "SampleAfterValue": "503", - "BriefDescription": "Loads with latency value being above 256.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Loads with latency value being above 32.", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 4 .", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 512.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Loads with latency value being above 512.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { + "MSRValue": "0x200", "PEBS": "2", - "EventCode": "0xCD", - "Counter": "3", - "UMask": "0x2", - "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", - "PRECISE_STORE": "1", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0x05", + "BriefDescription": "Loads with latency value being above 64.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 8.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", + "PEBS": "2", + "PRECISE_STORE": "1", + "SampleAfterValue": "2000003", + "TakenAlone": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x05", + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20004", + "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67fc00010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x67f800010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x87f820010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x107fc00010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3fffc20080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x600400077", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3FFFC20077", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFFC20077", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x187FC20077", + "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400077", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x187FC20077", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that miss in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67fc00010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x600400010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x67f800010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x107fc00010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x87f820010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20200", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3fffc20080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/other.json b/tools/perf/pmu-events/arch/x86/jaketown/other.json index 64b195b82c50..e251f535ec09 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/other.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/other.json @@ -1,58 +1,58 @@ [ { - "EventCode": "0x17", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Valid instructions written to IQ per cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100007", - "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4E", "EventName": "HW_PRE_REQ.DL1_MISS", "SampleAfterValue": "2000003", - "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Valid instructions written to IQ per cycle.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x17", + "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json index 783a5b4a67b1..87737c92c067 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json @@ -1,1216 +1,1202 @@ [ { - "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.", - "Counter": "Fixed counter 1", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 1" - }, - { - "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", - "Counter": "Fixed counter 2", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", - "Counter": "Fixed counter 3", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "CounterHTOff": "Fixed counter 3" - }, - { - "EventCode": "0x88", + "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.", "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x59", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", - "SampleAfterValue": "2000003", - "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", - "EventCode": "0x59", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least one slow LEA uop being allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x59", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", - "SampleAfterValue": "2000003", - "BriefDescription": "Multiply packed/scalar single precision uops allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RESOURCE_STALLS.LB", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the cycles of stall due to lack of load buffers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5B", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "RESOURCE_STALLS2.BOB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x5E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCC", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC0", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Counter - architectural event.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts the number of micro-ops retired.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Actually retired uops.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization.", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 10 actually retired uops.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Not taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "SampleAfterValue": "100007", - "BriefDescription": "Far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_MISP_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect mispredicted near call instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_MISP_RETIRED.NOT_TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted not taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.TAKEN", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", - "SampleAfterValue": "100003", - "BriefDescription": "Retired instructions experiencing ITLB misses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when divider is busy executing divide operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of the divide operations executed.", - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "ARITH.FPU_DIV", - "SampleAfterValue": "100003", - "BriefDescription": "Divide operations executed.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched per thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched from any thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", - "CounterMask": "2", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", - "CounterMask": "6", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x4C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS.DATA_UNKNOWN", - "SampleAfterValue": "100003", - "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "LD_BLOCKS.ALL_BLOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.", - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial compare.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB6", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "AGU_BYPASS_CANCEL.COUNT", "SampleAfterValue": "100003", - "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x3C", + "BriefDescription": "Divide operations executed.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0xc", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x30", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "EventName": "INST_RETIRED.PREC_DIST", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired. (Precise Event - PEBS).", - "TakenAlone": "1", - "CounterHTOff": "1" - }, - { - "EventCode": "0x5B", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls2 control structures full for physical registers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5B", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with either free list is empty.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "RESOURCE_STALLS.MEM_RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "RESOURCE_STALLS.OOO_RSRC", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5B", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "RESOURCE_STALLS2.OOO_RSRC", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls out of order resources full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "RESOURCE_STALLS.LB_SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to load or store buffers all being in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual.", - "EventCode": "0x59", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", "EdgeDetect": "1", - "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xE6", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV", + "PublicDescription": "This event counts the number of the divide operations executed.", "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Cycles when divider is busy executing divide operations.", "Counter": "0,1,2,3", - "UMask": "0xff", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative and retired branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xff" }, { - "EventCode": "0x89", + "BriefDescription": "Speculative and retired macro-conditional branches.", "Counter": "0,1,2,3", - "UMask": "0xff", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "UMask": "0xc2" + }, + { + "BriefDescription": "Speculative and retired direct near calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" + }, + { + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Speculative and retired indirect return branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0xc8" + }, + { + "BriefDescription": "Not taken macro-conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired macro-conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Taken speculative and retired direct near calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" + }, + { + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired indirect calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0x88" + }, + { + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Direct and indirect near call instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC2", - "Invert": "1", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" }, { - "EventCode": "0xA8", + "BriefDescription": "Speculative and retired mispredicted direct near calls.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" }, { - "EventCode": "0xc3", + "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" }, { - "EventCode": "0x5E", - "Invert": "1", + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" }, { - "Counter": "Fixed counter 2", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "Fixed counter 2" + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" }, { + "BriefDescription": "Taken speculative and retired mispredicted direct near calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "UMask": "0x88" + }, + { + "BriefDescription": "All mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Direct and indirect mispredicted near call instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Mispredicted not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NOT_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { + "BriefDescription": "Mispredicted taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x0D", + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 3", + "CounterHTOff": "Fixed counter 3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Stall cycles because IQ is full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Instructions retired. (Precise Event - PEBS).", + "Counter": "1", + "CounterHTOff": "1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "SampleAfterValue": "2000003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired instructions experiencing ITLB misses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", + "PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel? 64 and IA-32 Architectures Optimization Reference Manual.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Multiply packed/scalar single precision uops allocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Cycles with at least one slow LEA uop being allocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", + "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Resource-related stall cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the cycles of stall due to lack of load buffers.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.LB", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Resource stalls due to load or store buffers all being in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.LB_SB", + "SampleAfterValue": "2000003", + "UMask": "0xa" + }, + { + "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.MEM_RS", + "SampleAfterValue": "2000003", + "UMask": "0xe" + }, + { + "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.OOO_RSRC", + "SampleAfterValue": "2000003", + "UMask": "0xf0" + }, + { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with either free list is empty.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Resource stalls2 control structures full for physical registers.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", + "SampleAfterValue": "2000003", + "UMask": "0xf" + }, + { + "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.BOB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Resource stalls out of order resources full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.OOO_RSRC", + "SampleAfterValue": "2000003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Count cases of saving new LBR.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops dispatched from any thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_DISPATCHED.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops dispatched per thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_DISPATCHED.THREAD", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "This event counts the number of micro-ops retired.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json index a654ab771fce..4dd136d00a10 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json @@ -1,149 +1,149 @@ [ { - "EventCode": "0xAE", + "BriefDescription": "Load misses in all DTLB levels that cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100007", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4F", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "EPT.WALK_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "ITLB_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", - "BriefDescription": "Load misses in all DTLB levels that cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x08", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xBD", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", + "EventName": "EPT.WALK_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Misses at all ITLB levels that cause page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "DTLB flush attempts of the thread-specific entries.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "SampleAfterValue": "100007", - "BriefDescription": "DTLB flush attempts of the thread-specific entries.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", + "BriefDescription": "STLB flush attempts.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "SampleAfterValue": "100007", - "BriefDescription": "STLB flush attempts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json index e847b0fd696d..1bd50b186e93 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json @@ -1,2305 +1,2303 @@ [ { - "EventCode": "0x30", + "BriefDescription": "Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "L2_REQUESTS_REJECT.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times" - }, - { "EventCode": "0x31", - "Counter": "0,1", - "UMask": "0x0", "EventName": "CORE_REJECT_L2Q.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path." + "SampleAfterValue": "200003" }, { - "EventCode": "0x2E", + "BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses.", "Counter": "0,1", - "UMask": "0x4f", - "EventName": "L2_REQUESTS.REFERENCE", + "EventCode": "0x86", + "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "PublicDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of L2 cache references." + "UMask": "0x4" }, { - "EventCode": "0x2E", + "BriefDescription": "Counts the number of L2 cache misses", "Counter": "0,1", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "L2_REQUESTS.MISS", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of L2 cache misses" + "UMask": "0x41" }, { - "PublicDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.", - "EventCode": "0x86", + "BriefDescription": "Counts the total number of L2 cache references.", "Counter": "0,1", - "UMask": "0x4", - "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "EventCode": "0x2E", + "EventName": "L2_REQUESTS.REFERENCE", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cummulative count of core cycles the fetch stalled for all icache misses." + "UMask": "0x4f" }, { - "PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.", - "EventCode": "0x04", + "BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) exlcuding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x30", + "EventName": "L2_REQUESTS_REJECT.ALL", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts all the load micro-ops retired", + "Counter": "0,1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "This event counts the number of load micro-ops retired.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts all the store micro-ops retired", + "Counter": "0,1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "This event counts the number of store micro-ops retired.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the loads retired that get the data from the other core in the same tile in M state", + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.HITM", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache", + "Counter": "0,1", + "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", + "PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", - "SampleAfterValue": "200003", "BriefDescription": "Counts the number of load micro-ops retired that hit in the L2", - "Data_LA": "1" - }, - { + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", "PEBS": "1", - "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x4", - "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2", - "Data_LA": "1" + "SampleAfterValue": "200003", + "UMask": "0x2" }, { - "EventCode": "0x04", + "BriefDescription": "Counts the number of load micro-ops retired that miss in the L2", "Counter": "0,1", - "UMask": "0x10", + "Data_LA": "1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of load micro-ops retired that caused micro TLB miss", + "Counter": "0,1", + "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.UTLB_MISS_LOADS", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load micro-ops retired that caused micro TLB miss" + "UMask": "0x10" }, { - "PEBS": "1", - "EventCode": "0x04", + "BriefDescription": "Counts the matrix events specified by MSR_OFFCORE_RESPx", "Counter": "0,1", - "UMask": "0x20", - "EventName": "MEM_UOPS_RETIRED.HITM", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the loads retired that get the data from the other core in the same tile in M state", - "Data_LA": "1" - }, - { - "PublicDescription": "This event counts the number of load micro-ops retired.", - "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "SampleAfterValue": "200003", - "BriefDescription": "Counts all the load micro-ops retired" - }, - { - "PublicDescription": "This event counts the number of store micro-ops retired.", - "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x80", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts all the store micro-ops retired" - }, - { "EventCode": "0xB7", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100007", - "BriefDescription": "Counts the matrix events specified by MSR_OFFCORE_RESPx" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000070", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for any response", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x1000400070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x40000032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x10004032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x08004032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x10000832f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x08000832f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x00000132f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000000044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010044", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for any response", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000403091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800403091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000083091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800083091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000013091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000008000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000408000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800408000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000088000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800088000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000018000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000014800", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000014000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.ANY_RESPONSE", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000002000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000402000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800402000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000082000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800082000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000012000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000001000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000401000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800401000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000081000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800081000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000011000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010800", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000000400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000000200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.ANY_RESPONSE", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000000080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000000040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000020020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000000004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000000002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000400001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800400001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000080001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0800080001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_E_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for any response", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002001000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002002000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002008000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x00020032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0002000070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_M", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004001000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004002000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004008000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x00040032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0004000070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_E", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008001000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008002000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008008000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0008000044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x00080032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_S", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010001000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010002000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010008000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x00100032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0010000070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_F", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800181000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800182000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800188000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800183091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x18001832f7", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800180070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800400002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800400004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800400040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800400080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800400100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800400400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800401000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800402000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x1800408000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800403091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800400022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1800400044", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x18004032f7", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1800400070", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000013091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800403091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800403091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000403091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800183091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800083091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000083091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004003091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010003091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002003091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008003091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000003091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400070", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00000132f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18004032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08004032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18001832f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x08000832f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10000832f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00040032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00100032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00020032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00080032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x40000032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000018000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800408000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800408000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000408000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800188000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800088000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000088000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004008000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010008000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002008000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008008000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000008000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Full streaming stores (WC and should be programmed on PMC1) that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010800", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial streaming stores (WC and should be programmed on PMC1) that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a7", + "MSRValue": "0x0000014000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.ANY_RESPONSE", + "MSRIndex": "0x1a7", + "MSRValue": "0x0000010100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a7", + "MSRValue": "0x1800400100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a7", + "MSRValue": "0x0800400100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a7", + "MSRValue": "0x1000400100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a7", + "MSRValue": "0x1800180100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a7", + "MSRValue": "0x0800080100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a7", + "MSRValue": "0x1000080100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a7", + "MSRValue": "0x0004000100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a7", + "MSRValue": "0x0010000100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a7", + "MSRValue": "0x0002000100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a7", + "MSRValue": "0x0008000100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000012000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800402000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800402000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000402000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800182000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800082000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000082000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800400040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000020020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000011000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800401000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800401000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000401000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800181000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800081000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000081000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004001000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010001000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002001000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008001000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000001000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all streaming stores (WC and should be programmed on PMC1) that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a7", + "MSRValue": "0x0000014800", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for any response", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800400200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Far(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for reponses from snoop request hit with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1800180200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_E_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0800080200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_E", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0004000200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_F", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0010000200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_M", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0002000200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_S", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0008000200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json new file mode 100644 index 000000000000..5fce5020efa1 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json @@ -0,0 +1,29 @@ +[ + { + "BriefDescription": "Counts the number of floating operations retired that required microcode assists", + "Counter": "0,1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.", + "Counter": "0,1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.PACKED_SIMD", + "PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.", + "Counter": "0,1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.SCALAR_SIMD", + "PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.", + "SampleAfterValue": "200003", + "UMask": "0x20" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json index 6d38636689a4..d075ab594d75 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json @@ -1,34 +1,58 @@ [ { - "EventCode": "0x80", + "BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.", "Counter": "0,1", - "UMask": "0x3", + "EventCode": "0xE6", + "EventName": "BACLEARS.ALL", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.", + "Counter": "0,1", + "EventCode": "0xE6", + "EventName": "BACLEARS.COND", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.", + "Counter": "0,1", + "EventCode": "0xE6", + "EventName": "BACLEARS.RETURN", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts all instruction fetches, including uncacheable fetches.", + "Counter": "0,1", + "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200003", - "BriefDescription": "Counts all instruction fetches, including uncacheable fetches." + "UMask": "0x3" }, { - "EventCode": "0x80", + "BriefDescription": "Counts all instruction fetches that hit the instruction cache.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "200003", - "BriefDescription": "Counts all instruction fetches that hit the instruction cache." + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200003", - "BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding." + "UMask": "0x2" }, { - "EventCode": "0xE7", + "BriefDescription": "Counts the number of times the MSROM starts a flow of uops.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xE7", "EventName": "MS_DECODED.MS_ENTRY", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the MSROM starts a flow of uops." + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json index c6bb16ba0f86..5e6ca6896af1 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json @@ -1,1110 +1,1110 @@ [ { - "EventCode": "0xC3", + "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards" + "UMask": "0x2" }, { - "EventCode": "0xB7", - "MSRValue": "0x0100400070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x01004032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x00802032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x01010032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x00808032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100403091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080203091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080803091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100408000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080208000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101008000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080808000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100402000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080202000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101002000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080802000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100401000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080201000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101001000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080801000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x2000020080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x2000020020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0100400001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080200001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0101000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0080800001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600100", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM", - "MSRIndex": "0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180601000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180608000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180603091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x01806032f7", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0180600070", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181800001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181800002", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x0181800004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181800020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181800040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181800080", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181800200", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181800400", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181801000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181802000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181808000", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181803091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181800022", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0181800044", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x01818032f7", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200044", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181803091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101003091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080803091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180603091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100403091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080203091", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200070", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01818032f7", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01010032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00808032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01806032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x01004032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00802032f7", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181808000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101008000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080808000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180608000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100408000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080208000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200022", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200400", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR", + "MSRIndex": "0x1a7", + "MSRValue": "0x0101000100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR", + "MSRIndex": "0x1a7", + "MSRValue": "0x0080800100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM", + "MSRIndex": "0x1a7", + "MSRValue": "0x0180600100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR", + "MSRIndex": "0x1a7", + "MSRValue": "0x0100400100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR", + "MSRIndex": "0x1a7", + "MSRValue": "0x0080200100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181802000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080802000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100402000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080202000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181801000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101001000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080801000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180601000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100401000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080201000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0181800200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0101000200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080800200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0180600200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0100400200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080200200", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json index 92e4ef2e22c6..8f4213e5fbfd 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json @@ -1,432 +1,377 @@ [ { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of branch instructions retired", "Counter": "0,1", - "UMask": "0x0", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions retired" + "PEBS": "1", + "SampleAfterValue": "200003" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of near CALL branch instructions retired.", "Counter": "0,1", - "UMask": "0x7e", - "EventName": "BR_INST_RETIRED.JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps." - }, - { - "PEBS": "1", "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xfe", - "EventName": "BR_INST_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken." - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xf9", "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near CALL branch instructions retired." + "UMask": "0xf9" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of far branch instructions retired.", "Counter": "0,1", - "UMask": "0xfd", - "EventName": "BR_INST_RETIRED.REL_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near relative CALL branch instructions retired." - }, - { - "PEBS": "1", "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xfb", - "EventName": "BR_INST_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near indirect CALL branch instructions retired." - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xf7", - "EventName": "BR_INST_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near RET branch instructions retired." - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xeb", - "EventName": "BR_INST_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP." - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xbf", "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of far branch instructions retired." + "UMask": "0xbf" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", "Counter": "0,1", - "UMask": "0x0", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0xfd" + }, + { + "BriefDescription": "Counts the number of near RET branch instructions retired.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken.", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the number of mispredicted branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch instructions retired" + "PEBS": "1", + "SampleAfterValue": "200003" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired.", "Counter": "0,1", - "UMask": "0x7e", - "EventName": "BR_MISP_RETIRED.JCC", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CALL", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps." + "UMask": "0xf9" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted far branch instructions retired.", "Counter": "0,1", - "UMask": "0xfe", - "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.FAR_BRANCH", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken." + "UMask": "0xbf" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", "Counter": "0,1", - "UMask": "0xfb", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired." + "UMask": "0xfb" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps.", "Counter": "0,1", - "UMask": "0xf7", - "EventName": "BR_MISP_RETIRED.RETURN", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired." + "UMask": "0x7e" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP.", "Counter": "0,1", - "UMask": "0xeb", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP." + "UMask": "0xeb" }, { - "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.", - "EventCode": "0xC2", + "BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.MS", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS)." - }, - { - "PublicDescription": "This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists.", - "EventCode": "0xC2", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of micro-ops retired" - }, - { - "PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.", - "EventCode": "0xC2", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "UOPS_RETIRED.SCALAR_SIMD", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.REL_CALL", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt." + "UMask": "0xfd" }, { - "PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.", - "EventCode": "0xC2", + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.", "Counter": "0,1", - "UMask": "0x40", - "EventName": "UOPS_RETIRED.PACKED_SIMD", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies." + "UMask": "0xf7" }, { - "EventCode": "0xC3", + "BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.SMC", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page" + "UMask": "0xfe" }, { - "PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.", - "EventCode": "0xC3", + "BriefDescription": "Counts the number of unhalted reference clock cycles", "Counter": "0,1", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.FP_ASSIST", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of floating operations retired that required microcode assists" - }, - { - "EventCode": "0xC3", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "MACHINE_CLEARS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts all nukes" - }, - { - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "NO_ALLOC_CYCLES.ROB_FULL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB is full" - }, - { - "PublicDescription": "This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.", - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x4", - "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire." - }, - { - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "NO_ALLOC_CYCLES.RAT_STALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted." - }, - { - "PublicDescription": "This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched.", - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x90", - "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation." - }, - { - "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x7f", - "EventName": "NO_ALLOC_CYCLES.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for any reason." - }, - { - "EventCode": "0xCB", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "RS_FULL_STALL.MEC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry." - }, - { - "EventCode": "0xCB", - "Counter": "0,1", - "UMask": "0x1f", - "EventName": "RS_FULL_STALL.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full." - }, - { - "EventCode": "0xC0", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the total number of instructions retired" - }, - { - "PublicDescription": "This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides.", - "EventCode": "0xCD", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "CYCLES_DIV_BUSY.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider." - }, - { - "PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.", - "Counter": "Fixed counter 1", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of instructions retired" - }, - { "EventCode": "0x3C", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted core clock cycles" - }, - { - "EventCode": "0x3C", - "Counter": "0,1", - "UMask": "0x1", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted reference clock cycles" - }, - { - "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter", - "Counter": "Fixed counter 2", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles" + "UMask": "0x1" }, { + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", "Counter": "Fixed counter 3", - "UMask": "0x3", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles" + "UMask": "0x3" }, { - "EventCode": "0xE6", + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles", "Counter": "0,1", - "UMask": "0x1", - "EventName": "BACLEARS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end." + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003" }, { - "EventCode": "0xE6", + "BriefDescription": "Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider.", "Counter": "0,1", - "UMask": "0x8", - "EventName": "BACLEARS.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end." + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.ALL", + "PublicDescription": "This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "EventCode": "0xE6", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired", + "Counter": "Fixed counter 1", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of instructions retired", "Counter": "0,1", - "UMask": "0x10", - "EventName": "BACLEARS.COND", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end." + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003" }, { - "PEBS": "1", + "BriefDescription": "Counts all nukes", + "Counter": "0,1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.ALL", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page", + "Counter": "0,1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for any reason.", + "Counter": "0,1", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.ALL", + "SampleAfterValue": "200003", + "UMask": "0x7f" + }, + { + "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.", + "Counter": "0,1", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", + "PublicDescription": "This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation.", + "Counter": "0,1", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", + "PublicDescription": "This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched.", + "SampleAfterValue": "200003", + "UMask": "0x90" + }, + { + "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted.", + "Counter": "0,1", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.RAT_STALL", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB is full", + "Counter": "0,1", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.ROB_FULL", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any retired load that was pushed into the recycle queue for any reason.", + "Counter": "0,1", "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store", - "Data_LA": "1" - }, - { - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready" - }, - { - "PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.", - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x4", - "EventName": "RECYCLEQ.ST_SPLITS", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once." - }, - { - "PEBS": "1", - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "RECYCLEQ.LD_SPLITS", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once.", - "Data_LA": "1" - }, - { - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "RECYCLEQ.LOCK", - "SampleAfterValue": "200003", - "BriefDescription": "Counts all the retired locked loads. It does not include stores because we would double count if we count stores" - }, - { - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "RECYCLEQ.STA_FULL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full" - }, - { - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x40", "EventName": "RECYCLEQ.ANY_LD", "SampleAfterValue": "200003", - "BriefDescription": "Counts any retired load that was pushed into the recycle queue for any reason." + "UMask": "0x40" }, { - "EventCode": "0x03", + "BriefDescription": "Counts any retired store that was pushed into the recycle queue for any reason.", "Counter": "0,1", - "UMask": "0x80", + "EventCode": "0x03", "EventName": "RECYCLEQ.ANY_ST", "SampleAfterValue": "200003", - "BriefDescription": "Counts any retired store that was pushed into the recycle queue for any reason." + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready", "Counter": "0,1", - "UMask": "0xf9", - "EventName": "BR_MISP_RETIRED.CALL", + "EventCode": "0x03", + "EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired." + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store", "Counter": "0,1", - "UMask": "0xfd", - "EventName": "BR_MISP_RETIRED.REL_CALL", + "Data_LA": "1", + "EventCode": "0x03", + "EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired." + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once.", "Counter": "0,1", - "UMask": "0xbf", - "EventName": "BR_MISP_RETIRED.FAR_BRANCH", + "Data_LA": "1", + "EventCode": "0x03", + "EventName": "RECYCLEQ.LD_SPLITS", + "PEBS": "1", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted far branch instructions retired." + "UMask": "0x8" + }, + { + "BriefDescription": "Counts all the retired locked loads. It does not include stores because we would double count if we count stores", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "RECYCLEQ.LOCK", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "RECYCLEQ.STA_FULL", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once.", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "RECYCLEQ.ST_SPLITS", + "PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full.", + "Counter": "0,1", + "EventCode": "0xCB", + "EventName": "RS_FULL_STALL.ALL", + "SampleAfterValue": "200003", + "UMask": "0x1f" + }, + { + "BriefDescription": "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry.", + "Counter": "0,1", + "EventCode": "0xCB", + "EventName": "RS_FULL_STALL.MEC", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of micro-ops retired", + "Counter": "0,1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PublicDescription": "This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS).", + "Counter": "0,1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.MS", + "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json index 9e493977771f..eda299ef5ff8 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json @@ -1,65 +1,65 @@ [ { - "PEBS": "1", - "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", - "SampleAfterValue": "200003", "BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss", - "Data_LA": "1" + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0x8" }, { - "EventCode": "0x05", + "BriefDescription": "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_WALKS", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted", - "EdgeDetect": "1" + "EventCode": "0x05", + "EventName": "PAGE_WALKS.CYCLES", + "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.", + "SampleAfterValue": "200003", + "UMask": "0x3" }, { - "EventCode": "0x05", + "BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x05", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included." + "UMask": "0x1" }, { - "EventCode": "0x05", + "BriefDescription": "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted", "Counter": "0,1", - "UMask": "0x2", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included.", + "Counter": "0,1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total I-side page walks that are completed.", + "Counter": "0,1", + "EdgeDetect": "1", + "EventCode": "0x05", "EventName": "PAGE_WALKS.I_SIDE_WALKS", "SampleAfterValue": "100003", - "BriefDescription": "Counts the total I-side page walks that are completed.", - "EdgeDetect": "1" + "UMask": "0x2" }, { - "PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress.", - "EventCode": "0x05", + "BriefDescription": "Counts the total page walks that are completed (I-side and D-side)", "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included." - }, - { + "EdgeDetect": "1", "EventCode": "0x05", - "Counter": "0,1", - "UMask": "0x3", "EventName": "PAGE_WALKS.WALKS", "SampleAfterValue": "100003", - "BriefDescription": "Counts the total page walks that are completed (I-side and D-side)", - "EdgeDetect": "1" - }, - { - "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.", - "EventCode": "0x05", - "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included." + "UMask": "0x3" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv index 0cf2d1fa6b76..963a76fec277 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -42,6 +42,8 @@ GenuineIntel-6-6A,v1,icelakex,core GenuineIntel-6-6C,v1,icelakex,core GenuineIntel-6-86,v1,tremontx,core GenuineIntel-6-96,v1,elkhartlake,core +GenuineIntel-6-97,v1,alderlake,core +GenuineIntel-6-9A,v1,alderlake,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen3,core diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json index a11029efda2f..bcf74d793ae2 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json @@ -1,3229 +1,3229 @@ [ { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D locked", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D and L2 locked", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines replaced in M state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines allocated in the M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "L1D snoop eviction of cache lines in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { - "EventCode": "0x51", + "BriefDescription": "L1 data cache lines allocated", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { - "EventCode": "0x43", + "BriefDescription": "All references to the L1 data cache", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x43", "EventName": "L1D_ALL_REF.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All references to the L1 data cache" + "UMask": "0x1" }, { - "EventCode": "0x43", + "BriefDescription": "L1 data cacheable reads and writes", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x43", "EventName": "L1D_ALL_REF.CACHEABLE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cacheable reads and writes" + "UMask": "0x2" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in E state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x40", "EventName": "L1D_CACHE_LD.E_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in E state" + "UMask": "0x4" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in I state (misses)", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x40", "EventName": "L1D_CACHE_LD.I_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache reads", "Counter": "0,1", - "UMask": "0x8", - "EventName": "L1D_CACHE_LD.M_STATE", - "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in M state" - }, - { "EventCode": "0x40", - "Counter": "0,1", - "UMask": "0xf", "EventName": "L1D_CACHE_LD.MESI", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache reads" + "UMask": "0xf" }, { - "EventCode": "0x40", + "BriefDescription": "L1 data cache read in M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x40", + "EventName": "L1D_CACHE_LD.M_STATE", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "L1 data cache read in S state", + "Counter": "0,1", + "EventCode": "0x40", "EventName": "L1D_CACHE_LD.S_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache read in S state" + "UMask": "0x2" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load locks in E state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.E_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load locks in E state" + "UMask": "0x4" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load lock hits", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load lock hits" + "UMask": "0x1" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load locks in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.M_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load locks in M state" + "UMask": "0x8" }, { - "EventCode": "0x42", + "BriefDescription": "L1 data cache load locks in S state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.S_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache load locks in S state" + "UMask": "0x2" }, { - "EventCode": "0x53", + "BriefDescription": "L1D load lock accepted in fill buffer", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x53", "EventName": "L1D_CACHE_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D load lock accepted in fill buffer" + "UMask": "0x1" }, { - "EventCode": "0x52", + "BriefDescription": "L1D prefetch load lock accepted in fill buffer", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + "UMask": "0x1" }, { - "EventCode": "0x41", + "BriefDescription": "L1 data cache stores in E state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x41", "EventName": "L1D_CACHE_ST.E_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache stores in E state" + "UMask": "0x4" }, { - "EventCode": "0x41", + "BriefDescription": "L1 data cache stores in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x41", "EventName": "L1D_CACHE_ST.M_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache stores in M state" + "UMask": "0x8" }, { - "EventCode": "0x41", + "BriefDescription": "L1 data cache stores in S state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x41", "EventName": "L1D_CACHE_ST.S_STATE", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache stores in S state" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch misses", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests triggered", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "All L1 writebacks to L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" - }, - { "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0xf" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", + "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data requests", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand requests", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" - }, - { "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0xf" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data prefetches", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" - }, - { "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf0", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0xf0" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in M state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines alloacated", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch request" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x30" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_HIT", + "SampleAfterValue": "200000", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_MISS", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "L2 requests", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 misses", "Counter": "0,1,2,3", - "UMask": "0xaa", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 prefetches", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PREFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PREFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0xc0" }, { - "EventCode": "0x24", + "BriefDescription": "L2 prefetch hits", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCH_HIT", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCH_MISS", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", + "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xff" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO requests", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" + "UMask": "0xc" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO hits", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 fill transactions", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 instruction fetch transactions", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "L1D writeback to L2 transactions", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 Load transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 prefetch transactions", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO transactions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 writeback to LLC transactions", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe0", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" - }, - { "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf0", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0xf0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" - }, - { "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0xf" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache miss", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache reference", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", - "SampleAfterValue": "20000", - "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", - "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", - "SampleAfterValue": "4000", - "BriefDescription": "Load instructions retired IO (Precise Event)" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_SQ_FULL", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue full" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", + "MSRValue": "0x0", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + "UMask": "0x10" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F11", + "BriefDescription": "Instructions retired which contains a load (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x8" + }, + { + "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x20" + }, + { + "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x8" + }, + { + "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "PEBS": "1", + "SampleAfterValue": "4000", + "UMask": "0x80" + }, + { + "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "UMask": "0x40" + }, + { + "BriefDescription": "Offcore requests blocked due to Super Queue full", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF11", + "BriefDescription": "All offcore data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8011", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x111", + "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x111", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x211", + "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x211", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x411", + "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x411", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x711", + "BriefDescription": "Offcore data reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4711", + "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1811", + "BriefDescription": "Offcore data reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3811", + "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1011", + "BriefDescription": "Offcore data reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x811", + "BriefDescription": "Offcore data reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F44", + "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF44", + "BriefDescription": "All offcore code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8044", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x144", + "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x144", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x244", + "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x244", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x444", + "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x444", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x744", + "BriefDescription": "Offcore code reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4744", + "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1844", + "BriefDescription": "Offcore code reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3844", + "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1044", + "BriefDescription": "Offcore code reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x844", + "BriefDescription": "Offcore code reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FFF", + "BriefDescription": "Offcore requests satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7FFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFFFF", + "BriefDescription": "All offcore requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFFFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x80FF", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x80FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1FF", + "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x1FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x2FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x4FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FF", + "BriefDescription": "Offcore requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x7FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x47FF", + "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x47FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x18FF", + "BriefDescription": "Offcore requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x18FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x38FF", + "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x38FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x10FF", + "BriefDescription": "Offcore requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x10FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8FF", + "BriefDescription": "Offcore requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F22", + "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF22", + "BriefDescription": "All offcore RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8022", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x122", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x122", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x222", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x222", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x422", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x422", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1822", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3822", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1022", + "BriefDescription": "Offcore RFO requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x822", + "BriefDescription": "Offcore RFO requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F08", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF08", + "BriefDescription": "All offcore writebacks", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore writebacks", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8008", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x108", + "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x108", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x408", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x408", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x708", + "BriefDescription": "Offcore writebacks to the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4708", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1808", + "BriefDescription": "Offcore writebacks to a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3808", + "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1008", + "BriefDescription": "Offcore writebacks that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x808", + "BriefDescription": "Offcore writebacks that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F77", + "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF77", + "BriefDescription": "All offcore code or data read requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code or data read requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8077", + "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x177", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x177", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x277", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x277", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x477", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x477", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x777", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4777", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1877", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3877", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1077", + "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x877", + "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F33", + "BriefDescription": "Offcore request = all data, response = any cache_dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any cache_dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF33", + "BriefDescription": "Offcore request = all data, response = any location", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any location", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8033", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x133", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x133", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x233", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x233", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x433", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x433", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x733", + "BriefDescription": "Offcore request = all data, response = local cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = local cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4733", + "BriefDescription": "Offcore request = all data, response = local cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = local cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1833", + "BriefDescription": "Offcore request = all data, response = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3833", + "BriefDescription": "Offcore request = all data, response = remote cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = remote cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1033", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x833", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F03", + "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF03", + "BriefDescription": "All offcore demand data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8003", + "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x103", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x103", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x203", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x203", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x403", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x403", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x703", + "BriefDescription": "Offcore demand data requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4703", + "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1803", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3803", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1003", + "BriefDescription": "Offcore demand data requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x803", + "BriefDescription": "Offcore demand data requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F01", + "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF01", + "BriefDescription": "All offcore demand data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8001", + "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x101", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x101", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x201", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x201", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x401", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x401", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x701", + "BriefDescription": "Offcore demand data reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4701", + "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1801", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3801", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1001", + "BriefDescription": "Offcore demand data reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x801", + "BriefDescription": "Offcore demand data reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F04", + "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF04", + "BriefDescription": "All offcore demand code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8004", + "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x104", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x104", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x204", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x204", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x404", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x404", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x704", + "BriefDescription": "Offcore demand code reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4704", + "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1804", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3804", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1004", + "BriefDescription": "Offcore demand code reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x804", + "BriefDescription": "Offcore demand code reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F02", + "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF02", + "BriefDescription": "All offcore demand RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8002", + "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x102", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x102", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x202", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x202", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x402", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x402", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x702", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4702", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1802", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3802", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1002", + "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x802", + "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F80", + "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF80", + "BriefDescription": "All offcore other requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore other requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8080", + "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x180", + "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x180", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x280", + "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x280", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x480", + "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x480", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x780", + "BriefDescription": "Offcore other requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4780", + "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1880", + "BriefDescription": "Offcore other requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3880", + "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1080", + "BriefDescription": "Offcore other requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x880", + "BriefDescription": "Offcore other requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F30", + "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF30", + "BriefDescription": "All offcore prefetch data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8030", + "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x130", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x130", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x230", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x230", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x430", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x430", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x730", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4730", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1830", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3830", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1030", + "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x830", + "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F10", + "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF10", + "BriefDescription": "All offcore prefetch data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8010", + "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x110", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x110", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x210", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x210", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x410", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x410", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x710", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4710", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1810", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3810", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1010", + "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x810", + "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F40", + "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF40", + "BriefDescription": "All offcore prefetch code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8040", + "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x140", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x140", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x240", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x240", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x440", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x440", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x740", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4740", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1840", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3840", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1040", + "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x840", + "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F20", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF20", + "BriefDescription": "All offcore prefetch RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x120", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x120", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x220", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x220", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x420", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x420", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1020", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x820", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F70", + "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF70", + "BriefDescription": "All offcore prefetch requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8070", + "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x170", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x170", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x270", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x270", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x470", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x470", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x770", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4770", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1870", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3870", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1070", + "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x870", + "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json index 7d2f71a9dee3..39af1329224a 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json @@ -1,229 +1,229 @@ [ { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", - "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xF7", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.OUTPUT", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF7", + "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x2" + }, + { + "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" + "UMask": "0x2" }, { - "EventCode": "0x10", + "BriefDescription": "SSE2 integer Uops", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" - }, - { "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_COMP_OPS_EXE.SSE_FP", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" + "UMask": "0x8" }, { - "EventCode": "0x10", + "BriefDescription": "SSE* FP double precision Uops", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x80" + }, + { + "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "UMask": "0x20" + }, + { + "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x40" + }, + { + "BriefDescription": "Computational floating-point operations executed", + "Counter": "0,1,2,3", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations executed" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "All Floating Point to and from MMX transitions", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transitions" + "UMask": "0x3" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from MMX to Floating Point instructions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instructions" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from Floating Point to MMX instructions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instructions" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" + "UMask": "0x4" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" + "UMask": "0x10" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" + "UMask": "0x8" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" + "UMask": "0x4" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" + "UMask": "0x10" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit packed multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operations" + "UMask": "0x1" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" + "UMask": "0x2" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json index e5e21e03444d..8ac5c24888c5 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json @@ -1,26 +1,26 @@ [ { - "EventCode": "0xD0", + "BriefDescription": "Instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA6", + "BriefDescription": "Macro-fused instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x19", + "BriefDescription": "Two Uop instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json index f914a4525b65..26138ae639f4 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json @@ -1,739 +1,739 @@ [ { - "EventCode": "0xB7", - "MSRValue": "0x6011", + "BriefDescription": "Offcore data reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF811", + "BriefDescription": "Offcore data reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4011", + "BriefDescription": "Offcore data reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2011", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6044", + "BriefDescription": "Offcore code reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF844", + "BriefDescription": "Offcore code reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4044", + "BriefDescription": "Offcore code reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2044", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x60FF", + "BriefDescription": "Offcore requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x60FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF8FF", + "BriefDescription": "Offcore requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x40FF", + "BriefDescription": "Offcore requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x40FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x20FF", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x20FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6022", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF822", + "BriefDescription": "Offcore RFO requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4022", + "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2022", + "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6008", + "BriefDescription": "Offcore writebacks to any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF808", + "BriefDescription": "Offcore writebacks that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4008", + "BriefDescription": "Offcore writebacks to the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2008", + "BriefDescription": "Offcore writebacks to a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6077", + "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF877", + "BriefDescription": "Offcore code or data read requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4077", + "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2077", + "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6033", + "BriefDescription": "Offcore request = all data, response = any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF833", + "BriefDescription": "Offcore request = all data, response = any LLC miss", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any LLC miss", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4033", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2033", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6003", + "BriefDescription": "Offcore demand data requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF803", + "BriefDescription": "Offcore demand data requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4003", + "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2003", + "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6001", + "BriefDescription": "Offcore demand data reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF801", + "BriefDescription": "Offcore demand data reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4001", + "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2001", + "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6004", + "BriefDescription": "Offcore demand code reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF804", + "BriefDescription": "Offcore demand code reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4004", + "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2004", + "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6002", + "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF802", + "BriefDescription": "Offcore demand RFO requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4002", + "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2002", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6080", + "BriefDescription": "Offcore other requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF880", + "BriefDescription": "Offcore other requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2080", + "BriefDescription": "Offcore other requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6030", + "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF830", + "BriefDescription": "Offcore prefetch data requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4030", + "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2030", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6010", + "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF810", + "BriefDescription": "Offcore prefetch data reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4010", + "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2010", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6040", + "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF840", + "BriefDescription": "Offcore prefetch code reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4040", + "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2040", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF820", + "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6070", + "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF870", + "BriefDescription": "Offcore prefetch requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4070", + "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2070", + "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/other.json b/tools/perf/pmu-events/arch/x86/nehalemep/other.json index af0860622445..710b106ce12a 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/other.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/other.json @@ -1,210 +1,210 @@ [ { - "EventCode": "0xE8", + "BriefDescription": "Early Branch Prediciton Unit clears", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" + "UMask": "0x1" }, { - "EventCode": "0xE8", + "BriefDescription": "Late Branch Prediction Unit clears", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" + "UMask": "0x2" }, { - "EventCode": "0xE5", + "BriefDescription": "Branch prediction unit missed call or return", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" + "UMask": "0x1" }, { - "EventCode": "0xD5", + "BriefDescription": "ES segment renames", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" + "UMask": "0x1" }, { - "EventCode": "0x6C", + "BriefDescription": "I/O transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" + "UMask": "0x2" }, { - "EventCode": "0x80", + "BriefDescription": "L1I Instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" + "UMask": "0x3" }, { - "EventCode": "0x82", + "BriefDescription": "Large ITLB hit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "All loads dispatched", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" + "UMask": "0x7" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from the MOB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" + "UMask": "0x4" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched that bypass the MOB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from stage 305", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" + "UMask": "0x2" }, { - "EventCode": "0x7", + "BriefDescription": "False dependencies due to partial address aliasing", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address aliasing" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "All RAT stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" + "UMask": "0xf" }, { - "EventCode": "0xD2", + "BriefDescription": "Flag stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "Partial register stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xD2", + "BriefDescription": "ROB read port stalls cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" + "UMask": "0x4" }, { - "EventCode": "0xD2", + "BriefDescription": "Scoreboard stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x4", + "BriefDescription": "All Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" + "UMask": "0x7" }, { - "EventCode": "0xD4", + "BriefDescription": "Segment rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Thread responded HIT to snoop", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Thread responded HITE to snoop", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" + "UMask": "0x2" }, { - "EventCode": "0xB8", + "BriefDescription": "Thread responded HITM to snoop", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" + "UMask": "0x4" }, { - "EventCode": "0xF6", + "BriefDescription": "Super Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json index 41006ddcd893..e64d685c128a 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json @@ -1,881 +1,881 @@ [ { - "EventCode": "0x14", + "BriefDescription": "Cycles the divider is busy", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" + "UMask": "0x1" }, { - "EventCode": "0x14", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.DIV", - "SampleAfterValue": "2000000", "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0x14", + "EventName": "ARITH.DIV", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x14", + "BriefDescription": "Multiply operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted with bad target address", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted, regardless of cause", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " + "UMask": "0x1" }, { - "EventCode": "0xA7", + "BriefDescription": "Instruction queue forced BACLEAR", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" + "UMask": "0x1" }, { - "EventCode": "0xE0", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" + "UMask": "0x7f" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "All non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "Taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired conditional branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event)" + "SampleAfterValue": "200000", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Retired near call instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x2" + }, + { + "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" + "UMask": "0x7f" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted conditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted near retired calls (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0x0", + "BriefDescription": "Reference cycles when thread is not halted (fixed counter)", "Counter": "Fixed counter 3", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles when thread is not halted (fixed counter)", "Counter": "Fixed counter 2", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles when thread is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmable counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Total CPU cycles", - "CounterMask": "2" + "Counter": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x0" }, { - "EventCode": "0x87", + "BriefDescription": "Any Instruction Length Decoder stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" + "UMask": "0xf" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Length Change Prefix stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Stall cycles due to BPU MRU bypass", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Regen stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x18", + "BriefDescription": "Instructions that must be decoded by decoder 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder 0" + "UMask": "0x1" }, { - "EventCode": "0x1E", + "BriefDescription": "Instructions written to instruction queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instruction queue" - }, - { "EventCode": "0x17", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles instructions are written to the instruction queue", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "INST_QUEUE_WRITE_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired (fixed counter)", "Counter": "Fixed counter 1", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" + "UMask": "0x0" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Retired MMX instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" - }, - { - "PEBS": "1", - "EventCode": "0xC0", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", + "CounterMask": "16", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Event)" + "UMask": "0x1" }, { - "EventCode": "0x4C", + "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", + "CounterMask": "16", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired floating-point operations (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load operations conflicting with software prefetches", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software prefetches" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles when uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.INACTIVE", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.INACTIVE", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x20", + "BriefDescription": "Loops that can't stream from the instruction queue", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction queue" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles machine clear asserted", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "FPU control word write stall cycles", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Load buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "MXCSR rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" + "UMask": "0x40" }, { - "EventCode": "0xA2", + "BriefDescription": "Other Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" + "UMask": "0x80" }, { - "EventCode": "0xA2", + "BriefDescription": "ROB full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Reservation Station full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0xDB", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" + "EventCode": "0xC7", + "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x10" }, { + "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" + "UMask": "0x4" }, { - "EventCode": "0xD1", + "BriefDescription": "Stack pointer sync operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" + "UMask": "0x8" }, { - "EventCode": "0xD1", + "BriefDescription": "Uops decoded by Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DECODED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xD1", + "EventName": "UOPS_DECODED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on any port (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops issued on any port (core count)", - "CounterMask": "1" - }, - { + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1f" + }, + { + "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" - }, - { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 2, 3 or 4", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", "AnyThread": "1", + "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "AnyThread": "1", + "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", + "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 5", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" + "UMask": "0x20" }, { - "EventCode": "0xE", + "BriefDescription": "Uops issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", + "BriefDescription": "Fused Uops issued", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" + "UMask": "0x2" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Macro-fused Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Retirement slots used (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" - }, - { - "PEBS": "1", + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "CounterMask": "16", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" + }, + { + "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", + "EventCode": "0xDB", + "EventName": "UOP_UNFUSION", + "SampleAfterValue": "2000000", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json index 0596094e0ee9..6d3247c55bcd 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json @@ -1,109 +1,109 @@ [ { - "EventCode": "0x8", + "BriefDescription": "DTLB load misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" + "UMask": "0x1" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss caused by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" + "UMask": "0x10" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walks complete", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB first level misses but second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0xAE", + "BriefDescription": "ITLB flushes", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC8", + "BriefDescription": "ITLB miss", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" + "UMask": "0x2" }, { + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json index bb79e89c2049..92a7269eb444 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json @@ -1,1879 +1,1879 @@ [ { - "EventCode": "0x24", + "BriefDescription": "Allocated L1D data cache lines in M state.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "L2_RQSTS.ALL_RFO", - "SampleAfterValue": "200003", - "BriefDescription": "RFO requests to L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache misses when fetching instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "SampleAfterValue": "200003", - "BriefDescription": "L2 code requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PF_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PF_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", - "EventName": "L2_RQSTS.ALL_PF", - "SampleAfterValue": "200003", - "BriefDescription": "Requests from L2 hardware prefetchers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_STORE_LOCK_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that miss cache lines.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in E state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that hit cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_STORE_LOCK_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "RFOs that access cache lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_L1D_WB_RQSTS.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_L1D_WB_RQSTS.HIT_S", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_L1D_WB_RQSTS.HIT_E", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_L1D_WB_RQSTS.HIT_M", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "L2_L1D_WB_RQSTS.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests missed LLC.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x2E", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "100003", - "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D miss oustandings duration in cycles.", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding.", - "CounterMask": "1", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "Counter": "2", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "2" - }, - { - "EventCode": "0x48", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L1D_PEND_MISS.FB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x51", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L1D.REPLACEMENT", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data line replacements.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x51", - "Counter": "0,1,2,3", - "UMask": "0x2", "EventName": "L1D.ALLOCATED_IN_M", "SampleAfterValue": "2000003", - "BriefDescription": "Allocated L1D data cache lines in M state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L1D.EVICTION", - "SampleAfterValue": "2000003", - "BriefDescription": "L1D data cache lines in M state evicted due to replacement.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x51", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "L1D.ALL_M_REPLACEMENT", "SampleAfterValue": "2000003", - "BriefDescription": "Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0x60", + "BriefDescription": "L1D data cache lines in M state evicted due to replacement.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.EVICTION", "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0x60", + "BriefDescription": "L1D data line replacements.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "CounterMask": "6", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x60", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x63", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1D is locked.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand Data Read requests sent to uncore.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Cacheable and noncachaeble code read requests.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "SampleAfterValue": "100003", - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "SampleAfterValue": "100003", - "BriefDescription": "Demand and prefetch data reads.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { "EventCode": "0xBF", - "Counter": "0,1,2,3", - "UMask": "0x5", "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", "SampleAfterValue": "100003", - "BriefDescription": "Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.", + "UMask": "0x5" + }, + { + "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS)", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS)", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "SampleAfterValue": "100003", - "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts the number of load uops retired (Precise Event)", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", "SampleAfterValue": "2000003", - "BriefDescription": "All retired load uops. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x2" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of store uops retired. (Precise Event - PEBS)", - "EventCode": "0xD0", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "BriefDescription": "L1D miss oustandings duration in cycles.", + "Counter": "2", + "CounterHTOff": "2", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", "SampleAfterValue": "2000003", - "BriefDescription": "All retired store uops. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS)", - "EventCode": "0xD1", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", - "SampleAfterValue": "50021", - "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS)", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS)", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", - "SampleAfterValue": "20011", - "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xD2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", - "SampleAfterValue": "100003", - "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS)", - "EventCode": "0xD4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", - "SampleAfterValue": "100007", - "BriefDescription": "Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_TRANS.DEMAND_DATA_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", - "BriefDescription": "Demand Data Read requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xf" }, { - "EventCode": "0xF0", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_TRANS.RFO", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_E", "SampleAfterValue": "200003", - "BriefDescription": "RFO requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_TRANS.CODE_RD", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_M", "SampleAfterValue": "200003", - "BriefDescription": "L2 cache accesses when fetching instructions.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in S state.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_TRANS.ALL_PF", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.HIT_S", "SampleAfterValue": "200003", - "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_TRANS.L1D_WB", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x28", + "EventName": "L2_L1D_WB_RQSTS.MISS", "SampleAfterValue": "200003", - "BriefDescription": "L1D writebacks that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 cache lines filling L2.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_TRANS.L2_FILL", - "SampleAfterValue": "200003", - "BriefDescription": "L2 fill requests that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_TRANS.L2_WB", - "SampleAfterValue": "200003", - "BriefDescription": "L2 writebacks that access L2 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_TRANS.ALL_REQUESTS", - "SampleAfterValue": "200003", - "BriefDescription": "Transactions accessing L2 pipe.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "L2_LINES_IN.I", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in I state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 cache lines in E state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "L2_LINES_IN.S", - "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in S state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "L2_LINES_IN.E", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines in E state filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", + "BriefDescription": "L2 cache lines in I state filling L2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF1", - "Counter": "0,1,2,3", - "UMask": "0x7", - "EventName": "L2_LINES_IN.ALL", + "EventName": "L2_LINES_IN.I", "SampleAfterValue": "100003", - "BriefDescription": "L2 cache lines filling L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 cache lines in S state filling L2.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.S", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "Dirty L2 cache lines evicted by demand.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by demand.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "Dirty L2 cache lines filling the L2.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_LINES_OUT.PF_CLEAN", - "SampleAfterValue": "100003", - "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_LINES_OUT.PF_DIRTY", - "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xF2", - "Counter": "0,1,2,3", - "UMask": "0xa", "EventName": "L2_LINES_OUT.DIRTY_ALL", "SampleAfterValue": "100003", - "BriefDescription": "Dirty L2 cache lines filling the L2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa" }, { - "EventCode": "0xF4", + "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_CLEAN", "SampleAfterValue": "100003", - "BriefDescription": "Split locks in SQ.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0244", + "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.PF_DIRTY", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 code requests.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "SampleAfterValue": "200003", + "UMask": "0x30" + }, + { + "BriefDescription": "Demand Data Read requests.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Requests from L2 hardware prefetchers.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "SampleAfterValue": "200003", + "UMask": "0xc0" + }, + { + "BriefDescription": "RFO requests to L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "SampleAfterValue": "200003", + "UMask": "0xc" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "RFOs that access cache lines in any state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.ALL", + "SampleAfterValue": "200003", + "UMask": "0xf" + }, + { + "BriefDescription": "RFOs that hit cache lines in E state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "RFOs that hit cache lines in M state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "RFOs that miss cache lines.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x27", + "EventName": "L2_STORE_LOCK_RQSTS.MISS", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_PF", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Transactions accessing L2 pipe.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.ALL_REQUESTS", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 cache accesses when fetching instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.CODE_RD", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Demand Data Read requests that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.DEMAND_DATA_RD", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "L1D writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L1D_WB", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 fill requests that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_FILL", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "RFO requests that access L2 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.RFO", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when L1D is locked.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core-originated cacheable demand requests missed LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Core-originated cacheable demand requests that refer to LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "SampleAfterValue": "100003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state. (Precise Event - PEBS)", + "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2. (Precise Event - PEBS)", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load uops with unknown information as data source in cache serviced the load. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD4", + "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", + "PEBS": "1", + "PublicDescription": "This event counts retired demand loads that missed the last-level (L3) cache. This means that the load is usually satisfied from memory in a client system or possibly from the remote socket in a server. Demand loads are non speculative load uops. (Precise Event - PEBS)", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", + "PEBS": "1", + "PublicDescription": "This event counts retired load uops that hit in the last-level (L3) cache without snoops required. (Precise Event - PEBS)", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "All retired load uops. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load uops retired (Precise Event)", + "SampleAfterValue": "2000003", + "UMask": "0x81" + }, + { + "BriefDescription": "All retired store uops. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "PublicDescription": "This event counts the number of store uops retired. (Precise Event - PEBS)", + "SampleAfterValue": "2000003", + "UMask": "0x82" + }, + { + "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS)", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). (Precise Event - PEBS)", + "SampleAfterValue": "100003", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xD0", + "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Demand and prefetch data reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cacheable and noncachaeble code read requests.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0244", + "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0244", + "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0091", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0240", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0240", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0240", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0240", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0240", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0090", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0090", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0090", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0090", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0090", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0120", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch RFOs that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0120", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0120", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0120", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0120", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c03f7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c03f7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c03f7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c03f7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c03f7", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0122", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10008", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "COREWB & ANY_RESPONSE", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x18000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803c8000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2380408000", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) data reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3f803c0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003c0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10003c0100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003c0100", - "Counter": "0,1,2,3", - "UMask": "0x1", + "MSRValue": "0x2003c0244", "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED", - "MSRIndex": "0x1a6,0x1a7", "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003c0100", + "BriefDescription": "Counts all demand & prefetch data reads.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10400", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10800", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts non-temporal stores.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand data reads .", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand rfo's .", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010004", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand code reads.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000105B3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000105B3", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x00010122", + "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch prefetch RFOs .", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x000107F7", + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0091", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0091", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0091", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0091", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch code reads that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0240", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0240", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0240", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0240", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0240", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch data reads that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0090", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch RFOs that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0120", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x000107F7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) .", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10433", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c03f7", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c03f7", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c03f7", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c03f7", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c03f7", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch prefetch RFOs .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0122", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "COREWB & ANY_RESPONSE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10008", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10433", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = DATA_INTO_CORE and RESPONSE = ANY_RESPONSE", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1000040002", + "BriefDescription": "Counts all demand code reads.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010004", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data reads .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data reads that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand rfo's .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x00010002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_M and SNOOP = HITM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10040", + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803c8000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2380408000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_RESPONSE", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10080", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0040", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) data reads that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0200", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0200", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0200", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0200", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0200", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the LLC.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3f803c0100", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003c0100", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003c0100", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003c0100", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to LLC only) RFOs that hit in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003c0100", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = ANY_RESPONSE", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10200", + "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = ANY_RESPONSE", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts non-temporal stores.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Split locks in SQ.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json index ce26537c7d47..713878fd062b 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json @@ -1,138 +1,138 @@ [ { - "EventCode": "0x10", + "BriefDescription": "Cycles with any input/output SSE or FP assist.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "FP_COMP_OPS_EXE.X87", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x11", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SIMD_FP_256.PACKED_SINGLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x11", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SIMD_FP_256.PACKED_DOUBLE", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OTHER_ASSISTS.AVX_STORE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OTHER_ASSISTS.AVX_TO_SSE", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "OTHER_ASSISTS.SSE_TO_AVX", - "SampleAfterValue": "100003", - "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.X87_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to output value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_ASSIST.X87_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of X87 assists due to input value.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "FP_ASSIST.SIMD_OUTPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to Output values.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_ASSIST.SIMD_INPUT", - "SampleAfterValue": "100003", - "BriefDescription": "Number of SIMD FP assists due to input values.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xCA", - "Counter": "0,1,2,3", - "UMask": "0x1e", "EventName": "FP_ASSIST.ANY", "SampleAfterValue": "100003", - "BriefDescription": "Cycles with any input/output SSE or FP assist.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1e" + }, + { + "BriefDescription": "Number of SIMD FP assists due to input values.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_INPUT", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SIMD FP assists due to Output values.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.SIMD_OUTPUT", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_INPUT", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCA", + "EventName": "FP_ASSIST.X87_OUTPUT", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.X87", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_STORE", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.AVX_TO_SSE", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.SSE_TO_AVX", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_DOUBLE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x11", + "EventName": "SIMD_FP_256.PACKED_SINGLE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json index e58ed14a204c..fa22f9463b66 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json @@ -1,305 +1,314 @@ [ { - "EventCode": "0x79", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "IDQ.EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", - "CounterHTOff": "0,1,2,3" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x1f" }, { - "EventCode": "0x79", + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "IDQ.MITE_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "IDQ.DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "IDQ.MS_DSB_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EdgeDetect": "1", - "EventName": "IDQ.MS_DSB_OCCUR", - "SampleAfterValue": "2000003", - "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x18", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "IDQ.MS_MITE_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering 4 Uops.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x24", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles MITE is delivering any Uop.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual for more information.", - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "IDQ.MS_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EdgeDetect": "1", - "EventName": "IDQ.MS_SWITCHES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x79", - "Counter": "0,1,2,3", - "UMask": "0x3c", - "EventName": "IDQ.MITE_ALL_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ICACHE.HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.", - "EventCode": "0x80", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", - "SampleAfterValue": "200003", - "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.", - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x9C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "DSB2MITE_SWITCHES.COUNT", "SampleAfterValue": "2000003", - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.", - "EventCode": "0xAB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "SampleAfterValue": "2000003", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xAC", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DSB_FILL.OTHER_CANCEL", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "This event counts the cycles attributed to a switch from the Decoded Stream Buffer (DSB), which holds decoded instructions, to the legacy decode pipeline. It excludes cycles when the back-end cannot accept new micro-ops. The penalty for these switches is potentially several cycles of instruction starvation, where no micro-ops are delivered to the back-end.", "SampleAfterValue": "2000003", - "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0xAC", + "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DSB_FILL.EXCEED_DSB_LINES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAC", - "Counter": "0,1,2,3", - "UMask": "0xa", "EventName": "DSB_FILL.ALL_CANCEL", "SampleAfterValue": "2000003", - "BriefDescription": "Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0xa" + }, + { + "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.EXCEED_DSB_LINES", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cases of cancelling valid DSB fill not because of exceeding way limit.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAC", + "EventName": "DSB_FILL.OTHER_CANCEL", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instruction cache, streaming buffer and victim cache misses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes unchacheable accesses.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles MITE is delivering 4 Uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.EMPTY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_ALL_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x3c" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "This event counts cycles during which the microcode sequencer assisted the front-end in delivering uops. Microcode assists are used for complex instructions or scenarios that can't be handled by the standard decoder. Using other instructions, if possible, will usually improve performance. See the Intel 64 and IA-32 Architectures Optimization Reference Manual for more information.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_OCCUR", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled .", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "This event counts the number of uops not delivered to the back-end per cycle, per thread, when the back-end was not stalled. In the ideal case 4 uops can be delivered each cycle. The event counts the undelivered uops - so if 3 were delivered in one cycle, the counter would be incremented by 1 for that cycle (4 - 3). If the back-end is stalled, the count for this event is not incremented even when uops were not delivered, because the back-end would not have been able to accept them. This event is used in determining the front-end bound category of the top-down pipeline slots characterization.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when 1 or more uops were delivered to the by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json index 78c1a987f9a2..931892d34076 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json @@ -1,445 +1,445 @@ [ { - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MISALIGN_MEM_REF.LOADS", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x05", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MISALIGN_MEM_REF.STORES", - "SampleAfterValue": "2000003", - "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xBE", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "PAGE_WALKS.LLC_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "SampleAfterValue": "100003", "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x4", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", "SampleAfterValue": "100003", - "BriefDescription": "Loads with latency value being above 4 .", - "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x2" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x8", + "BriefDescription": "Loads with latency value being above 128.", "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "SampleAfterValue": "50021", - "BriefDescription": "Loads with latency value being above 8.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", + "CounterHTOff": "3", "EventCode": "0xCD", - "MSRValue": "0x10", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "SampleAfterValue": "20011", - "BriefDescription": "Loads with latency value being above 16.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x20", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "SampleAfterValue": "100007", - "BriefDescription": "Loads with latency value being above 32.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x40", - "Counter": "3", - "UMask": "0x1", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "SampleAfterValue": "2003", - "BriefDescription": "Loads with latency value being above 64.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x80", - "Counter": "3", - "UMask": "0x1", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", "SampleAfterValue": "1009", - "BriefDescription": "Loads with latency value being above 128.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x100", + "BriefDescription": "Loads with latency value being above 16.", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "SampleAfterValue": "20011", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 256.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "SampleAfterValue": "503", - "BriefDescription": "Loads with latency value being above 256.", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xCD", - "MSRValue": "0x200", + "BriefDescription": "Loads with latency value being above 32.", "Counter": "3", - "UMask": "0x1", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 4 .", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "SampleAfterValue": "100003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 512.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", - "SampleAfterValue": "101", - "BriefDescription": "Loads with latency value being above 512.", - "TakenAlone": "1", - "CounterHTOff": "3" - }, - { + "MSRValue": "0x200", "PEBS": "2", - "EventCode": "0xCD", - "Counter": "3", - "UMask": "0x2", - "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", - "PRECISE_STORE": "1", + "SampleAfterValue": "101", "TakenAlone": "1", - "CounterHTOff": "3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400244", + "BriefDescription": "Loads with latency value being above 64.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "SampleAfterValue": "2003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Loads with latency value being above 8.", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", + "Counter": "3", + "CounterHTOff": "3", + "EventCode": "0xCD", + "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", + "PEBS": "2", + "PRECISE_STORE": "1", + "SampleAfterValue": "2000003", + "TakenAlone": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.LOADS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "MISALIGN_MEM_REF.STORES", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400244", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400091", + "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400091", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400240", + "BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400240", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch code reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400090", + "BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400090", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch data reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400120", + "BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400120", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch RFOs that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3004003f7", + "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3004003f7", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400122", + "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400122", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand & prefetch RFOs that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400004", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400001", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400002", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400040", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400010", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400020", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400200", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400080", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x300400100", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6004001b3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", - "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts LLC replacements.", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM", - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80408fff", - "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80408fff", + "Offcore": "1", + "PublicDescription": "This event counts any requests that miss the LLC where the data was returned from local DRAM", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x17004001b3", + "BriefDescription": "Counts LLC replacements.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6004001b3", "Offcore": "1", + "PublicDescription": "This event counts all data requests (demand/prefetch data reads and demand data writes (RFOs) that miss the LLC where the data is returned from local DRAM", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_LLC_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x17004001b3", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = DATA_IN_SOCKET and RESPONSE = LLC_MISS_LOCAL and SNOOP = ANY_LLC_HIT", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400004", + "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400004", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400004", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400010", + "BriefDescription": "Counts demand data writes (RFOs) that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400002", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400010", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400040", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400040", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400080", + "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from dram.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400040", "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400200", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400080", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x300400100", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400080", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = PF_LLC_DATA_RD and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1f80400200", + "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", - "Offcore": "1", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1f80400200", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "REQUEST = PF_LLC_IFETCH and RESPONSE = LLC_MISS_LOCAL and SNOOP = DRAM", - "CounterHTOff": "0,1,2,3" + "UMask": "0x1" + }, + { + "BriefDescription": "Number of any page walk that had a miss in LLC. Does not necessary cause a SUSPEND.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBE", + "EventName": "PAGE_WALKS.LLC_MISS", + "SampleAfterValue": "100003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/other.json b/tools/perf/pmu-events/arch/x86/sandybridge/other.json index 874eb40a2e0f..e251f535ec09 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/other.json @@ -1,58 +1,58 @@ [ { - "EventCode": "0x17", + "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Valid instructions written to IQ per cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4E", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "HW_PRE_REQ.DL1_MISS", - "SampleAfterValue": "2000003", - "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x5C", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", "EdgeDetect": "1", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0_TRANS", "SampleAfterValue": "100007", - "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x5C", + "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", - "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4E", + "EventName": "HW_PRE_REQ.DL1_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Valid instructions written to IQ per cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x17", + "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json index b7150f65f16d..b9a3f194a00a 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json @@ -1,1226 +1,1212 @@ [ { - "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", - "Counter": "Fixed counter 2", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the core is not in halt state.", - "CounterHTOff": "Fixed counter 2" - }, - { - "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.", - "Counter": "Fixed counter 0", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired from execution.", - "CounterHTOff": "Fixed counter 0" - }, - { - "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", - "Counter": "Fixed counter 1", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when the thread is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "Counter": "Fixed counter 1", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "Fixed counter 1" - }, - { - "EventCode": "0x03", + "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS.DATA_UNKNOWN", - "SampleAfterValue": "100003", - "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "SampleAfterValue": "100003", - "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS.NO_SR", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x03", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "LD_BLOCKS.ALL_BLOCK", - "SampleAfterValue": "100003", - "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.", - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "SampleAfterValue": "100003", - "BriefDescription": "False dependencies in MOB due to partial compare.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x07", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "EdgeDetect": "1", - "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x3", - "AnyThread": "1", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0D", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "INT_MISC.RAT_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.", - "EventCode": "0x0E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x0E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.FPU_DIV_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when divider is busy executing divide operations.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of the divide operations executed.", - "EventCode": "0x14", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "ARITH.FPU_DIV", - "SampleAfterValue": "100003", - "BriefDescription": "Divide operations executed.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Thread cycles when thread is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x0", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0x3C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4C", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LOAD_HIT_PRE.SW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4C", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "LOAD_HIT_PRE.HW_PF", - "SampleAfterValue": "100003", - "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x59", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", - "SampleAfterValue": "2000003", - "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual.", - "EventCode": "0x59", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel\u00ae 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", - "EventCode": "0x59", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with at least one slow LEA uop being allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x59", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", - "SampleAfterValue": "2000003", - "BriefDescription": "Multiply packed/scalar single precision uops allocated.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5B", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with either free list is empty.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5B", - "Counter": "0,1,2,3", - "UMask": "0xf", - "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls2 control structures full for physical registers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5B", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "RESOURCE_STALLS2.BOB_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5B", - "Counter": "0,1,2,3", - "UMask": "0x4f", - "EventName": "RESOURCE_STALLS2.OOO_RSRC", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls out of order resources full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x5E", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EdgeDetect": "1", - "EventName": "RS_EVENTS.EMPTY_END", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ILD_STALL.LCP", - "SampleAfterValue": "2000003", - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x87", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ILD_STALL.IQ_FULL", - "SampleAfterValue": "2000003", - "BriefDescription": "Stall cycles because IQ is full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired indirect calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc2", - "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xc8", - "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired indirect return branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x88", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_INST_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0x90", - "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xa0", - "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc1", - "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xc4", - "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", - "SampleAfterValue": "200003", - "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xd0", - "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted direct near calls.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x89", - "Counter": "0,1,2,3", - "UMask": "0xff", - "EventName": "BR_MISP_EXEC.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 1.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0xc", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0xc", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x30", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x30", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 4.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per thread when uops are dispatched to port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA1", - "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", - "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles per core when uops are dispatched to port 5.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "RESOURCE_STALLS.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource-related stall cycles.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "RESOURCE_STALLS.LB", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the cycles of stall due to lack of load buffers.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "RESOURCE_STALLS.RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no eligible RS entry available.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "RESOURCE_STALLS.SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0xa", - "EventName": "RESOURCE_STALLS.LB_SB", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to load or store buffers all being in use.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "RESOURCE_STALLS.MEM_RS", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "RESOURCE_STALLS.ROB", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles stalled due to re-order buffer full.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA2", - "Counter": "0,1,2,3", - "UMask": "0xf0", - "EventName": "RESOURCE_STALLS.OOO_RSRC", - "SampleAfterValue": "2000003", - "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x2", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", - "CounterMask": "2", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "0,1,2,3", - "UMask": "0x5", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.", - "CounterMask": "5", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xA3", - "Counter": "2", - "UMask": "0x6", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", - "SampleAfterValue": "2000003", - "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", - "CounterMask": "6", - "CounterHTOff": "2" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of Uops delivered by the LSD.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_ACTIVE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xA8", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.CYCLES_4_UOPS", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DISPATCHED.THREAD", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched per thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_DISPATCHED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Uops dispatched from any thread.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "CounterMask": "2", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "CounterMask": "3", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", - "CounterMask": "4", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xB6", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "AGU_BYPASS_CANCEL.COUNT", "SampleAfterValue": "100003", - "BriefDescription": "This event counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in an.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC0", + "BriefDescription": "Divide operations executed.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of instructions retired. General Counter - architectural event.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xC0", - "Counter": "1", - "UMask": "0x1", - "EventName": "INST_RETIRED.PREC_DIST", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired. (Precise Event - PEBS).", - "TakenAlone": "1", - "CounterHTOff": "1" - }, - { - "EventCode": "0xC1", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", - "SampleAfterValue": "100003", - "BriefDescription": "Retired instructions experiencing ITLB misses.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts the number of micro-ops retired. (Precise Event)", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Actually retired uops. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", + "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles with less than 10 actually retired uops.", - "CounterMask": "10", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles without actually retired uops.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS)", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "SampleAfterValue": "2000003", - "BriefDescription": "Retirement slots used. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0xc3", - "Counter": "0,1,2,3", - "UMask": "0x1", "EdgeDetect": "1", - "EventName": "MACHINE_CLEARS.COUNT", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV", + "PublicDescription": "This event counts the number of the divide operations executed.", "SampleAfterValue": "100003", - "BriefDescription": "Number of machine clears (nukes) of any type.", - "CounterMask": "1", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", - "EventCode": "0xC3", + "BriefDescription": "Cycles when divider is busy executing divide operations.", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "100003", - "BriefDescription": "Self-modifying code (SMC) detected.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x14", + "EventName": "ARITH.FPU_DIV_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", - "EventCode": "0xC3", + "BriefDescription": "Speculative and retired branches.", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MACHINE_CLEARS.MASKMOV", - "SampleAfterValue": "100003", - "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "UMask": "0xff" }, { - "EventCode": "0xC4", + "BriefDescription": "Speculative and retired macro-conditional branches.", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Speculative and retired macro-unconditional branches excluding calls and indirects.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", + "SampleAfterValue": "200003", + "UMask": "0xc2" + }, + { + "BriefDescription": "Speculative and retired direct near calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" + }, + { + "BriefDescription": "Speculative and retired indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Speculative and retired indirect return branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0xc8" + }, + { + "BriefDescription": "Not taken macro-conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired macro-conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired macro-conditional branch instructions excluding calls and indirects.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Taken speculative and retired direct near calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" + }, + { + "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired indirect calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x88", + "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", + "SampleAfterValue": "200003", + "UMask": "0x88" + }, + { "BriefDescription": "All (macro) branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009" }, { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", - "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "2", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "SampleAfterValue": "400009", "BriefDescription": "All (macro) branch instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" - }, - { - "PEBS": "1", - "EventCode": "0xC4", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "SampleAfterValue": "100007", - "BriefDescription": "Return instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3", "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", "SampleAfterValue": "400009", - "BriefDescription": "Not taken branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x4" }, { + "BriefDescription": "Conditional branch instructions retired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "SampleAfterValue": "400009", - "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xC4", + "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", - "UMask": "0x40", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "SampleAfterValue": "100007", - "BriefDescription": "Far branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x40" }, { - "EventCode": "0xC5", + "BriefDescription": "Direct and indirect near call instructions retired. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "400009", - "BriefDescription": "All mispredicted macro branch instructions retired.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_MISP_RETIRED.NEAR_CALL", "SampleAfterValue": "100007", - "BriefDescription": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { + "BriefDescription": "Direct and indirect macro near call instructions retired (captured in ring 3). (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_BRANCHES", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "Speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Speculative and retired mispredicted direct near calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xd0" + }, + { + "BriefDescription": "Mispredicted indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "Not taken speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted macro conditional branches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted direct near calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0x90" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches excluding calls and returns.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", + "SampleAfterValue": "200003", + "UMask": "0x84" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect calls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", + "SampleAfterValue": "200003", + "UMask": "0xa0" + }, + { + "BriefDescription": "Taken speculative and retired mispredicted indirect branches with return mnemonic.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x89", + "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", + "SampleAfterValue": "200003", + "UMask": "0x88" + }, + { + "BriefDescription": "All mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", "PublicDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS)", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted macro branch instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted conditional branch instructions retired. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "BR_MISP_RETIRED.NOT_TAKEN", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Direct and indirect mispredicted near call instructions retired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { "BriefDescription": "Mispredicted not taken branch instructions retired.(Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PEBS": "1", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "BR_MISP_RETIRED.TAKEN", + "EventName": "BR_MISP_RETIRED.NOT_TAKEN", + "PEBS": "1", "SampleAfterValue": "400009", - "BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0xCC", + "BriefDescription": "Mispredicted taken branch instructions retired. (Precise Event - PEBS).", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Count XClk pulses when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "PublicDescription": "Reference cycles when the thread is unhalted (counts at 100 MHz rate)", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread cycles when thread is not in halt state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "SampleAfterValue": "2000003" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Each cycle there was a miss-pending demand load this thread, increment by 1. Note this is in DCU and connected to Umask 1. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Each cycle there was a MLC-miss pending demand load this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Each cycle there was no dispatch for this thread, increment by 1. Note this is connect to Umask 2. No dispatch can be deduced from the UOPS_EXECUTED event.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Each cycle there was a miss-pending demand load this thread and no uops dispatched, increment by 1. Note this is in DCU and connected to Umask 1 and 2. Miss Pending demand load should be deduced by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "Counter": "2", + "CounterHTOff": "2", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Each cycle there was a MLC-miss pending demand load and no uops dispatched on this thread (i.e. Non-completed valid SQ entry allocated for demand load and waiting for Uncore), increment by 1. Note this is in MLC and connected to Umask 0 and 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Stall cycles because IQ is full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.IQ_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Instructions retired. (Precise Event - PEBS).", + "Counter": "1", + "CounterHTOff": "1", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "SampleAfterValue": "2000003", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RAT_STALL_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc...).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_STALLS_COUNT", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Number of cases where any load ends up with a valid block-code written to the load buffer (including blocks due to Memory Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL_BLOCK", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed due to SB blocks, preceding store operations with known addresses but unknown data.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwarding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Aliasing occurs when a load is issued after a store and their memory addresses are offset by 4K. This event counts the number of loads that aliased with a preceding store, resulting in an extended address check in the pipeline. The enhanced address check typically has a performance penalty of 5 cycles.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for hardware prefetch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.HW_PF", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Not software-prefetch load dispatches that hit FB allocated for software prefetch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MASKMOV", + "PublicDescription": "Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event is incremented when self-modifying code (SMC) is detected, which causes a machine clear. Machine clears can have a significant performance impact if they are happening frequently.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired instructions experiencing ITLB misses.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Increments the number of flags-merge uops in flight each cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Performance sensitive flags-merging uops added by Sandy Bridge u-arch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", + "PublicDescription": "This event counts the number of cycles spent executing performance-sensitive flags-merging uops. For example, shift CL (merge_arith_flags). For more details, See the Intel 64 and IA-32 Architectures Optimization Reference Manual.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Multiply packed/scalar single precision uops allocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Cycles with at least one slow LEA uop being allocated.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", + "PublicDescription": "This event counts the number of cycles with at least one slow LEA uop being allocated. A uop is generally considered as slow LEA if it has three sources (for example, two sources and immediate) regardless of whether it is a result of LEA instruction or not. Examples of the slow LEA uop are or uops with base, index, and offset source operands using base and index reqisters, where base is EBR/RBP/R13, using RIP relative or 16-bit addressing modes. See the Intel 64 and IA-32 Architectures Optimization Reference Manual for more details about slow LEA instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Resource-related stall cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the cycles of stall due to lack of load buffers.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.LB", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Resource stalls due to load or store buffers all being in use.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.LB_SB", + "SampleAfterValue": "2000003", + "UMask": "0xa" + }, + { + "BriefDescription": "Resource stalls due to memory buffers or Reservation Station (RS) being fully utilized.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.MEM_RS", + "SampleAfterValue": "2000003", + "UMask": "0xe" + }, + { + "BriefDescription": "Resource stalls due to Rob being full, FCSW, MXCSR and OTHER.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.OOO_RSRC", + "SampleAfterValue": "2000003", + "UMask": "0xf0" + }, + { + "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.ROB", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles stalled due to no eligible RS entry available.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.RS", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with either free list is empty.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Resource stalls2 control structures full for physical registers.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", + "SampleAfterValue": "2000003", + "UMask": "0xf" + }, + { + "BriefDescription": "Cycles when Allocator is stalled if BOB is full and new branch needs it.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.BOB_FULL", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Resource stalls out of order resources full.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5B", + "EventName": "RESOURCE_STALLS2.OOO_RSRC", + "SampleAfterValue": "2000003", + "UMask": "0x4f" + }, + { + "BriefDescription": "Count cases of saving new LBR.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "SampleAfterValue": "2000003", - "BriefDescription": "Count cases of saving new LBR.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" }, { - "EventCode": "0xE6", + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread.", "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "BACLEARS.ANY", - "SampleAfterValue": "100003", - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops dispatched from any thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_DISPATCHED.CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops dispatched per thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_DISPATCHED.THREAD", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 1.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 2.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Cycles per thread when load or STA uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when load or STA uops are dispatched to port 3.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 4.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles per thread when uops are dispatched to port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles per core when uops are dispatched to port 5.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA1", + "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "This event counts the number of Uops issued by the front-end of the pipeilne to the back-end.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Actually retired uops. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PublicDescription": "This event counts the number of micro-ops retired. (Precise Event)", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retirement slots used. (Precise Event - PEBS).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retirement slots used each cycle. There are potentially 4 slots that can be used each cycle - meaning, 4 micro-ops or 4 instructions could retire each cycle. This event is used in determining the 'Retiring' category of the Top-Down pipeline slots characterization. (Precise Event - PEBS)", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 10 actually retired uops.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json index fb2d7b8875f8..c8e7050d9c26 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json @@ -1,142 +1,132 @@ [ { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Frontend_Bound", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Frontend_Bound_SMT", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Bad_Speculation", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Bad_Speculation_SMT", "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )", "MetricGroup": "TopdownL1", "MetricName": "Backend_Bound", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", + "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", "MetricGroup": "TopdownL1_SMT", "MetricName": "Backend_Bound_SMT", "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", "MetricName": "Retiring", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " }, { "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", "MetricName": "Retiring_SMT", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "TopDownL1", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, - { - "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", - "MetricExpr": "min( 1 , UOPS_ISSUED.ANY / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 32 * ( ICACHE.HIT + ICACHE.MISSES ) / 4 ) )", - "MetricGroup": "PGO;IcMiss", - "MetricName": "IFetch_Line_Utilization" - }, - { - "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", - "MetricGroup": "DSB;Fetch_BW", - "MetricName": "DSB_Coverage" - }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", - "MetricGroup": "Pipeline;Summary", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", "MetricExpr": "CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * cycles", - "MetricGroup": "TopDownL1", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", - "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "TopDownL1_SMT", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "BriefDescription": "Total number of retired Instructions", - "MetricExpr": "INST_RETIRED.ANY", - "MetricGroup": "Summary", - "MetricName": "Instructions" + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_DISPATCHED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / cycles", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "SMT", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / cycles", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_DISPATCHED.THREAD / (( cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_DISPATCHED.CORE\\,cmask\\=1@)", - "MetricGroup": "Pipeline", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { @@ -145,16 +135,34 @@ "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1", + "MetricName": "Instructions" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", + "MetricGroup": "DSB;Fed;FetchBW", + "MetricName": "DSB_Coverage" + }, { "BriefDescription": "Average CPU Utilization", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", - "MetricGroup": "Summary", + "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, + { + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "( (( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE )) / 1000000000 ) / duration_time", - "MetricGroup": "FLOPS;Summary", + "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -165,22 +173,46 @@ }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", - "MetricGroup": "SMT;Summary", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", + "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", - "MetricGroup": "Memory_BW", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, + { + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "IpFarBranch" + }, { "BriefDescription": "C3 residency percent per core", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json new file mode 100644 index 000000000000..6b0639944d78 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json @@ -0,0 +1,252 @@ +[ + { + "BriefDescription": "L3 Lookup any request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in E or S-state.", + "UMask": "0x86", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in I-state.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in M-state.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup any request that access cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup any request that access cache and found line in MESI-state.", + "UMask": "0x8f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in E or S-state.", + "UMask": "0x46", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in I-state.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in M-state.", + "UMask": "0x41", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup external snoop request that access cache and found line in MESI-state.", + "UMask": "0x4f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in E or S-state.", + "UMask": "0x16", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in I-state.", + "UMask": "0x18", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.", + "UMask": "0x11", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup read request that access cache and found line in any MESI-state.", + "UMask": "0x1f", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in E or S-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in E or S-state.", + "UMask": "0x26", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in I-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in I-state.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in M-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in M-state.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "L3 Lookup write request that access cache and found line in MESI-state.", + "Counter": "0,1", + "EventCode": "0x34", + "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", + "PerPkg": "1", + "PublicDescription": "L3 Lookup write request that access cache and found line in MESI-state.", + "UMask": "0x2f", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.", + "UMask": "0x88", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a modified line in some processor core.", + "UMask": "0x28", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core.", + "UMask": "0x48", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.", + "UMask": "0x84", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop hits a non-modified line in some processor core.", + "UMask": "0x24", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core.", + "UMask": "0x44", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.", + "UMask": "0x81", + "Unit": "CBO" + }, + { + "BriefDescription": "An external snoop misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", + "PerPkg": "1", + "PublicDescription": "An external snoop misses in some processor core.", + "UMask": "0x21", + "Unit": "CBO" + }, + { + "BriefDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", + "Counter": "0,1", + "EventCode": "0x22", + "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", + "PerPkg": "1", + "PublicDescription": "A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core.", + "UMask": "0x41", + "Unit": "CBO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json new file mode 100644 index 000000000000..6278068908cf --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-other.json @@ -0,0 +1,91 @@ +[ + { + "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", + "EventCode": "0x83", + "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of requests allocated in Coherency Tracker.", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Number of requests allocated in Coherency Tracker.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "Counter": "0,1", + "CounterMask": "10", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", + "PerPkg": "1", + "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "Counter": "0,1", + "CounterMask": "1", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", + "PerPkg": "1", + "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of LLC evictions allocated.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", + "PerPkg": "1", + "PublicDescription": "Counts the number of LLC evictions allocated.", + "UMask": "0x80", + "Unit": "ARB" + }, + { + "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", + "Counter": "0,1", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", + "UMask": "0x20", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "Counter": "Fixed", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", + "UMask": "0x01", + "Unit": "ARB" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore.json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore.json deleted file mode 100644 index 42c70eed05a2..000000000000 --- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore.json +++ /dev/null @@ -1,314 +0,0 @@ -[ - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x01", - "EventName": "UNC_CBO_XSNP_RESPONSE.MISS", - "BriefDescription": "A snoop misses in some processor core.", - "PublicDescription": "A snoop misses in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x02", - "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL", - "BriefDescription": "A snoop invalidates a non-modified line in some processor core.", - "PublicDescription": "A snoop invalidates a non-modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x04", - "EventName": "UNC_CBO_XSNP_RESPONSE.HIT", - "BriefDescription": "A snoop hits a non-modified line in some processor core.", - "PublicDescription": "A snoop hits a non-modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x08", - "EventName": "UNC_CBO_XSNP_RESPONSE.HITM", - "BriefDescription": "A snoop hits a modified line in some processor core.", - "PublicDescription": "A snoop hits a modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x10", - "EventName": "UNC_CBO_XSNP_RESPONSE.INVAL_M", - "BriefDescription": "A snoop invalidates a modified line in some processor core.", - "PublicDescription": "A snoop invalidates a modified line in some processor core.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x20", - "EventName": "UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to external snoop request.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x40", - "EventName": "UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to processor core memory request.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x22", - "UMask": "0x80", - "EventName": "UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", - "BriefDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", - "PublicDescription": "Filter on cross-core snoops initiated by this Cbox due to LLC eviction.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x01", - "EventName": "UNC_CBO_CACHE_LOOKUP.M", - "BriefDescription": "LLC lookup request that access cache and found line in M-state.", - "PublicDescription": "LLC lookup request that access cache and found line in M-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x02", - "EventName": "UNC_CBO_CACHE_LOOKUP.E", - "BriefDescription": "LLC lookup request that access cache and found line in E-state.", - "PublicDescription": "LLC lookup request that access cache and found line in E-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x04", - "EventName": "UNC_CBO_CACHE_LOOKUP.S", - "BriefDescription": "LLC lookup request that access cache and found line in S-state.", - "PublicDescription": "LLC lookup request that access cache and found line in S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x08", - "EventName": "UNC_CBO_CACHE_LOOKUP.I", - "BriefDescription": "LLC lookup request that access cache and found line in I-state.", - "PublicDescription": "LLC lookup request that access cache and found line in I-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x10", - "EventName": "UNC_CBO_CACHE_LOOKUP.READ_FILTER", - "BriefDescription": "Filter on processor core initiated cacheable read requests.", - "PublicDescription": "Filter on processor core initiated cacheable read requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x20", - "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", - "BriefDescription": "Filter on processor core initiated cacheable write requests.", - "PublicDescription": "Filter on processor core initiated cacheable write requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x40", - "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", - "BriefDescription": "Filter on external snoop requests.", - "PublicDescription": "Filter on external snoop requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x80", - "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", - "BriefDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.", - "PublicDescription": "Filter on any IRQ or IPQ initiated requests including uncacheable, non-coherent requests.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", - "BriefDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "PublicDescription": "Counts cycles weighted by the number of requests waiting for data returning from the memory controller. Accounts for coherent and non-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_REQUESTS.ALL", - "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "PublicDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x20", - "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", - "BriefDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", - "PublicDescription": "Counts the number of allocated write entries, include full, partial, and LLC evictions.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x81", - "UMask": "0x80", - "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", - "BriefDescription": "Counts the number of LLC evictions allocated.", - "PublicDescription": "Counts the number of LLC evictions allocated.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x83", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", - "BriefDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", - "PublicDescription": "Cycles weighted by number of requests pending in Coherency Tracker.", - "Counter": "0", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x84", - "UMask": "0x01", - "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", - "BriefDescription": "Number of requests allocated in Coherency Tracker.", - "PublicDescription": "Number of requests allocated in Coherency Tracker.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", - "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "Counter": "0,1", - "CounterMask": "1", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x80", - "UMask": "0x01", - "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", - "BriefDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "PublicDescription": "Cycles with at least half of the requests outstanding are waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.", - "Counter": "0,1", - "CounterMask": "10", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "ARB", - "EventCode": "0x0", - "UMask": "0x01", - "EventName": "UNC_CLOCK.SOCKET", - "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.", - "Counter": "Fixed", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - }, - { - "Unit": "CBO", - "EventCode": "0x34", - "UMask": "0x06", - "EventName": "UNC_CBO_CACHE_LOOKUP.ES", - "BriefDescription": "LLC lookup request that access cache and found line in E-state or S-state.", - "PublicDescription": "LLC lookup request that access cache and found line in E-state or S-state.", - "Counter": "0,1", - "CounterMask": "0", - "Invert": "0", - "EdgeDetect": "0" - } -] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json index b8eccce5d75d..4dd136d00a10 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json @@ -1,149 +1,149 @@ [ { - "EventCode": "0x08", + "BriefDescription": "Load misses in all DTLB levels that cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", - "BriefDescription": "Load misses in all DTLB levels that cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x08", + "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", - "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x2" }, { - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", + "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "Store misses in all DTLB levels that cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x10", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x4F", + "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", "Counter": "0,1,2,3", - "UMask": "0x10", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_DURATION", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x10" }, { - "EventCode": "0x85", + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "ITLB_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { + "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xAE", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB.ITLB_FLUSH", "SampleAfterValue": "100007", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", + "BriefDescription": "Misses at all ITLB levels that cause page walks.", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Misses in all ITLB levels that cause completed page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_DURATION", + "PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "DTLB flush attempts of the thread-specific entries.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "SampleAfterValue": "100007", - "BriefDescription": "DTLB flush attempts of the thread-specific entries.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x1" }, { - "EventCode": "0xBD", + "BriefDescription": "STLB flush attempts.", "Counter": "0,1,2,3", - "UMask": "0x20", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "SampleAfterValue": "100007", - "BriefDescription": "STLB flush attempts.", - "CounterHTOff": "0,1,2,3,4,5,6,7" + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/perf/pmu-events/arch/x86/silvermont/cache.json index 805ef1436539..e16e1d910e4a 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json @@ -1,812 +1,810 @@ [ { - "PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).", - "EventCode": "0x30", + "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.", "Counter": "0,1", - "UMask": "0x0", - "EventName": "L2_REJECT_XQ.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ" - }, - { - "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)", "EventCode": "0x31", - "Counter": "0,1", - "UMask": "0x0", "EventName": "CORE_REJECT_L2Q.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL." + "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a core?s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.)", + "SampleAfterValue": "200003" }, { - "PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.", - "EventCode": "0x2E", + "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", "Counter": "0,1", - "UMask": "0x4f", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache requests from this core" - }, - { - "PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.", - "EventCode": "0x2E", - "Counter": "0,1", - "UMask": "0x41", - "EventName": "LONGEST_LAT_CACHE.MISS", - "SampleAfterValue": "200003", - "BriefDescription": "L2 cache request misses" - }, - { - "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", "EventCode": "0x86", - "Counter": "0,1", - "UMask": "0x4", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", + "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ICache miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ICache miss. Note: this event is not the same as the total number of cycles spent retrieving instruction cache lines from the memory hierarchy.\r\nCounts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss." + "UMask": "0x4" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch.", - "EventCode": "0x03", + "BriefDescription": "Counts the number of request from the L2 that were not accepted into the XQ", "Counter": "0,1", - "UMask": "0x1", - "EventName": "REHABQ.LD_BLOCK_ST_FORWARD", - "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store forward restriction" + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ALL", + "PublicDescription": "This event counts the number of demand and prefetch transactions that the L2 XQ rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) and WOB (L2 write-back victims).", + "SampleAfterValue": "200003" }, { - "PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time.", - "EventCode": "0x03", + "BriefDescription": "L2 cache request misses", "Counter": "0,1", - "UMask": "0x2", - "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "This event counts the total number of L2 cache references and the number of L2 cache misses respectively.", "SampleAfterValue": "200003", - "BriefDescription": "Loads blocked due to store data not ready" + "UMask": "0x41" }, { - "PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits.", - "EventCode": "0x03", + "BriefDescription": "L2 cache requests from this core", "Counter": "0,1", - "UMask": "0x4", - "EventName": "REHABQ.ST_SPLITS", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "This event counts requests originating from the core that references a cache line in the L2 cache.", "SampleAfterValue": "200003", - "BriefDescription": "Store uops that split cache line boundary" + "UMask": "0x4f" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of retire loads that experienced cache line boundary splits.", - "EventCode": "0x03", + "BriefDescription": "All Loads", "Counter": "0,1", - "UMask": "0x8", - "EventName": "REHABQ.LD_SPLITS", - "SampleAfterValue": "200003", - "BriefDescription": "Load uops that split cache line boundary" - }, - { - "PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0).", - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "REHABQ.LOCK", - "SampleAfterValue": "200003", - "BriefDescription": "Uops with lock semantics" - }, - { - "PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available.", - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "REHABQ.STA_FULL", - "SampleAfterValue": "200003", - "BriefDescription": "Store address buffer full" - }, - { - "PublicDescription": "This event counts the number of load uops reissued from Rehabq.", - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x40", - "EventName": "REHABQ.ANY_LD", - "SampleAfterValue": "200003", - "BriefDescription": "Any reissued load uops" - }, - { - "PublicDescription": "This event counts the number of store uops reissued from Rehabq.", - "EventCode": "0x03", - "Counter": "0,1", - "UMask": "0x80", - "EventName": "REHABQ.ANY_ST", - "SampleAfterValue": "200003", - "BriefDescription": "Any reissued store uops" - }, - { - "PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.", "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "This event counts the number of load ops retired.", "SampleAfterValue": "200003", - "BriefDescription": "Loads missed L1" + "UMask": "0x40" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of load ops retired that hit in the L2.", - "EventCode": "0x04", + "BriefDescription": "All Stores", "Counter": "0,1", - "UMask": "0x2", - "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PublicDescription": "This event counts the number of store ops retired.", "SampleAfterValue": "200003", - "BriefDescription": "Loads hit L2" + "UMask": "0x80" }, { - "PEBS": "1", - "PublicDescription": "This event counts the number of load ops retired that miss in the L2.", - "EventCode": "0x04", + "BriefDescription": "Cross core or cross module hitm", "Counter": "0,1", - "UMask": "0x4", - "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", - "SampleAfterValue": "100007", - "BriefDescription": "Loads missed L2" - }, - { - "PublicDescription": "This event counts the number of load ops retired that had UTLB miss.", "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x10", - "EventName": "MEM_UOPS_RETIRED.UTLB_MISS", - "SampleAfterValue": "200003", - "BriefDescription": "Loads missed UTLB" - }, - { + "EventName": "MEM_UOPS_RETIRED.HITM", "PEBS": "1", "PublicDescription": "This event counts the number of load ops retired that got data from the other core or from the other module.", - "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x20", - "EventName": "MEM_UOPS_RETIRED.HITM", "SampleAfterValue": "200003", - "BriefDescription": "Cross core or cross module hitm" + "UMask": "0x20" }, { - "PublicDescription": "This event counts the number of load ops retired.", - "EventCode": "0x04", + "BriefDescription": "Loads missed L1", "Counter": "0,1", - "UMask": "0x40", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", + "PublicDescription": "This event counts the number of load ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted.", "SampleAfterValue": "200003", - "BriefDescription": "All Loads" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of store ops retired.", - "EventCode": "0x04", + "BriefDescription": "Loads hit L2", "Counter": "0,1", - "UMask": "0x80", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops retired that hit in the L2.", "SampleAfterValue": "200003", - "BriefDescription": "All Stores" + "UMask": "0x2" }, { - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "BriefDescription": "Loads missed L2", + "Counter": "0,1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "This event counts the number of load ops retired that miss in the L2.", + "SampleAfterValue": "100007", + "UMask": "0x4" + }, + { + "BriefDescription": "Loads missed UTLB", + "Counter": "0,1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.UTLB_MISS", + "PublicDescription": "This event counts the number of load ops retired that had UTLB miss.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", + "Counter": "0,1", "EventCode": "0xB7", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100007", - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000044", + "BriefDescription": "Counts any code reads (demand & prefetch) that have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x1000000044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0400000044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0200000044", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010044", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any code reads (demand & prefetch) that have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000022", + "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000000022", + "BriefDescription": "Counts any code reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000022", + "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200000022", + "BriefDescription": "Counts any code reads (demand & prefetch) that miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000044", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000010022", + "BriefDescription": "Counts any data read (demand & prefetch) that have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any rfo reads (demand & prefetch) that have any response type.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x1680003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that miss L2.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0400003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0200003091", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000013091", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000013091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any data read (demand & prefetch) that have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680004800", + "BriefDescription": "Counts any data read (demand & prefetch) that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts streaming store that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000008008", + "BriefDescription": "Counts any data read (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400008008", + "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200008008", + "BriefDescription": "Counts any data read (demand & prefetch) that miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200003091", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000018008", + "BriefDescription": "Counts any request that have any response type.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000018008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680002000", + "BriefDescription": "Counts any request that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000008008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1000002000", + "BriefDescription": "Counts any request that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400008008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400002000", + "BriefDescription": "Counts any request that miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200008008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0200002000", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0000012000", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts DCU hardware prefetcher data read that have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000100", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that hit in the other module where modified copies were found in other core's L1 cache.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Countsof demand RFO requests to write to partial cache lines that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000080", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand reads of partial cache lines (including UC and WC) that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000040", + "BriefDescription": "Counts any rfo reads (demand & prefetch) that miss L2 with a snoop miss response.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000022", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0400000040", + "BriefDescription": "Counts writeback (modified to exclusive) that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x0200000040", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1680000020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000000020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0400000020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0200000020", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1680000010", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000000010", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0400000010", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0200000010", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1680000008", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts writeback (modified to exclusive) that miss L2.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x0080000008", + "BriefDescription": "Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0080000008", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts writeback (modified to exclusive) that miss L2 with no details on snoop-related information.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000004", + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x1680000004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0400000004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0200000004", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010004", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that have any response type.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4000000002", + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that miss L2 with a snoop miss response.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000004", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch instruction cacheline that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", + "MSRValue": "0x4000000004", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1680000002", + "BriefDescription": "Counts demand and DCU prefetch data read that have any response type.", "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2.", - "Offcore": "1" - }, - { "EventCode": "0xB7", - "MSRValue": "0x1000000002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0400000002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0200000002", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x4000000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", - "MSRIndex": "0x1a6", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1680000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that miss L2.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x1000000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0400000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0200000001", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.", - "Offcore": "1" - }, - { - "EventCode": "0xB7", - "MSRValue": "0x0000010001", - "Counter": "0,1", - "UMask": "0x1", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000010001", + "Offcore": "1", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand and DCU prefetch data read that have any response type.", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch data read that miss L2.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch data read that hit in the other module where modified copies were found in other core's L1 cache.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch data read that miss L2 with a snoop miss response.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch data read that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000001", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch RFOs that hit in the other module where modified copies were found in other core's L1 cache.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch RFOs that miss L2 with a snoop miss response.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand and DCU prefetch RFOs that are are outstanding, per cycle, from the time of the L2 miss to when any response is received.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x4000000002", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads of partial cache lines (including UC and WC) that miss L2.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000080", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Countsof demand RFO requests to write to partial cache lines that miss L2.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000100", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts DCU hardware prefetcher data read that have any response type.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0000012000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts DCU hardware prefetcher data read that hit in the other module where modified copies were found in other core's L1 cache.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts DCU hardware prefetcher data read that miss L2 with a snoop miss response.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200002000", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts code reads generated by L2 prefetchers that miss L2 with a snoop miss response.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000040", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000010", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000010", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000010", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts data cacheline reads generated by L2 prefetchers that miss L2 with a snoop miss response.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000010", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680000020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts RFO requests generated by L2 prefetchers that hit in the other module where modified copies were found in other core's L1 cache.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0400000020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts RFO requests generated by L2 prefetchers that miss L2 with a snoop miss response.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x0200000020", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming store that miss L2.", + "Counter": "0,1", + "EventCode": "0xB7", + "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1680004800", + "Offcore": "1", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Any reissued load uops", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.ANY_LD", + "PublicDescription": "This event counts the number of load uops reissued from Rehabq.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Any reissued store uops", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.ANY_ST", + "PublicDescription": "This event counts the number of store uops reissued from Rehabq.", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Loads blocked due to store data not ready", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY", + "PublicDescription": "This event counts the cases where a forward was technically possible, but did not occur because the store data was not available at the right time.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Loads blocked due to store forward restriction", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.LD_BLOCK_ST_FORWARD", + "PEBS": "1", + "PublicDescription": "This event counts the number of retired loads that were prohibited from receiving forwarded data from the store because of address mismatch.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Load uops that split cache line boundary", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.LD_SPLITS", + "PEBS": "1", + "PublicDescription": "This event counts the number of retire loads that experienced cache line boundary splits.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops with lock semantics", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.LOCK", + "PublicDescription": "This event counts the number of retired memory operations with lock semantics. These are either implicit locked instructions such as the XCHG instruction or instructions with an explicit LOCK prefix (0xF0).", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Store address buffer full", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.STA_FULL", + "PublicDescription": "This event counts the number of retired stores that are delayed because there is not a store address buffer available.", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Store uops that split cache line boundary", + "Counter": "0,1", + "EventCode": "0x03", + "EventName": "REHABQ.ST_SPLITS", + "PublicDescription": "This event counts the number of retire stores that experienced cache line boundary splits.", + "SampleAfterValue": "200003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json new file mode 100644 index 000000000000..1d75b35694ac --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json @@ -0,0 +1,11 @@ +[ + { + "BriefDescription": "Stalls due to FP assists", + "Counter": "0,1", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PublicDescription": "This event counts the number of times that pipeline stalled due to FP operations needing assists.", + "SampleAfterValue": "200003", + "UMask": "0x4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json index 204473badf5a..a4c98e43f677 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json @@ -1,47 +1,74 @@ [ { - "PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\nfetches.", - "EventCode": "0x80", + "BriefDescription": "Counts the number of baclears", "Counter": "0,1", - "UMask": "0x3", - "EventName": "ICACHE.ACCESSES", + "EventCode": "0xE6", + "EventName": "BACLEARS.ALL", + "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch.", "SampleAfterValue": "200003", - "BriefDescription": "Instruction fetches" + "UMask": "0x1" }, { - "PublicDescription": "This event counts all instruction fetches from the instruction cache.", - "EventCode": "0x80", + "BriefDescription": "Counts the number of JCC baclears", "Counter": "0,1", - "UMask": "0x1", - "EventName": "ICACHE.HIT", + "EventCode": "0xE6", + "EventName": "BACLEARS.COND", + "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears.", "SampleAfterValue": "200003", - "BriefDescription": "Instruction fetches from Icache" + "UMask": "0x10" }, { - "PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.", - "EventCode": "0x80", + "BriefDescription": "Counts the number of RETURN baclears", "Counter": "0,1", - "UMask": "0x2", - "EventName": "ICACHE.MISSES", + "EventCode": "0xE6", + "EventName": "BACLEARS.RETURN", + "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears.", "SampleAfterValue": "200003", - "BriefDescription": "Icache miss" + "UMask": "0x8" }, { - "PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.", - "EventCode": "0xE7", + "BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction", "Counter": "0,1", - "UMask": "0x1", - "EventName": "MS_DECODED.MS_ENTRY", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count." - }, - { - "PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction.", "EventCode": "0xE9", - "Counter": "0,1", - "UMask": "0x1", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PublicDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times a decode restriction reduced the decode throughput due to wrong instruction length prediction" + "UMask": "0x1" + }, + { + "BriefDescription": "Instruction fetches", + "Counter": "0,1", + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "PublicDescription": "This event counts all instruction fetches, not including most uncacheable\r\nfetches.", + "SampleAfterValue": "200003", + "UMask": "0x3" + }, + { + "BriefDescription": "Instruction fetches from Icache", + "Counter": "0,1", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PublicDescription": "This event counts all instruction fetches from the instruction cache.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Icache miss", + "Counter": "0,1", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PublicDescription": "This event counts all instruction fetches that miss the Instruction cache or produce memory requests. This includes uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. Speculative count.", + "Counter": "0,1", + "EventCode": "0xE7", + "EventName": "MS_DECODED.MS_ENTRY", + "PublicDescription": "Counts the number of times the MSROM starts a flow of UOPS. It does not count every time a UOP is read from the microcode ROM. The most common case that this counts is when a micro-coded instruction is encountered by the front end of the machine. Other cases include when an instruction encounters a fault, trap, or microcode assist of any sort. The event will count MSROM startups for UOPS that are speculative, and subsequently cleared by branch mispredict or machine clear. Background: UOPS are produced by two mechanisms. Either they are generated by hardware that decodes instructions into UOPS, or they are delivered by a ROM (called the MSROM) that holds UOPS associated with a specific instruction. MSROM UOPS might also be delivered in response to some condition such as a fault or other exceptional condition. This event is an excellent mechanism for detecting instructions that require the use of MSROM instructions.", + "SampleAfterValue": "200003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/memory.json b/tools/perf/pmu-events/arch/x86/silvermont/memory.json index d72e09a5f929..5e21fc3fd078 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/memory.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/memory.json @@ -1,11 +1,11 @@ [ { - "PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues.", - "EventCode": "0xC3", + "BriefDescription": "Stalls due to Memory ordering", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "This event counts the number of times that pipeline was cleared due to memory ordering issues.", "SampleAfterValue": "200003", - "BriefDescription": "Stalls due to Memory ordering" + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/other.json b/tools/perf/pmu-events/arch/x86/silvermont/other.json index 47814046fa9d..16d16a1ce6de 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/other.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/other.json @@ -1,20 +1,20 @@ [ { - "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.", - "EventCode": "0x86", + "BriefDescription": "Cycles code-fetch stalled due to any reason.", "Counter": "0,1", - "UMask": "0x2", - "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", + "EventCode": "0x86", + "EventName": "FETCH_STALL.ALL", + "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss." + "UMask": "0x3f" }, { - "PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.", - "EventCode": "0x86", + "BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss.", "Counter": "0,1", - "UMask": "0x3f", - "EventName": "FETCH_STALL.ALL", + "EventCode": "0x86", + "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", + "PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.", "SampleAfterValue": "200003", - "BriefDescription": "Cycles code-fetch stalled due to any reason." + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json index 1ed62ad4cf77..03a4c7f26698 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json @@ -1,356 +1,316 @@ [ { + "BriefDescription": "Counts the number of branch instructions retired...", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", "PublicDescription": "ALL_BRANCHES counts the number of any branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions retired..." + "SampleAfterValue": "200003" }, { - "PEBS": "1", - "PublicDescription": "JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of taken branch instructions retired", "Counter": "0,1", - "UMask": "0x7e", - "EventName": "BR_INST_RETIRED.JCC", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", + "PEBS": "2", + "PEBScounters": "0,1", + "PublicDescription": "ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of JCC branch instructions retired" + "UMask": "0x80" }, { - "PEBS": "1", - "PublicDescription": "TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of near CALL branch instructions retired", "Counter": "0,1", - "UMask": "0xfe", - "EventName": "BR_INST_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of taken JCC branch instructions retired" - }, - { + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CALL", "PEBS": "1", "PublicDescription": "CALL counts the number of near CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xf9", - "EventName": "BR_INST_RETIRED.CALL", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near CALL branch instructions retired" + "UMask": "0xf9" }, { - "PEBS": "1", - "PublicDescription": "REL_CALL counts the number of near relative CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", + "BriefDescription": "Counts the number of far branch instructions retired", "Counter": "0,1", - "UMask": "0xfd", - "EventName": "BR_INST_RETIRED.REL_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near relative CALL branch instructions retired" - }, - { - "PEBS": "1", - "PublicDescription": "IND_CALL counts the number of near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xfb", - "EventName": "BR_INST_RETIRED.IND_CALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near indirect CALL branch instructions retired" - }, - { - "PEBS": "1", - "PublicDescription": "RETURN counts the number of near RET branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xf7", - "EventName": "BR_INST_RETIRED.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near RET branch instructions retired" - }, - { - "PEBS": "1", - "PublicDescription": "NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xeb", - "EventName": "BR_INST_RETIRED.NON_RETURN_IND", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired" - }, - { + "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", "PublicDescription": "FAR counts the number of far branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0xbf", - "EventName": "BR_INST_RETIRED.FAR_BRANCH", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of far branch instructions retired" + "UMask": "0xbf" }, { + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "1", + "PublicDescription": "IND_CALL counts the number of near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "Counts the number of JCC branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "1", + "PublicDescription": "JCC counts the number of conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PublicDescription": "NON_RETURN_IND counts the number of near indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of near relative CALL branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "1", + "PublicDescription": "REL_CALL counts the number of near relative CALL branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "SampleAfterValue": "200003", + "UMask": "0xfd" + }, + { + "BriefDescription": "Counts the number of near RET branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "1", + "PublicDescription": "RETURN counts the number of near RET branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Counts the number of taken JCC branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PublicDescription": "TAKEN_JCC counts the number of taken conditional branch (JCC) instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the number of mispredicted branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", "PublicDescription": "ALL_BRANCHES counts the number of any mispredicted branch instructions retired. This umask is an architecturally defined event. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", - "EventCode": "0xC5", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch instructions retired" + "SampleAfterValue": "200003" }, { - "PEBS": "1", - "PublicDescription": "JCC counts the number of mispredicted conditional branches (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", - "EventCode": "0xC5", + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired", "Counter": "0,1", - "UMask": "0x7e", - "EventName": "BR_MISP_RETIRED.JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted JCC branch instructions retired" - }, - { - "PEBS": "1", - "PublicDescription": "TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", "EventCode": "0xC5", - "Counter": "0,1", - "UMask": "0xfe", - "EventName": "BR_MISP_RETIRED.TAKEN_JCC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted taken JCC branch instructions retired" - }, - { + "EventName": "BR_MISP_RETIRED.IND_CALL", "PEBS": "1", "PublicDescription": "IND_CALL counts the number of mispredicted near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", - "EventCode": "0xC5", - "Counter": "0,1", - "UMask": "0xfb", - "EventName": "BR_MISP_RETIRED.IND_CALL", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired" + "UMask": "0xfb" }, { + "BriefDescription": "Counts the number of mispredicted JCC branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.JCC", "PEBS": "1", - "PublicDescription": "RETURN counts the number of mispredicted near RET branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", - "EventCode": "0xC5", - "Counter": "0,1", - "UMask": "0xf7", - "EventName": "BR_MISP_RETIRED.RETURN", + "PublicDescription": "JCC counts the number of mispredicted conditional branches (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired" + "UMask": "0x7e" }, { + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired", + "Counter": "0,1", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "PEBS": "1", "PublicDescription": "NON_RETURN_IND counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired", + "Counter": "0,1", "EventCode": "0xC5", - "Counter": "0,1", - "UMask": "0xeb", - "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "1", + "PublicDescription": "RETURN counts the number of mispredicted near RET branch instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired" + "UMask": "0xf7" }, { - "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.", - "EventCode": "0xC2", + "BriefDescription": "Counts the number of mispredicted taken JCC branch instructions retired", "Counter": "0,1", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.MS", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PublicDescription": "TAKEN_JCC counts the number of mispredicted taken conditional branch (JCC) instructions retired. This event counts the number of retired branch instructions that were mispredicted by the processor, categorized by type. A branch misprediction occurs when the processor predicts that the branch would be taken, but it is not, or vice-versa. When the misprediction is discovered, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.CORE", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", "SampleAfterValue": "2000003", - "BriefDescription": "MSROM micro-ops retired" + "UMask": "0x2" }, { - "PublicDescription": "This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops.", - "EventCode": "0xC2", + "BriefDescription": "Core cycles when core is not halted", "Counter": "0,1", - "UMask": "0x10", - "EventName": "UOPS_RETIRED.ALL", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "PublicDescription": "This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Reference cycles when core is not halted", + "Counter": "0,1", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF", + "PublicDescription": "This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.", "SampleAfterValue": "2000003", - "BriefDescription": "Micro-ops retired" + "UMask": "0x1" }, { - "PublicDescription": "This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors.", - "EventCode": "0xC3", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "MACHINE_CLEARS.SMC", - "SampleAfterValue": "200003", - "BriefDescription": "Self-Modifying Code detected" + "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", + "Counter": "Fixed counter 3", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "PublicDescription": "This event counts the number of times that pipeline stalled due to FP operations needing assists.", - "EventCode": "0xC3", + "BriefDescription": "Cycles the divider is busy. Does not imply a stall waiting for the divider.", "Counter": "0,1", - "UMask": "0x4", - "EventName": "MACHINE_CLEARS.FP_ASSIST", - "SampleAfterValue": "200003", - "BriefDescription": "Stalls due to FP assists" + "EventCode": "0xCD", + "EventName": "CYCLES_DIV_BUSY.ALL", + "PublicDescription": "Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PublicDescription": "Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions \"older\" than this one will be allowed to finish. This instruction and all \"younger\" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY.", - "EventCode": "0xC3", + "BriefDescription": "Fixed Counter: Counts the number of instructions retired", + "Counter": "Fixed counter 1", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of \"retirement\" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts all machine clears", + "Counter": "0,1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.ALL", + "PublicDescription": "Machine clears happen when something happens in the machine that causes the hardware to need to take special care to get the right answer. When such a condition is signaled on an instruction, the front end of the machine is notified that it must restart, so no more instructions will be decoded from the current path. All instructions \"older\" than this one will be allowed to finish. This instruction and all \"younger\" instructions must be cleared, since they must not be allowed to complete. Essentially, the hardware waits until the problematic instruction is the oldest instruction in the machine. This means all older instructions are retired, and all pending stores (from older instructions) are completed. Then the new path of instructions from the front end are allowed to start into the machine. There are many conditions that might cause a machine clear (including the receipt of an interrupt, or a trap or a fault). All those conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING, MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY event. In addition, some conditions can be specifically counted (i.e. SMC, MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and FP_ASSIST machine clears will not necessarily equal the number of ANY.", "SampleAfterValue": "200003", - "BriefDescription": "Counts all machine clears" + "UMask": "0x8" }, { - "PublicDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available).", - "EventCode": "0xCA", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1", - "UMask": "0x1", - "EventName": "NO_ALLOC_CYCLES.ROB_FULL", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "This event counts the number of times that a program writes to a code section. Self-modifying code causes a severe penalty in all Intel? architecture processors.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)" + "UMask": "0x1" }, { - "PublicDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted.", - "EventCode": "0xCA", + "BriefDescription": "Counts the number of cycles when no uops are allocated for any reason.", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.ALL", + "PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle.", + "SampleAfterValue": "200003", + "UMask": "0x3f" + }, + { + "BriefDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted", + "Counter": "0,1", + "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", + "PublicDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted jump to retire. After the misprediction is detected, the front end will start immediately but the allocate pipe stalls until the mispredicted" + "UMask": "0x4" }, { - "EventCode": "0xCA", + "BriefDescription": "Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation.", "Counter": "0,1", - "UMask": "0x20", + "EventCode": "0xCA", + "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", + "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidth.", + "SampleAfterValue": "200003", + "UMask": "0x50" + }, + { + "BriefDescription": "Counts the number of cycles when no uops are allocated and a RATstall is asserted.", + "Counter": "0,1", + "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.RAT_STALL", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are allocated and a RATstall is asserted." + "UMask": "0x20" }, { - "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is used to measure front-end inefficiencies, i.e. when front-end of the machine is not delivering micro-ops to the back-end and the back-end is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into micro-ops (uops) in machine understandable format and putting them into a micro-op queue to be consumed by back end. The back-end then takes these micro-ops, allocates the required resources. When all resources are ready, micro-ops are executed. If the back-end is not ready to accept micro-ops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more UOPS. This event counts the cycles only when back-end is requesting more uops and front-end is not able to provide them. Some examples of conditions that cause front-end efficiencies are: Icache misses, ITLB misses, and decoder restrictions that limit the the front-end bandwidth.", + "BriefDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available)", + "Counter": "0,1", "EventCode": "0xCA", - "Counter": "0,1", - "UMask": "0x50", - "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", + "EventName": "NO_ALLOC_CYCLES.ROB_FULL", + "PublicDescription": "Counts the number of cycles when no uops are allocated and the ROB is full (less than 2 entries available).", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are allocated, the IQ is empty, and no other condition is blocking allocation." + "UMask": "0x1" }, { - "PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the number of cycles when the front-end does not provide any instructions to be allocated for any reason. This event indicates the cycles where an allocation stalls occurs, and no UOPS are allocated in that cycle.", - "EventCode": "0xCA", + "BriefDescription": "Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts.", "Counter": "0,1", - "UMask": "0x3f", - "EventName": "NO_ALLOC_CYCLES.ALL", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles when no uops are allocated for any reason." - }, - { - "PublicDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M.", "EventCode": "0xCB", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "RS_FULL_STALL.MEC", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M" - }, - { - "EventCode": "0xCB", - "Counter": "0,1", - "UMask": "0x1f", "EventName": "RS_FULL_STALL.ALL", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of cycles the Alloc pipeline is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event is a superset of all the individual RS stall event counts." + "UMask": "0x1f" }, { - "PublicDescription": "This event counts the number of instructions that retire execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers.", - "EventCode": "0xC0", + "BriefDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M", "Counter": "0,1", - "UMask": "0x0", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Instructions retired" - }, - { - "PublicDescription": "Cycles the divider is busy.This event counts the cycles when the divide unit is unable to accept a new divide UOP because it is busy processing a previously dispatched UOP. The cycles will be counted irrespective of whether or not another divide UOP is waiting to enter the divide unit (from the RS). This event might count cycles while a divide is in progress even if the RS is empty. The divide instruction is one of the longest latency instructions in the machine. Hence, it has a special event associated with it to help determine if divides are delaying the retirement of instructions.", - "EventCode": "0xCD", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "CYCLES_DIV_BUSY.ALL", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles the divider is busy. Does not imply a stall waiting for the divider." - }, - { - "PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. Background: Modern microprocessors employ extensive pipelining and speculative techniques. Since sometimes an instruction is started but never completed, the notion of \"retirement\" is introduced. A retired instruction is one that commits its states. Or stated differently, an instruction might be abandoned at some point. No instruction is truly finished until it retires. This counter measures the number of completed instructions. The fixed event is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.", - "Counter": "Fixed counter 1", - "UMask": "0x1", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of instructions retired" - }, - { - "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. In systems with a constant core frequency, this event can give you a measurement of the elapsed time while the core was not in halt state by dividing the event count by the core frequency. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", - "Counter": "Fixed counter 2", - "UMask": "0x2", - "EventName": "CPU_CLK_UNHALTED.CORE", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles" - }, - { - "PublicDescription": "Counts the number of reference cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. Divide this event count by core frequency to determine the elapsed time while the core was not in halt state. This event is architecturally defined and is a designated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the core frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", - "Counter": "Fixed counter 3", - "UMask": "0x3", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "SampleAfterValue": "2000003", - "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles" - }, - { - "PublicDescription": "This event counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time.", - "EventCode": "0x3C", - "Counter": "0,1", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.CORE_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Core cycles when core is not halted" - }, - { - "PublicDescription": "This event counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time.", - "EventCode": "0x3C", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "CPU_CLK_UNHALTED.REF", - "SampleAfterValue": "2000003", - "BriefDescription": "Reference cycles when core is not halted" - }, - { - "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.ANY event counts the number of baclears for any type of branch.", - "EventCode": "0xE6", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "BACLEARS.ALL", + "EventCode": "0xCB", + "EventName": "RS_FULL_STALL.MEC", + "PublicDescription": "Counts the number of cycles and allocation pipeline is stalled and is waiting for a free MEC reservation station entry. The cycles should be appropriately counted in case of the cracked ops e.g. In case of a cracked load-op, the load portion is sent to M.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of baclears" + "UMask": "0x1" }, { - "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.RETURN event counts the number of RETURN baclears.", - "EventCode": "0xE6", + "BriefDescription": "Micro-ops retired", "Counter": "0,1", - "UMask": "0x8", - "EventName": "BACLEARS.RETURN", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of RETURN baclears" + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ALL", + "PublicDescription": "This event counts the number of micro-ops retired. The processor decodes complex macro instructions into a sequence of simpler micro-ops. Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. In some cases micro-op sequences are fused or whole instructions are fused into one micro-op. See other UOPS_RETIRED events for differentiating retired fused and non-fused micro-ops.", + "SampleAfterValue": "2000003", + "UMask": "0x10" }, { - "PublicDescription": "The BACLEARS event counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. The BACLEARS.COND event counts the number of JCC (Jump on Condtional Code) baclears.", - "EventCode": "0xE6", + "BriefDescription": "MSROM micro-ops retired", "Counter": "0,1", - "UMask": "0x10", - "EventName": "BACLEARS.COND", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of JCC baclears" - }, - { - "PEBS": "2", - "PublicDescription": "ALL_TAKEN_BRANCHES counts the number of all taken branch instructions retired. Branch prediction predicts the branch target and enables the processor to begin executing instructions long before the branch true execution path is known. All branches utilize the branch prediction unit (BPU) for prediction. This unit predicts the target address not only based on the EIP of the branch but also based on the execution path through which execution reached this EIP. The BPU can efficiently predict the following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, returns.", - "EventCode": "0xC4", - "Counter": "0,1", - "UMask": "0x80", - "PEBScounters": "0,1", - "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of taken branch instructions retired" + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.MS", + "PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.", + "SampleAfterValue": "2000003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json index ad31479f8f60..f4b8a1ef48f6 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json @@ -1,69 +1,69 @@ [ { + "BriefDescription": "Loads missed DTLB", + "Counter": "0,1", + "EventCode": "0x04", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", "PEBS": "1", "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.", - "EventCode": "0x04", - "Counter": "0,1", - "UMask": "0x8", - "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", "SampleAfterValue": "200003", - "BriefDescription": "Loads missed DTLB" + "UMask": "0x8" }, { - "PublicDescription": "This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", - "EventCode": "0x05", + "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)", "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_WALKS", - "SampleAfterValue": "100003", - "BriefDescription": "D-side page-walks", - "EdgeDetect": "1" - }, - { - "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", "EventCode": "0x05", - "Counter": "0,1", - "UMask": "0x1", - "EventName": "PAGE_WALKS.D_SIDE_CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Duration of D-side page-walks in core cycles" - }, - { - "PublicDescription": "This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", - "EventCode": "0x05", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_WALKS", - "SampleAfterValue": "100003", - "BriefDescription": "I-side page-walks", - "EdgeDetect": "1" - }, - { - "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", - "EventCode": "0x05", - "Counter": "0,1", - "UMask": "0x2", - "EventName": "PAGE_WALKS.I_SIDE_CYCLES", - "SampleAfterValue": "200003", - "BriefDescription": "Duration of I-side page-walks in core cycles" - }, - { - "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", - "EventCode": "0x05", - "Counter": "0,1", - "UMask": "0x3", - "EventName": "PAGE_WALKS.WALKS", - "SampleAfterValue": "100003", - "BriefDescription": "Total page walks that are completed (I-side and D-side)", - "EdgeDetect": "1" - }, - { - "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.", - "EventCode": "0x05", - "Counter": "0,1", - "UMask": "0x3", "EventName": "PAGE_WALKS.CYCLES", + "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.", "SampleAfterValue": "200003", - "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)" + "UMask": "0x3" + }, + { + "BriefDescription": "Duration of D-side page-walks in core cycles", + "Counter": "0,1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.D_SIDE_CYCLES", + "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "D-side page-walks", + "Counter": "0,1", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.D_SIDE_WALKS", + "PublicDescription": "This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Duration of I-side page-walks in core cycles", + "Counter": "0,1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.I_SIDE_CYCLES", + "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "I-side page-walks", + "Counter": "0,1", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.I_SIDE_WALKS", + "PublicDescription": "This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Total page walks that are completed (I-side and D-side)", + "Counter": "0,1", + "EdgeDetect": "1", + "EventCode": "0x05", + "EventName": "PAGE_WALKS.WALKS", + "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", + "SampleAfterValue": "100003", + "UMask": "0x3" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json index 27ea2b00ad00..c5d9a4ed10d7 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json @@ -1,1633 +1,4 @@ [ - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0080001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", - "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", - "SampleAfterValue": "100003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts all demand code readshave any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", - "Offcore": "1", - "PublicDescription": "Counts all demand code readshave any response type.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.PF_MISS", - "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x38" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC01C0004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040100001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_MISS", - "PublicDescription": "Demand requests that miss L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x27" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080028000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040080004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions with L3 cache hits as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L3_HIT", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", - "SampleAfterValue": "50021", - "UMask": "0x4" - }, - { - "BriefDescription": "L2 writebacks that access L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF0", - "EventName": "L2_TRANS.L2_WB", - "PublicDescription": "Counts L2 writebacks that access L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x40" - }, - { - "BriefDescription": "L2 cache lines filling L2", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF1", - "EventName": "L2_LINES_IN.ALL", - "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", - "SampleAfterValue": "100003", - "UMask": "0x1f" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00401C0002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand Data Read requests sent to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", - "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001C0004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801C0002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions missed L3 cache as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L3_MISS", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", - "SampleAfterValue": "100007", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040020001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "All retired store instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.ALL_STORES", - "L1_Hit_Indication": "1", - "PEBS": "1", - "SampleAfterValue": "2000003", - "UMask": "0x82" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.SILENT", - "SampleAfterValue": "200003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040048000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000088000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001C0002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", - "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001C0004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000028000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200028000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001C0001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001C8000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Core-originated cacheable demand requests missed L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL057", - "EventCode": "0x2E", - "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.", - "SampleAfterValue": "100003", - "UMask": "0x41" - }, - { - "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_PF", - "PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.", - "SampleAfterValue": "200003", - "UMask": "0xf8" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0080004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040040002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100028000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", - "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "RFO requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_MISS", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x22" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400040001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.NON_SILENT", - "SampleAfterValue": "200003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040028000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.USELESS_HWPF", - "SampleAfterValue": "200003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)have any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)have any response type.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001C0002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00401C0004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "All requests that miss L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.MISS", - "PublicDescription": "All requests that miss L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0x3f" - }, - { - "BriefDescription": "L2 code requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_CODE_RD", - "PublicDescription": "Counts the total number of L2 code requests.", - "SampleAfterValue": "200003", - "UMask": "0xe4" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0100002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "RFO requests that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.RFO_HIT", - "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0xc2" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080048000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", - "PEBS": "1", - "PublicDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache.", - "SampleAfterValue": "20011", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001C0001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0028000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000080004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions missed L1 cache as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L1_MISS", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "L2 cache misses when fetching instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_MISS", - "PublicDescription": "Counts L2 cache misses when fetching instructions.", - "SampleAfterValue": "200003", - "UMask": "0x24" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001C0001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", - "PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040080002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC01C0001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400028000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400088000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001C8000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", - "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Demand requests to L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", - "PublicDescription": "Demand requests to L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0xe7" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100048000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000020001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040100002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0040002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "AnyThread": "1", - "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC01C8000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x02001C0001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200088000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Core-originated cacheable demand requests that refer to L3", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL057", - "EventCode": "0x2E", - "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3.", - "SampleAfterValue": "100003", - "UMask": "0x4f" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200048000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0020004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040080001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0040004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040040001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100020004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions that miss the STLB.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", - "PEBS": "1", - "SampleAfterValue": "100003", - "UMask": "0x11" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data readshave any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", - "Offcore": "1", - "PublicDescription": "Counts demand data readshave any response type.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001C8000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "L1D data line replacements", "Counter": "0,1,2,3", @@ -1639,226 +10,23 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200040004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD4", - "EventName": "MEM_LOAD_MISC_RETIRED.UC", - "PEBS": "1", - "SampleAfterValue": "100007", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.FB_HIT", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", - "SampleAfterValue": "100007", - "UMask": "0x40" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0020001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", + "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF2", - "EventName": "L2_LINES_OUT.USELESS_PREF", - "SampleAfterValue": "200003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.PF_HIT", - "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.", - "SampleAfterValue": "200003", - "UMask": "0xd8" - }, - { - "BriefDescription": "Demand Data Read miss L2, no rejects", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", - "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", - "SampleAfterValue": "200003", - "UMask": "0x21" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040020004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400100001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", - "PEBS": "1", - "PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops required.", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "All retired load instructions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.ALL_LOADS", - "PEBS": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.", "SampleAfterValue": "2000003", - "UMask": "0x81" + "UMask": "0x2" }, { - "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", - "PEBS": "1", - "SampleAfterValue": "20011", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand Data Read requests", + "BriefDescription": "L1D miss outstandings duration in cycles", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", - "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", - "SampleAfterValue": "200003", - "UMask": "0xe1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "All L2 requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.REFERENCES", - "PublicDescription": "All L2 requests.", - "SampleAfterValue": "200003", - "UMask": "0xff" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { @@ -1873,217 +41,142 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100088000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", + "AnyThread": "1", + "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", - "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0048000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00401C8000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of cache line split locks sent to uncore.", + "BriefDescription": "L2 cache lines filling L2", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xF4", - "EventName": "SQ_MISC.SPLIT_LOCK", - "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", + "EventCode": "0xF1", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", "SampleAfterValue": "100003", - "UMask": "0x10" + "UMask": "0x1f" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC01C0002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10001C0002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions with L2 cache hits as data sources", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD1", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "PEBS": "1", - "PublicDescription": "Retired load instructions with L2 cache hits as data sources.", - "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.NON_SILENT", + "SampleAfterValue": "200003", "UMask": "0x2" }, { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0040001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000020004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "L1D miss outstandings duration in cycles", + "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.PENDING", - "PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", - "SampleAfterValue": "2000003", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.SILENT", + "SampleAfterValue": "200003", "UMask": "0x1" }, + { + "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event L2_LINES_OUT.USELESS_HWPF", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF2", + "EventName": "L2_LINES_OUT.USELESS_PREF", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_CODE_RD", + "PublicDescription": "Counts the total number of L2 code requests.", + "SampleAfterValue": "200003", + "UMask": "0xe4" + }, + { + "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", + "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0xe1" + }, + { + "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PublicDescription": "Demand requests that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x27" + }, + { + "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "PublicDescription": "Demand requests to L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xe7" + }, + { + "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_PF", + "PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.", + "SampleAfterValue": "200003", + "UMask": "0xf8" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "UMask": "0xe2" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, code reads.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Counts L2 cache misses when fetching instructions.", + "SampleAfterValue": "200003", + "UMask": "0x24" + }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", "Counter": "0,1,2,3", @@ -2095,68 +188,165 @@ "UMask": "0xc1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Demand Data Read miss L2, no rejects", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", + "SampleAfterValue": "200003", + "UMask": "0x21" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "All requests that miss L2 cache", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04001C0004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "PublicDescription": "All requests that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x3f" }, { - "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3", + "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_HIT", + "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xd8" + }, + { + "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PF_MISS", + "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x38" + }, + { + "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PublicDescription": "All L2 requests.", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc2" + }, + { + "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x22" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF0", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Core-originated cacheable demand requests missed L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL057", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Core-originated cacheable demand requests that refer to L3", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL057", + "EventCode": "0x2E", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all accesses to the L3.", + "SampleAfterValue": "100003", + "UMask": "0x4f" + }, + { + "BriefDescription": "All retired load instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xD2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ALL_LOADS", "PEBS": "1", - "PublicDescription": "Retired load instructions which data sources were HitM responses from shared L3.", - "SampleAfterValue": "20011", - "UMask": "0x4" + "SampleAfterValue": "2000003", + "UMask": "0x81" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "All retired store instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0100001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ALL_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x82" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "All retired memory instructions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001C0002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "SampleAfterValue": "2000003", + "UMask": "0x83" + }, + { + "BriefDescription": "Retired load instructions with locked access.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0x41" }, { "BriefDescription": "Retired store instructions that split across a cacheline boundary.", @@ -2172,380 +362,99 @@ "UMask": "0x42" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Retired load instructions that miss the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0x11" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Retired store instructions that miss the STLB.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000100004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0x12" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801C0004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Any memory transaction that reached the SQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", - "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..", - "SampleAfterValue": "100003", - "UMask": "0x80" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requestshave any response type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000018000", - "Offcore": "1", - "PublicDescription": "Counts any other requestshave any response type.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cacheable and noncachaeble code read requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", - "PublicDescription": "Counts both cacheable and non-cacheable code read requests.", - "SampleAfterValue": "100003", + "Data_LA": "1", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache.", + "SampleAfterValue": "20011", "UMask": "0x2" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040040004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "Data_LA": "1", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources were HitM responses from shared L3.", + "SampleAfterValue": "20011", + "UMask": "0x4" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", + "Data_LA": "1", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "SampleAfterValue": "20011", "UMask": "0x1" }, { - "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", - "PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0088000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", + "Data_LA": "1", + "EventCode": "0xD2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops required.", "SampleAfterValue": "100003", - "UMask": "0x1" + "UMask": "0x8" }, { - "BriefDescription": "L2 cache hits when fetching instructions, code reads.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.CODE_RD_HIT", - "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.", - "SampleAfterValue": "200003", - "UMask": "0xc4" - }, - { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "Data_LA": "1", + "EventCode": "0xD4", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x4" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100040004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080088000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000040001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040088000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100100004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040100004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x48", - "EventName": "L1D_PEND_MISS.FB_FULL", - "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400048000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0040108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000048000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400080004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200100004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801C0001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.", + "SampleAfterValue": "100007", + "UMask": "0x40" }, { "BriefDescription": "Retired load instructions with L1 cache hits as data sources", @@ -2560,295 +469,29 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1000408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0100004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions with locked access.", + "BriefDescription": "Retired load instructions missed L1 cache as data sources", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", "PEBS": "1", - "SampleAfterValue": "100007", - "UMask": "0x21" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00801C8000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080040002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001C0004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand and prefetch data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", - "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.", "SampleAfterValue": "100003", "UMask": "0x8" }, { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired load instructions that split across a cacheline boundary.", + "BriefDescription": "Retired load instructions with L2 cache hits as data sources", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", - "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.", + "PublicDescription": "Retired load instructions with L2 cache hits as data sources.", "SampleAfterValue": "100003", - "UMask": "0x41" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0100080001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB2", - "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", - "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "6", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", - "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", - "SampleAfterValue": "2000003", "UMask": "0x2" }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080100002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired store instructions that miss the STLB.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xD0", - "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", - "L1_Hit_Indication": "1", - "PEBS": "1", - "SampleAfterValue": "100003", - "UMask": "0x12" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200080001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01001C8000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "RFO requests to L2 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x24", - "EventName": "L2_RQSTS.ALL_RFO", - "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", - "SampleAfterValue": "200003", - "UMask": "0xe2" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0200400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Retired load instructions missed L2 cache as data sources", "Counter": "0,1,2,3", @@ -2862,29 +505,87 @@ "UMask": "0x10" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Retired load instructions with L3 cache hits as data sources", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0400020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.", + "SampleAfterValue": "50021", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions missed L3 cache as data sources", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD1", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.", + "SampleAfterValue": "100007", + "UMask": "0x20" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", + "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Cacheable and noncachaeble code read requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Counts both cacheable and non-cacheable code read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0080080001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", + "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { @@ -2898,15 +599,746 @@ "UMask": "0x8" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", + "PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", + "EventName": "OFFCORE_RESPONSE", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code readshave any response type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC0080002", + "MSRValue": "0x10004", "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC01C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0020004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400020004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200020004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80020004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100020004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40020004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data readshave any response type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC01C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -2917,10 +1349,1629 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00401C0001", + "MSRValue": "0x401C0001", "Offcore": "1", - "PublicDescription": "Counts demand data reads", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0020001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400020001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200020001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80020001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100020001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40020001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)have any response type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC01C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0020002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000020002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400020002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200020002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80020002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100020002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40020002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requestshave any response type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC01C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401C8000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC0028000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000028000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400028000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200028000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80028000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100028000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40028000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of cache line split locks sent to uncore.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "SampleAfterValue": "2000003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json index 834e1cd841fc..73cfb2a39722 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json @@ -1,40 +1,64 @@ [ { - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", - "UMask": "0x2" + "UMask": "0x8" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, + { + "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, { "BriefDescription": "Cycles with any input/output SSE or FP assist", "Counter": "0,1,2,3", @@ -45,23 +69,5 @@ "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", "SampleAfterValue": "100003", "UMask": "0x1e" - }, - { - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC7", - "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC7", - "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", - "SampleAfterValue": "2000003", - "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/perf/pmu-events/arch/x86/skylake/frontend.json index e84504d6adea..ecce4273ae52 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json @@ -1,13 +1,61 @@ [ { - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", + "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x80", - "EventName": "ICACHE_16B.IFDATA_STALL", - "PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", + "EventCode": "0xE6", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.COUNT", + "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.", "SampleAfterValue": "2000003", - "UMask": "0x4" + "UMask": "0x1" + }, + { + "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAB", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "PEBS": "1", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" }, { "BriefDescription": "Retired Instructions who experienced iTLB true miss.", @@ -24,153 +72,18 @@ "UMask": "0x1" }, { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", - "MSRValue": "0x408006", + "MSRValue": "0x12", "PEBS": "1", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" }, - { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.DSB_CYCLES", - "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", - "PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xE6", - "EventName": "BACLEARS.ANY", - "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.DSB_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x11", - "PEBS": "1", - "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", - "PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", - "MSRIndex": "0x3F7", - "MSRValue": "0x401006", - "PEBS": "1", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x79", - "EventName": "IDQ.MITE_UOPS", - "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", - "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MS_CYCLES", - "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", - "SampleAfterValue": "2000003", - "UMask": "0x30" - }, - { - "BriefDescription": "Cycles MITE is delivering any Uop", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", - "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "UMask": "0x24" - }, - { - "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_HIT", - "SampleAfterValue": "200003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x79", - "EventName": "IDQ.MS_SWITCHES", - "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", - "SampleAfterValue": "2000003", - "UMask": "0x30" - }, { "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.", "Counter": "0,1,2,3", @@ -184,131 +97,6 @@ "TakenAlone": "1", "UMask": "0x1" }, - { - "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MITE_CYCLES", - "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", - "MSRIndex": "0x3F7", - "MSRValue": "0x404006", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", - "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x79", - "EventName": "IDQ.MS_MITE_UOPS", - "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", - "SampleAfterValue": "2000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x83", - "EventName": "ICACHE_64B.IFTAG_STALL", - "SampleAfterValue": "200003", - "UMask": "0x4" - }, - { - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xAB", - "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", - "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", - "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", - "SampleAfterValue": "2000003", - "UMask": "0x18" - }, - { - "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.STLB_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x15", - "PEBS": "1", - "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x79", - "EventName": "IDQ.DSB_UOPS", - "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", - "MSRIndex": "0x3F7", - "MSRValue": "0x420006", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", - "MSRIndex": "0x3F7", - "MSRValue": "0x400806", - "PEBS": "1", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, { "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle", "Counter": "0,1,2,3", @@ -323,6 +111,33 @@ "TakenAlone": "1", "UMask": "0x1" }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "MSRIndex": "0x3F7", + "MSRValue": "0x408006", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "MSRIndex": "0x3F7", + "MSRValue": "0x401006", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, { "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", @@ -336,51 +151,6 @@ "TakenAlone": "1", "UMask": "0x1" }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", - "MSRIndex": "0x3F7", - "MSRValue": "0x400406", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles MITE is delivering 4 Uops", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0x79", - "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", - "PublicDescription": "Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", - "SampleAfterValue": "2000003", - "UMask": "0x24" - }, - { - "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x79", - "EventName": "IDQ.MS_DSB_CYCLES", - "PublicDescription": "Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x79", - "EventName": "IDQ.MS_UOPS", - "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", - "SampleAfterValue": "2000003", - "UMask": "0x30" - }, { "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", @@ -394,6 +164,20 @@ "TakenAlone": "1", "UMask": "0x1" }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, { "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 2 bubble-slots for a period of 2 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", @@ -420,41 +204,6 @@ "TakenAlone": "1", "UMask": "0x1" }, - { - "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", - "MSRIndex": "0x3F7", - "MSRValue": "0x100206", - "PEBS": "1", - "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0x79", - "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", - "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", - "SampleAfterValue": "2000003", - "UMask": "0x18" - }, - { - "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xAB", - "EventName": "DSB2MITE_SWITCHES.COUNT", - "PublicDescription": "This event counts the number of the Decode Stream Buffer (DSB)-to-MITE switches including all misses because of missing Decode Stream Buffer (DSB) cache and u-arch forced misses.\nNote: Invoking MITE requires two or three cycles delay.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, { "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.", "Counter": "0,1,2,3", @@ -470,14 +219,89 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "MSRIndex": "0x3F7", + "MSRValue": "0x400406", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "MSRIndex": "0x3F7", + "MSRValue": "0x420006", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "MSRIndex": "0x3F7", + "MSRValue": "0x404006", + "PEBS": "1", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "MSRIndex": "0x3F7", + "MSRValue": "0x400806", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x9C", - "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", - "Invert": "1", + "EventCode": "0x80", + "EventName": "ICACHE_16B.IFDATA_STALL", + "PublicDescription": "Cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.", "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_HIT", + "SampleAfterValue": "200003", "UMask": "0x1" }, { @@ -490,16 +314,206 @@ "UMask": "0x2" }, { - "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.", + "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC6", - "EventName": "FRONTEND_RETIRED.L1I_MISS", - "MSRIndex": "0x3F7", - "MSRValue": "0x12", - "PEBS": "1", - "SampleAfterValue": "100007", - "TakenAlone": "1", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x83", + "EventName": "ICACHE_64B.IFTAG_STALL", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", + "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", + "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x18" + }, + { + "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", + "PublicDescription": "Counts the number of cycles 4 uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", + "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. Counting includes uops that may 'bypass' the IDQ. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x24" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may 'bypass' the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES", + "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_DSB_CYCLES", + "PublicDescription": "Counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_MITE_UOPS", + "PublicDescription": "Counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.", + "SampleAfterValue": "2000003", + "UMask": "0x30" + }, + { + "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "Counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread. b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions). c. Instruction Decode Queue (IDQ) delivers four uops.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "Counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", + "PublicDescription": "Counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >= 3.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0x9C", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", + "PublicDescription": "Cycles with less than 2 uops delivered by the front-end.", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { diff --git a/tools/perf/pmu-events/arch/x86/skylake/memory.json b/tools/perf/pmu-events/arch/x86/skylake/memory.json index 7bd3ae338343..8500fc65e0e8 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/memory.json +++ b/tools/perf/pmu-events/arch/x86/skylake/memory.json @@ -1,108 +1,261 @@ [ { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000080004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times HLE abort was triggered.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_EVENTS", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_MEM", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", + "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_TIMER", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an HLE execution successfully committed", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.COMMIT", + "PublicDescription": "Number of times HLE commit succeeded.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC8", + "EventName": "HLE_RETIRED.START", + "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL089", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "1009", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000100002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "20011", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084008000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "503", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x007C400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "100007", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", "SampleAfterValue": "100003", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "101", + "TakenAlone": "1", "UMask": "0x1" }, { - "BriefDescription": "Counts any other requests", + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000088000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "2003", + "TakenAlone": "1", "UMask": "0x1" }, + { + "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", + "SampleAfterValue": "50021", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand Data Read requests who miss L3 cache", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "PublicDescription": "Demand Data Read requests who miss L3 cache.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, { "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", "Counter": "0,1,2,3", @@ -113,16 +266,926 @@ "SampleAfterValue": "2000003", "UMask": "0x10" }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20001C0004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000080004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000040004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000100004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFC400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103C400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x43C400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x23C400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xBC400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203C400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x13C400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7C400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC4000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x404000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x204000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x44000004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000400004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020004", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20001C0001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000080001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000040001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000100001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFC400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103C400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x43C400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x23C400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xBC400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203C400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x13C400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7C400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC4000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x404000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x204000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x44000001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000400001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020001", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20001C0002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000080002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000040002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000100002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFC400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103C400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x43C400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x23C400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xBC400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203C400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x13C400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7C400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC4000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x404000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x204000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x44000002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000400002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000020002", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts any other requests", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC408000", + "MSRValue": "0x20001C8000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000088000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000048000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000108000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FFC408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -135,44 +1198,238 @@ "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x103C408000", "Offcore": "1", - "PublicDescription": "Counts any other requests", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x43C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x23C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xBC408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x13C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7C408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FC4008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x404008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x204008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x84008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x44008000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000408000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000028000", + "Offcore": "1", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_TIMER", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", + "PublicDescription": "Number of times RTM abort was triggered.", "SampleAfterValue": "2000003", - "UMask": "0x10" + "UMask": "0x4" }, { - "BriefDescription": "Counts demand data reads", + "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_EVENTS", + "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "SampleAfterValue": "2000003", + "UMask": "0x80" }, { "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", @@ -195,241 +1452,80 @@ "UMask": "0x40" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000080002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1004008000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", + "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_TIMER", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", + "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of times an RTM execution successfully committed", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.COMMIT", + "PublicDescription": "Number of times RTM commit succeeded.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000028000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFC408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", - "MSRIndex": "0x3F6", - "MSRValue": "0x20", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "100007", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000020004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0044000002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204008000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", + "BriefDescription": "Number of times an RTM execution started.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", - "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "EventCode": "0xC9", + "EventName": "RTM_RETIRED.START", + "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC1", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC2", + "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC3", + "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x103C400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", + "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Number of times a TSX line had a cache conflict.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1004000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000080001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", - "MSRIndex": "0x3F6", - "MSRValue": "0x40", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "2003", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0204000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000020002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", - "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", + "EventCode": "0x5d", + "EventName": "TX_EXEC.MISC4", + "PublicDescription": "RTM region detected inside HLE.", "SampleAfterValue": "2000003", "UMask": "0x8" }, @@ -443,767 +1539,6 @@ "SampleAfterValue": "2000003", "UMask": "0x10" }, - { - "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC4", - "PublicDescription": "RTM region detected inside HLE.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC3", - "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC2", - "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5d", - "EventName": "TX_EXEC.MISC1", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an RTM execution successfully committed", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.COMMIT", - "PublicDescription": "Number of times RTM commit succeeded.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000100001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x103C400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000048000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x203C400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x007C408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104000004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.ABORTED_TIMER", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2004000004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1004000004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0044008000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0044000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", - "SampleAfterValue": "2000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000040004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x20001C0004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x103C400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404008000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0104008000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an HLE execution successfully committed", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.COMMIT", - "PublicDescription": "Number of times HLE commit succeeded.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000020001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x203C408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000040002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Demand Data Read requests who miss L3 cache", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB0", - "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", - "PublicDescription": "Demand Data Read requests who miss L3 cache.", - "SampleAfterValue": "100003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2004000002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFC400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", - "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", - "SampleAfterValue": "2000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_MEM", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", - "MSRIndex": "0x3F6", - "MSRValue": "0x100", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "503", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x203C400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x007C400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC4008000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.ABORTED", - "PEBS": "1", - "PublicDescription": "Number of times RTM abort was triggered.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED", - "PEBS": "1", - "PublicDescription": "Number of times HLE abort was triggered.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x203C400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", - "MSRIndex": "0x3F6", - "MSRValue": "0x10", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "20011", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2004008000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", - "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", - "SampleAfterValue": "2000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x60", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC4000004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", - "MSRIndex": "0x3F6", - "MSRValue": "0x200", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "101", - "TakenAlone": "1", - "UMask": "0x1" - }, { "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", "Counter": "0,1,2,3", @@ -1214,49 +1549,15 @@ "UMask": "0x2" }, { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0084000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", + "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", - "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", - "SampleAfterValue": "2000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Number of times an RTM execution started.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_CONFLICT", + "PublicDescription": "Number of times a TSX line had a cache conflict.", "SampleAfterValue": "2000003", "UMask": "0x1" }, - { - "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL089", - "EventCode": "0xC3", - "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", - "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, { "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", "Counter": "0,1,2,3", @@ -1268,195 +1569,34 @@ "UMask": "0x10" }, { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x20001C0002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x1004000002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x20001C0001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC4000002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x007C400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000100004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x00BC400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x043C400001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFC400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", + "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC9", - "EventName": "RTM_RETIRED.ABORTED_EVENTS", - "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", + "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", "SampleAfterValue": "2000003", - "UMask": "0x80" + "UMask": "0x8" }, { - "BriefDescription": "Number of times an HLE execution started.", + "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.START", - "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", + "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", "SampleAfterValue": "2000003", - "UMask": "0x1" + "UMask": "0x20" }, { - "BriefDescription": "Counts all demand code reads", + "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FFC400004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2004000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3FC4000001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", - "MSRIndex": "0x3F6", - "MSRValue": "0x80", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "1009", - "TakenAlone": "1", - "UMask": "0x1" + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x54", + "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", + "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", + "SampleAfterValue": "2000003", + "UMask": "0x4" }, { "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", @@ -1467,145 +1607,5 @@ "PublicDescription": "Number of times we could not allocate Lock Buffer.", "SampleAfterValue": "2000003", "UMask": "0x40" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000108000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand code reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SPL_HIT", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0044000004", - "Offcore": "1", - "PublicDescription": "Counts all demand code reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x013C400002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "6", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", - "SampleAfterValue": "2000003", - "UMask": "0x6" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x023C408000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC8", - "EventName": "HLE_RETIRED.ABORTED_EVENTS", - "SampleAfterValue": "2000003", - "UMask": "0x80" - }, - { - "BriefDescription": "Counts any other requests", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x20001C8000", - "Offcore": "1", - "PublicDescription": "Counts any other requests", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand data reads", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_DRAM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x2000040001", - "Offcore": "1", - "PublicDescription": "Counts demand data reads", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", - "MSRIndex": "0x3F6", - "MSRValue": "0x4", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "100003", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Data_LA": "1", - "EventCode": "0xcd", - "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", - "MSRIndex": "0x3F6", - "MSRValue": "0x8", - "PEBS": "2", - "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", - "SampleAfterValue": "50021", - "TakenAlone": "1", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts all demand data writes (RFOs)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0404000002", - "Offcore": "1", - "PublicDescription": "Counts all demand data writes (RFOs)", - "SampleAfterValue": "100003", - "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json index 1a3683f1de91..4f4839024915 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json @@ -1,22 +1,4 @@ [ - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, { "BriefDescription": "Number of hardware interrupts received by the processor.", "Counter": "0,1,2,3", @@ -27,24 +9,6 @@ "SampleAfterValue": "203", "UMask": "0x1" }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, { "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json index f46e93a57fb4..12eabae3e224 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json @@ -1,36 +1,4 @@ [ - { - "BriefDescription": "Number of instructions retired. General Counter - architectural event", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091, SKL044", - "EventCode": "0xC0", - "EventName": "INST_RETIRED.ANY_P", - "PublicDescription": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", - "SampleAfterValue": "2000003" - }, - { - "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.STALL_CYCLES", - "Invert": "1", - "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", - "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, { "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.", "Counter": "0,1,2,3", @@ -42,15 +10,50 @@ "UMask": "0x1" }, { - "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "BriefDescription": "All (macro) branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x07", - "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", - "PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", - "SampleAfterValue": "100003", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PublicDescription": "Counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts conditional branch instructions retired.", + "SampleAfterValue": "400009", "UMask": "0x1" }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "PublicDescription": "This event counts not taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, { "BriefDescription": "Far branch instructions retired.", "Counter": "0,1,2,3", @@ -64,23 +67,81 @@ "UMask": "0x40" }, { - "BriefDescription": "Counts the number of x87 uops dispatched.", + "BriefDescription": "Direct and indirect near call instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.X87", - "PublicDescription": "Counts the number of x87 uops executed.", - "SampleAfterValue": "2000003", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "This event counts both direct and indirect near call instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "This event counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "This event counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NOT_TAKEN", + "PublicDescription": "This event counts not taken branch instructions retired.", + "SampleAfterValue": "400009", "UMask": "0x10" }, { - "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "BriefDescription": "All mispredicted macro branch instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x4C", - "EventName": "LOAD_HIT_PRE.SW_PF", - "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", - "SampleAfterValue": "100003", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", + "SampleAfterValue": "400009" + }, + { + "BriefDescription": "Mispredicted macro branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", + "PEBS": "2", + "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x4" + }, + { + "BriefDescription": "Mispredicted conditional branch instructions retired.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.CONDITIONAL", + "PEBS": "1", + "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", + "SampleAfterValue": "400009", "UMask": "0x1" }, { @@ -95,33 +156,106 @@ "UMask": "0x2" }, { - "BriefDescription": "Total execution stalls.", + "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.SLOW_LEA", - "SampleAfterValue": "2000003", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "SampleAfterValue": "400009", "UMask": "0x20" }, { - "BriefDescription": "Cycles with less than 10 actually retired uops.", + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "10", - "EventCode": "0xC2", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "Invert": "1", - "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "25003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", + "SampleAfterValue": "25003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "25003", + "UMask": "0x1" + }, + { + "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "SampleAfterValue": "25003", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when the core is not in halt state.", + "Counter": "Fixed counter 2", + "CounterHTOff": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", + "SampleAfterValue": "2000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK", + "SampleAfterValue": "25003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", + "SampleAfterValue": "25003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.RING0_TRANS", + "PublicDescription": "Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).", + "SampleAfterValue": "100007" + }, + { + "BriefDescription": "Core cycles when the thread is not in halt state", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", + "Counter": "Fixed counter 1", + "CounterHTOff": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, @@ -135,23 +269,308 @@ "SampleAfterValue": "2000003" }, { - "BriefDescription": "Cycles where at least 2 uops were executed per-thread", + "AnyThread": "1", + "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", - "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "8", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", + "BriefDescription": "Cycles while memory subsystem has an outstanding load.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", - "SampleAfterValue": "25003", + "CounterMask": "16", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "12", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "2000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "CounterMask": "20", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x14" + }, + { + "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA6", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of the instruction.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x87", + "EventName": "ILD_STALL.LCP", + "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", + "CounterHTOff": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of instructions retired. General Counter - architectural event", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.ANY_P", + "PublicDescription": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", + "Counter": "1", + "CounterHTOff": "1", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "2", + "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.", + "Counter": "0,2,3", + "CounterHTOff": "0,2,3", + "CounterMask": "10", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "PublicDescription": "Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16)", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "AnyThread": "1", + "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0D", + "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "False dependencies in MOB due to partial compare on address.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x07", + "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", + "PublicDescription": "Counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4C", + "EventName": "LOAD_HIT_PRE.SW_PF", + "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_4_UOPS", + "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.CYCLES_ACTIVE", + "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xA8", + "EventName": "LSD.UOPS", + "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).", + "SampleAfterValue": "2000003", "UMask": "0x1" }, { @@ -166,95 +585,96 @@ "UMask": "0x1" }, { - "AnyThread": "1", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "BriefDescription": "Self-modifying code (SMC) detected.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.THREAD", - "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "EventCode": "0xC3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xC1", + "EventName": "OTHER_ASSISTS.ANY", + "SampleAfterValue": "100003", + "UMask": "0x3f" + }, + { + "BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x59", + "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", + "PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Cycles where at least 3 uops were executed per-thread", + "BriefDescription": "Resource-related stall cycles", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "3", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", - "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.ANY", + "PublicDescription": "Counts resource-related stall cycles.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", + "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", - "Invert": "1", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Cycles where the Store Buffer was full and no outstanding load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", - "SampleAfterValue": "2000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "8", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "EventCode": "0xA2", + "EventName": "RESOURCE_STALLS.SB", + "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { - "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.", + "BriefDescription": "Increments whenever there is an update to the LBR array.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", + "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xCC", + "EventName": "ROB_MISC_EVENTS.PAUSE_INST", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_CYCLES", + "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0xA8", - "EventName": "LSD.CYCLES_ACTIVE", - "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).", + "EdgeDetect": "1", + "EventCode": "0x5E", + "EventName": "RS_EVENTS.EMPTY_END", + "Invert": "1", + "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues.", "SampleAfterValue": "2000003", "UMask": "0x1" }, - { - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.RECOVERY_CYCLES", - "PublicDescription": "Core cycles the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Core crystal clock cycles when the thread is unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK", - "SampleAfterValue": "25003", - "UMask": "0x1" - }, { "BriefDescription": "Cycles per thread when uops are executed in port 0", "Counter": "0,1,2,3", @@ -336,108 +756,12 @@ "UMask": "0x80" }, { - "AnyThread": "1", - "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).", + "BriefDescription": "Number of uops executed on the core.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", - "Counter": "1", - "CounterHTOff": "1", - "Errata": "SKL091, SKL044", - "EventCode": "0xC0", - "EventName": "INST_RETIRED.PREC_DIST", - "PEBS": "2", - "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "4", - "EventCode": "0xA8", - "EventName": "LSD.CYCLES_4_UOPS", - "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector).", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", - "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.STORE_FORWARD", - "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "AnyThread": "1", - "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "25003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles where the pipeline is stalled due to serializing operations.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x59", - "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", - "PublicDescription": "This event counts cycles during which the microcode scoreboard stalls happen.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "Invert": "1", - "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Not taken branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xc4", - "EventName": "BR_INST_RETIRED.COND_NTAKEN", - "PublicDescription": "This event counts not taken branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x10" - }, - { - "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "3", "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Number of uops executed from any thread.", "SampleAfterValue": "2000003", "UMask": "0x2" }, @@ -451,6 +775,26 @@ "SampleAfterValue": "2000003", "UMask": "0x2" }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, { "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.", "Counter": "0,1,2,3", @@ -462,207 +806,49 @@ "UMask": "0x2" }, { - "BriefDescription": "Reference cycles when the core is not in halt state.", - "Counter": "Fixed counter 2", - "CounterHTOff": "Fixed counter 2", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.", - "SampleAfterValue": "2000003", - "UMask": "0x3" - }, - { - "BriefDescription": "All mispredicted macro branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC5", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.", - "SampleAfterValue": "400009" - }, - { - "BriefDescription": "Number of times a microcode assist is invoked by HW other than FP-assist. Examples include AD (page Access Dirty) and AVX* related assists.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC1", - "EventName": "OTHER_ASSISTS.ANY", - "SampleAfterValue": "100003", - "UMask": "0x3f" - }, - { - "BriefDescription": "Cycles without actually retired uops.", + "BriefDescription": "Cycles with no micro-ops executed from any thread on physical core.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0xC2", - "EventName": "UOPS_RETIRED.STALL_CYCLES", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "Invert": "1", - "PublicDescription": "This event counts cycles without actually retired uops.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "BriefDescription": "Number of Uops delivered by the LSD.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA8", - "EventName": "LSD.UOPS", - "PublicDescription": "Number of uops delivered to the back-end by the LSD(Loop Stream Detector).", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "25003", - "UMask": "0x2" - }, - { - "BriefDescription": "Stalls caused by changing prefix length of the instruction.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x87", - "EventName": "ILD_STALL.LCP", - "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.", + "BriefDescription": "Cycles where at least 1 uop was executed per-thread", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x5E", - "EventName": "RS_EVENTS.EMPTY_END", - "Invert": "1", - "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate front-end Latency Bound issues.", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", + "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Cycles while memory subsystem has an outstanding load.", + "BriefDescription": "Cycles where at least 2 uops were executed per-thread", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "16", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "Taken branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.NEAR_TAKEN", - "PEBS": "1", - "PublicDescription": "This event counts taken branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x20" - }, - { - "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x03", - "EventName": "LD_BLOCKS.NO_SR", - "PublicDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0E", - "EventName": "UOPS_ISSUED.ANY", - "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "CounterMask": "2", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", + "PublicDescription": "Cycles where at least 2 uops were executed per-thread.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Core cycles when the thread is not in halt state", - "Counter": "Fixed counter 1", - "CounterHTOff": "Fixed counter 1", - "EventName": "CPU_CLK_UNHALTED.THREAD", - "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "AnyThread": "1", - "BriefDescription": "Core crystal clock cycles when at least one thread on the physical core is unhalted.", + "BriefDescription": "Cycles where at least 3 uops were executed per-thread", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", - "SampleAfterValue": "25003", - "UMask": "0x1" - }, - { - "BriefDescription": "Direct and indirect near call instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PEBS": "1", - "PublicDescription": "This event counts both direct and indirect near call instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of retired PAUSE instructions (that do not end up with a VMExit to the VMM; TSX aborted Instructions may be counted). This event is not supported on first SKL and KBL products.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xCC", - "EventName": "ROB_MISC_EVENTS.PAUSE_INST", - "SampleAfterValue": "2000003", - "UMask": "0x40" - }, - { - "BriefDescription": "Resource-related stall cycles", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xa2", - "EventName": "RESOURCE_STALLS.ANY", - "PublicDescription": "Counts resource-related stall cycles.", + "CounterMask": "3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", + "PublicDescription": "Cycles where at least 3 uops were executed per-thread.", "SampleAfterValue": "2000003", "UMask": "0x1" }, - { - "BriefDescription": "Self-modifying code (SMC) detected.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC3", - "EventName": "MACHINE_CLEARS.SMC", - "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.", - "SampleAfterValue": "100003", - "UMask": "0x4" - }, - { - "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "5", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", - "SampleAfterValue": "2000003", - "UMask": "0x5" - }, - { - "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", - "SampleAfterValue": "25003", - "UMask": "0x2" - }, { "BriefDescription": "Cycles where at least 4 uops were executed per-thread", "Counter": "0,1,2,3", @@ -675,68 +861,68 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.", + "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC5", - "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PEBS": "1", - "SampleAfterValue": "400009", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.THREAD", + "PublicDescription": "Number of uops to be executed per-thread each cycle.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.X87", + "PublicDescription": "Counts the number of x87 uops executed.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.SLOW_LEA", + "SampleAfterValue": "2000003", "UMask": "0x20" }, { - "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "CounterMask": "20", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", - "SampleAfterValue": "2000003", - "UMask": "0x14" - }, - { - "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.", + "BriefDescription": "Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", - "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of cycles using always true condition applied to PEBS instructions retired event.", - "Counter": "0,2,3", - "CounterHTOff": "0,2,3", - "CounterMask": "10", - "Errata": "SKL091, SKL044", - "EventCode": "0xC0", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "CounterMask": "1", + "EventCode": "0x0E", + "EventName": "UOPS_ISSUED.STALL_CYCLES", "Invert": "1", - "PEBS": "2", - "PublicDescription": "Number of cycles using an always true condition applied to PEBS instructions retired event. (inst_ret< 16)", + "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.", "SampleAfterValue": "2000003", "UMask": "0x1" }, - { - "BriefDescription": "Retirement slots used.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC2", - "EventName": "UOPS_RETIRED.RETIRE_SLOTS", - "PublicDescription": "Counts the retirement slots used.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "AnyThread": "1", - "BriefDescription": "Core cycles when at least one thread on the physical core is not in halt state.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", - "SampleAfterValue": "2000003" - }, { "BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector registers.", "Counter": "0,1,2,3", @@ -758,212 +944,37 @@ "UMask": "0x4" }, { - "BriefDescription": "Increments whenever there is an update to the LBR array.", + "BriefDescription": "Retirement slots used.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xCC", - "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", - "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.", - "SampleAfterValue": "2000003", - "UMask": "0x20" - }, - { - "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x5E", - "EventName": "RS_EVENTS.EMPTY_CYCLES", - "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for the thread.; Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Instructions retired from execution.", - "Counter": "Fixed counter 0", - "CounterHTOff": "Fixed counter 0", - "EventName": "INST_RETIRED.ANY", - "PublicDescription": "Counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, Counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "2", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PublicDescription": "Counts the retirement slots used.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA2", - "EventName": "RESOURCE_STALLS.SB", - "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Counts when there is a transition from ring 1, 2 or 3 to ring 0.", + "BriefDescription": "Cycles without actually retired uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EdgeDetect": "1", - "EventCode": "0x3C", - "EventName": "CPU_CLK_UNHALTED.RING0_TRANS", - "PublicDescription": "Counts when the Current Privilege Level (CPL) transitions from ring 1, 2 or 3 to ring 0 (Kernel).", - "SampleAfterValue": "100007" - }, - { - "BriefDescription": "All (macro) branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", - "PEBS": "2", - "PublicDescription": "This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x4" - }, - { - "BriefDescription": "Mispredicted macro branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3", - "EventCode": "0xC5", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", - "PEBS": "2", - "PublicDescription": "This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x4" - }, - { - "BriefDescription": "Return instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PEBS": "1", - "PublicDescription": "This event counts return instructions retired.", - "SampleAfterValue": "100007", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", - "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually retired uops.", "SampleAfterValue": "2000003", "UMask": "0x2" }, { - "BriefDescription": "Not taken branch instructions retired.", + "BriefDescription": "Cycles with less than 10 actually retired uops.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.NOT_TAKEN", - "PublicDescription": "This event counts not taken branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x10" - }, - { - "BriefDescription": "Conditional branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.CONDITIONAL", - "PEBS": "1", - "PublicDescription": "This event counts conditional branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x1" - }, - { - "BriefDescription": "Mispredicted conditional branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xC5", - "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "PEBS": "1", - "PublicDescription": "This event counts mispredicted conditional branch instructions retired.", - "SampleAfterValue": "400009", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of uops executed on the core.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CORE", - "PublicDescription": "Number of uops executed from any thread.", + "CounterMask": "10", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PublicDescription": "Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.", "SampleAfterValue": "2000003", "UMask": "0x2" - }, - { - "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "12", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", - "SampleAfterValue": "2000003", - "UMask": "0xc" - }, - { - "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xA6", - "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", - "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Cycles the issue-stage is waiting for front-end to fetch from resteered path following branch misprediction or machine clear events.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x0D", - "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", - "SampleAfterValue": "2000003", - "UMask": "0x80" - }, - { - "BriefDescription": "All (macro) branch instructions retired.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "Errata": "SKL091", - "EventCode": "0xC4", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PublicDescription": "Counts all (macro) branch instructions retired.", - "SampleAfterValue": "400009" - }, - { - "BriefDescription": "Cycles where at least 1 uop was executed per-thread", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xB1", - "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", - "PublicDescription": "Cycles where at least 1 uop was executed per-thread.", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0xA3", - "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", - "SampleAfterValue": "2000003", - "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json index 4cd246782dde..defbca9a6038 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json @@ -1,371 +1,614 @@ [ { - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound.", "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", - "MetricName": "Frontend_Bound" + "MetricName": "Frontend_Bound", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." }, { - "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU.", "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", - "MetricName": "Frontend_Bound_SMT" + "MetricName": "Frontend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." }, { - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.", "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", - "MetricName": "Bad_Speculation" + "MetricName": "Bad_Speculation", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." }, { - "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU.", "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", - "MetricName": "Bad_Speculation_SMT" + "MetricName": "Bad_Speculation_SMT", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." }, { - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricGroup": "TopdownL1", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound.", "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", - "MetricName": "Backend_Bound" - }, - { - "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", - "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU.", - "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", - "MetricGroup": "TopdownL1_SMT", - "MetricName": "Backend_Bound_SMT" - }, - { - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. ", - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", "MetricGroup": "TopdownL1", - "MetricName": "Retiring" + "MetricName": "Backend_Bound", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." }, { - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", - "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU.", - "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", "MetricGroup": "TopdownL1_SMT", - "MetricName": "Retiring_SMT" + "MetricName": "Backend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Retiring", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Retiring_SMT", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "Mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts_SMT", + "MetricName": "Mispredictions_SMT" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (OFFCORE_REQUESTS_BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "Memory_Bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore_SMT", + "MetricName": "Memory_Bandwidth_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (10 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore", + "MetricName": "Memory_Latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (10 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore_SMT", + "MetricName": "Memory_Latency_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Memory_Data_TLBs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB;_SMT", + "MetricName": "Memory_Data_TLBs_SMT" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "Ret_SMT", + "MetricName": "Branching_Overhead_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB_SMT", + "MetricName": "Big_Code_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "Instruction_Fetch_BW" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "Fed;FetchBW;Frontend_SMT", + "MetricName": "Instruction_Fetch_BW_SMT" }, { - "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", "BriefDescription": "Instructions Per Cycle (per Logical Processor)", - "MetricGroup": "Summary", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { - "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", "BriefDescription": "Uops Per Instruction", - "MetricGroup": "Pipeline;Retire", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "BriefDescription": "Instruction per taken branch", - "MetricGroup": "Branches;Fetch_BW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { - "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", "BriefDescription": "Cycles Per Instruction (per Logical Processor)", - "MetricGroup": "Pipeline", + "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD", "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", - "MetricGroup": "Summary", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", "MetricName": "CLKS" }, { - "MetricExpr": "4 * cycles", "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricGroup": "TopDownL1", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", "MetricName": "SLOTS" }, { - "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", - "MetricGroup": "TopDownL1_SMT", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", "MetricName": "SLOTS_SMT" }, { - "MetricExpr": "INST_RETIRED.ANY / cycles", - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricGroup": "SMT;TopDownL1", + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", - "BriefDescription": "Instructions Per Cycle (per physical core)", - "MetricGroup": "SMT;TopDownL1", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { - "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / cycles", "BriefDescription": "Floating Point Operations Per Cycle", - "MetricGroup": "FLOPS", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { - "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", "BriefDescription": "Floating Point Operations Per Cycle", - "MetricGroup": "FLOPS_SMT", + "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, { - "MetricExpr": "UOPS_EXECUTED.THREAD / ( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 )", + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", - "MetricGroup": "Pipeline;Ports_Utilization", + "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, { - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) * (( INT_MISC.CLEAR_RESTEER_CYCLES + 9 * BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * cycles)) ) * (4 * cycles) / BR_MISP_RETIRED.ALL_BRANCHES", "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricGroup": "BrMispredicts", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", "MetricName": "Branch_Misprediction_Cost" }, { - "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (( INT_MISC.CLEAR_RESTEER_CYCLES + 9 * BACLEARS.ANY ) / cycles) / (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", - "MetricGroup": "BrMispredicts_SMT", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", "MetricName": "Branch_Misprediction_Cost_SMT" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", - "MetricGroup": "BrMispredicts", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { - "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", + "MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD", "MetricGroup": "SMT", "MetricName": "CORE_CLKS" }, { - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)", - "MetricGroup": "Instruction_Type", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", "MetricName": "IpLoad" }, { - "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", "BriefDescription": "Instructions per Store (lower number means higher occurrence rate)", - "MetricGroup": "Instruction_Type", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", "MetricName": "IpStore" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", - "MetricGroup": "Branches;Instruction_Type", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", - "MetricGroup": "Branches", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, { - "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, + { "BriefDescription": "Branch instructions per taken branch. ", - "MetricGroup": "Branches;PGO", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { - "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", - "MetricGroup": "FLOPS;FP_Arith;Instruction_Type", + "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", - "BriefDescription": "Total number of retired Instructions", - "MetricGroup": "Summary;TopDownL1", + "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, { - "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, + { "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", - "MetricGroup": "DSB;Fetch_BW", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", - "MetricGroup": "Memory_Bound;Memory_Lat", - "MetricName": "Load_Miss_Real_Latency" + "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "DSB_Misses_Cost" + }, + { + "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "DSBmiss;Fed_SMT", + "MetricName": "DSB_Misses_Cost_SMT" + }, + { + "BriefDescription": "Number of Instructions per non-speculative DSB miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { - "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", - "MetricGroup": "Memory_Bound;Memory_BW", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, { - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * cycles )", - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricGroup": "TLB", - "MetricName": "Page_Walks_Utilization" - }, - { - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricGroup": "TLB_SMT", - "MetricName": "Page_Walks_Utilization_SMT" - }, - { - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", - "MetricGroup": "Memory_BW", + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", - "MetricGroup": "Memory_BW", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", - "MetricGroup": "Memory_BW", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", - "MetricGroup": "Memory_BW;Offcore", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", - "MetricGroup": "Cache_Misses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, + { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", - "MetricGroup": "Cache_Misses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { - "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", - "MetricGroup": "Cache_Misses;Offcore", + "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, { - "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", + "BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, + { "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", - "MetricGroup": "Cache_Misses", + "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, { - "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, + { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", - "MetricGroup": "Cache_Misses", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, { - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructions for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, + { "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", "MetricGroup": "HPC;Summary", "MetricName": "CPU_Utilization" }, { - "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time", + "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]", + "MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time", + "MetricGroup": "Summary;Power", + "MetricName": "Average_Frequency" + }, + { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricGroup": "FLOPS;HPC", + "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, { - "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 )", "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", + "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", "MetricGroup": "SMT", "MetricName": "SMT_2T_Utilization" }, { - "MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD", "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, { - "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, + { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", - "MetricGroup": "HPC;Memory_BW;SoC", + "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { - "MetricExpr": "arb@event\\=0x80\\,umask\\=0x2@ / arb@event\\=0x80\\,umask\\=0x2\\,cmask\\=1@", + "BriefDescription": "Average latency of all requests to external memory (in Uncore cycles)", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Request_Latency" + }, + { + "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests", + "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@", + "MetricGroup": "Mem;SoC", + "MetricName": "MEM_Parallel_Requests" + }, + { "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", - "MetricGroup": "Memory_BW;SoC", + "MetricExpr": "arb@event\\=0x80\\,umask\\=0x2@ / arb@event\\=0x80\\,umask\\=0x2\\,cmask\\=1@", + "MetricGroup": "Mem;MemoryBW;SoC", "MetricName": "MEM_Parallel_Reads" }, { - "MetricExpr": "INST_RETIRED.ANY / ( BR_INST_RETIRED.FAR_BRANCH / 2 )", "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", "MetricGroup": "Branches;OS", "MetricName": "IpFarBranch" }, { - "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C3 residency percent per core", + "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C3_Core_Residency" }, { - "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C6 residency percent per core", + "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Core_Residency" }, { - "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C7 residency percent per core", + "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Core_Residency" }, { - "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C2 residency percent per package", + "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C2_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C3 residency percent per package", + "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C3_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C6 residency percent per package", + "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C6_Pkg_Residency" }, { - "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "BriefDescription": "C7 residency percent per package", + "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", "MetricGroup": "Power", "MetricName": "C7_Pkg_Residency" } diff --git a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json index 432530d15c26..792ca39f013a 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json @@ -1,65 +1,14 @@ [ { - "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "BriefDescription": "Load misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", - "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", "SampleAfterValue": "100003", "UMask": "0x1" }, - { - "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "UMask": "0x4" - }, - { - "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_PENDING", - "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.", - "SampleAfterValue": "100003", - "UMask": "0x10" - }, - { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xAE", - "EventName": "ITLB.ITLB_FLUSH", - "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", - "SampleAfterValue": "100007", - "UMask": "0x1" - }, - { - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_ACTIVE", - "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.", - "SampleAfterValue": "100003", - "UMask": "0x10" - }, { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", "Counter": "0,1,2,3", @@ -71,24 +20,55 @@ "UMask": "0x20" }, { - "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_PENDING", - "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.", - "SampleAfterValue": "2000003", + "CounterMask": "1", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.", + "SampleAfterValue": "100003", "UMask": "0x10" }, { - "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xBD", - "EventName": "TLB_FLUSH.DTLB_THREAD", - "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", - "SampleAfterValue": "100007", - "UMask": "0x1" + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Page walk completed due to a demand data load to a 1G page", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Page walk completed due to a demand data load to a 4K page", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "2000003", + "UMask": "0x2" }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", @@ -101,23 +81,12 @@ "UMask": "0x10" }, { - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", + "BriefDescription": "Store misses in all DTLB levels that cause page walks", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", - "CounterMask": "1", "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", - "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", - "SampleAfterValue": "100003", - "UMask": "0x10" - }, - { - "BriefDescription": "Misses at all ITLB levels that cause page walks", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.", + "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -132,135 +101,16 @@ "UMask": "0x20" }, { - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "UMask": "0xe" - }, - { - "BriefDescription": "Page walk completed due to a demand data store to a 4K page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x49", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", - "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "UMask": "0xe" - }, - { - "BriefDescription": "Page walk completed due to a demand data load to a 4K page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "UMask": "0x20" - }, - { - "BriefDescription": "Page walk completed due to a demand data load to a 2M/4M page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "2000003", - "UMask": "0x4" - }, - { - "BriefDescription": "Load misses in all DTLB levels that cause page walks", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", - "PublicDescription": "Counts demand data loads that caused a page walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB levels, but the walk need not have completed.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x4f", - "EventName": "EPT.WALK_PENDING", - "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.", - "SampleAfterValue": "2000003", - "UMask": "0x10" - }, - { - "BriefDescription": "STLB flush attempts", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0xBD", - "EventName": "TLB_FLUSH.STLB_ANY", - "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", - "SampleAfterValue": "100007", - "UMask": "0x20" - }, - { - "BriefDescription": "Page walk completed due to a demand data load to a 1G page", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a load. EPT page walk duration are excluded in Skylake.", + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "CounterMask": "1", - "EventCode": "0x08", - "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", - "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a load.", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.", "SampleAfterValue": "100003", "UMask": "0x10" }, - { - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x85", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", - "SampleAfterValue": "100003", - "UMask": "0x4" - }, { "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", "Counter": "0,1,2,3", @@ -280,5 +130,155 @@ "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "UMask": "0x8" + }, + { + "BriefDescription": "Page walk completed due to a demand data store to a 2M/4M page", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Page walk completed due to a demand data store to a 4K page", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PublicDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for a store. EPT page walk duration are excluded in Skylake microarchitecture.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a EPT (Extended Page Table) walk for any request type.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x4f", + "EventName": "EPT.WALK_PENDING", + "PublicDescription": "Counts cycles for each PMH (Page Miss Handler) that is busy with an EPT (Extended Page Table) walk for any request type.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xAE", + "EventName": "ITLB.ITLB_FLUSH", + "PublicDescription": "Counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", + "PublicDescription": "Counts page walks of any page size (4K/2M/4M/1G) caused by a code fetch. This implies it missed in the ITLB and further levels of TLB, but the walk need not have completed.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "PublicDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request. EPT page walk duration are excluded in Skylake microarchitecture.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0xe" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "Counts completed page walks (1G page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts 1 per cycle for each PMH that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_PENDING", + "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss Handler) that is busy with a page walk for an instruction fetch request. EPT page walk duration are excluded in Skylake michroarchitecture.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.DTLB_THREAD", + "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0xBD", + "EventName": "TLB_FLUSH.STLB_ANY", + "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", + "SampleAfterValue": "100007", + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/perf/pmu-events/arch/x86/skylakex/cache.json index 9ff67206ade4..6639e18a7068 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json @@ -314,6 +314,19 @@ "SampleAfterValue": "2000003", "UMask": "0x82" }, + { + "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xD0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "SampleAfterValue": "2000003", + "UMask": "0x83" + }, { "BriefDescription": "Retired load instructions with locked access.", "Counter": "0,1,2,3", @@ -358,6 +371,7 @@ "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x11" }, @@ -370,6 +384,7 @@ "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", "L1_Hit_Indication": "1", "PEBS": "1", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x12" }, @@ -733,7 +748,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010491", + "MSRValue": "0x10491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -772,7 +787,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0491", + "MSRValue": "0x4003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -785,7 +800,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0491", + "MSRValue": "0x1003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -798,7 +813,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0491", + "MSRValue": "0x8003C0491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -811,7 +826,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010490", + "MSRValue": "0x10490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -850,7 +865,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0490", + "MSRValue": "0x4003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -863,7 +878,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0490", + "MSRValue": "0x1003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -876,7 +891,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0490", + "MSRValue": "0x8003C0490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -889,7 +904,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010120", + "MSRValue": "0x10120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -928,7 +943,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0120", + "MSRValue": "0x4003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -941,7 +956,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0120", + "MSRValue": "0x1003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -954,7 +969,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0120", + "MSRValue": "0x8003C0120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -967,7 +982,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010122", + "MSRValue": "0x10122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1006,7 +1021,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0122", + "MSRValue": "0x4003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1019,7 +1034,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0122", + "MSRValue": "0x1003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1032,7 +1047,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0122", + "MSRValue": "0x8003C0122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1045,7 +1060,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010004", + "MSRValue": "0x10004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1084,7 +1099,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0004", + "MSRValue": "0x4003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1097,7 +1112,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0004", + "MSRValue": "0x1003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1110,7 +1125,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0004", + "MSRValue": "0x8003C0004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1123,7 +1138,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010001", + "MSRValue": "0x10001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1162,7 +1177,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0001", + "MSRValue": "0x4003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1175,7 +1190,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0001", + "MSRValue": "0x1003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1188,7 +1203,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0001", + "MSRValue": "0x8003C0001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1201,7 +1216,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010002", + "MSRValue": "0x10002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1240,7 +1255,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0002", + "MSRValue": "0x4003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1253,7 +1268,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0002", + "MSRValue": "0x1003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1266,7 +1281,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0002", + "MSRValue": "0x8003C0002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1279,7 +1294,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010400", + "MSRValue": "0x10400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1318,7 +1333,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0400", + "MSRValue": "0x4003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1331,7 +1346,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0400", + "MSRValue": "0x1003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1344,7 +1359,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0400", + "MSRValue": "0x8003C0400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1357,7 +1372,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010010", + "MSRValue": "0x10010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1396,7 +1411,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0010", + "MSRValue": "0x4003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1409,7 +1424,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0010", + "MSRValue": "0x1003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1422,7 +1437,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0010", + "MSRValue": "0x8003C0010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1435,7 +1450,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010020", + "MSRValue": "0x10020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1474,7 +1489,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0020", + "MSRValue": "0x4003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1487,7 +1502,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0020", + "MSRValue": "0x1003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1500,7 +1515,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0020", + "MSRValue": "0x8003C0020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1513,7 +1528,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010080", + "MSRValue": "0x10080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1552,7 +1567,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0080", + "MSRValue": "0x4003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1565,7 +1580,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0080", + "MSRValue": "0x1003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1578,7 +1593,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0080", + "MSRValue": "0x8003C0080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1591,7 +1606,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0000010100", + "MSRValue": "0x10100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1630,7 +1645,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x04003C0100", + "MSRValue": "0x4003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1643,7 +1658,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x01003C0100", + "MSRValue": "0x1003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1656,7 +1671,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x08003C0100", + "MSRValue": "0x8003C0100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1671,5 +1686,41 @@ "PublicDescription": "Counts the number of cache line split locks sent to the uncore.", "SampleAfterValue": "100003", "UMask": "0x10" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "SampleAfterValue": "2000003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json index 503737ed3a83..9e873ab22450 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json @@ -1,73 +1,81 @@ [ { - "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x4" }, { - "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instruction retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 128-bit packed computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed double computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x10" }, { - "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Counts once for most SIMD 256-bit packed single computational precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x20" }, { - "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x40" }, { - "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x80" }, { - "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Counts once for most SIMD scalar computational double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x1" }, { - "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SUB instructions retired.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3,4,5,6,7", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Counts once for most SIMD scalar computational single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SIMD scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "2000003", "UMask": "0x2" }, diff --git a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json index 078706a50091..ecce4273ae52 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json @@ -30,7 +30,21 @@ "UMask": "0x2" }, { - "BriefDescription": "Retired Instructions who experienced decode stream buffer (DSB - the decoded instruction-cache) miss.", + "BriefDescription": "Retired Instructions who experienced DSB miss.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3", + "EventCode": "0xC6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", "Counter": "0,1,2,3", "CounterHTOff": "0,1,2,3", "EventCode": "0xC6", @@ -38,7 +52,7 @@ "MSRIndex": "0x3F7", "MSRValue": "0x11", "PEBS": "1", - "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" diff --git a/tools/perf/pmu-events/arch/x86/skylakex/memory.json b/tools/perf/pmu-events/arch/x86/skylakex/memory.json index 6f29b02fa320..60c286b4fe54 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/memory.json @@ -299,7 +299,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00491", + "MSRValue": "0x83FC00491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -312,7 +312,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00491", + "MSRValue": "0x63FC00491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -325,7 +325,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000491", + "MSRValue": "0x604000491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -338,7 +338,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800491", + "MSRValue": "0x63B800491", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -377,7 +377,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00490", + "MSRValue": "0x83FC00490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -390,7 +390,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00490", + "MSRValue": "0x63FC00490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -403,7 +403,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000490", + "MSRValue": "0x604000490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -416,7 +416,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800490", + "MSRValue": "0x63B800490", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -455,7 +455,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00120", + "MSRValue": "0x83FC00120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -468,7 +468,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00120", + "MSRValue": "0x63FC00120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -481,7 +481,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000120", + "MSRValue": "0x604000120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -494,7 +494,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800120", + "MSRValue": "0x63B800120", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -533,7 +533,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00122", + "MSRValue": "0x83FC00122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -546,7 +546,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00122", + "MSRValue": "0x63FC00122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -559,7 +559,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000122", + "MSRValue": "0x604000122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -572,7 +572,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800122", + "MSRValue": "0x63B800122", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -611,7 +611,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00004", + "MSRValue": "0x83FC00004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -624,7 +624,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00004", + "MSRValue": "0x63FC00004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -637,7 +637,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000004", + "MSRValue": "0x604000004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -650,7 +650,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800004", + "MSRValue": "0x63B800004", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -689,7 +689,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00001", + "MSRValue": "0x83FC00001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -702,7 +702,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00001", + "MSRValue": "0x63FC00001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -715,7 +715,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000001", + "MSRValue": "0x604000001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -728,7 +728,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800001", + "MSRValue": "0x63B800001", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -767,7 +767,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00002", + "MSRValue": "0x83FC00002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -780,7 +780,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00002", + "MSRValue": "0x63FC00002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -793,7 +793,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000002", + "MSRValue": "0x604000002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -806,7 +806,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800002", + "MSRValue": "0x63B800002", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -845,7 +845,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00400", + "MSRValue": "0x83FC00400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -858,7 +858,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00400", + "MSRValue": "0x63FC00400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -871,7 +871,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000400", + "MSRValue": "0x604000400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -884,7 +884,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800400", + "MSRValue": "0x63B800400", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -923,7 +923,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00010", + "MSRValue": "0x83FC00010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -936,7 +936,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00010", + "MSRValue": "0x63FC00010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -949,7 +949,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000010", + "MSRValue": "0x604000010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -962,7 +962,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800010", + "MSRValue": "0x63B800010", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1001,7 +1001,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00020", + "MSRValue": "0x83FC00020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1014,7 +1014,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00020", + "MSRValue": "0x63FC00020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1027,7 +1027,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000020", + "MSRValue": "0x604000020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1040,7 +1040,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800020", + "MSRValue": "0x63B800020", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1079,7 +1079,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00080", + "MSRValue": "0x83FC00080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1092,7 +1092,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00080", + "MSRValue": "0x63FC00080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1105,7 +1105,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000080", + "MSRValue": "0x604000080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1118,7 +1118,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800080", + "MSRValue": "0x63B800080", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1157,7 +1157,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x083FC00100", + "MSRValue": "0x83FC00100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1170,7 +1170,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063FC00100", + "MSRValue": "0x63FC00100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1183,7 +1183,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x0604000100", + "MSRValue": "0x604000100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", @@ -1196,7 +1196,7 @@ "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x063B800100", + "MSRValue": "0x63B800100", "Offcore": "1", "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/perf/pmu-events/arch/x86/skylakex/other.json index 8b344259176f..779654e62d97 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json @@ -76,41 +76,5 @@ "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "SampleAfterValue": "2000003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "SampleAfterValue": "2000003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "SampleAfterValue": "2000003", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "Counter": "0,1,2,3", - "CounterHTOff": "0,1,2,3,4,5,6,7", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "SampleAfterValue": "2000003", - "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json index ca5748120666..12eabae3e224 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json @@ -435,6 +435,17 @@ "PublicDescription": "Counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).", "SampleAfterValue": "2000003" }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3", + "CounterHTOff": "0,1,2,3,4,5,6,7", + "Errata": "SKL091, SKL044", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, { "BriefDescription": "Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution", "Counter": "1", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json index 863c9e103969..b016f7d1ff3d 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json @@ -1,26 +1,167 @@ [ + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Frontend_Bound", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." + }, + { + "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Frontend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Bad_Speculation", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." + }, + { + "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Bad_Speculation_SMT", + "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Backend_Bound", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." + }, + { + "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Backend_Bound_SMT", + "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)", + "MetricGroup": "TopdownL1", + "MetricName": "Retiring", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. " + }, + { + "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", + "MetricGroup": "TopdownL1_SMT", + "MetricName": "Retiring_SMT", + "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "Mispredictions" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks", + "MetricExpr": "100 * ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )", + "MetricGroup": "Bad;BadSpec;BrMispredicts_SMT", + "MetricName": "Mispredictions_SMT" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (OFFCORE_REQUESTS_BUFFER.SQ_FULL / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "Memory_Bandwidth" + }, + { + "BriefDescription": "Total pipeline cost of (external) Memory Bandwidth related bottlenecks", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) ) + ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( ((L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )) * cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ / CPU_CLK_UNHALTED.THREAD) / #(max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) ", + "MetricGroup": "Mem;MemoryBW;Offcore_SMT", + "MetricName": "Memory_Bandwidth_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore", + "MetricName": "Memory_Latency" + }, + { + "BriefDescription": "Total pipeline cost of Memory Latency related bottlenecks (external memory and off-core caches)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( CPU_CLK_UNHALTED.THREAD , OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD ) / CPU_CLK_UNHALTED.THREAD - (min( CPU_CLK_UNHALTED.THREAD , cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=4@ ) / CPU_CLK_UNHALTED.THREAD)) / #(CYCLE_ACTIVITY.STALLS_L3_MISS / CPU_CLK_UNHALTED.THREAD + (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD) - (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD))) ) + ( (( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( (20.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) - (3.5 * ((CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time)) ) * MEM_LOAD_RETIRED.L3_HIT * (1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) / 2) / CPU_CLK_UNHALTED.THREAD) / #(( CYCLE_ACTIVITY.STALLS_L2_MISS - CYCLE_ACTIVITY.STALLS_L3_MISS ) / CPU_CLK_UNHALTED.THREAD) ) + ( (( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) / ( (MEM_LOAD_RETIRED.L2_HIT * ( 1 + (MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) )) + cpu@L1D_PEND_MISS.FB_FULL\\,cmask\\=1@ ) ) * (( CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS ) / CPU_CLK_UNHALTED.THREAD)) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) )", + "MetricGroup": "Mem;MemoryLat;Offcore_SMT", + "MetricName": "Memory_Latency_SMT" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - ( UOPS_ISSUED.ANY + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / CPU_CLK_UNHALTED.THREAD) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Memory_Data_TLBs" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * ( ( (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) / ((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (min( 9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_LOAD_MISSES.WALK_ACTIVE , max( CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS , 0 ) ) / CPU_CLK_UNHALTED.THREAD) / (max( ( CYCLE_ACTIVITY.STALLS_MEM_ANY - CYCLE_ACTIVITY.STALLS_L1D_MISS ) / CPU_CLK_UNHALTED.THREAD , 0 )) ) + ( (EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) / #((( CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES ) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES)) * (1 - (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - ( UOPS_ISSUED.ANY + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) ) * ( (( 9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=1@ + DTLB_STORE_MISSES.WALK_ACTIVE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / #(EXE_ACTIVITY.BOUND_ON_STORES / CPU_CLK_UNHALTED.THREAD) ) ) ", + "MetricGroup": "Mem;MemoryTLB;_SMT", + "MetricName": "Memory_Data_TLBs_SMT" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "Ret", + "MetricName": "Branching_Overhead" + }, + { + "BriefDescription": "Total pipeline cost of branch related instructions (used for program control-flow including function calls)", + "MetricExpr": "100 * (( BR_INST_RETIRED.CONDITIONAL + 3 * BR_INST_RETIRED.NEAR_CALL + (BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "Ret_SMT", + "MetricName": "Branching_Overhead_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "Big_Code" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)", + "MetricExpr": "100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", + "MetricGroup": "BigFoot;Fed;Frontend;IcMiss;MemoryTLB_SMT", + "MetricName": "Big_Code_SMT" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "MetricGroup": "Fed;FetchBW;Frontend", + "MetricName": "Instruction_Fetch_BW" + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks", + "MetricExpr": "100 * ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) - (100 * (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ( (ICACHE_64B.IFTAG_STALL / CPU_CLK_UNHALTED.THREAD) + (( ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=1\\,edge@ ) / CPU_CLK_UNHALTED.THREAD) + (9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) ) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "Fed;FetchBW;Frontend_SMT", + "MetricName": "Instruction_Fetch_BW_SMT" + }, { "BriefDescription": "Instructions Per Cycle (per Logical Processor)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Summary", + "MetricGroup": "Ret;Summary", "MetricName": "IPC" }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", - "MetricGroup": "Pipeline;Retire", + "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "UPI" }, { "BriefDescription": "Instruction per taken branch", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;FetchBW;PGO", - "MetricName": "IpTB" + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "UpTB" }, { "BriefDescription": "Cycles Per Instruction (per Logical Processor)", "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)", - "MetricGroup": "Pipeline", + "MetricGroup": "Pipeline;Mem", "MetricName": "CPI" }, { @@ -30,39 +171,84 @@ "MetricName": "CLKS" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "TmaL1", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "TmaL1_SMT", + "MetricName": "SLOTS_SMT" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "Execute_per_Issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1", "MetricName": "CoreIPC" }, { - "BriefDescription": "Instructions Per Cycle (per physical core)", + "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)", "MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", - "MetricGroup": "SMT;TmaL1", + "MetricGroup": "Ret;SMT;TmaL1_SMT", "MetricName": "CoreIPC_SMT" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD", - "MetricGroup": "Flops", + "MetricGroup": "Ret;Flops", "MetricName": "FLOPc" }, { "BriefDescription": "Floating Point Operations Per Cycle", "MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", - "MetricGroup": "Flops_SMT", + "MetricGroup": "Ret;Flops_SMT", "MetricName": "FLOPc_SMT" }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "FP_Arith_Utilization", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting." + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Cor;Flops;HPC_SMT", + "MetricName": "FP_Arith_Utilization_SMT", + "PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU." + }, { "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "MetricExpr": "UOPS_EXECUTED.THREAD / (( UOPS_EXECUTED.CORE_CYCLES_GE_1 / 2 ) if #SMT_on else UOPS_EXECUTED.CORE_CYCLES_GE_1)", - "MetricGroup": "Pipeline;PortsUtil", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", "MetricName": "ILP" }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "Branch_Misprediction_Cost" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": " ( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BrMispredicts_SMT", + "MetricName": "Branch_Misprediction_Cost_SMT" + }, { "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricGroup": "BrMispredicts", + "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "IpMispredict" }, { @@ -86,122 +272,249 @@ { "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricGroup": "Branches;InsType", + "MetricGroup": "Branches;Fed;InsType", "MetricName": "IpBranch" }, { "BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", - "MetricGroup": "Branches", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "IpCall" }, + { + "BriefDescription": "Instruction per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO", + "MetricName": "IpTB" + }, { "BriefDescription": "Branch instructions per taken branch. ", "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", - "MetricGroup": "Branches;PGO", + "MetricGroup": "Branches;Fed;PGO", "MetricName": "BpTkBranch" }, { "BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)", "MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", - "MetricGroup": "Flops;FpArith;InsType", + "MetricGroup": "Flops;InsType", "MetricName": "IpFLOP" }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) )", + "MetricGroup": "Flops;InsType", + "MetricName": "IpArith", + "PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_SP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "IpArith_Scalar_DP", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX128", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX256", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE )", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "IpArith_AVX512", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting." + }, { "BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST", "MetricExpr": "INST_RETIRED.ANY", "MetricGroup": "Summary;TmaL1", "MetricName": "Instructions" }, + { + "BriefDescription": "Average number of Uops issued by front-end when it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=1@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "Fetch_UpC" + }, { "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS)", - "MetricGroup": "DSB;FetchBW", + "MetricGroup": "DSB;Fed;FetchBW", "MetricName": "DSB_Coverage" }, { - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", + "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / CPU_CLK_UNHALTED.THREAD / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)))", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "DSB_Misses_Cost" + }, + { + "BriefDescription": "Total penalty related to DSB (uop cache) misses - subset/see of/the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + ((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) * (( IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) / 2) / #((IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) - (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))))", + "MetricGroup": "DSBmiss;Fed_SMT", + "MetricName": "DSB_Misses_Cost_SMT" + }, + { + "BriefDescription": "Number of Instructions per non-speculative DSB miss", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "IpDSB_Miss_Ret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken conditionals", + "MetricExpr": "BR_INST_RETIRED.NOT_TAKEN / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_NT" + }, + { + "BriefDescription": "Fraction of branches that are taken conditionals", + "MetricExpr": "( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "Cond_TK" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "( BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_RETURN ) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "CallRet" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - ( BR_INST_RETIRED.CONDITIONAL - BR_INST_RETIRED.NOT_TAKEN ) - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "Jump" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_RETIRED.L1_MISS + MEM_LOAD_RETIRED.FB_HIT )", - "MetricGroup": "MemoryBound;MemoryLat", - "MetricName": "Load_Miss_Real_Latency" + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "Load_Miss_Real_Latency", + "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings." }, { "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", - "MetricGroup": "MemoryBound;MemoryBW", + "MetricGroup": "Mem;MemoryBound;MemoryBW", "MetricName": "MLP" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", - "MetricConstraint": "NO_NMI_WATCHDOG", - "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CORE_CLKS )", - "MetricGroup": "MemoryTLB", - "MetricName": "Page_Walks_Utilization" - }, { "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L1D_Cache_Fill_BW" }, { "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L2_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", - "MetricGroup": "MemoryBW", + "MetricGroup": "Mem;MemoryBW", "MetricName": "L3_Cache_Fill_BW" }, { "BriefDescription": "Average per-core data access bandwidth to the L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1000000000 / duration_time", - "MetricGroup": "MemoryBW;Offcore", + "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "L3_Cache_Access_BW" }, { "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L1MPKI" }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L1MPKI_Load" + }, { "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;Backend;CacheMisses", "MetricName": "L2MPKI" }, { "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", "MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses;Offcore", + "MetricGroup": "Mem;CacheMisses;Offcore", "MetricName": "L2MPKI_All" }, + { + "BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2MPKI_Load" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", "MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L2HPKI_All" }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)", + "MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "L2HPKI_Load" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", "MetricExpr": "1000 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "CacheMisses", + "MetricGroup": "Mem;CacheMisses", "MetricName": "L3MPKI" }, + { + "BriefDescription": "Fill Buffer (FB) true hits per kilo instructions for retired demand loads", + "MetricExpr": "1000 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "Mem;CacheMisses", + "MetricName": "FB_HPKI" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricConstraint": "NO_NMI_WATCHDOG", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * CPU_CLK_UNHALTED.THREAD )", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "Page_Walks_Utilization" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "( ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_PENDING + DTLB_STORE_MISSES.WALK_PENDING + EPT.WALK_PENDING ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )", + "MetricGroup": "Mem;MemoryTLB_SMT", + "MetricName": "Page_Walks_Utilization_SMT" + }, { "BriefDescription": "Rate of silent evictions from the L2 cache per Kilo instruction where the evicted lines are dropped (no writeback to L3 or memory)", "MetricExpr": "1000 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_Silent_PKI" }, { "BriefDescription": "Rate of non silent evictions from the L2 cache per Kilo instruction", "MetricExpr": "1000 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Server", + "MetricGroup": "L2Evicts;Mem;Server", "MetricName": "L2_Evictions_NonSilent_PKI" }, { @@ -219,7 +532,7 @@ { "BriefDescription": "Giga Floating Point Operations Per Second", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * ( FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE ) + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE ) / 1000000000 ) / duration_time", - "MetricGroup": "Flops;HPC", + "MetricGroup": "Cor;Flops;HPC", "MetricName": "GFLOPs" }, { @@ -228,6 +541,48 @@ "MetricGroup": "Power", "MetricName": "Turbo_Utilization" }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Power", + "MetricName": "Power_License0_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL0_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License0_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Power", + "MetricName": "Power_License1_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL1_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License1_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions. SMT version; use when SMT is enabled and measuring per logical CPU." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX)", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Power", + "MetricName": "Power_License2_Utilization", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions." + }, + { + "BriefDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). SMT version; use when SMT is enabled and measuring per logical CPU.", + "MetricExpr": "CORE_POWER.LVL2_TURBO_LICENSE / 2 / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", + "MetricGroup": "Power_SMT", + "MetricName": "Power_License2_Utilization_SMT", + "PublicDescription": "Fraction of Core cycles where the core was running with power-delivery for license level 2 (introduced in SKX). This includes high current AVX 512-bit instructions. SMT version; use when SMT is enabled and measuring per logical CPU." + }, { "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", @@ -240,34 +595,46 @@ "MetricGroup": "OS", "MetricName": "Kernel_Utilization" }, + { + "BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "Kernel_CPI" + }, { "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", "MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time", - "MetricGroup": "HPC;MemoryBW;SoC", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", "MetricName": "DRAM_BW_Use" }, { "BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "1000000000 * ( cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x35\\,umask\\=0x21\\,config\\=0x40433@ ) / ( cha_0@event\\=0x0@ / duration_time )", - "MetricGroup": "MemoryLat;SoC", + "MetricGroup": "Mem;MemoryLat;SoC", "MetricName": "MEM_Read_Latency" }, { "BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches", "MetricExpr": "cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433@ / cha@event\\=0x36\\,umask\\=0x21\\,config\\=0x40433\\,thresh\\=1@", - "MetricGroup": "MemoryBW;SoC", + "MetricGroup": "Mem;MemoryBW;SoC", "MetricName": "MEM_Parallel_Reads" }, + { + "BriefDescription": "Average latency of data read request to external DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data-read prefetches", + "MetricExpr": "1000000000 * ( UNC_M_RPQ_OCCUPANCY / UNC_M_RPQ_INSERTS ) / imc_0@event\\=0x0@", + "MetricGroup": "Mem;MemoryLat;SoC;Server", + "MetricName": "MEM_DRAM_Read_Latency" + }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use for Writes [GB / sec]", "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 ) * 4 / 1000000000 / duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Write_BW" }, { "BriefDescription": "Average IO (network or disk) Bandwidth Use for Reads [GB / sec]", "MetricExpr": "( UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 + UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 ) * 4 / 1000000000 / duration_time", - "MetricGroup": "IoBW;SoC;Server", + "MetricGroup": "IoBW;Mem;SoC;Server", "MetricName": "IO_Read_BW" }, { diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json index 6ed92bc5c129..06c5ca26ca3f 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json @@ -537,6 +537,18 @@ "PublicDescription": "Counts clockticks of the 1GHz trafiic controller clock in the IIO unit.", "Unit": "IIO" }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x4", + "PerPkg": "1", + "PortMask": "0x0f", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3", + "UMask": "0x03", + "Unit": "IIO" + }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", "Counter": "0,1,2,3", @@ -585,6 +597,17 @@ "UMask": "0x03", "Unit": "IIO" }, + { + "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0-3", + "UMask": "0x0f", + "Unit": "IIO" + }, { "BriefDescription": "PCIe Completion Buffer occupancy of completions with data: Part 0", "Counter": "2,3", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json index 8d767b8932b0..0569b2c704ca 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json @@ -145,6 +145,17 @@ "SampleAfterValue": "200003", "UMask": "0x24" }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, { "BriefDescription": "All requests that miss L2 cache", "CollectPEBSRecord": "2", @@ -185,7 +196,7 @@ "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_HIT", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", + "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", "SampleAfterValue": "200003", "UMask": "0xc8" }, @@ -196,7 +207,7 @@ "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_MISS", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.", + "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.", "SampleAfterValue": "200003", "UMask": "0x28" }, @@ -222,6 +233,17 @@ "SampleAfterValue": "2000003", "UMask": "0x2" }, + { + "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, { "BriefDescription": "All retired load instructions.", "CollectPEBSRecord": "2", @@ -249,6 +271,20 @@ "SampleAfterValue": "1000003", "UMask": "0x82" }, + { + "BriefDescription": "All retired memory instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ANY", + "L1_Hit_Indication": "1", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts all retired memory instructions - loads and stores.", + "SampleAfterValue": "1000003", + "UMask": "0x83" + }, { "BriefDescription": "Retired load instructions with locked access.", "CollectPEBSRecord": "2", @@ -298,7 +334,7 @@ "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired load instructions that true miss the STLB.", + "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x11" }, @@ -312,7 +348,7 @@ "L1_Hit_Indication": "1", "PEBS": "1", "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts retired store instructions that true miss the STLB.", + "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).", "SampleAfterValue": "100003", "UMask": "0x12" }, @@ -457,6 +493,48 @@ "SampleAfterValue": "50021", "UMask": "0x20" }, + { + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Demand and prefetch data reads", "CollectPEBSRecord": "2", @@ -591,5 +669,49 @@ "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.", "SampleAfterValue": "100003", "UMask": "0x4" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHW instructions executed.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", + "SampleAfterValue": "100003", + "UMask": "0x4" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json index 402f01851313..de8eb2b34a3a 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json @@ -17,6 +17,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x4" }, @@ -27,7 +28,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x8" }, @@ -38,6 +39,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x10" }, @@ -48,6 +50,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x20" }, @@ -58,16 +61,18 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x40" }, { - "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", + "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x80" }, @@ -78,6 +83,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x1" }, @@ -88,6 +94,7 @@ "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", "SampleAfterValue": "100003", "UMask": "0x2" } diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json b/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json index 24c736ac8f8e..2eaa33cc574e 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json @@ -39,12 +39,27 @@ "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "TakenAlone": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired Instructions who experienced a critical DSB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", "MSRValue": "0x11", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.", "SampleAfterValue": "100007", "TakenAlone": "1", "UMask": "0x1" diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/perf/pmu-events/arch/x86/tigerlake/other.json index b1143fe74246..304cd09fe159 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json @@ -43,48 +43,6 @@ "SampleAfterValue": "200003", "UMask": "0x20" }, - { - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x8003C0001", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0xB7, 0xBB", - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", - "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x10003C0002", - "Offcore": "1", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, { "BriefDescription": "Counts streaming stores that have any type of response.", "CollectPEBSRecord": "2", @@ -98,92 +56,5 @@ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", "SampleAfterValue": "100003", "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHNTA instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.NTA", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", - "SampleAfterValue": "100003", - "UMask": "0x1" - }, - { - "BriefDescription": "Number of PREFETCHW instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHW instructions executed.", - "SampleAfterValue": "100003", - "UMask": "0x8" - }, - { - "BriefDescription": "Number of PREFETCHT0 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T0", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3", - "EventCode": "0x32", - "EventName": "SW_PREFETCH_ACCESS.T1_T2", - "PEBScounters": "0,1,2,3", - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", - "SampleAfterValue": "100003", - "UMask": "0x4" - }, - { - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", - "SampleAfterValue": "10000003", - "UMask": "0x2" - }, - { - "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", - "SampleAfterValue": "10000003", - "UMask": "0x8" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "Fixed counter 3", - "EventName": "TOPDOWN.SLOTS", - "PEBScounters": "35", - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", - "SampleAfterValue": "10000003", - "UMask": "0x4" - }, - { - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", - "CollectPEBSRecord": "2", - "Counter": "0,1,2,3,4,5,6,7", - "EventCode": "0xa4", - "EventName": "TOPDOWN.SLOTS_P", - "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", - "SampleAfterValue": "10000003", - "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json index d0d8a09bc470..d436775c80db 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json @@ -71,14 +71,14 @@ "UMask": "0x40" }, { - "BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch).", + "BriefDescription": "Indirect near branch instructions retired (excluding returns)", "CollectPEBSRecord": "2", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", "PEBScounters": "0,1,2,3,4,5,6,7", - "PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).", + "PublicDescription": "Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.", "SampleAfterValue": "100003", "UMask": "0x80" }, @@ -442,6 +442,17 @@ "SampleAfterValue": "500009", "UMask": "0x1" }, + { + "BriefDescription": "Instruction decoders utilized in a cycle", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "INST_DECODED.DECODERS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, { "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", "CollectPEBSRecord": "2", @@ -464,6 +475,17 @@ "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.", "SampleAfterValue": "2000003" }, + { + "BriefDescription": "Number of all retired NOP instructions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5,6,7", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, { "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution", "CollectPEBSRecord": "2", @@ -689,6 +711,60 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", + "SampleAfterValue": "10000003", + "UMask": "0x2" + }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.", + "SampleAfterValue": "10000003", + "UMask": "0x8" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 3", + "EventName": "TOPDOWN.SLOTS", + "PEBScounters": "35", + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", + "SampleAfterValue": "10000003", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.SLOTS_P", + "PEBScounters": "0,1,2,3,4,5,6,7", + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", + "SampleAfterValue": "10000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UOPS_DECODED.DEC0", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Uops exclusively fetched by decoder 0", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, { "BriefDescription": "Number of uops executed on port 0", "CollectPEBSRecord": "2", diff --git a/tools/perf/pmu-events/arch/x86/tremontx/cache.json b/tools/perf/pmu-events/arch/x86/tremontx/cache.json index f88040171b4d..e142f294b42e 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/cache.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/cache.json @@ -1,111 +1,1136 @@ [ { + "BriefDescription": "Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts cacheable memory requests that miss in the the Last Level Cache. Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.", - "EventCode": "0x2e", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x31", + "EventName": "CORE_REJECT_L2Q.ANY", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "DL1.DIRTY_EVICTION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the total number of L2 Cache accesses. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a hit. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of L2 Cache accesses that resulted in a miss. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.MISS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of L2 Cache accesses that miss the L2 and get rejected. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.REJECTS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of L2 Cache accesses that miss the L2 and get BBL reject short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", - "BriefDescription": "Counts memory requests originating from the core that miss in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2." + "UMask": "0x41" }, { + "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts cacheable memory requests that access the Last Level Cache. Requests include Demand Loads, Reads for Ownership(RFO), Instruction fetches and L1 HW prefetches. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2.", - "EventCode": "0x2e", "Counter": "0,1,2,3", - "UMask": "0x4f", - "PEBScounters": "0,1,2,3", + "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PDIR_COUNTER": "na", - "SampleAfterValue": "200003", - "BriefDescription": "Counts memory requests originating from the core that reference a cache line in the last level cache. If the platform has an L3 cache, last level cache is the L3, otherwise it is the L2." - }, - { - "PEBS": "1", - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of load uops retired. This event is Precise Event capable", - "EventCode": "0xd0", - "Counter": "0,1,2,3", - "UMask": "0x81", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired.", - "Data_LA": "1" + "UMask": "0x4f" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of store uops retired. This event is Precise Event capable", - "EventCode": "0xd0", "Counter": "0,1,2,3", - "UMask": "0x82", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH", "PEBScounters": "0,1,2,3", - "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of store uops retired.", - "Data_LA": "1" + "UMask": "0x38" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles a core is stalled due to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM).", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x7" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of cycles a core is stalled due to a store buffer being full.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of load ops retired that hit in DRAM.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", "EventCode": "0xd1", - "Counter": "0,1,2,3", - "UMask": "0x1", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PEBS": "1", "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of retired loads that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of load uops retired that hit in the L1 data cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that hit the level 1 data cache", - "Data_LA": "1" + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of load uops retired that miss in the L1 data cache.", "CollectPEBSRecord": "2", - "EventCode": "0xd1", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that hit in the level 2 cache", - "Data_LA": "1" - }, - { - "PEBS": "1", - "CollectPEBSRecord": "2", + "Data_LA": "1", "EventCode": "0xd1", - "Counter": "0,1,2,3", - "UMask": "0x4", - "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that miss in the level 3 cache" - }, - { - "PEBS": "1", - "CollectPEBSRecord": "2", - "EventCode": "0xd1", - "Counter": "0,1,2,3", - "UMask": "0x8", - "PEBScounters": "0,1,2,3", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that miss in the level 1 data cache", - "Data_LA": "1" + "UMask": "0x8" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.", "CollectPEBSRecord": "2", - "EventCode": "0xd1", "Counter": "0,1,2,3", - "UMask": "0x10", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", "PEBScounters": "0,1,2,3", - "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of load uops retired that miss in the level 2 cache", - "Data_LA": "1" + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of load uops retired that miss in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x83" + }, + { + "BriefDescription": "Counts the number of load uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of load uops retired.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Counts the number of store uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of store uops retired.", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Counts the number of load uops retired that performed one or more locks.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "Counts the number of memory uops retired that were splits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x43" + }, + { + "BriefDescription": "Counts the number of retired split loads uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Counts the number of retired split store uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x42" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3001F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003C0477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1F803C0800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x101F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1010003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001003C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x201F803C0000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ICACHE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x20" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json b/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json new file mode 100644 index 000000000000..c7780fa54689 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/tremontx/floating-point.json @@ -0,0 +1,36 @@ +[ + { + "BriefDescription": "Counts the number of cycles the floating point divider is busy. Does not imply a stall waiting for the divider.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcd", + "EventName": "CYCLES_DIV_BUSY.FPDIV", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", + "SampleAfterValue": "20003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.FPDIV", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x8" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/frontend.json b/tools/perf/pmu-events/arch/x86/tremontx/frontend.json index 73b0a1ed5756..c752c52ba03e 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/frontend.json @@ -1,26 +1,105 @@ [ { + "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line and that cache line is not in the ICache (miss). The event strives to count on a cache line basis, so that multiple accesses which miss in a single cache line count as one ICACHE.MISS. Specifically, the event counts when straight line code crosses the cache line boundary, or when a branch target is to a new line, and that cache line is not in the ICache.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "ICACHE.MISSES", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", "SampleAfterValue": "200003", - "BriefDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in a cache line and they do not hit in the ICache (miss)." + "UMask": "0x1" }, { + "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes in an ICache Line. The event strives to count on a cache line basis, so that multiple fetches to a single cache line count as one ICACHE.ACCESS. Specifically, the event counts when accesses from straight line code crosses the cache line boundary, or when a branch target is to a new line.", - "EventCode": "0x80", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xe6", + "EventName": "BACLEARS.COND", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of BACLEARS due to an indirect branch.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xe6", + "EventName": "BACLEARS.INDIRECT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of BACLEARS due to a return branch.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xe6", + "EventName": "BACLEARS.RETURN", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xe6", + "EventName": "BACLEARS.UNCOND", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xe9", + "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", "SampleAfterValue": "200003", - "BriefDescription": "Counts requests to the Instruction Cache (ICache) for one or more bytes cache Line." + "UMask": "0x3" + }, + { + "BriefDescription": "Counts the number of instruction cache hits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of requests that hit in the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of instruction cache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", + "SampleAfterValue": "200003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/memory.json b/tools/perf/pmu-events/arch/x86/tremontx/memory.json index 65469e84f35b..76eaefafdc89 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/memory.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/memory.json @@ -1,26 +1,442 @@ [ { - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "EventCode": "0XB7", - "MSRValue": "0x000000003F04000001", + "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that was not supplied by the L3 cache.", - "Offcore": "1" + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "UMask": "0x2" }, { - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "EventCode": "0XB7", - "MSRValue": "0x000000003F04000002", + "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache.", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.OTHER.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184008000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.OTHER.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184008000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PREFETCHES.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000470", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2184000800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/other.json b/tools/perf/pmu-events/arch/x86/tremontx/other.json index 85bf3c8f3914..4f20f45a4898 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/other.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/other.json @@ -1,26 +1,686 @@ [ { - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "EventCode": "0XB7", - "MSRValue": "0x000000000000010001", + "BriefDescription": "Counts the total number of BTCLEARS.", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", - "MSRIndex": "0x1a6,0x1a7", - "SampleAfterValue": "100003", - "BriefDescription": "Counts demand data reads that have any response type.", - "Offcore": "1" + "EventCode": "0xe8", + "EventName": "BTCLEAR.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "SampleAfterValue": "200003" }, { - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", - "EventCode": "0XB7", - "MSRValue": "0x000000000000010002", + "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS", + "CollectPEBSRecord": "2", "Counter": "0,1,2,3", - "UMask": "0x1", + "EdgeDetect": "1", + "EventCode": "0x63", + "EventName": "BUS_LOCK.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "BUS_LOCK.BLOCK_CYCLES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x63", + "EventName": "BUS_LOCK.LOCK_CYCLES", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EdgeDetect": "1", + "EventCode": "0x63", + "EventName": "BUS_LOCK.SELF_LOCKS", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "C0_STALLS.LOAD_DRAM_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "C0_STALLS.LOAD_L2_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "C0_STALLS.LOAD_LLC_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of core cycles during which interrupts are masked (disabled).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcb", + "EventName": "HW_INTERRUPTS.MASKED", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcb", + "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of hardware interrupts received by the processor.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcb", + "EventName": "HW_INTERRUPTS.RECEIVED", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "203", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.ALL_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000044", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3000000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.COREWB_M.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8003000000000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000004", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000001", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "Offcore": "1", "SampleAfterValue": "100003", - "BriefDescription": "Counts all demand reads for ownership (RFO) requests and software based prefetches for exclusive ownership (PREFETCHW) that have any response type.", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.DEMAND_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000002", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x800000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10400", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000040", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000010", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000020", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L1WB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1000000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.L2WB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2000000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.OTHER.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x400000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all hardware and software prefetches that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.PREFETCHES.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10470", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x184000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.READS_TO_CORE.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000000000000477", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x100184000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_RD.OUTSTANDING", + "MSRIndex": "0x1a6", + "MSRValue": "0x8000100000000000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts uncached memory writes that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0XB7", + "EventName": "OCR.UC_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x200000010000", + "Offcore": "1", + "SampleAfterValue": "100003", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json b/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json index 05a8f6a7d9c0..0a77e9f9a16a 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/pipeline.json @@ -1,111 +1,674 @@ [ { - "PEBS": "1", + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of instructions that retire. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.", - "Counter": "32", - "UMask": "0x1", - "PEBScounters": "32", - "EventName": "INST_RETIRED.ANY", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of instructions retired. (Fixed event)" + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", + "SampleAfterValue": "200003" }, { + "BriefDescription": "Counts the number of near CALL branch instructions retired.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", - "Counter": "33", - "UMask": "0x2", - "PEBScounters": "33", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xf9" + }, + { + "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xbf" + }, + { + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfd" + }, + { + "BriefDescription": "Counts the number of near RET branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PDIR_COUNTER": "na", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)" + "UMask": "0x2" }, { + "BriefDescription": "Counts the number of unhalted core clock cycles.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time. This event is not affected by core frequency changes and at a fixed frequency. This event uses fixed counter 2.", - "Counter": "34", - "UMask": "0x3", - "PEBScounters": "34", - "EventName": "CPU_CLK_UNHALTED.REF_TSC", - "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)" - }, - { - "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", - "EventCode": "0x3c", "Counter": "0,1,2,3", - "PEBScounters": "0,1,2,3", + "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted core clock cycles." + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003" }, { + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts reference cycles (at TSC frequency) when core is not halted. This event uses a programmable general purpose perfmon counter.", - "EventCode": "0x3c", "Counter": "0,1,2,3", - "UMask": "0x1", - "PEBScounters": "0,1,2,3", + "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency." + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a Programmable general purpose perfmon counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event.", - "EventCode": "0xc0", - "Counter": "0,1,2,3", - "PEBScounters": "0,1,2,3", - "EventName": "INST_RETIRED.ANY_P", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of instructions retired." - }, - { - "CollectPEBSRecord": "2", - "EventCode": "0xc3", - "Counter": "0,1,2,3", - "PEBScounters": "0,1,2,3", - "EventName": "MACHINE_CLEARS.ANY", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PDIR_COUNTER": "na", - "SampleAfterValue": "20003", - "BriefDescription": "Counts all machine clears due to, but not limited to memory ordering, memory disambiguation, SMC, page faults and FP assist." + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.", + "SampleAfterValue": "2000003", + "UMask": "0x3" }, { - "PEBS": "1", + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.", - "EventCode": "0xc4", "Counter": "0,1,2,3", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PEBScounters": "0,1,2,3", - "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of branch instructions retired for all branch types." + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003", + "UMask": "0x1" }, { - "PEBS": "1", + "BriefDescription": "This event is deprecated.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts mispredicted branch instructions retired for all branch types. This event is Precise Event capable. This is an architectural event.", - "EventCode": "0xc5", "Counter": "0,1,2,3", - "PEBScounters": "0,1,2,3", - "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of mispredicted branch instructions retired." - }, - { - "CollectPEBSRecord": "2", "EventCode": "0xcd", - "Counter": "0,1,2,3", - "PEBScounters": "0,1,2,3", "EventName": "CYCLES_DIV_BUSY.ANY", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xcd", + "EventName": "CYCLES_DIV_BUSY.IDIV", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of instructions retired. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.", "SampleAfterValue": "2000003", - "BriefDescription": "Counts cycles the floating point divider or integer divider or both are busy. Does not imply a stall waiting for either divider." + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.STORE_FORWARD", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003" + }, + { + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of machine clears due typically to program modifying data (self modifying code) within 1K of a recently fetched code page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "20003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "SampleAfterValue": "1000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REGISTER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "This event is deprecated.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.CISC", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.DECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8d" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x72" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ITLB", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.OTHER", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the total number of consumed retirement slots.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the number of uops issued by the front end every cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the total number of uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts the number of integer divide uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.MS", + "PDIR_COUNTER": "na", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.X87", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x2" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json b/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json index 15376f2cf052..0d342efae154 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/uncore-memory.json @@ -50,13 +50,79 @@ "Unit": "iMC" }, { - "BriefDescription": "Precharge due to read on page miss, write on page miss or PGT", + "BriefDescription": "DRAM Activate Count : All Activates", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_M_ACT_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.", + "UMask": "0x0B", + "Unit": "iMC" + }, + { + "BriefDescription": "All DRAM CAS commands issued", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_CAS_COUNT.ALL", + "PerPkg": "1", + "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.", + "UMask": "0x3f", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "PerPkg": "1", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.", + "UMask": "0x04", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC", + "PerPkg": "1", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x45", + "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "PerPkg": "1", + "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Half clockticks for IMC", + "Counter": "FIXED", + "CounterType": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_M_HCLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Half clockticks for IMC", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM Precharge commands.", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", - "UMask": "0x1c", + "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.", + "UMask": "0x1C", "Unit": "iMC" }, { @@ -66,8 +132,92 @@ "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", - "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel.", + "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table", "UMask": "0x10", "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests.", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Unit": "iMC" + }, + { + "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", + "PerPkg": "1", + "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS.PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "UMask": "0x01", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M_WPQ_INSERTS.PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.", + "UMask": "0x02", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x82", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Unit": "iMC" + }, + { + "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", + "PerPkg": "1", + "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA. The posted filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts.", + "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json b/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json index 6deff1fe89e3..0f73582248f9 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/uncore-other.json @@ -69,6 +69,26 @@ "UMaskExt": "0xC001FE", "Unit": "CHA" }, + { + "BriefDescription": "read requests from home agent", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", + "PerPkg": "1", + "UMask": "0x03", + "Unit": "CHA" + }, + { + "BriefDescription": "write requests from home agent", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "PerPkg": "1", + "UMask": "0x0c", + "Unit": "CHA" + }, { "BriefDescription": "PCI Express bandwidth reading at IIO. Derived from unc_iio_data_req_of_cpu.mem_read.part0", "Counter": "0,1", @@ -180,101 +200,736 @@ "Unit": "IIO" }, { - "BriefDescription": "TOR Inserts; CRd misses from local IA", + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "CMS Clockticks", + "Unit": "CHA" + }, + { + "BriefDescription": "Normal priority reads issued to the memory controller from the CHA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x59", + "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA.", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x5B", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "PerPkg": "1", + "PublicDescription": "Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels.", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1BC1FF", + "UMaskExt": "0x1BC1", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : All Lines Victimized", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.ALL", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.", + "UMask": "0x0F", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for E-state entries.", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.E_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x02", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for M-state entries.", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.M_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x01", + "Unit": "CHA" + }, + { + "BriefDescription": "Snoop filter capacity evictions for S-state entries.", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x3D", + "EventName": "UNC_CHA_SF_EVICTION.S_STATE", + "PerPkg": "1", + "PublicDescription": "Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline.", + "UMask": "0x04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FF01", + "UMaskExt": "0xC001FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC8C7FF01", + "UMaskExt": "0xC8C7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC80FFF01", + "UMaskExt": "0xC80FFF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC827FF01", + "UMaskExt": "0xC827FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC8A7FF01", + "UMaskExt": "0xC8A7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FD01", + "UMaskExt": "0xC001FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC80FFD01", + "UMaskExt": "0xC80FFD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC88FFD01", + "UMaskExt": "0xC88FFD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC827FD01", + "UMaskExt": "0xC827FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC8A7FD01", + "UMaskExt": "0xC8A7FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC807FD01", + "UMaskExt": "0xC807FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC887FD01", + "UMaskExt": "0xC887FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read from local IA that misses in the snoop filter", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0xC80FFE01", "UMaskExt": "0xC80FFE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; CRd Pref misses from local IA", + "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Code read prefetch from local IA that misses in the snoop filter", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0xC88FFE01", "UMaskExt": "0xC88FFE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; DRd Opt misses from local IA", + "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt from local IA that misses in the snoop filter", + "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0xC827FE01", "UMaskExt": "0xC827FE", "Unit": "CHA" }, { - "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local IA", + "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read opt prefetch from local IA that misses in the snoop filter", + "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0xC8A7FE01", "UMaskExt": "0xC8A7FE", "Unit": "CHA" }, - { - "BriefDescription": "TOR Inserts; RFO misses from local IA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership from local IA that misses in the snoop filter", - "UMask": "0xC807FE01", - "UMaskExt": "0xC807FE", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; RFO pref misses from local IA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter", - "UMask": "0xC887FE01", - "UMaskExt": "0xC887FE", - "Unit": "CHA" - }, - { - "BriefDescription": "TOR Inserts; WCiL misses from local IA", - "Counter": "0,1,2,3", - "CounterType": "PGMABLE", - "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", - "PerPkg": "1", - "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", - "UMask": "0xC86FFE01", - "UMaskExt": "0xC86FFE", - "Unit": "CHA" - }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", "Counter": "0,1,2,3", "CounterType": "PGMABLE", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc867fe01", + "UMaskExt": "0xc867fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Data read from local IA that misses in the snoop filter", + "UMask": "0xc86ffe01", + "UMaskExt": "0xc86ffe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC807FE01", + "UMaskExt": "0xC807FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC887FE01", + "UMaskExt": "0xC887FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC877DE01", + "UMaskExt": "0xC877DE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC86FFE01", + "UMaskExt": "0xC86FFE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", "UMask": "0xC867FE01", "UMaskExt": "0xC867FE", "Unit": "CHA" }, + { + "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC87FDE01", + "UMaskExt": "0xC87FDE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC807FF01", + "UMaskExt": "0xC807FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC887FF01", + "UMaskExt": "0xC887FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FF04", + "UMaskExt": "0xC001FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FD04", + "UMaskExt": "0xC001FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCC43FD04", + "UMaskExt": "0xCC43FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCD43FD04", + "UMaskExt": "0xCD43FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC8F3FD04", + "UMaskExt": "0xC8F3FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCC43FF04", + "UMaskExt": "0xCC43FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCD43FF04", + "UMaskExt": "0xCD43FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : All requests from IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FE04", + "UMaskExt": "0xC001FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCC43FE04", + "UMaskExt": "0xCC43FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xCD43FE04", + "UMaskExt": "0xCD43FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC8F3FE04", + "UMaskExt": "0xC8F3FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC8F3FF04", + "UMaskExt": "0xC8F3FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FF01", + "UMaskExt": "0xC001FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC80FFF01", + "UMaskExt": "0xC80FFF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC827FF01", + "UMaskExt": "0xC827FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC8A7FF01", + "UMaskExt": "0xC8A7FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FD01", + "UMaskExt": "0xC001FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC827FD01", + "UMaskExt": "0xC827FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC8A7FD01", + "UMaskExt": "0xC8A7FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FE01", + "UMaskExt": "0xC001FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC80FFE01", + "UMaskExt": "0xC80FFE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC827FE01", + "UMaskExt": "0xC827FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC807FE01", + "UMaskExt": "0xC807FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC807FF01", + "UMaskExt": "0xC807FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FF04", + "UMaskExt": "0xC001FF", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FD04", + "UMaskExt": "0xC001FD", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC001FE04", + "UMaskExt": "0xC001FE", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xc8f3fe04", + "UMaskExt": "0xc8f3fe", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices", + "CounterType": "PGMABLE", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts.", + "UMask": "0xC8F3FF04", + "UMaskExt": "0xC8F3FF", + "Unit": "CHA" + }, { "BriefDescription": "Clockticks of the integrated IO (IIO) traffic controller", "Counter": "0,1,2,3", @@ -286,7 +941,552 @@ "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "BriefDescription": "Free running counter that increments for IIO clocktick", + "CounterType": "FREERUN", + "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", + "PerPkg": "1", + "PublicDescription": "Free running counter that increments for integrated IO (IIO) traffic controller clockticks", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0xff", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 4", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 5", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 6", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 7", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "UMask": "0x03", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0-7", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", + "UMask": "0xff", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 0", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 1", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1", + "UMask": "0x02", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 2", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 3", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3", + "UMask": "0x08", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 4", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 5", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 6", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIe Completion Buffer Occupancy of completions with data : Part 7", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xd5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "FCMask": "0x04", + "PerPkg": "1", + "PublicDescription": "PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to Card's MMIO space", + "Counter": "2,3", + "CounterType": "PGMABLE", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", @@ -294,12 +1494,12 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", @@ -307,12 +1507,12 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", @@ -320,12 +1520,12 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card reading from DRAM", + "BriefDescription": "Four byte data request of the CPU : Card reading from DRAM", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", @@ -333,12 +1533,12 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "PublicDescription": "Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", "UMask": "0x04", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", @@ -346,12 +1546,12 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", @@ -359,12 +1559,12 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", @@ -372,12 +1572,12 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", "UMask": "0x01", "Unit": "IIO" }, { - "BriefDescription": "Data requested of the CPU : Card writing to DRAM", + "BriefDescription": "Four byte data request of the CPU : Card writing to DRAM", "Counter": "0,1", "CounterType": "PGMABLE", "EventCode": "0x83", @@ -385,10 +1585,554 @@ "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", - "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "PublicDescription": "Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", "UMask": "0x01", "Unit": "IIO" }, + { + "BriefDescription": "Number requests PCIe makes of the main die : All", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0xFF", + "PublicDescription": "Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU.", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card reading from DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x04", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x01", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Card writing to DRAM", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "PublicDescription": "Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7", + "UMask": "0x01", + "Unit": "IIO" + }, + { + "BriefDescription": "Total IRP occupancy of inbound read and write requests to coherent memory.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x0f", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "PerPkg": "1", + "PublicDescription": "Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy.", + "UMask": "0x04", + "Unit": "IRP" + }, { "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", "Counter": "0,1", @@ -399,6 +2143,112 @@ "PublicDescription": "Clockticks of the IO coherency tracker (IRP)", "Unit": "IRP" }, + { + "BriefDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.PCITOM", + "PerPkg": "1", + "PublicDescription": "PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache.", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Coherent Ops : WbMtoI", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x10", + "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "PerPkg": "1", + "PublicDescription": "Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP", + "UMask": "0x40", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF RF full", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x17", + "EventName": "UNC_I_FAF_FULL", + "PerPkg": "1", + "PublicDescription": "FAF RF full", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and inserted into the FAF queue.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "PublicDescription": "Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "Occupancy of the IRP FAF queue.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "PerPkg": "1", + "PublicDescription": "Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP.", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x16", + "EventName": "UNC_I_FAF_TRANSACTIONS", + "PerPkg": "1", + "PublicDescription": "FAF allocation -- sent to ADQ", + "Unit": "IRP" + }, + { + "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "PerPkg": "1", + "PublicDescription": ": All Inserts Inbound (p2p + faf + cset)", + "UMask": "0x01", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.LOST_FWD", + "PerPkg": "1", + "PublicDescription": "Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Responses to snoops of any type that hit M line in the IIO cache", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x12", + "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "PerPkg": "1", + "PublicDescription": "Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache", + "UMask": "0x78", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests received by the IRP.", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "PublicDescription": "Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh.", + "UMask": "0x08", + "Unit": "IRP" + }, { "BriefDescription": "Clockticks of the mesh to memory (M2M)", "Counter": "0,1,2,3", @@ -408,6 +2258,16 @@ "PublicDescription": "Clockticks of the mesh to memory (M2M)", "Unit": "M2M" }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "CMS Clockticks", + "Unit": "M2M" + }, { "BriefDescription": "Clockticks of the mesh to PCI (M2P)", "Counter": "0,1,2,3", @@ -418,10 +2278,20 @@ "PublicDescription": "Clockticks of the mesh to PCI (M2P)", "Unit": "M2PCIe" }, + { + "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", + "CounterType": "PGMABLE", + "EventCode": "0xc0", + "EventName": "UNC_M2P_CMS_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "CMS Clockticks", + "Unit": "M2PCIe" + }, { "BriefDescription": "Clockticks in the UBOX using a dedicated 48-bit Fixed Counter", "Counter": "FIXED", - "CounterType": "PGMABLE", + "CounterType": "FIXED", "EventCode": "0xff", "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json index 93e407a0f645..ecbfc335a9b6 100644 --- a/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/tremontx/virtual-memory.json @@ -1,86 +1,365 @@ [ { + "BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a 4K page." + "UMask": "0x80" }, { + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to loads that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetches) whose address translations missed in all TLB levels and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", - "EventCode": "0x08", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", "SampleAfterValue": "200003", - "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page." + "UMask": "0x4" }, { + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K page.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PDIR_COUNTER": "na", - "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data store to a 4K page." + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0x2" }, { + "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for loads every cycle.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", - "EventCode": "0x49", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for loads every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks due to storse that miss the PDE (Page Directory Entry) cache.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to a demand data store to a 2M or 4M page." + "UMask": "0x4" }, { + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 4K page.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.", - "EventCode": "0x81", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of Extended Page Directory Entry hits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4f", + "EventName": "EPT.EPDE_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of Extended Page Directory Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of Extended Page Directory Entry misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4f", + "EventName": "EPT.EPDE_MISS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of Extended Page Directory Pointer Entry hits.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4f", + "EventName": "EPT.EPDPE_HIT", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number Extended Page Directory Pointer Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of Extended Page Directory Pointer Entry misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4f", + "EventName": "EPT.EPDPE_MISS", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number Extended Page Directory Pointer Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x4f", + "EventName": "EPT.WALK_PENDING", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x81", "EventName": "ITLB.FILLS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.", "SampleAfterValue": "200003", - "BriefDescription": "Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB." + "UMask": "0x4" }, { + "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x2", - "PEBScounters": "0,1,2,3", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.PDE_CACHE_MISS", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fetch in a 4K page." + "UMask": "0x80" }, { + "BriefDescription": "Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will results in a DTLB write from STLB.", "CollectPEBSRecord": "2", - "PublicDescription": "Counts page walks completed due to instruction fetches whose address translations missed in the TLB and were mapped to 2M or 4M pages. The page walks can end with or without a page fault.", - "EventCode": "0x85", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.STLB_HIT", + "PDIR_COUNTER": "na", "PEBScounters": "0,1,2,3", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 1G page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault.", "SampleAfterValue": "2000003", - "BriefDescription": "Page walk completed due to an instruction fetch in a 2M or 4M page." + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to a 4K page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_PENDING", + "PDIR_COUNTER": "na", + "PEBScounters": "0,1,2,3", + "PublicDescription": "Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk).", + "SampleAfterValue": "200003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of retired loads that are blocked due to a first level TLB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DTLB_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of memory retired ops that missed in the second level TLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x13" + }, + { + "BriefDescription": "Counts the number of load ops retired that miss in the second Level TLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x11" + }, + { + "BriefDescription": "Counts the number of store ops retired that miss in the second level TLB.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", + "PEBS": "1", + "PEBScounters": "0,1,2,3", + "SampleAfterValue": "200003", + "UMask": "0x12" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json index 6e61ae20d01a..0f01cf223777 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json @@ -1,2817 +1,2817 @@ [ { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D locked", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D and L2 locked", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines replaced in M state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines allocated in the M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "L1D snoop eviction of cache lines in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { - "EventCode": "0x51", + "BriefDescription": "L1 data cache lines allocated", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { - "EventCode": "0x52", + "BriefDescription": "L1D prefetch load lock accepted in fill buffer", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch misses", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests triggered", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "All L1 writebacks to L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" - }, - { "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0xf" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", + "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data requests", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand requests", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" - }, - { "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0xf" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data prefetches", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" - }, - { "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf0", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0xf0" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in M state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines alloacated", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch request" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x30" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_HIT", + "SampleAfterValue": "200000", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_MISS", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "L2 requests", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 misses", "Counter": "0,1,2,3", - "UMask": "0xaa", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 prefetches", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PREFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PREFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0xc0" }, { - "EventCode": "0x24", + "BriefDescription": "L2 prefetch hits", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCH_HIT", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCH_MISS", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", + "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xff" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO requests", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" + "UMask": "0xc" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO hits", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 fill transactions", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 instruction fetch transactions", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "L1D writeback to L2 transactions", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 Load transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 prefetch transactions", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO transactions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 writeback to LLC transactions", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe0", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" - }, - { "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf0", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0xf0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" - }, - { "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0xf" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache miss", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache reference", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "OFFCORE_REQUESTS.ANY", - "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ANY.READ", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OFFCORE_REQUESTS.ANY.RFO", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore reads" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore reads busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand code reads" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand code read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand data reads" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand data read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand RFOs" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand RFOs busy", - "CounterMask": "1" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_SQ_FULL", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue full" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SQ_MISC.LRU_HINTS", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue LRU hints sent to LLC" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", + "MSRValue": "0x0", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + "UMask": "0x10" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5011", + "BriefDescription": "Instructions retired which contains a load (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x8" + }, + { + "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ANY", + "SampleAfterValue": "100000", + "UMask": "0x80" + }, + { + "BriefDescription": "Offcore read requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ANY.READ", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "Offcore RFO requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ANY.RFO", + "SampleAfterValue": "100000", + "UMask": "0x10" + }, + { + "BriefDescription": "Offcore demand code read requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", + "SampleAfterValue": "100000", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore demand data read requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore demand RFO requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", + "SampleAfterValue": "100000", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "UMask": "0x40" + }, + { + "BriefDescription": "Outstanding offcore reads", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "Outstanding offcore demand code reads", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles offcore demand code read busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Outstanding offcore demand data reads", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Outstanding offcore demand RFOs", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore requests blocked due to Super Queue full", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f11", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff11", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8011", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x111", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x111", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x211", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x211", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x411", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x411", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x711", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1011", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x811", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5044", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f44", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff44", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8044", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x144", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x144", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x244", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x244", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x444", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x444", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x744", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1044", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x844", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x50ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x50ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7fff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7fff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xffff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xffff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x80ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5022", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f22", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff22", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8022", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x122", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x122", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x222", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x222", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x422", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x422", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x722", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1022", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x822", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5008", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f08", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff08", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8008", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x108", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x108", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x208", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x208", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x408", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x408", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x708", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1008", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x808", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5077", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f77", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff77", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8077", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x177", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x177", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x277", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x277", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x477", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x477", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x777", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1077", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x877", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5033", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f33", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff33", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8033", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x133", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x133", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x233", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x233", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x433", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x433", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x733", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1033", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x833", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5003", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f03", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff03", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8003", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x103", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x203", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x403", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x403", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x703", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5001", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f01", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff01", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8001", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x101", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x101", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x201", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x201", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x401", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x701", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1001", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x801", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5004", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f04", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff04", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8004", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x104", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x204", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x204", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x404", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x404", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x704", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1004", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x804", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5002", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f02", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff02", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8002", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x102", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x202", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x402", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x702", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1002", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x802", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5080", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f80", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff80", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8080", + "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x180", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x180", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x280", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x280", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x480", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x480", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x780", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1080", + "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x880", + "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5050", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f50", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f50", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff50", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff50", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8050", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x150", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x150", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x250", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x250", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x450", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x450", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x750", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x750", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1050", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x850", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5010", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f10", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff10", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8010", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x110", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x110", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x210", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x210", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x410", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x410", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x710", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1010", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x810", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5040", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f40", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff40", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8040", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x140", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x140", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x240", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x240", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x440", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x440", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x740", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1040", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x840", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5020", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f20", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff20", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8020", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x120", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x120", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x220", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x220", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x420", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x420", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x720", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1020", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x820", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5070", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7f70", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7f70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xff70", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xff70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8070", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x170", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x170", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x270", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x270", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x470", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x470", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x770", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1070", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x870", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json index 7d2f71a9dee3..39af1329224a 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json @@ -1,229 +1,229 @@ [ { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", - "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xF7", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.OUTPUT", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF7", + "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x2" + }, + { + "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" + "UMask": "0x2" }, { - "EventCode": "0x10", + "BriefDescription": "SSE2 integer Uops", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" - }, - { "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_COMP_OPS_EXE.SSE_FP", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" + "UMask": "0x8" }, { - "EventCode": "0x10", + "BriefDescription": "SSE* FP double precision Uops", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x80" + }, + { + "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "UMask": "0x20" + }, + { + "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x40" + }, + { + "BriefDescription": "Computational floating-point operations executed", + "Counter": "0,1,2,3", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations executed" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "All Floating Point to and from MMX transitions", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transitions" + "UMask": "0x3" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from MMX to Floating Point instructions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instructions" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from Floating Point to MMX instructions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instructions" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" + "UMask": "0x4" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" + "UMask": "0x10" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" + "UMask": "0x8" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" + "UMask": "0x4" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" + "UMask": "0x10" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit packed multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operations" + "UMask": "0x1" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" + "UMask": "0x2" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json index e5e21e03444d..8ac5c24888c5 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json @@ -1,26 +1,26 @@ [ { - "EventCode": "0xD0", + "BriefDescription": "Instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA6", + "BriefDescription": "Macro-fused instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x19", + "BriefDescription": "Two Uop instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json index 6e0829b7617f..36fbea313c6f 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json @@ -1,758 +1,758 @@ [ { - "EventCode": "0x5", + "BriefDescription": "Misaligned store references", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.STORE", "SampleAfterValue": "200000", - "BriefDescription": "Misaligned store references" + "UMask": "0x2" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3011", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf811", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4011", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2011", + "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3044", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf844", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4044", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2044", + "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x30ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x30ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf8ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf8ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x40ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x20ff", + "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20ff", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3022", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf822", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4022", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2022", + "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3008", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf808", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4008", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2008", + "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3077", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf877", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4077", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2077", + "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3033", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf833", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4033", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2033", + "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3003", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf803", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003", + "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3001", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf801", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4001", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2001", + "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3004", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf804", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4004", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2004", + "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3002", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf802", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4002", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2002", + "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3080", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf880", + "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4080", + "BriefDescription": "REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2080", + "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3050", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf850", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4050", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2050", + "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3010", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf810", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4010", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2010", + "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3040", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf840", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4040", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2040", + "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3020", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf820", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4020", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2020", + "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x3070", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_DRAM AND REMOTE_FWD", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xf870", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xf870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LLC_MISS", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4070", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = OTHER_LOCAL_DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2070", + "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_DRAM", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json index 85133d6a5ce0..23dcd554728c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json @@ -1,287 +1,287 @@ [ { - "EventCode": "0xE8", + "BriefDescription": "Early Branch Prediciton Unit clears", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" + "UMask": "0x1" }, { - "EventCode": "0xE8", + "BriefDescription": "Late Branch Prediction Unit clears", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" + "UMask": "0x2" }, { - "EventCode": "0xE5", + "BriefDescription": "Branch prediction unit missed call or return", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" + "UMask": "0x1" }, { - "EventCode": "0xD5", + "BriefDescription": "ES segment renames", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" + "UMask": "0x1" }, { - "EventCode": "0x6C", + "BriefDescription": "I/O transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" + "UMask": "0x2" }, { - "EventCode": "0x80", + "BriefDescription": "L1I Instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" + "UMask": "0x3" }, { - "EventCode": "0x82", + "BriefDescription": "Large ITLB hit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" + "UMask": "0x1" }, { - "EventCode": "0x3", + "BriefDescription": "Loads that partially overlap an earlier store", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", - "BriefDescription": "Loads that partially overlap an earlier store" + "UMask": "0x2" }, { - "EventCode": "0x13", + "BriefDescription": "All loads dispatched", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" + "UMask": "0x7" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from the MOB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" + "UMask": "0x4" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched that bypass the MOB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from stage 305", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" + "UMask": "0x2" }, { - "EventCode": "0x7", + "BriefDescription": "False dependencies due to partial address aliasing", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address aliasing" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "All RAT stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" + "UMask": "0xf" }, { - "EventCode": "0xD2", + "BriefDescription": "Flag stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "Partial register stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xD2", + "BriefDescription": "ROB read port stalls cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" + "UMask": "0x4" }, { - "EventCode": "0xD2", + "BriefDescription": "Scoreboard stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x4", + "BriefDescription": "All Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" + "UMask": "0x7" }, { - "EventCode": "0xD4", + "BriefDescription": "Segment rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Snoop code requests", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SNOOP_RESPONSE.HIT", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SNOOP_RESPONSE.HITE", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SNOOP_RESPONSE.HITM", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" - }, - { "EventCode": "0xB4", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop code requests" + "UMask": "0x4" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", - "BriefDescription": "Snoop data requests" + "UMask": "0x1" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop invalidate requests", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding snoop code requests", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop code requests" + "UMask": "0x4" }, { + "BriefDescription": "Cycles snoop code requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop code requests queued", - "CounterMask": "1" + "UMask": "0x4" }, { + "BriefDescription": "Outstanding snoop data requests", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop data requests" + "UMask": "0x1" }, { + "BriefDescription": "Cycles snoop data requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop data requests queued", - "CounterMask": "1" + "UMask": "0x1" }, { + "BriefDescription": "Outstanding snoop invalidate requests", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Cycles snoop invalidate requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop invalidate requests queued", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xF6", + "BriefDescription": "Thread responded HIT to snoop", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json index f130510f7616..10140f460fbb 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json @@ -1,899 +1,899 @@ [ { - "EventCode": "0x14", + "BriefDescription": "Cycles the divider is busy", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" + "UMask": "0x1" }, { - "EventCode": "0x14", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.DIV", - "SampleAfterValue": "2000000", "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0x14", + "EventName": "ARITH.DIV", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x14", + "BriefDescription": "Multiply operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted with bad target address", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted, regardless of cause", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " + "UMask": "0x1" }, { - "EventCode": "0xA7", + "BriefDescription": "Instruction queue forced BACLEAR", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" + "UMask": "0x1" }, { - "EventCode": "0xE0", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" + "UMask": "0x7f" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "All non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "Taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired conditional branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event)" + "SampleAfterValue": "200000", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Retired near call instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x2" + }, + { + "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" + "UMask": "0x7f" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted conditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted conditional retired branches (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional retired branches (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_MISP_RETIRED.NEAR_CALL", - "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Event)" + "SampleAfterValue": "20000", + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Mispredicted near retired calls (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "2000", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when thread is not halted (fixed counter)", "Counter": "Fixed counter 3", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles when thread is not halted (fixed counter)", "Counter": "Fixed counter 2", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles when thread is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmable counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Total CPU cycles", - "CounterMask": "2" + "Counter": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x0" }, { - "EventCode": "0x87", + "BriefDescription": "Any Instruction Length Decoder stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" + "UMask": "0xf" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Length Change Prefix stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Stall cycles due to BPU MRU bypass", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Regen stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x18", + "BriefDescription": "Instructions that must be decoded by decoder 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder 0" + "UMask": "0x1" }, { - "EventCode": "0x1E", + "BriefDescription": "Instructions written to instruction queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instruction queue" - }, - { "EventCode": "0x17", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles instructions are written to the instruction queue", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "INST_QUEUE_WRITE_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired (fixed counter)", "Counter": "Fixed counter 1", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" + "UMask": "0x0" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Retired MMX instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" - }, - { - "PEBS": "1", - "EventCode": "0xC0", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", + "CounterMask": "16", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Event)" + "UMask": "0x1" }, { - "EventCode": "0x4C", + "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", + "CounterMask": "16", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired floating-point operations (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load operations conflicting with software prefetches", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software prefetches" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles when uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.INACTIVE", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.INACTIVE", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x20", + "BriefDescription": "Loops that can't stream from the instruction queue", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction queue" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles machine clear asserted", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "FPU control word write stall cycles", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Load buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "MXCSR rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" + "UMask": "0x40" }, { - "EventCode": "0xA2", + "BriefDescription": "Other Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" + "UMask": "0x80" }, { - "EventCode": "0xA2", + "BriefDescription": "ROB full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Reservation Station full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0xDB", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" + "EventCode": "0xC7", + "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x10" }, { + "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" + "UMask": "0x4" }, { - "EventCode": "0xD1", + "BriefDescription": "Stack pointer sync operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" + "UMask": "0x8" }, { - "EventCode": "0xD1", + "BriefDescription": "Uops decoded by Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DECODED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xD1", + "EventName": "UOPS_DECODED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on any port (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops issued on any port (core count)", - "CounterMask": "1" - }, - { + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1f" + }, + { + "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" - }, - { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 2, 3 or 4", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", "AnyThread": "1", + "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "AnyThread": "1", + "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", + "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 5", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" + "UMask": "0x20" }, { - "EventCode": "0xE", + "BriefDescription": "Uops issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", + "BriefDescription": "Fused Uops issued", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" + "UMask": "0x2" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Macro-fused Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Retirement slots used (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" - }, - { - "PEBS": "1", + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "CounterMask": "16", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" + }, + { + "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", + "EventCode": "0xDB", + "EventName": "UOP_UNFUSION", + "SampleAfterValue": "2000000", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json index 57b53562e2bd..d63e469a43e1 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json @@ -1,173 +1,173 @@ [ { - "EventCode": "0x8", + "BriefDescription": "DTLB load misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" + "UMask": "0x1" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss caused by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" + "UMask": "0x10" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walks complete", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" + "UMask": "0x2" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses casued by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses casued by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB first level misses but second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x4F", + "BriefDescription": "Extended Page Table walk cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Extended Page Table walk cycles" + "UMask": "0x10" }, { - "EventCode": "0xAE", + "BriefDescription": "ITLB flushes", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC8", + "BriefDescription": "ITLB miss", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB miss page walk cycles" + "UMask": "0x4" }, { + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json index dad20f0e3cac..2ecd80f8fa67 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json @@ -1,3233 +1,3233 @@ [ { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D locked", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D and L2 locked", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines replaced in M state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines allocated in the M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "L1D snoop eviction of cache lines in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { - "EventCode": "0x51", + "BriefDescription": "L1 data cache lines allocated", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { - "EventCode": "0x52", + "BriefDescription": "L1D prefetch load lock accepted in fill buffer", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch misses", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests triggered", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "All L1 writebacks to L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" - }, - { "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0xf" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", + "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data requests", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand requests", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" - }, - { "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0xf" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data prefetches", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" - }, - { "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf0", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0xf0" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in M state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines alloacated", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch request" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x30" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_HIT", + "SampleAfterValue": "200000", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_MISS", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "L2 requests", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 misses", "Counter": "0,1,2,3", - "UMask": "0xaa", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 prefetches", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PREFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PREFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0xc0" }, { - "EventCode": "0x24", + "BriefDescription": "L2 prefetch hits", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCH_HIT", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCH_MISS", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", + "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xff" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO requests", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" + "UMask": "0xc" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO hits", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 fill transactions", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 instruction fetch transactions", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "L1D writeback to L2 transactions", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 Load transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 prefetch transactions", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO transactions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 writeback to LLC transactions", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe0", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" - }, - { "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf0", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0xf0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" - }, - { "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0xf" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache miss", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache reference", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", - "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", - "SampleAfterValue": "20000", - "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", - "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", - "SampleAfterValue": "4000", - "BriefDescription": "Load instructions retired IO (Precise Event)" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "OFFCORE_REQUESTS.ANY", - "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ANY.READ", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OFFCORE_REQUESTS.ANY.RFO", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore uncached memory accesses" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore reads" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore reads busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand code reads" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand code read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand data reads" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand data read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand RFOs" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand RFOs busy", - "CounterMask": "1" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_SQ_FULL", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue full" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SQ_MISC.LRU_HINTS", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue LRU hints sent to LLC" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", + "MSRValue": "0x0", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + "UMask": "0x10" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F11", + "BriefDescription": "Instructions retired which contains a load (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x8" + }, + { + "BriefDescription": "Load instructions retired with a data source of local DRAM or locally homed remote hitm (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load instructions retired remote cache HIT data source (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x8" + }, + { + "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x20" + }, + { + "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "PEBS": "1", + "SampleAfterValue": "4000", + "UMask": "0x80" + }, + { + "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ANY", + "SampleAfterValue": "100000", + "UMask": "0x80" + }, + { + "BriefDescription": "Offcore read requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ANY.READ", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "Offcore RFO requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ANY.RFO", + "SampleAfterValue": "100000", + "UMask": "0x10" + }, + { + "BriefDescription": "Offcore demand code read requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", + "SampleAfterValue": "100000", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore demand data read requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore demand RFO requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", + "SampleAfterValue": "100000", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "UMask": "0x40" + }, + { + "BriefDescription": "Offcore uncached memory accesses", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", + "SampleAfterValue": "100000", + "UMask": "0x20" + }, + { + "BriefDescription": "Outstanding offcore reads", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "Outstanding offcore demand code reads", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles offcore demand code read busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Outstanding offcore demand data reads", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Outstanding offcore demand RFOs", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore requests blocked due to Super Queue full", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", + "Counter": "0,1,2,3", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF11", + "BriefDescription": "All offcore data reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8011", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x111", + "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x111", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x211", + "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x211", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x411", + "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x411", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x711", + "BriefDescription": "Offcore data reads satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2711", + "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1811", + "BriefDescription": "Offcore data reads satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5811", + "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1011", + "BriefDescription": "Offcore data reads that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x811", + "BriefDescription": "Offcore data reads that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F44", + "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF44", + "BriefDescription": "All offcore code reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8044", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x144", + "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x144", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x244", + "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x244", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x444", + "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x444", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x744", + "BriefDescription": "Offcore code reads satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2744", + "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1844", + "BriefDescription": "Offcore code reads satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5844", + "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1044", + "BriefDescription": "Offcore code reads that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x844", + "BriefDescription": "Offcore code reads that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7FFF", + "BriefDescription": "Offcore requests satisfied by any cache or DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7FFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFFFF", + "BriefDescription": "All offcore requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFFFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x80FF", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x80FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1FF", + "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7FF", + "BriefDescription": "Offcore requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x27FF", + "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x27FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x18FF", + "BriefDescription": "Offcore requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x18FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x58FF", + "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x58FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x10FF", + "BriefDescription": "Offcore requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8FF", + "BriefDescription": "Offcore requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F22", + "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF22", + "BriefDescription": "All offcore RFO requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8022", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x122", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x122", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x222", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x222", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x422", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x422", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1822", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5822", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1022", + "BriefDescription": "Offcore RFO requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x822", + "BriefDescription": "Offcore RFO requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F08", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF08", + "BriefDescription": "All offcore writebacks", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore writebacks", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8008", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x108", + "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x108", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x408", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x408", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x708", + "BriefDescription": "Offcore writebacks to the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2708", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1808", + "BriefDescription": "Offcore writebacks to a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5808", + "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1008", + "BriefDescription": "Offcore writebacks that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x808", + "BriefDescription": "Offcore writebacks that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F77", + "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF77", + "BriefDescription": "All offcore code or data read requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code or data read requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8077", + "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x177", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x177", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x277", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x277", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x477", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x477", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x777", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2777", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1877", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5877", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1077", + "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x877", + "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F33", + "BriefDescription": "Offcore request = all data, response = any cache_dram", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any cache_dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF33", + "BriefDescription": "Offcore request = all data, response = any location", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any location", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8033", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x133", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x133", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x233", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x233", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x433", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x433", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x733", + "BriefDescription": "Offcore request = all data, response = local cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = local cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2733", + "BriefDescription": "Offcore request = all data, response = local cache or dram", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = local cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1833", + "BriefDescription": "Offcore request = all data, response = remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5833", + "BriefDescription": "Offcore request = all data, response = remote cache or dram", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = remote cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1033", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x833", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F03", + "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF03", + "BriefDescription": "All offcore demand data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8003", + "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x103", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x103", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x203", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x203", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x403", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x403", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x703", + "BriefDescription": "Offcore demand data requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2703", + "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1803", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5803", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1003", + "BriefDescription": "Offcore demand data requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x803", + "BriefDescription": "Offcore demand data requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F01", + "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF01", + "BriefDescription": "All offcore demand data reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8001", + "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x101", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x101", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x201", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x201", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x401", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x401", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x701", + "BriefDescription": "Offcore demand data reads satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2701", + "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1801", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5801", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1001", + "BriefDescription": "Offcore demand data reads that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x801", + "BriefDescription": "Offcore demand data reads that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F04", + "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF04", + "BriefDescription": "All offcore demand code reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8004", + "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x104", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x204", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x204", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x404", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x404", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x704", + "BriefDescription": "Offcore demand code reads satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2704", + "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1804", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5804", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1004", + "BriefDescription": "Offcore demand code reads that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x804", + "BriefDescription": "Offcore demand code reads that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F02", + "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF02", + "BriefDescription": "All offcore demand RFO requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8002", + "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x102", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x102", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x202", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x202", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x402", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x402", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x702", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2702", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1802", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5802", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1002", + "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x802", + "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F80", + "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF80", + "BriefDescription": "All offcore other requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore other requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8080", + "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x180", + "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x180", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x280", + "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x280", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x480", + "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x480", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x780", + "BriefDescription": "Offcore other requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2780", + "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1880", + "BriefDescription": "Offcore other requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5880", + "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1080", + "BriefDescription": "Offcore other requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x880", + "BriefDescription": "Offcore other requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F50", + "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F50", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF50", + "BriefDescription": "All offcore prefetch data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF50", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8050", + "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x150", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x150", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x250", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x250", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x450", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x450", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x750", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x750", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2750", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2750", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1850", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5850", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1050", + "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x850", + "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F10", + "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF10", + "BriefDescription": "All offcore prefetch data reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8010", + "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x110", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x110", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x210", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x210", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x410", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x410", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x710", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2710", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1810", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5810", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1010", + "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x810", + "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F40", + "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF40", + "BriefDescription": "All offcore prefetch code reads", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8040", + "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x140", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x140", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x240", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x240", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x440", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x440", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x740", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2740", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1840", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5840", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1040", + "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x840", + "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F20", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF20", + "BriefDescription": "All offcore prefetch RFO requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x120", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x120", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x220", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x220", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x420", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x420", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1020", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x820", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x7F70", + "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x7F70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xFF70", + "BriefDescription": "All offcore prefetch requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xFF70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x8070", + "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x170", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x170", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x270", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x270", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x470", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x470", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x770", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2770", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1870", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x5870", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x5870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x1070", + "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x1070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x870", + "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json index 7d2f71a9dee3..39af1329224a 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json @@ -1,229 +1,229 @@ [ { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", - "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xF7", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.OUTPUT", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF7", + "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x2" + }, + { + "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" + "UMask": "0x2" }, { - "EventCode": "0x10", + "BriefDescription": "SSE2 integer Uops", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" - }, - { "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_COMP_OPS_EXE.SSE_FP", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" + "UMask": "0x8" }, { - "EventCode": "0x10", + "BriefDescription": "SSE* FP double precision Uops", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x80" + }, + { + "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "UMask": "0x20" + }, + { + "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x40" + }, + { + "BriefDescription": "Computational floating-point operations executed", + "Counter": "0,1,2,3", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations executed" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "All Floating Point to and from MMX transitions", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transitions" + "UMask": "0x3" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from MMX to Floating Point instructions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instructions" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from Floating Point to MMX instructions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instructions" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" + "UMask": "0x4" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" + "UMask": "0x10" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" + "UMask": "0x8" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" + "UMask": "0x4" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" + "UMask": "0x10" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit packed multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operations" + "UMask": "0x1" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" + "UMask": "0x2" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json index e5e21e03444d..8ac5c24888c5 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json @@ -1,26 +1,26 @@ [ { - "EventCode": "0xD0", + "BriefDescription": "Instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA6", + "BriefDescription": "Macro-fused instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x19", + "BriefDescription": "Two Uop instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json index 90eb6aac357b..623a0087c8f3 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json @@ -1,739 +1,739 @@ [ { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6011", + "BriefDescription": "Offcore data reads satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF811", + "BriefDescription": "Offcore data reads that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2011", + "BriefDescription": "Offcore data reads satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4011", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6044", + "BriefDescription": "Offcore code reads satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF844", + "BriefDescription": "Offcore code reads that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2044", + "BriefDescription": "Offcore code reads satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4044", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x60FF", + "BriefDescription": "Offcore requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x60FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF8FF", + "BriefDescription": "Offcore requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x20FF", + "BriefDescription": "Offcore requests satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x20FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x40FF", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x40FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6022", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF822", + "BriefDescription": "Offcore RFO requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2022", + "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4022", + "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6008", + "BriefDescription": "Offcore writebacks to any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF808", + "BriefDescription": "Offcore writebacks that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2008", + "BriefDescription": "Offcore writebacks to the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4008", + "BriefDescription": "Offcore writebacks to a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6077", + "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF877", + "BriefDescription": "Offcore code or data read requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2077", + "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4077", + "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6033", + "BriefDescription": "Offcore request = all data, response = any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF833", + "BriefDescription": "Offcore request = all data, response = any LLC miss", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any LLC miss", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2033", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4033", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6003", + "BriefDescription": "Offcore demand data requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF803", + "BriefDescription": "Offcore demand data requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2003", + "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4003", + "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6001", + "BriefDescription": "Offcore demand data reads satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF801", + "BriefDescription": "Offcore demand data reads that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2001", + "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4001", + "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6004", + "BriefDescription": "Offcore demand code reads satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF804", + "BriefDescription": "Offcore demand code reads that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2004", + "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4004", + "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6002", + "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF802", + "BriefDescription": "Offcore demand RFO requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2002", + "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4002", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6080", + "BriefDescription": "Offcore other requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF880", + "BriefDescription": "Offcore other requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4080", + "BriefDescription": "Offcore other requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6050", + "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF850", + "BriefDescription": "Offcore prefetch data requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF850", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2050", + "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4050", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4050", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6010", + "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF810", + "BriefDescription": "Offcore prefetch data reads that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2010", + "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4010", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6040", + "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF840", + "BriefDescription": "Offcore prefetch code reads that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2040", + "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4040", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF820", + "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x6070", + "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x6070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0xF870", + "BriefDescription": "Offcore prefetch requests that missed the LLC", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0xF870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x2070", + "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x2070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7, 0xBB", - "MSRValue": "0x4070", + "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json index 85133d6a5ce0..23dcd554728c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json @@ -1,287 +1,287 @@ [ { - "EventCode": "0xE8", + "BriefDescription": "Early Branch Prediciton Unit clears", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" + "UMask": "0x1" }, { - "EventCode": "0xE8", + "BriefDescription": "Late Branch Prediction Unit clears", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" + "UMask": "0x2" }, { - "EventCode": "0xE5", + "BriefDescription": "Branch prediction unit missed call or return", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" + "UMask": "0x1" }, { - "EventCode": "0xD5", + "BriefDescription": "ES segment renames", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" + "UMask": "0x1" }, { - "EventCode": "0x6C", + "BriefDescription": "I/O transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" + "UMask": "0x2" }, { - "EventCode": "0x80", + "BriefDescription": "L1I Instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" + "UMask": "0x3" }, { - "EventCode": "0x82", + "BriefDescription": "Large ITLB hit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" + "UMask": "0x1" }, { - "EventCode": "0x3", + "BriefDescription": "Loads that partially overlap an earlier store", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", - "BriefDescription": "Loads that partially overlap an earlier store" + "UMask": "0x2" }, { - "EventCode": "0x13", + "BriefDescription": "All loads dispatched", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" + "UMask": "0x7" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from the MOB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" + "UMask": "0x4" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched that bypass the MOB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from stage 305", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" + "UMask": "0x2" }, { - "EventCode": "0x7", + "BriefDescription": "False dependencies due to partial address aliasing", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address aliasing" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "All RAT stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" + "UMask": "0xf" }, { - "EventCode": "0xD2", + "BriefDescription": "Flag stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "Partial register stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xD2", + "BriefDescription": "ROB read port stalls cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" + "UMask": "0x4" }, { - "EventCode": "0xD2", + "BriefDescription": "Scoreboard stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x4", + "BriefDescription": "All Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" + "UMask": "0x7" }, { - "EventCode": "0xD4", + "BriefDescription": "Segment rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Snoop code requests", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SNOOP_RESPONSE.HIT", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SNOOP_RESPONSE.HITE", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SNOOP_RESPONSE.HITM", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" - }, - { "EventCode": "0xB4", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop code requests" + "UMask": "0x4" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", - "BriefDescription": "Snoop data requests" + "UMask": "0x1" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop invalidate requests", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding snoop code requests", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop code requests" + "UMask": "0x4" }, { + "BriefDescription": "Cycles snoop code requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop code requests queued", - "CounterMask": "1" + "UMask": "0x4" }, { + "BriefDescription": "Outstanding snoop data requests", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop data requests" + "UMask": "0x1" }, { + "BriefDescription": "Cycles snoop data requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop data requests queued", - "CounterMask": "1" + "UMask": "0x1" }, { + "BriefDescription": "Outstanding snoop invalidate requests", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Cycles snoop invalidate requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop invalidate requests queued", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xF6", + "BriefDescription": "Thread responded HIT to snoop", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json index f130510f7616..10140f460fbb 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json @@ -1,899 +1,899 @@ [ { - "EventCode": "0x14", + "BriefDescription": "Cycles the divider is busy", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" + "UMask": "0x1" }, { - "EventCode": "0x14", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.DIV", - "SampleAfterValue": "2000000", "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0x14", + "EventName": "ARITH.DIV", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x14", + "BriefDescription": "Multiply operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted with bad target address", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted, regardless of cause", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " + "UMask": "0x1" }, { - "EventCode": "0xA7", + "BriefDescription": "Instruction queue forced BACLEAR", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" + "UMask": "0x1" }, { - "EventCode": "0xE0", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" + "UMask": "0x7f" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "All non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "Taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired conditional branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event)" + "SampleAfterValue": "200000", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Retired near call instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x2" + }, + { + "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" + "UMask": "0x7f" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted conditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted conditional retired branches (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional retired branches (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_MISP_RETIRED.NEAR_CALL", - "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Event)" + "SampleAfterValue": "20000", + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Mispredicted near retired calls (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "2000", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when thread is not halted (fixed counter)", "Counter": "Fixed counter 3", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles when thread is not halted (fixed counter)", "Counter": "Fixed counter 2", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles when thread is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmable counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Total CPU cycles", - "CounterMask": "2" + "Counter": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x0" }, { - "EventCode": "0x87", + "BriefDescription": "Any Instruction Length Decoder stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" + "UMask": "0xf" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Length Change Prefix stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Stall cycles due to BPU MRU bypass", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Regen stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x18", + "BriefDescription": "Instructions that must be decoded by decoder 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder 0" + "UMask": "0x1" }, { - "EventCode": "0x1E", + "BriefDescription": "Instructions written to instruction queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instruction queue" - }, - { "EventCode": "0x17", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles instructions are written to the instruction queue", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "INST_QUEUE_WRITE_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired (fixed counter)", "Counter": "Fixed counter 1", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" + "UMask": "0x0" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Retired MMX instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" - }, - { - "PEBS": "1", - "EventCode": "0xC0", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", + "CounterMask": "16", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Event)" + "UMask": "0x1" }, { - "EventCode": "0x4C", + "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", + "CounterMask": "16", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired floating-point operations (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load operations conflicting with software prefetches", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software prefetches" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles when uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.INACTIVE", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.INACTIVE", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x20", + "BriefDescription": "Loops that can't stream from the instruction queue", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction queue" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles machine clear asserted", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "FPU control word write stall cycles", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Load buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "MXCSR rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" + "UMask": "0x40" }, { - "EventCode": "0xA2", + "BriefDescription": "Other Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" + "UMask": "0x80" }, { - "EventCode": "0xA2", + "BriefDescription": "ROB full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Reservation Station full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0xDB", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" + "EventCode": "0xC7", + "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x10" }, { + "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" + "UMask": "0x4" }, { - "EventCode": "0xD1", + "BriefDescription": "Stack pointer sync operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" + "UMask": "0x8" }, { - "EventCode": "0xD1", + "BriefDescription": "Uops decoded by Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DECODED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xD1", + "EventName": "UOPS_DECODED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on any port (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops issued on any port (core count)", - "CounterMask": "1" - }, - { + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1f" + }, + { + "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" - }, - { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 2, 3 or 4", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", "AnyThread": "1", + "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "AnyThread": "1", + "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", + "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 5", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" + "UMask": "0x20" }, { - "EventCode": "0xE", + "BriefDescription": "Uops issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", + "BriefDescription": "Fused Uops issued", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" + "UMask": "0x2" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Macro-fused Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Retirement slots used (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" - }, - { - "PEBS": "1", + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "CounterMask": "16", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" + }, + { + "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", + "EventCode": "0xDB", + "EventName": "UOP_UNFUSION", + "SampleAfterValue": "2000000", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json index 2153b3f5d7b0..0252f77a844b 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json @@ -1,149 +1,149 @@ [ { - "EventCode": "0x8", + "BriefDescription": "DTLB load misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" + "UMask": "0x1" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss caused by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" + "UMask": "0x10" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walks complete", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" + "UMask": "0x2" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB first level misses but second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x4F", + "BriefDescription": "Extended Page Table walk cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Extended Page Table walk cycles" + "UMask": "0x10" }, { - "EventCode": "0xAE", + "BriefDescription": "ITLB flushes", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC8", + "BriefDescription": "ITLB miss", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB miss page walk cycles" + "UMask": "0x4" }, { + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/cache.json b/tools/perf/pmu-events/arch/x86/westmereex/cache.json index f9bc7fdd48d6..23de93ea347a 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/cache.json @@ -1,3225 +1,3225 @@ [ { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D locked", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D locked" + "UMask": "0x2" }, { - "EventCode": "0x63", + "BriefDescription": "Cycles L1D and L2 locked", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles L1D and L2 locked" + "UMask": "0x1" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines replaced in M state", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines replaced in M state" + "UMask": "0x4" }, { - "EventCode": "0x51", + "BriefDescription": "L1D cache lines allocated in the M state", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1D cache lines allocated in the M state" + "UMask": "0x2" }, { - "EventCode": "0x51", + "BriefDescription": "L1D snoop eviction of cache lines in M state", "Counter": "0,1", - "UMask": "0x8", + "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D snoop eviction of cache lines in M state" + "UMask": "0x8" }, { - "EventCode": "0x51", + "BriefDescription": "L1 data cache lines allocated", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", - "BriefDescription": "L1 data cache lines allocated" + "UMask": "0x1" }, { - "EventCode": "0x52", + "BriefDescription": "L1D prefetch load lock accepted in fill buffer", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "L1D prefetch load lock accepted in fill buffer" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch misses", "Counter": "0,1", - "UMask": "0x2", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch misses" + "UMask": "0x2" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests" + "UMask": "0x1" }, { - "EventCode": "0x4E", + "BriefDescription": "L1D hardware prefetch requests triggered", "Counter": "0,1", - "UMask": "0x4", + "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", - "BriefDescription": "L1D hardware prefetch requests triggered" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in E state" + "UMask": "0x4" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x28", + "BriefDescription": "All L1 writebacks to L2", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L1D_WB_L2.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in M state" - }, - { "EventCode": "0x28", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All L1 writebacks to L2" + "UMask": "0xf" }, { - "EventCode": "0x28", + "BriefDescription": "L1 writebacks to L2 in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x28", + "EventName": "L1D_WB_L2.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", + "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L1 writebacks to L2 in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data requests", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data requests" + "UMask": "0xff" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in E state" + "UMask": "0x4" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand requests", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in M state" - }, - { "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand requests" + "UMask": "0xf" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data demand loads in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data demand loads in S state" + "UMask": "0x2" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in E state" + "UMask": "0x40" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in the I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x26", + "BriefDescription": "All L2 data prefetches", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", - "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in M state" - }, - { "EventCode": "0x26", - "Counter": "0,1,2,3", - "UMask": "0xf0", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", - "BriefDescription": "All L2 data prefetches" + "UMask": "0xf0" }, { - "EventCode": "0x26", + "BriefDescription": "L2 data prefetches in M state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x26", + "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", + "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", - "BriefDescription": "L2 data prefetches in the S state" + "UMask": "0x20" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines alloacated", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines alloacated" + "UMask": "0x7" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the E state", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the E state" + "UMask": "0x4" }, { - "EventCode": "0xF1", + "BriefDescription": "L2 lines allocated in the S state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines allocated in the S state" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted" + "UMask": "0xf" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a demand request" + "UMask": "0x1" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a demand request", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a demand request" + "UMask": "0x2" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", - "BriefDescription": "L2 lines evicted by a prefetch request" + "UMask": "0x4" }, { - "EventCode": "0xF2", + "BriefDescription": "L2 modified lines evicted by a prefetch request", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", - "BriefDescription": "L2 modified lines evicted by a prefetch request" + "UMask": "0x8" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "L2_RQSTS.IFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "L2_RQSTS.IFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x30", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetches" + "UMask": "0x30" }, { - "EventCode": "0x24", + "BriefDescription": "L2 instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_HIT", + "SampleAfterValue": "200000", + "UMask": "0x10" + }, + { + "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.IFETCH_MISS", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", - "BriefDescription": "L2 load hits" + "UMask": "0x1" }, { - "EventCode": "0x24", + "BriefDescription": "L2 load misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", - "BriefDescription": "L2 load misses" + "UMask": "0x2" }, { - "EventCode": "0x24", + "BriefDescription": "L2 requests", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", - "BriefDescription": "L2 requests" + "UMask": "0x3" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 misses", "Counter": "0,1,2,3", - "UMask": "0xaa", + "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", - "BriefDescription": "All L2 misses" + "UMask": "0xaa" }, { - "EventCode": "0x24", + "BriefDescription": "All L2 prefetches", "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "L2_RQSTS.PREFETCH_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_RQSTS.PREFETCH_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc0", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 prefetches" + "UMask": "0xc0" }, { - "EventCode": "0x24", + "BriefDescription": "L2 prefetch hits", "Counter": "0,1,2,3", - "UMask": "0xff", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCH_HIT", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.PREFETCH_MISS", + "SampleAfterValue": "200000", + "UMask": "0x80" + }, + { + "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", + "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", - "BriefDescription": "All L2 requests" + "UMask": "0xff" }, { - "EventCode": "0x24", + "BriefDescription": "L2 RFO requests", "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "L2_RQSTS.RFO_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO hits" - }, - { "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_RQSTS.RFO_MISS", - "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO misses" - }, - { - "EventCode": "0x24", - "Counter": "0,1,2,3", - "UMask": "0xc", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO requests" + "UMask": "0xc" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO hits", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "SampleAfterValue": "200000", + "UMask": "0x8" + }, + { + "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All L2 transactions" + "UMask": "0x80" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 fill transactions", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", - "BriefDescription": "L2 fill transactions" + "UMask": "0x20" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 instruction fetch transactions", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 instruction fetch transactions" + "UMask": "0x4" }, { - "EventCode": "0xF0", + "BriefDescription": "L1D writeback to L2 transactions", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", - "BriefDescription": "L1D writeback to L2 transactions" + "UMask": "0x10" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 Load transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", - "BriefDescription": "L2 Load transactions" + "UMask": "0x1" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 prefetch transactions", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", - "BriefDescription": "L2 prefetch transactions" + "UMask": "0x8" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 RFO transactions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", - "BriefDescription": "L2 RFO transactions" + "UMask": "0x2" }, { - "EventCode": "0xF0", + "BriefDescription": "L2 writeback to LLC transactions", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", - "BriefDescription": "L2 writeback to LLC transactions" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in E state", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in E state" + "UMask": "0x40" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe0", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs that hit the cache" + "UMask": "0xe0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in I state (misses)" + "UMask": "0x10" }, { - "EventCode": "0x27", + "BriefDescription": "All demand L2 lock RFOs", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "L2_WRITE.LOCK.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in M state" - }, - { "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf0", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All demand L2 lock RFOs" + "UMask": "0xf0" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand lock RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x27", + "EventName": "L2_WRITE.LOCK.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x80" + }, + { + "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", + "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand lock RFOs in S state" + "UMask": "0x20" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs that hit the cache", "Counter": "0,1,2,3", - "UMask": "0xe", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs that hit the cache" + "UMask": "0xe" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in I state (misses)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in I state (misses)" + "UMask": "0x1" }, { - "EventCode": "0x27", + "BriefDescription": "All L2 demand store RFOs", "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "L2_WRITE.RFO.M_STATE", - "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in M state" - }, - { "EventCode": "0x27", - "Counter": "0,1,2,3", - "UMask": "0xf", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", - "BriefDescription": "All L2 demand store RFOs" + "UMask": "0xf" }, { - "EventCode": "0x27", + "BriefDescription": "L2 demand store RFOs in M state", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x27", + "EventName": "L2_WRITE.RFO.M_STATE", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", + "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", - "BriefDescription": "L2 demand store RFOs in S state" + "UMask": "0x2" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache miss", "Counter": "0,1,2,3", - "UMask": "0x41", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", - "BriefDescription": "Longest latency cache miss" + "UMask": "0x41" }, { - "EventCode": "0x2E", + "BriefDescription": "Longest latency cache reference", "Counter": "0,1,2,3", - "UMask": "0x4f", + "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", - "BriefDescription": "Longest latency cache reference" + "UMask": "0x4f" }, { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_INST_RETIRED.LOADS", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a load (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_INST_RETIRED.STORES", - "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired which contains a store (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "MEM_LOAD_RETIRED.HIT_LFB", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "MEM_LOAD_RETIRED.L1D_HIT", - "SampleAfterValue": "2000000", - "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_LOAD_RETIRED.L2_HIT", - "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "MEM_LOAD_RETIRED.LLC_MISS", - "SampleAfterValue": "10000", - "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", - "SampleAfterValue": "20000", - "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", - "SampleAfterValue": "10000", - "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", - "SampleAfterValue": "4000", - "BriefDescription": "Load instructions retired IO (Precise Event)" - }, - { - "PEBS": "1", - "EventCode": "0xF", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM", - "SampleAfterValue": "40000", - "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "OFFCORE_REQUESTS.ANY", - "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS.ANY.READ", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "OFFCORE_REQUESTS.ANY.RFO", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data read requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests" - }, - { - "EventCode": "0xB0", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore L1 data cache writebacks" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore reads" - }, - { - "EventCode": "0x60", - "UMask": "0x8", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore reads busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand code reads" - }, - { - "EventCode": "0x60", - "UMask": "0x2", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand code read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand data reads" - }, - { - "EventCode": "0x60", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand data read busy", - "CounterMask": "1" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", - "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding offcore demand RFOs" - }, - { - "EventCode": "0x60", - "UMask": "0x4", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles offcore demand RFOs busy", - "CounterMask": "1" - }, - { - "EventCode": "0xB2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "OFFCORE_REQUESTS_SQ_FULL", - "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests blocked due to Super Queue full" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SQ_MISC.LRU_HINTS", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue LRU hints sent to LLC" - }, - { - "EventCode": "0xF4", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SQ_MISC.SPLIT_LOCK", - "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue lock splits across a cache line" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "STORE_BLOCKS.AT_RET", - "SampleAfterValue": "200000", - "BriefDescription": "Loads delayed with at-Retirement block code" - }, - { - "EventCode": "0x6", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "STORE_BLOCKS.L1D_BLOCK", - "SampleAfterValue": "200000", - "BriefDescription": "Cacheable loads delayed with L1D block code" - }, - { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x0", + "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", + "MSRValue": "0x0", + "PEBS": "2", "SampleAfterValue": "2000000", - "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x400", + "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", "SampleAfterValue": "100", - "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x80", + "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", "SampleAfterValue": "1000", - "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x10", + "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", "SampleAfterValue": "10000", - "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4000", + "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", + "MSRValue": "0x4000", + "PEBS": "2", "SampleAfterValue": "5", - "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x800", + "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", "SampleAfterValue": "50", - "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x100", + "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", "SampleAfterValue": "500", - "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x20", + "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", "SampleAfterValue": "5000", - "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8000", + "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", + "MSRValue": "0x8000", + "PEBS": "2", "SampleAfterValue": "3", - "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x4", + "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", "SampleAfterValue": "50000", - "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x1000", + "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", + "MSRValue": "0x1000", + "PEBS": "2", "SampleAfterValue": "20", - "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x200", + "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", "SampleAfterValue": "200", - "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x40", + "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", "SampleAfterValue": "2000", - "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x8", + "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", "SampleAfterValue": "20000", - "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)" + "UMask": "0x10" }, { - "PEBS": "2", - "EventCode": "0xB", - "MSRValue": "0x2000", + "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)", "Counter": "3", - "UMask": "0x10", + "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", + "MSRValue": "0x2000", + "PEBS": "2", "SampleAfterValue": "10", - "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)" + "UMask": "0x10" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F11", + "BriefDescription": "Instructions retired which contains a load (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.LOADS", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired which contains a store (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xB", + "EventName": "MEM_INST_RETIRED.STORES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.HIT_LFB", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L1D_HIT", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_MISS", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xCB", + "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x8" + }, + { + "BriefDescription": "Load instructions retired local dram and remote cache HIT data sources (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x8" + }, + { + "BriefDescription": "Load instructions retired that HIT modified data in sibling core (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", + "PEBS": "1", + "SampleAfterValue": "10000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that hit remote socket in modified state (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM", + "PEBS": "1", + "SampleAfterValue": "40000", + "UMask": "0x4" + }, + { + "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xF", + "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", + "PEBS": "1", + "SampleAfterValue": "4000", + "UMask": "0x80" + }, + { + "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ANY", + "SampleAfterValue": "100000", + "UMask": "0x80" + }, + { + "BriefDescription": "Offcore read requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ANY.READ", + "SampleAfterValue": "100000", + "UMask": "0x8" + }, + { + "BriefDescription": "Offcore RFO requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.ANY.RFO", + "SampleAfterValue": "100000", + "UMask": "0x10" + }, + { + "BriefDescription": "Offcore demand code read requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", + "SampleAfterValue": "100000", + "UMask": "0x2" + }, + { + "BriefDescription": "Offcore demand data read requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore demand RFO requests", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", + "SampleAfterValue": "100000", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", + "EventCode": "0xB0", + "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", + "SampleAfterValue": "100000", + "UMask": "0x40" + }, + { + "BriefDescription": "Outstanding offcore reads", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles offcore reads busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x8" + }, + { + "BriefDescription": "Outstanding offcore demand code reads", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles offcore demand code read busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Outstanding offcore demand data reads", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles offcore demand data read busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Outstanding offcore demand RFOs", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles offcore demand RFOs busy", + "CounterMask": "1", + "EventCode": "0x60", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Offcore requests blocked due to Super Queue full", + "Counter": "0,1,2,3", + "EventCode": "0xB2", + "EventName": "OFFCORE_REQUESTS_SQ_FULL", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF11", + "BriefDescription": "All offcore data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF11", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8011", + "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x111", + "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x111", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x211", + "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x211", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x411", + "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x411", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x711", + "BriefDescription": "Offcore data reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4711", + "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4711", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1811", + "BriefDescription": "Offcore data reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3811", + "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1011", + "BriefDescription": "Offcore data reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x811", + "BriefDescription": "Offcore data reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F44", + "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF44", + "BriefDescription": "All offcore code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF44", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8044", + "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x144", + "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x144", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x244", + "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x244", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x444", + "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x444", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x744", + "BriefDescription": "Offcore code reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4744", + "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4744", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1844", + "BriefDescription": "Offcore code reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3844", + "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1044", + "BriefDescription": "Offcore code reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x844", + "BriefDescription": "Offcore code reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FFF", + "BriefDescription": "Offcore requests satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7FFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFFFF", + "BriefDescription": "All offcore requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFFFF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x80FF", + "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x80FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1FF", + "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x1FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x2FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4FF", + "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x4FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7FF", + "BriefDescription": "Offcore requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x7FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x47FF", + "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x47FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x18FF", + "BriefDescription": "Offcore requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x18FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x38FF", + "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x38FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x10FF", + "BriefDescription": "Offcore requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x10FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8FF", + "BriefDescription": "Offcore requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F22", + "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF22", + "BriefDescription": "All offcore RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF22", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8022", + "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x122", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x122", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x222", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x222", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x422", + "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x422", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4722", + "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4722", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1822", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3822", + "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1022", + "BriefDescription": "Offcore RFO requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x822", + "BriefDescription": "Offcore RFO requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F08", + "BriefDescription": "Offcore writebacks to any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF08", + "BriefDescription": "All offcore writebacks", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF08", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore writebacks", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8008", + "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x108", + "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x108", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x408", + "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x408", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x708", + "BriefDescription": "Offcore writebacks to the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4708", + "BriefDescription": "Offcore writebacks to the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4708", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1808", + "BriefDescription": "Offcore writebacks to a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3808", + "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1008", + "BriefDescription": "Offcore writebacks that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x808", + "BriefDescription": "Offcore writebacks that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F77", + "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF77", + "BriefDescription": "All offcore code or data read requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF77", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore code or data read requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8077", + "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x177", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x177", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x277", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x277", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x477", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x477", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x777", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4777", + "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4777", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1877", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3877", + "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1077", + "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x877", + "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F33", + "BriefDescription": "Offcore request = all data, response = any cache_dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any cache_dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF33", + "BriefDescription": "Offcore request = all data, response = any location", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF33", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any location", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8033", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x133", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x133", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x233", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x233", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x433", + "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x433", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x733", + "BriefDescription": "Offcore request = all data, response = local cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = local cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4733", + "BriefDescription": "Offcore request = all data, response = local cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4733", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = local cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1833", + "BriefDescription": "Offcore request = all data, response = remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3833", + "BriefDescription": "Offcore request = all data, response = remote cache or dram", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = remote cache or dram", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1033", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that HIT in a remote cache ", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x833", + "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F03", + "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF03", + "BriefDescription": "All offcore demand data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF03", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8003", + "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x103", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x103", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x203", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x203", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x403", + "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x403", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x703", + "BriefDescription": "Offcore demand data requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4703", + "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4703", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1803", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3803", + "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1003", + "BriefDescription": "Offcore demand data requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x803", + "BriefDescription": "Offcore demand data requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F01", + "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF01", + "BriefDescription": "All offcore demand data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF01", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8001", + "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x101", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x101", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x201", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x201", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x401", + "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x401", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x701", + "BriefDescription": "Offcore demand data reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4701", + "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4701", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1801", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3801", + "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1001", + "BriefDescription": "Offcore demand data reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x801", + "BriefDescription": "Offcore demand data reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F04", + "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF04", + "BriefDescription": "All offcore demand code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF04", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8004", + "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x104", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x104", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x204", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x204", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x404", + "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x404", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x704", + "BriefDescription": "Offcore demand code reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4704", + "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4704", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1804", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3804", + "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1004", + "BriefDescription": "Offcore demand code reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x804", + "BriefDescription": "Offcore demand code reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F02", + "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF02", + "BriefDescription": "All offcore demand RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF02", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore demand RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8002", + "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x102", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x102", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x202", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x202", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x402", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x402", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x702", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4702", + "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4702", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1802", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3802", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1002", + "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x802", + "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F80", + "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF80", + "BriefDescription": "All offcore other requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF80", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore other requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8080", + "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x180", + "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x180", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x280", + "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x280", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x480", + "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x480", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x780", + "BriefDescription": "Offcore other requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4780", + "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4780", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1880", + "BriefDescription": "Offcore other requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3880", + "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1080", + "BriefDescription": "Offcore other requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x880", + "BriefDescription": "Offcore other requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F30", + "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by any cache or DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF30", + "BriefDescription": "All offcore prefetch data requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF30", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8030", + "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the IO, CSR, MMIO unit.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x130", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x130", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x230", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x230", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x430", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x430", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x730", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4730", + "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4730", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1830", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3830", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1030", + "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x830", + "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F10", + "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF10", + "BriefDescription": "All offcore prefetch data reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF10", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch data reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8010", + "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x110", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x110", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x210", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x210", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x410", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x410", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x710", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4710", + "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4710", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1810", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3810", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1010", + "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x810", + "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F40", + "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF40", + "BriefDescription": "All offcore prefetch code reads", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF40", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch code reads", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8040", + "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x140", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x140", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x240", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x240", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x440", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x440", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x740", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4740", + "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4740", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1840", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3840", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1040", + "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x840", + "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F20", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF20", + "BriefDescription": "All offcore prefetch RFO requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF20", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch RFO requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x120", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x120", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x220", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x220", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x420", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x420", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4720", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4720", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3820", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1020", + "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x820", + "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x7F70", + "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x7F70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any cache or DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xFF70", + "BriefDescription": "All offcore prefetch requests", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", + "MSRValue": "0xFF70", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "All offcore prefetch requests", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x8070", + "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", + "MSRValue": "0x8070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the IO, CSR, MMIO unit", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x170", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", + "MSRValue": "0x170", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and not found in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x270", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x270", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HIT in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x470", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x470", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC and HITM in a sibling core", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x770", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4770", + "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4770", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the LLC or local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1870", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", + "MSRValue": "0x1870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x3870", + "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x3870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote cache or remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x1070", + "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", + "MSRValue": "0x1070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HIT in a remote cache", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x870", + "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", + "MSRValue": "0x870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that HITM in a remote cache", - "Offcore": "1" + "UMask": "0x1" + }, + { + "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.LRU_HINTS", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", + "EventCode": "0xF4", + "EventName": "SQ_MISC.SPLIT_LOCK", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.AT_RET", + "SampleAfterValue": "200000", + "UMask": "0x4" + }, + { + "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", + "EventCode": "0x6", + "EventName": "STORE_BLOCKS.L1D_BLOCK", + "SampleAfterValue": "200000", + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json index 7d2f71a9dee3..39af1329224a 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json @@ -1,229 +1,229 @@ [ { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating point assists (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xF7", + "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", - "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xF7", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "FP_ASSIST.OUTPUT", "SampleAfterValue": "20000", - "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)" + "UMask": "0x4" }, { - "EventCode": "0x10", + "BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xF7", + "EventName": "FP_ASSIST.OUTPUT", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x2" + }, + { + "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", - "BriefDescription": "MMX Uops" + "UMask": "0x2" }, { - "EventCode": "0x10", + "BriefDescription": "SSE2 integer Uops", "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP double precision Uops" - }, - { "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "FP_COMP_OPS_EXE.SSE_FP", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE and SSE2 FP Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP packed Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE FP scalar Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", - "SampleAfterValue": "2000000", - "BriefDescription": "SSE* FP single precision Uops" - }, - { - "EventCode": "0x10", - "Counter": "0,1,2,3", - "UMask": "0x8", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", - "BriefDescription": "SSE2 integer Uops" + "UMask": "0x8" }, { - "EventCode": "0x10", + "BriefDescription": "SSE* FP double precision Uops", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x80" + }, + { + "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", + "SampleAfterValue": "2000000", + "UMask": "0x10" + }, + { + "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", + "SampleAfterValue": "2000000", + "UMask": "0x20" + }, + { + "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", + "SampleAfterValue": "2000000", + "UMask": "0x40" + }, + { + "BriefDescription": "Computational floating-point operations executed", + "Counter": "0,1,2,3", + "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", - "BriefDescription": "Computational floating-point operations executed" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "All Floating Point to and from MMX transitions", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All Floating Point to and from MMX transitions" + "UMask": "0x3" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from MMX to Floating Point instructions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from MMX to Floating Point instructions" + "UMask": "0x1" }, { - "EventCode": "0xCC", + "BriefDescription": "Transitions from Floating Point to MMX instructions", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", - "BriefDescription": "Transitions from Floating Point to MMX instructions" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer pack operations" + "UMask": "0x4" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer logical operations" + "UMask": "0x10" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer multiply operations" + "UMask": "0x1" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shift operations" + "UMask": "0x2" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0x12", + "BriefDescription": "128 bit SIMD integer unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "128 bit SIMD integer unpack operations" + "UMask": "0x8" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit pack operations", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit pack operations" + "UMask": "0x4" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit arithmetic operations", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit arithmetic operations" + "UMask": "0x20" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit logical operations", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit logical operations" + "UMask": "0x10" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit packed multiply operations", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit packed multiply operations" + "UMask": "0x1" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shift operations", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shift operations" + "UMask": "0x2" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit shuffle/move operations", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit shuffle/move operations" + "UMask": "0x40" }, { - "EventCode": "0xFD", + "BriefDescription": "SIMD integer 64 bit unpack operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", - "BriefDescription": "SIMD integer 64 bit unpack operations" + "UMask": "0x8" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json index e5e21e03444d..8ac5c24888c5 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json @@ -1,26 +1,26 @@ [ { - "EventCode": "0xD0", + "BriefDescription": "Instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0xA6", + "BriefDescription": "Macro-fused instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x19", + "BriefDescription": "Two Uop instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Two Uop instructions decoded" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/memory.json b/tools/perf/pmu-events/arch/x86/westmereex/memory.json index 3ba555e73cbd..a2132858b9c1 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/memory.json @@ -1,747 +1,747 @@ [ { - "EventCode": "0x5", + "BriefDescription": "Misaligned store references", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.STORE", "SampleAfterValue": "200000", - "BriefDescription": "Misaligned store references" + "UMask": "0x2" }, { - "EventCode": "0xB7", - "MSRValue": "0x6011", + "BriefDescription": "Offcore data reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF811", + "BriefDescription": "Offcore data reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF811", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4011", + "BriefDescription": "Offcore data reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2011", + "BriefDescription": "Offcore data reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2011", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6044", + "BriefDescription": "Offcore code reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF844", + "BriefDescription": "Offcore code reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF844", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4044", + "BriefDescription": "Offcore code reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2044", + "BriefDescription": "Offcore code reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2044", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x60FF", + "BriefDescription": "Offcore requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x60FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF8FF", + "BriefDescription": "Offcore requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF8FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x40FF", + "BriefDescription": "Offcore requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x40FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x20FF", + "BriefDescription": "Offcore requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x20FF", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6022", + "BriefDescription": "Offcore RFO requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF822", + "BriefDescription": "Offcore RFO requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF822", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4022", + "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2022", + "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2022", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore RFO requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6008", + "BriefDescription": "Offcore writebacks to any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF808", + "BriefDescription": "Offcore writebacks that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF808", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4008", + "BriefDescription": "Offcore writebacks to the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2008", + "BriefDescription": "Offcore writebacks to a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2008", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore writebacks to a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6077", + "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF877", + "BriefDescription": "Offcore code or data read requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF877", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4077", + "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2077", + "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2077", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore code or data read requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6033", + "BriefDescription": "Offcore request = all data, response = any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF833", + "BriefDescription": "Offcore request = all data, response = any LLC miss", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF833", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore request = all data, response = any LLC miss", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4033", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the local DRAM.", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2033", + "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2033", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore data reads, RFO's and prefetches statisfied by the remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6003", + "BriefDescription": "Offcore demand data requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF803", + "BriefDescription": "Offcore demand data requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF803", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4003", + "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2003", + "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2003", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6001", + "BriefDescription": "Offcore demand data reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF801", + "BriefDescription": "Offcore demand data reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF801", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4001", + "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2001", + "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2001", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand data reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6004", + "BriefDescription": "Offcore demand code reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF804", + "BriefDescription": "Offcore demand code reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF804", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4004", + "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2004", + "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2004", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand code reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6002", + "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF802", + "BriefDescription": "Offcore demand RFO requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF802", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4002", + "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2002", + "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2002", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore demand RFO requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6080", + "BriefDescription": "Offcore other requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF880", + "BriefDescription": "Offcore other requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF880", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2080", + "BriefDescription": "Offcore other requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2080", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore other requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6030", + "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF830", + "BriefDescription": "Offcore prefetch data requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF830", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4030", + "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2030", + "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2030", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6010", + "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF810", + "BriefDescription": "Offcore prefetch data reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF810", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4010", + "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2010", + "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2010", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch data reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6040", + "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF840", + "BriefDescription": "Offcore prefetch code reads that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF840", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4040", + "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2040", + "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2040", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch code reads satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF820", + "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF820", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2020", + "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2020", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch RFO requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x6070", + "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x6070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by any DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0xF870", + "BriefDescription": "Offcore prefetch requests that missed the LLC", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", + "MSRValue": "0xF870", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests that missed the LLC", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x4070", + "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x4070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by the local DRAM", - "Offcore": "1" + "UMask": "0x1" }, { - "EventCode": "0xB7", - "MSRValue": "0x2070", + "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", "Counter": "2", - "UMask": "0x1", + "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", + "MSRValue": "0x2070", + "Offcore": "1", "SampleAfterValue": "100000", - "BriefDescription": "Offcore prefetch requests satisfied by a remote DRAM", - "Offcore": "1" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/perf/pmu-events/arch/x86/westmereex/other.json index 85133d6a5ce0..23dcd554728c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json @@ -1,287 +1,287 @@ [ { - "EventCode": "0xE8", + "BriefDescription": "Early Branch Prediciton Unit clears", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", - "BriefDescription": "Early Branch Prediciton Unit clears" + "UMask": "0x1" }, { - "EventCode": "0xE8", + "BriefDescription": "Late Branch Prediction Unit clears", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", - "BriefDescription": "Late Branch Prediction Unit clears" + "UMask": "0x2" }, { - "EventCode": "0xE5", + "BriefDescription": "Branch prediction unit missed call or return", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", - "BriefDescription": "Branch prediction unit missed call or return" + "UMask": "0x1" }, { - "EventCode": "0xD5", + "BriefDescription": "ES segment renames", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", - "BriefDescription": "ES segment renames" + "UMask": "0x1" }, { - "EventCode": "0x6C", + "BriefDescription": "I/O transactions", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", - "BriefDescription": "I/O transactions" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch hits", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch hits" + "UMask": "0x1" }, { - "EventCode": "0x80", + "BriefDescription": "L1I instruction fetch misses", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", - "BriefDescription": "L1I instruction fetch misses" + "UMask": "0x2" }, { - "EventCode": "0x80", + "BriefDescription": "L1I Instruction fetches", "Counter": "0,1,2,3", - "UMask": "0x3", + "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", - "BriefDescription": "L1I Instruction fetches" + "UMask": "0x3" }, { - "EventCode": "0x82", + "BriefDescription": "Large ITLB hit", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", - "BriefDescription": "Large ITLB hit" + "UMask": "0x1" }, { - "EventCode": "0x3", + "BriefDescription": "Loads that partially overlap an earlier store", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", - "BriefDescription": "Loads that partially overlap an earlier store" + "UMask": "0x2" }, { - "EventCode": "0x13", + "BriefDescription": "All loads dispatched", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All loads dispatched" + "UMask": "0x7" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from the MOB", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from the MOB" + "UMask": "0x4" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched that bypass the MOB", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched that bypass the MOB" + "UMask": "0x1" }, { - "EventCode": "0x13", + "BriefDescription": "Loads dispatched from stage 305", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", - "BriefDescription": "Loads dispatched from stage 305" + "UMask": "0x2" }, { - "EventCode": "0x7", + "BriefDescription": "False dependencies due to partial address aliasing", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", - "BriefDescription": "False dependencies due to partial address aliasing" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "All RAT stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "All RAT stall cycles" + "UMask": "0xf" }, { - "EventCode": "0xD2", + "BriefDescription": "Flag stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", - "BriefDescription": "Flag stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xD2", + "BriefDescription": "Partial register stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", - "BriefDescription": "Partial register stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xD2", + "BriefDescription": "ROB read port stalls cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", - "BriefDescription": "ROB read port stalls cycles" + "UMask": "0x4" }, { - "EventCode": "0xD2", + "BriefDescription": "Scoreboard stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", - "BriefDescription": "Scoreboard stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x4", + "BriefDescription": "All Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", - "BriefDescription": "All Store buffer stall cycles" + "UMask": "0x7" }, { - "EventCode": "0xD4", + "BriefDescription": "Segment rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", - "BriefDescription": "Segment rename stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xB8", + "BriefDescription": "Snoop code requests", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "SNOOP_RESPONSE.HIT", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HIT to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "SNOOP_RESPONSE.HITE", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITE to snoop" - }, - { - "EventCode": "0xB8", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "SNOOP_RESPONSE.HITM", - "SampleAfterValue": "100000", - "BriefDescription": "Thread responded HITM to snoop" - }, - { "EventCode": "0xB4", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop code requests" + "UMask": "0x4" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop data requests", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", - "BriefDescription": "Snoop data requests" + "UMask": "0x1" }, { - "EventCode": "0xB4", + "BriefDescription": "Snoop invalidate requests", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", - "BriefDescription": "Snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Outstanding snoop code requests", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop code requests" + "UMask": "0x4" }, { + "BriefDescription": "Cycles snoop code requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x4", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop code requests queued", - "CounterMask": "1" + "UMask": "0x4" }, { + "BriefDescription": "Outstanding snoop data requests", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop data requests" + "UMask": "0x1" }, { + "BriefDescription": "Cycles snoop data requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x1", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop data requests queued", - "CounterMask": "1" + "UMask": "0x1" }, { + "BriefDescription": "Outstanding snoop invalidate requests", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", - "BriefDescription": "Outstanding snoop invalidate requests" + "UMask": "0x2" }, { + "BriefDescription": "Cycles snoop invalidate requests queued", + "CounterMask": "1", "EventCode": "0xB3", - "UMask": "0x2", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles snoop invalidate requests queued", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xF6", + "BriefDescription": "Thread responded HIT to snoop", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HIT", + "SampleAfterValue": "100000", + "UMask": "0x1" + }, + { + "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITE", + "SampleAfterValue": "100000", + "UMask": "0x2" + }, + { + "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", + "EventCode": "0xB8", + "EventName": "SNOOP_RESPONSE.HITM", + "SampleAfterValue": "100000", + "UMask": "0x4" + }, + { + "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", + "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Super Queue full stall cycles" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json index 799c57d94c39..620d9084d860 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json @@ -1,905 +1,897 @@ [ { - "EventCode": "0x14", + "BriefDescription": "Cycles the divider is busy", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles the divider is busy" + "UMask": "0x1" }, { - "EventCode": "0x14", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ARITH.DIV", - "SampleAfterValue": "2000000", "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0x14", + "EventName": "ARITH.DIV", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x14", + "BriefDescription": "Multiply operations executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", - "BriefDescription": "Multiply operations executed" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted with bad target address", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted with bad target address" + "UMask": "0x2" }, { - "EventCode": "0xE6", + "BriefDescription": "BACLEAR asserted, regardless of cause", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", - "BriefDescription": "BACLEAR asserted, regardless of cause " + "UMask": "0x1" }, { - "EventCode": "0xA7", + "BriefDescription": "Instruction queue forced BACLEAR", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction queue forced BACLEAR" + "UMask": "0x1" }, { - "EventCode": "0xE0", + "BriefDescription": "Branch instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", - "BriefDescription": "Branch instructions decoded" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", - "BriefDescription": "Branch instructions executed" + "UMask": "0x7f" }, { - "EventCode": "0x88", + "BriefDescription": "Conditional branch instructions executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", - "BriefDescription": "Conditional branch instructions executed" + "UMask": "0x1" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", - "BriefDescription": "Unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x88", + "BriefDescription": "Unconditional call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Unconditional call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", - "BriefDescription": "Indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x88", + "BriefDescription": "Call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x88", + "BriefDescription": "All non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", - "BriefDescription": "All non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x88", + "BriefDescription": "Indirect return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", - "BriefDescription": "Indirect return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x88", + "BriefDescription": "Taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", - "BriefDescription": "Taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC4", + "BriefDescription": "Retired conditional branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", - "SampleAfterValue": "200000", - "BriefDescription": "Retired conditional branch instructions (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC4", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_INST_RETIRED.NEAR_CALL", - "SampleAfterValue": "20000", - "BriefDescription": "Retired near call instructions (Precise Event)" + "SampleAfterValue": "200000", + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Retired near call instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x7f", + "EventCode": "0xC4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "20000", + "UMask": "0x2" + }, + { + "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted branches executed" + "UMask": "0x7f" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted conditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional branches executed" + "UMask": "0x1" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted unconditional branches executed", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted unconditional branches executed" + "UMask": "0x2" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x10" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect call branches executed", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect call branches executed" + "UMask": "0x20" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted indirect non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted indirect non call branches executed" + "UMask": "0x4" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted call branches executed", "Counter": "0,1,2,3", - "UMask": "0x30", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted call branches executed" + "UMask": "0x30" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted non call branches executed", "Counter": "0,1,2,3", - "UMask": "0x7", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted non call branches executed" + "UMask": "0x7" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted return branches executed", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted return branches executed" + "UMask": "0x8" }, { - "EventCode": "0x89", + "BriefDescription": "Mispredicted taken branches executed", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted taken branches executed" + "UMask": "0x40" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted retired branch instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted retired branch instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC5", + "BriefDescription": "Mispredicted conditional retired branches (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", - "SampleAfterValue": "20000", - "BriefDescription": "Mispredicted conditional retired branches (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC5", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "BR_MISP_RETIRED.NEAR_CALL", - "SampleAfterValue": "2000", - "BriefDescription": "Mispredicted near retired calls (Precise Event)" + "SampleAfterValue": "20000", + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Mispredicted near retired calls (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC5", + "EventName": "BR_MISP_RETIRED.NEAR_CALL", + "PEBS": "1", + "SampleAfterValue": "2000", + "UMask": "0x2" + }, + { + "BriefDescription": "Reference cycles when thread is not halted (fixed counter)", "Counter": "Fixed counter 3", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000", - "BriefDescription": "Reference cycles when thread is not halted (fixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", - "BriefDescription": "Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)" + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles when thread is not halted (fixed counter)", "Counter": "Fixed counter 2", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (fixed counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", + "BriefDescription": "Cycles when thread is not halted (programmable counter)", "Counter": "0,1,2,3", - "UMask": "0x0", + "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when thread is not halted (programmable counter)" + "UMask": "0x0" }, { - "EventCode": "0x3C", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Total CPU cycles", - "CounterMask": "2" + "Counter": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x3C", + "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x0" }, { - "EventCode": "0x87", + "BriefDescription": "Any Instruction Length Decoder stall cycles", "Counter": "0,1,2,3", - "UMask": "0xf", + "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Any Instruction Length Decoder stall cycles" + "UMask": "0xf" }, { - "EventCode": "0x87", + "BriefDescription": "Instruction Queue full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Instruction Queue full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0x87", + "BriefDescription": "Length Change Prefix stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", - "BriefDescription": "Length Change Prefix stall cycles" + "UMask": "0x1" }, { - "EventCode": "0x87", + "BriefDescription": "Stall cycles due to BPU MRU bypass", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", - "BriefDescription": "Stall cycles due to BPU MRU bypass" + "UMask": "0x2" }, { - "EventCode": "0x87", + "BriefDescription": "Regen stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", - "BriefDescription": "Regen stall cycles" + "UMask": "0x8" }, { - "EventCode": "0x18", + "BriefDescription": "Instructions that must be decoded by decoder 0", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions that must be decoded by decoder 0" + "UMask": "0x1" }, { - "EventCode": "0x1E", + "BriefDescription": "Instructions written to instruction queue.", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_QUEUE_WRITE_CYCLES", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles instructions are written to the instruction queue" - }, - { "EventCode": "0x17", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions written to instruction queue." + "UMask": "0x1" }, { - "EventCode": "0x0", + "BriefDescription": "Cycles instructions are written to the instruction queue", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "INST_QUEUE_WRITE_CYCLES", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Instructions retired (fixed counter)", "Counter": "Fixed counter 1", - "UMask": "0x0", + "EventCode": "0x0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (fixed counter)" + "UMask": "0x0" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Instructions retired (Programmable counter and Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Instructions retired (Programmable counter and Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC0", + "BriefDescription": "Retired MMX instructions (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired MMX instructions (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC0", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" - }, - { - "PEBS": "1", - "EventCode": "0xC0", "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "INST_RETIRED.X87", + "CounterMask": "16", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retired floating-point operations (Precise Event)" + "UMask": "0x1" }, { - "EventCode": "0x4C", + "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", + "CounterMask": "16", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "Invert": "1", + "PEBS": "2", + "SampleAfterValue": "2000000", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired floating-point operations (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC0", + "EventName": "INST_RETIRED.X87", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x2" + }, + { + "BriefDescription": "Load operations conflicting with software prefetches", "Counter": "0,1", - "UMask": "0x1", + "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", - "BriefDescription": "Load operations conflicting with software prefetches" + "UMask": "0x1" }, { - "EventCode": "0xA8", + "BriefDescription": "Cycles when uops were delivered by the LSD", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xA8", "EventName": "LSD.ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles when uops were delivered by the LSD", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xA8", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "LSD.INACTIVE", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no uops were delivered by the LSD", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xA8", + "EventName": "LSD.INACTIVE", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0x20", + "BriefDescription": "Loops that can't stream from the instruction queue", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", - "BriefDescription": "Loops that can't stream from the instruction queue" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Cycles machine clear asserted", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", - "BriefDescription": "Cycles machine clear asserted" + "UMask": "0x1" }, { - "EventCode": "0xC3", + "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", - "BriefDescription": "Execution pipeline restart due to Memory ordering conflicts" + "UMask": "0x2" }, { - "EventCode": "0xC3", + "BriefDescription": "Self-Modifying Code detected", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", - "BriefDescription": "Self-Modifying Code detected" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Resource related stall cycles" + "UMask": "0x1" }, { - "EventCode": "0xA2", + "BriefDescription": "FPU control word write stall cycles", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", - "BriefDescription": "FPU control word write stall cycles" + "UMask": "0x20" }, { - "EventCode": "0xA2", + "BriefDescription": "Load buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", - "BriefDescription": "Load buffer stall cycles" + "UMask": "0x2" }, { - "EventCode": "0xA2", + "BriefDescription": "MXCSR rename stall cycles", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", - "BriefDescription": "MXCSR rename stall cycles" + "UMask": "0x40" }, { - "EventCode": "0xA2", + "BriefDescription": "Other Resource related stall cycles", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", - "BriefDescription": "Other Resource related stall cycles" + "UMask": "0x80" }, { - "EventCode": "0xA2", + "BriefDescription": "ROB full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "ROB full stall cycles" + "UMask": "0x10" }, { - "EventCode": "0xA2", + "BriefDescription": "Reservation Station full stall cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", - "BriefDescription": "Reservation Station full stall cycles" + "UMask": "0x4" }, { - "EventCode": "0xA2", + "BriefDescription": "Store buffer stall cycles", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", - "BriefDescription": "Store buffer stall cycles" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Double Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Packed-Single Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Event)" + "UMask": "0x8" }, { - "PEBS": "1", - "EventCode": "0xC7", + "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", - "SampleAfterValue": "200000", - "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Event)" - }, - { "PEBS": "1", - "EventCode": "0xC7", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "SampleAfterValue": "200000", - "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)" + "UMask": "0x2" }, { - "EventCode": "0x3C", + "BriefDescription": "SIMD Vector Integer Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x0", - "EventName": "CPU_CLK_UNHALTED.THREAD_P", - "SampleAfterValue": "2000000", - "BriefDescription": "Cycles thread is active" + "EventCode": "0xC7", + "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", + "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x10" }, { - "EventCode": "0xDB", + "BriefDescription": "Stack pointer instructions decoded", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOP_UNFUSION", - "SampleAfterValue": "2000000", - "BriefDescription": "Uop unfusions due to FP exceptions" - }, - { "EventCode": "0xD1", - "Counter": "0,1,2,3", - "UMask": "0x4", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer instructions decoded" + "UMask": "0x4" }, { - "EventCode": "0xD1", + "BriefDescription": "Stack pointer sync operations", "Counter": "0,1,2,3", - "UMask": "0x8", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", - "BriefDescription": "Stack pointer sync operations" + "UMask": "0x8" }, { - "EventCode": "0xD1", + "BriefDescription": "Uops decoded by Microcode Sequencer", "Counter": "0,1,2,3", - "UMask": "0x2", + "CounterMask": "1", + "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops decoded by Microcode Sequencer", - "CounterMask": "1" + "UMask": "0x2" }, { - "EventCode": "0xD1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_DECODED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops are decoded", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xD1", + "EventName": "UOPS_DECODED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on any port (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on any port (core count)", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x1f", "AnyThread": "1", + "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops executed on ports 0-4 (core count)", - "CounterMask": "1" + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x3f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", - "SampleAfterValue": "2000000", "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", - "EdgeDetect": "1" + "EdgeDetect": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1f" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x3f", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops issued on any port (core count)", - "CounterMask": "1" - }, - { + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1f", - "AnyThread": "1", - "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", - "CounterMask": "1" + "UMask": "0x3f" }, { - "EventCode": "0xB1", + "AnyThread": "1", + "BriefDescription": "Cycles no Uops issued on ports 0-4 (core count)", "Counter": "0,1,2,3", - "UMask": "0x1", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1f" + }, + { + "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 0" + "UMask": "0x1" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 0, 1 or 5", "Counter": "0,1,2,3", - "UMask": "0x40", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 0, 1 or 5" + "UMask": "0x40" }, { - "EventCode": "0xB1", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x40" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 1", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 1" + "UMask": "0x2" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x4", "AnyThread": "1", - "EventName": "UOPS_EXECUTED.PORT2_CORE", - "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 2 (core count)" - }, - { - "EventCode": "0xB1", + "BriefDescription": "Uops issued on ports 2, 3 or 4", "Counter": "0,1,2,3", - "UMask": "0x80", - "AnyThread": "1", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued on ports 2, 3 or 4" + "UMask": "0x80" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x8", "AnyThread": "1", + "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", + "EventName": "UOPS_EXECUTED.PORT2_CORE", + "SampleAfterValue": "2000000", + "UMask": "0x4" + }, + { + "AnyThread": "1", + "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 3 (core count)" + "UMask": "0x8" }, { - "EventCode": "0xB1", - "Counter": "0,1,2,3", - "UMask": "0x10", "AnyThread": "1", + "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 4 (core count)" + "UMask": "0x10" }, { - "EventCode": "0xB1", + "BriefDescription": "Uops executed on port 5", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", - "BriefDescription": "Uops executed on port 5" + "UMask": "0x20" }, { - "EventCode": "0xE", + "BriefDescription": "Uops issued", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", - "BriefDescription": "Uops issued" + "UMask": "0x1" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", - "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops were issued on any thread", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", + "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "EventCode": "0xE", - "Counter": "0,1,2,3", - "UMask": "0x1", "AnyThread": "1", + "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", "SampleAfterValue": "2000000", - "BriefDescription": "Cycles Uops were issued on either thread", - "CounterMask": "1" + "UMask": "0x1" }, { - "EventCode": "0xE", + "BriefDescription": "Fused Uops issued", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", - "BriefDescription": "Fused Uops issued" + "UMask": "0x2" }, { - "EventCode": "0xE", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_ISSUED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles no Uops were issued", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xE", + "EventName": "UOPS_ISSUED.STALL_CYCLES", + "Invert": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles Uops are being retired", - "CounterMask": "1" + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", + "PEBS": "1", + "SampleAfterValue": "2000000", + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Uops retired (Precise Event)" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Macro-fused Uops retired (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Macro-fused Uops retired (Precise Event)" + "UMask": "0x4" }, { - "PEBS": "1", - "EventCode": "0xC2", + "BriefDescription": "Retirement slots used (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Retirement slots used (Precise Event)" + "UMask": "0x2" }, { - "PEBS": "1", - "EventCode": "0xC2", - "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.STALL_CYCLES", - "SampleAfterValue": "2000000", "BriefDescription": "Cycles Uops are not retiring (Precise Event)", - "CounterMask": "1" - }, - { - "PEBS": "1", + "Counter": "0,1,2,3", + "CounterMask": "1", "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.STALL_CYCLES", "Invert": "1", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" }, { - "PEBS": "2", - "EventCode": "0xC0", - "Invert": "1", + "BriefDescription": "Total cycles using precise uop retired event (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", + "CounterMask": "16", + "EventCode": "0xC2", + "EventName": "UOPS_RETIRED.TOTAL_CYCLES", + "Invert": "1", + "PEBS": "1", "SampleAfterValue": "2000000", - "BriefDescription": "Total cycles (Precise Event)", - "CounterMask": "16" + "UMask": "0x1" + }, + { + "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", + "EventCode": "0xDB", + "EventName": "UOP_UNFUSION", + "SampleAfterValue": "2000000", + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json index ad989207e8f8..5d1e017d1261 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json @@ -1,173 +1,173 @@ [ { - "EventCode": "0x8", + "BriefDescription": "DTLB load misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load misses" + "UMask": "0x1" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss caused by low part of address", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss caused by low part of address" + "UMask": "0x20" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB second level hit" + "UMask": "0x10" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walks complete", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walks complete" + "UMask": "0x2" }, { - "EventCode": "0x8", + "BriefDescription": "DTLB load miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", - "BriefDescription": "DTLB load miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses" + "UMask": "0x1" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.", "Counter": "0,1,2,3", - "UMask": "0x20", + "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", - "BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE." + "UMask": "0x20" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB first level misses but second level hit", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", - "BriefDescription": "DTLB first level misses but second level hit" + "UMask": "0x10" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "DTLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x49", + "BriefDescription": "DTLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "DTLB miss page walk cycles" + "UMask": "0x4" }, { - "EventCode": "0x4F", + "BriefDescription": "Extended Page Table walk cycles", "Counter": "0,1,2,3", - "UMask": "0x10", + "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "Extended Page Table walk cycles" + "UMask": "0x10" }, { - "EventCode": "0xAE", + "BriefDescription": "ITLB flushes", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB flushes" + "UMask": "0x1" }, { - "PEBS": "1", - "EventCode": "0xC8", + "BriefDescription": "ITLB miss", "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISS_RETIRED", - "SampleAfterValue": "200000", - "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)" - }, - { "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss" + "UMask": "0x1" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss large page walks", "Counter": "0,1,2,3", - "UMask": "0x80", + "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss large page walks" + "UMask": "0x80" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walks", "Counter": "0,1,2,3", - "UMask": "0x2", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", - "BriefDescription": "ITLB miss page walks" + "UMask": "0x2" }, { - "EventCode": "0x85", + "BriefDescription": "ITLB miss page walk cycles", "Counter": "0,1,2,3", - "UMask": "0x4", + "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", - "BriefDescription": "ITLB miss page walk cycles" + "UMask": "0x4" }, { + "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", + "Counter": "0,1,2,3", + "EventCode": "0xC8", + "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", + "SampleAfterValue": "200000", + "UMask": "0x20" + }, + { + "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", - "Counter": "0,1,2,3", - "UMask": "0x80", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired loads that miss the DTLB (Precise Event)" + "UMask": "0x80" }, { - "PEBS": "1", - "EventCode": "0xC", + "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", "Counter": "0,1,2,3", - "UMask": "0x1", + "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", + "PEBS": "1", "SampleAfterValue": "200000", - "BriefDescription": "Retired stores that miss the DTLB (Precise Event)" + "UMask": "0x1" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 1a57c3f81dd4..159d9eab6e79 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -277,6 +277,7 @@ static struct map { { "CPU-M-CF", "cpum_cf" }, { "CPU-M-SF", "cpum_sf" }, { "UPI LL", "uncore_upi" }, + { "hisi_sicl,cpa", "hisi_sicl,cpa"}, { "hisi_sccl,ddrc", "hisi_sccl,ddrc" }, { "hisi_sccl,hha", "hisi_sccl,hha" }, { "hisi_sccl,l3c", "hisi_sccl,l3c" }, diff --git a/tools/perf/scripts/python/export-to-postgresql.py b/tools/perf/scripts/python/export-to-postgresql.py index d187e46c2683..3a6bdcd74e60 100644 --- a/tools/perf/scripts/python/export-to-postgresql.py +++ b/tools/perf/scripts/python/export-to-postgresql.py @@ -399,7 +399,8 @@ if branches: 'in_tx boolean,' 'call_path_id bigint,' 'insn_count bigint,' - 'cyc_count bigint)') + 'cyc_count bigint,' + 'flags integer)') else: do_query(query, 'CREATE TABLE samples (' 'id bigint NOT NULL,' @@ -425,7 +426,8 @@ else: 'in_tx boolean,' 'call_path_id bigint,' 'insn_count bigint,' - 'cyc_count bigint)') + 'cyc_count bigint,' + 'flags integer)') if perf_db_export_calls or perf_db_export_callchains: do_query(query, 'CREATE TABLE call_paths (' @@ -604,7 +606,8 @@ do_query(query, 'CREATE VIEW samples_view AS ' 'in_tx,' 'insn_count,' 'cyc_count,' - 'CASE WHEN cyc_count=0 THEN CAST(0 AS NUMERIC(20, 2)) ELSE CAST((CAST(insn_count AS FLOAT) / cyc_count) AS NUMERIC(20, 2)) END AS IPC' + 'CASE WHEN cyc_count=0 THEN CAST(0 AS NUMERIC(20, 2)) ELSE CAST((CAST(insn_count AS FLOAT) / cyc_count) AS NUMERIC(20, 2)) END AS IPC,' + 'flags' ' FROM samples') do_query(query, 'CREATE VIEW ptwrite_view AS ' @@ -804,7 +807,7 @@ def trace_begin(): comm_table(0, "unknown", 0, 0, 0) dso_table(0, 0, "unknown", "unknown", "") symbol_table(0, 0, 0, 0, 0, "unknown") - sample_table(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + sample_table(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) if perf_db_export_calls or perf_db_export_callchains: call_path_table(0, 0, 0, 0) call_return_table(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) @@ -1025,11 +1028,11 @@ def branch_type_table(branch_type, name, *x): value = struct.pack(fmt, 2, 4, branch_type, n, name) branch_type_file.write(value) -def sample_table(sample_id, evsel_id, machine_id, thread_id, comm_id, dso_id, symbol_id, sym_offset, ip, time, cpu, to_dso_id, to_symbol_id, to_sym_offset, to_ip, period, weight, transaction, data_src, branch_type, in_tx, call_path_id, insn_cnt, cyc_cnt, *x): +def sample_table(sample_id, evsel_id, machine_id, thread_id, comm_id, dso_id, symbol_id, sym_offset, ip, time, cpu, to_dso_id, to_symbol_id, to_sym_offset, to_ip, period, weight, transaction, data_src, branch_type, in_tx, call_path_id, insn_cnt, cyc_cnt, flags, *x): if branches: - value = struct.pack("!hiqiqiqiqiqiqiqiqiqiqiiiqiqiqiqiiiBiqiqiq", 20, 8, sample_id, 8, evsel_id, 8, machine_id, 8, thread_id, 8, comm_id, 8, dso_id, 8, symbol_id, 8, sym_offset, 8, ip, 8, time, 4, cpu, 8, to_dso_id, 8, to_symbol_id, 8, to_sym_offset, 8, to_ip, 4, branch_type, 1, in_tx, 8, call_path_id, 8, insn_cnt, 8, cyc_cnt) + value = struct.pack("!hiqiqiqiqiqiqiqiqiqiqiiiqiqiqiqiiiBiqiqiqii", 21, 8, sample_id, 8, evsel_id, 8, machine_id, 8, thread_id, 8, comm_id, 8, dso_id, 8, symbol_id, 8, sym_offset, 8, ip, 8, time, 4, cpu, 8, to_dso_id, 8, to_symbol_id, 8, to_sym_offset, 8, to_ip, 4, branch_type, 1, in_tx, 8, call_path_id, 8, insn_cnt, 8, cyc_cnt, 4, flags) else: - value = struct.pack("!hiqiqiqiqiqiqiqiqiqiqiiiqiqiqiqiqiqiqiqiiiBiqiqiq", 24, 8, sample_id, 8, evsel_id, 8, machine_id, 8, thread_id, 8, comm_id, 8, dso_id, 8, symbol_id, 8, sym_offset, 8, ip, 8, time, 4, cpu, 8, to_dso_id, 8, to_symbol_id, 8, to_sym_offset, 8, to_ip, 8, period, 8, weight, 8, transaction, 8, data_src, 4, branch_type, 1, in_tx, 8, call_path_id, 8, insn_cnt, 8, cyc_cnt) + value = struct.pack("!hiqiqiqiqiqiqiqiqiqiqiiiqiqiqiqiqiqiqiqiiiBiqiqiqii", 25, 8, sample_id, 8, evsel_id, 8, machine_id, 8, thread_id, 8, comm_id, 8, dso_id, 8, symbol_id, 8, sym_offset, 8, ip, 8, time, 4, cpu, 8, to_dso_id, 8, to_symbol_id, 8, to_sym_offset, 8, to_ip, 8, period, 8, weight, 8, transaction, 8, data_src, 4, branch_type, 1, in_tx, 8, call_path_id, 8, insn_cnt, 8, cyc_cnt, 4, flags) sample_file.write(value) def call_path_table(cp_id, parent_id, symbol_id, ip, *x): diff --git a/tools/perf/scripts/python/export-to-sqlite.py b/tools/perf/scripts/python/export-to-sqlite.py index 8043a7272a56..73c992feb1b9 100644 --- a/tools/perf/scripts/python/export-to-sqlite.py +++ b/tools/perf/scripts/python/export-to-sqlite.py @@ -223,7 +223,8 @@ if branches: 'in_tx boolean,' 'call_path_id bigint,' 'insn_count bigint,' - 'cyc_count bigint)') + 'cyc_count bigint,' + 'flags integer)') else: do_query(query, 'CREATE TABLE samples (' 'id integer NOT NULL PRIMARY KEY,' @@ -249,7 +250,8 @@ else: 'in_tx boolean,' 'call_path_id bigint,' 'insn_count bigint,' - 'cyc_count bigint)') + 'cyc_count bigint,' + 'flags integer)') if perf_db_export_calls or perf_db_export_callchains: do_query(query, 'CREATE TABLE call_paths (' @@ -442,7 +444,8 @@ do_query(query, 'CREATE VIEW samples_view AS ' 'in_tx,' 'insn_count,' 'cyc_count,' - 'CASE WHEN cyc_count=0 THEN CAST(0 AS FLOAT) ELSE ROUND(CAST(insn_count AS FLOAT) / cyc_count, 2) END AS IPC' + 'CASE WHEN cyc_count=0 THEN CAST(0 AS FLOAT) ELSE ROUND(CAST(insn_count AS FLOAT) / cyc_count, 2) END AS IPC,' + 'flags' ' FROM samples') do_query(query, 'CREATE VIEW ptwrite_view AS ' @@ -584,9 +587,9 @@ branch_type_query = QSqlQuery(db) branch_type_query.prepare("INSERT INTO branch_types VALUES (?, ?)") sample_query = QSqlQuery(db) if branches: - sample_query.prepare("INSERT INTO samples VALUES (?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?)") + sample_query.prepare("INSERT INTO samples VALUES (?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?)") else: - sample_query.prepare("INSERT INTO samples VALUES (?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?)") + sample_query.prepare("INSERT INTO samples VALUES (?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?, ?)") if perf_db_export_calls or perf_db_export_callchains: call_path_query = QSqlQuery(db) call_path_query.prepare("INSERT INTO call_paths VALUES (?, ?, ?, ?)") @@ -618,7 +621,7 @@ def trace_begin(): comm_table(0, "unknown", 0, 0, 0) dso_table(0, 0, "unknown", "unknown", "") symbol_table(0, 0, 0, 0, 0, "unknown") - sample_table(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) + sample_table(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) if perf_db_export_calls or perf_db_export_callchains: call_path_table(0, 0, 0, 0) call_return_table(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) @@ -703,11 +706,11 @@ def sample_table(*x): if branches: for xx in x[0:15]: sample_query.addBindValue(str(xx)) - for xx in x[19:24]: + for xx in x[19:25]: sample_query.addBindValue(str(xx)) do_query_(sample_query) else: - bind_exec(sample_query, 24, x) + bind_exec(sample_query, 25, x) def call_path_table(*x): bind_exec(call_path_query, 4, x) diff --git a/tools/perf/scripts/python/intel-pt-events.py b/tools/perf/scripts/python/intel-pt-events.py index 66452a8ec358..973bd12b7b40 100644 --- a/tools/perf/scripts/python/intel-pt-events.py +++ b/tools/perf/scripts/python/intel-pt-events.py @@ -76,16 +76,16 @@ def trace_begin(): glb_args = ap.parse_args() if glb_args.insn_trace: print("Intel PT Instruction Trace") - itrace = "i0nsepwx" + itrace = "i0nsepwxI" glb_insn = True elif glb_args.src_trace: print("Intel PT Source Trace") - itrace = "i0nsepwx" + itrace = "i0nsepwxI" glb_insn = True glb_src = True else: - print("Intel PT Branch Trace, Power Events and PTWRITE") - itrace = "bepwx" + print("Intel PT Branch Trace, Power Events, Event Trace and PTWRITE") + itrace = "bepwxI" global glb_disassembler try: glb_disassembler = LibXED() @@ -149,6 +149,43 @@ def print_psb(raw_buf): offset = data[1] print("offset: %#x" % (offset), end=' ') +glb_cfe = ["", "INTR", "IRET", "SMI", "RSM", "SIPI", "INIT", "VMENTRY", "VMEXIT", + "VMEXIT_INTR", "SHUTDOWN", "", "UINT", "UIRET"] + [""] * 18 +glb_evd = ["", "PFA", "VMXQ", "VMXR"] + [""] * 60 + +def print_evt(raw_buf): + data = struct.unpack_from("> 7 + vector = data[1] + evd_cnt = data[2] + s = glb_cfe[typ] + if s: + print(" cfe: %s IP: %u vector: %u" % (s, ip_flag, vector), end=' ') + else: + print(" cfe: %u IP: %u vector: %u" % (typ, ip_flag, vector), end=' ') + pos = 4 + for i in range(evd_cnt): + data = struct.unpack_from("%u %s branch" % (old_iflag, iflag, s), end=' ') + def common_start_str(comm, sample): ts = sample["time"] cpu = sample["cpu"] @@ -164,7 +201,7 @@ def print_common_start(comm, sample, name): # weight = sample["weight"] # transaction = sample["transaction"] # cpumode = get_optional_zero(sample, "cpumode") - print(common_start_str(comm, sample) + "%7s %19s" % (name, flags_disp), end=' ') + print(common_start_str(comm, sample) + "%8s %21s" % (name, flags_disp), end=' ') def print_instructions_start(comm, sample): if "x" in get_optional_null(sample, "flags"): @@ -315,6 +352,14 @@ def do_process_event(param_dict): print_common_start(comm, sample, name) print_psb(raw_buf) print_common_ip(param_dict, sample, symbol, dso) + elif name == "evt": + print_common_start(comm, sample, name) + print_evt(raw_buf) + print_common_ip(param_dict, sample, symbol, dso) + elif name == "iflag": + print_common_start(comm, sample, name) + print_iflag(raw_buf) + print_common_ip(param_dict, sample, symbol, dso) else: print_common_start(comm, sample, name) print_common_ip(param_dict, sample, symbol, dso) diff --git a/tools/perf/tests/attr/README b/tools/perf/tests/attr/README index 1116fc6bf2ac..454505d343fa 100644 --- a/tools/perf/tests/attr/README +++ b/tools/perf/tests/attr/README @@ -58,6 +58,8 @@ Following tests are defined (with perf commands): perf record -c 100 -P kill (test-record-period) perf record -c 1 --pfm-events=cycles:period=2 (test-record-pfm-period) perf record -R kill (test-record-raw) + perf record -c 2 -e arm_spe_0// -- kill (test-record-spe-period) + perf record -e arm_spe_0/period=3/ -- kill (test-record-spe-period-term) perf stat -e cycles kill (test-stat-basic) perf stat kill (test-stat-default) perf stat -d kill (test-stat-detailed-1) diff --git a/tools/perf/tests/attr/base-record-spe b/tools/perf/tests/attr/base-record-spe new file mode 100644 index 000000000000..08fa96b59240 --- /dev/null +++ b/tools/perf/tests/attr/base-record-spe @@ -0,0 +1,40 @@ +[event] +fd=* +group_fd=-1 +flags=* +cpu=* +type=* +size=* +config=* +sample_period=* +sample_type=* +read_format=* +disabled=* +inherit=* +pinned=* +exclusive=* +exclude_user=* +exclude_kernel=* +exclude_hv=* +exclude_idle=* +mmap=* +comm=* +freq=* +inherit_stat=* +enable_on_exec=* +task=* +watermark=* +precise_ip=* +mmap_data=* +sample_id_all=* +exclude_host=* +exclude_guest=* +exclude_callchain_kernel=* +exclude_callchain_user=* +wakeup_events=* +bp_type=* +config1=* +config2=* +branch_sample_type=* +sample_regs_user=* +sample_stack_user=* diff --git a/tools/perf/tests/attr/test-record-spe-period b/tools/perf/tests/attr/test-record-spe-period new file mode 100644 index 000000000000..75f8c9cd8e3f --- /dev/null +++ b/tools/perf/tests/attr/test-record-spe-period @@ -0,0 +1,12 @@ +[config] +command = record +args = --no-bpf-event -c 2 -e arm_spe_0// -- kill >/dev/null 2>&1 +ret = 1 +arch = aarch64 + +[event-10:base-record-spe] +sample_period=2 +freq=0 + +# dummy event +[event-1:base-record-spe] diff --git a/tools/perf/tests/attr/test-record-spe-period-term b/tools/perf/tests/attr/test-record-spe-period-term new file mode 100644 index 000000000000..8f60a4fec657 --- /dev/null +++ b/tools/perf/tests/attr/test-record-spe-period-term @@ -0,0 +1,12 @@ +[config] +command = record +args = --no-bpf-event -e arm_spe_0/period=3/ -- kill >/dev/null 2>&1 +ret = 1 +arch = aarch64 + +[event-10:base-record-spe] +sample_period=3 +freq=0 + +# dummy event +[event-1:base-record-spe] diff --git a/tools/perf/tests/bpf.c b/tools/perf/tests/bpf.c index 573490530194..57b9591f7cbb 100644 --- a/tools/perf/tests/bpf.c +++ b/tools/perf/tests/bpf.c @@ -281,8 +281,8 @@ out: static int check_env(void) { + LIBBPF_OPTS(bpf_prog_load_opts, opts); int err; - unsigned int kver_int; char license[] = "GPL"; struct bpf_insn insns[] = { @@ -290,19 +290,13 @@ static int check_env(void) BPF_EXIT_INSN(), }; - err = fetch_kernel_version(&kver_int, NULL, 0); + err = fetch_kernel_version(&opts.kern_version, NULL, 0); if (err) { pr_debug("Unable to get kernel version\n"); return err; } - -/* temporarily disable libbpf deprecation warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wdeprecated-declarations" - err = bpf_load_program(BPF_PROG_TYPE_KPROBE, insns, - ARRAY_SIZE(insns), - license, kver_int, NULL, 0); -#pragma GCC diagnostic pop + err = bpf_prog_load(BPF_PROG_TYPE_KPROBE, NULL, license, insns, + ARRAY_SIZE(insns), &opts); if (err < 0) { pr_err("Missing basic BPF support, skip this test: %s\n", strerror(errno)); diff --git a/tools/perf/tests/cpumap.c b/tools/perf/tests/cpumap.c index 84e87e31f119..f94929ebb54b 100644 --- a/tools/perf/tests/cpumap.c +++ b/tools/perf/tests/cpumap.c @@ -35,10 +35,10 @@ static int process_event_mask(struct perf_tool *tool __maybe_unused, } map = cpu_map__new_data(data); - TEST_ASSERT_VAL("wrong nr", map->nr == 20); + TEST_ASSERT_VAL("wrong nr", perf_cpu_map__nr(map) == 20); for (i = 0; i < 20; i++) { - TEST_ASSERT_VAL("wrong cpu", map->map[i].cpu == i); + TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, i).cpu == i); } perf_cpu_map__put(map); @@ -66,9 +66,9 @@ static int process_event_cpus(struct perf_tool *tool __maybe_unused, TEST_ASSERT_VAL("wrong cpu", cpus->cpu[1] == 256); map = cpu_map__new_data(data); - TEST_ASSERT_VAL("wrong nr", map->nr == 2); - TEST_ASSERT_VAL("wrong cpu", map->map[0].cpu == 1); - TEST_ASSERT_VAL("wrong cpu", map->map[1].cpu == 256); + TEST_ASSERT_VAL("wrong nr", perf_cpu_map__nr(map) == 2); + TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, 0).cpu == 1); + TEST_ASSERT_VAL("wrong cpu", perf_cpu_map__cpu(map, 1).cpu == 256); TEST_ASSERT_VAL("wrong refcnt", refcount_read(&map->refcnt) == 1); perf_cpu_map__put(map); return 0; @@ -130,7 +130,7 @@ static int test__cpu_map_merge(struct test_suite *test __maybe_unused, int subte struct perf_cpu_map *c = perf_cpu_map__merge(a, b); char buf[100]; - TEST_ASSERT_VAL("failed to merge map: bad nr", c->nr == 5); + TEST_ASSERT_VAL("failed to merge map: bad nr", perf_cpu_map__nr(c) == 5); cpu_map__snprint(c, buf, sizeof(buf)); TEST_ASSERT_VAL("failed to merge map: bad result", !strcmp(buf, "1-2,4-5,7")); perf_cpu_map__put(b); diff --git a/tools/perf/tests/maps.c b/tools/perf/tests/maps.c index e308a3296cef..a69988a89d26 100644 --- a/tools/perf/tests/maps.c +++ b/tools/perf/tests/maps.c @@ -35,7 +35,6 @@ static int check_maps(struct map_def *merged, unsigned int size, struct maps *ma static int test__maps__merge_in(struct test_suite *t __maybe_unused, int subtest __maybe_unused) { - struct maps maps; unsigned int i; struct map_def bpf_progs[] = { { "bpf_prog_1", 200, 300 }, @@ -63,8 +62,9 @@ static int test__maps__merge_in(struct test_suite *t __maybe_unused, int subtest }; struct map *map_kcore1, *map_kcore2, *map_kcore3; int ret; + struct maps *maps = maps__new(NULL); - maps__init(&maps, NULL); + TEST_ASSERT_VAL("failed to create maps", maps); for (i = 0; i < ARRAY_SIZE(bpf_progs); i++) { struct map *map; @@ -74,7 +74,7 @@ static int test__maps__merge_in(struct test_suite *t __maybe_unused, int subtest map->start = bpf_progs[i].start; map->end = bpf_progs[i].end; - maps__insert(&maps, map); + maps__insert(maps, map); map__put(map); } @@ -99,25 +99,25 @@ static int test__maps__merge_in(struct test_suite *t __maybe_unused, int subtest map_kcore3->start = 880; map_kcore3->end = 1100; - ret = maps__merge_in(&maps, map_kcore1); + ret = maps__merge_in(maps, map_kcore1); TEST_ASSERT_VAL("failed to merge map", !ret); - ret = check_maps(merged12, ARRAY_SIZE(merged12), &maps); + ret = check_maps(merged12, ARRAY_SIZE(merged12), maps); TEST_ASSERT_VAL("merge check failed", !ret); - ret = maps__merge_in(&maps, map_kcore2); + ret = maps__merge_in(maps, map_kcore2); TEST_ASSERT_VAL("failed to merge map", !ret); - ret = check_maps(merged12, ARRAY_SIZE(merged12), &maps); + ret = check_maps(merged12, ARRAY_SIZE(merged12), maps); TEST_ASSERT_VAL("merge check failed", !ret); - ret = maps__merge_in(&maps, map_kcore3); + ret = maps__merge_in(maps, map_kcore3); TEST_ASSERT_VAL("failed to merge map", !ret); - ret = check_maps(merged3, ARRAY_SIZE(merged3), &maps); + ret = check_maps(merged3, ARRAY_SIZE(merged3), maps); TEST_ASSERT_VAL("merge check failed", !ret); - maps__exit(&maps); + maps__delete(maps); return TEST_OK; } diff --git a/tools/perf/tests/pmu-events.c b/tools/perf/tests/pmu-events.c index 1c695fb5a79c..299a215eb54c 100644 --- a/tools/perf/tests/pmu-events.c +++ b/tools/perf/tests/pmu-events.c @@ -994,8 +994,18 @@ static int test__parsing(struct test_suite *test __maybe_unused, } if (expr__parse(&result, ctx, pe->metric_expr)) { - expr_failure("Parse failed", map, pe); - ret++; + /* + * Parsing failed, make numbers go from large to + * small which can resolve divide by zero + * issues. + */ + k = 1024; + hashmap__for_each_entry(ctx->ids, cur, bkt) + expr__add_id_val(ctx, strdup(cur->key), k--); + if (expr__parse(&result, ctx, pe->metric_expr)) { + expr_failure("Parse failed", map, pe); + ret++; + } } } } @@ -1054,10 +1064,20 @@ static int metric_parse_fake(const char *str) } } - if (expr__parse(&result, ctx, str)) - pr_err("expr__parse failed\n"); - else - ret = 0; + ret = 0; + if (expr__parse(&result, ctx, str)) { + /* + * Parsing failed, make numbers go from large to small which can + * resolve divide by zero issues. + */ + i = 1024; + hashmap__for_each_entry(ctx->ids, cur, bkt) + expr__add_id_val(ctx, strdup(cur->key), i--); + if (expr__parse(&result, ctx, str)) { + pr_err("expr__parse failed\n"); + ret = -1; + } + } out: expr__ctx_free(ctx); diff --git a/tools/perf/tests/shell/stat_all_metrics.sh b/tools/perf/tests/shell/stat_all_metrics.sh index 7f4ba3cad632..e7c59e5a7a98 100755 --- a/tools/perf/tests/shell/stat_all_metrics.sh +++ b/tools/perf/tests/shell/stat_all_metrics.sh @@ -4,6 +4,7 @@ set -e +err=0 for m in $(perf list --raw-dump metrics); do echo "Testing $m" result=$(perf stat -M "$m" true 2>&1) @@ -14,9 +15,14 @@ for m in $(perf list --raw-dump metrics); do if [[ ! "$result" =~ "$m" ]]; then echo "Metric '$m' not printed in:" echo "$result" - exit 1 + if [[ "$result" =~ "FP_ARITH" && "$err" != "1" ]]; then + echo "Skip, not fail, for FP issues" + err=2 + else + err=1 + fi fi fi done -exit 0 +exit "$err" diff --git a/tools/perf/tests/shell/test_arm_callgraph_fp.sh b/tools/perf/tests/shell/test_arm_callgraph_fp.sh new file mode 100755 index 000000000000..6ffbb27afaba --- /dev/null +++ b/tools/perf/tests/shell/test_arm_callgraph_fp.sh @@ -0,0 +1,68 @@ +#!/bin/sh +# Check Arm64 callgraphs are complete in fp mode +# SPDX-License-Identifier: GPL-2.0 + +lscpu | grep -q "aarch64" || exit 2 + +if ! [ -x "$(command -v cc)" ]; then + echo "failed: no compiler, install gcc" + exit 2 +fi + +PERF_DATA=$(mktemp /tmp/__perf_test.perf.data.XXXXX) +TEST_PROGRAM_SOURCE=$(mktemp /tmp/test_program.XXXXX.c) +TEST_PROGRAM=$(mktemp /tmp/test_program.XXXXX) + +cleanup_files() +{ + rm -f $PERF_DATA + rm -f $TEST_PROGRAM_SOURCE + rm -f $TEST_PROGRAM +} + +trap cleanup_files exit term int + +cat << EOF > $TEST_PROGRAM_SOURCE +int a = 0; +void leaf(void) { + for (;;) + a += a; +} +void parent(void) { + leaf(); +} +int main(void) { + parent(); + return 0; +} +EOF + +echo " + Compiling test program ($TEST_PROGRAM)..." + +CFLAGS="-g -O0 -fno-inline -fno-omit-frame-pointer" +cc $CFLAGS $TEST_PROGRAM_SOURCE -o $TEST_PROGRAM || exit 1 + +# Add a 1 second delay to skip samples that are not in the leaf() function +perf record -o $PERF_DATA --call-graph fp -e cycles//u -D 1000 -- $TEST_PROGRAM 2> /dev/null & +PID=$! + +echo " + Recording (PID=$PID)..." +sleep 2 +echo " + Stopping perf-record..." + +kill $PID +wait $PID + +# expected perf-script output: +# +# program +# 728 leaf +# 753 parent +# 76c main +# ... + +perf script -i $PERF_DATA -F comm,ip,sym | head -n4 +perf script -i $PERF_DATA -F comm,ip,sym | head -n4 | \ + awk '{ if ($2 != "") sym[i++] = $2 } END { if (sym[0] != "leaf" || + sym[1] != "parent" || + sym[2] != "main") exit 1 }' diff --git a/tools/perf/tests/vmlinux-kallsyms.c b/tools/perf/tests/vmlinux-kallsyms.c index e80df13c0420..93dee542a177 100644 --- a/tools/perf/tests/vmlinux-kallsyms.c +++ b/tools/perf/tests/vmlinux-kallsyms.c @@ -119,7 +119,7 @@ static int test__vmlinux_matches_kallsyms(struct test_suite *test __maybe_unused struct symbol *sym; struct map *kallsyms_map, *vmlinux_map, *map; struct machine kallsyms, vmlinux; - struct maps *maps = machine__kernel_maps(&vmlinux); + struct maps *maps; u64 mem_start, mem_end; bool header_printed; @@ -132,6 +132,8 @@ static int test__vmlinux_matches_kallsyms(struct test_suite *test __maybe_unused machine__init(&kallsyms, "", HOST_KERNEL_ID); machine__init(&vmlinux, "", HOST_KERNEL_ID); + maps = machine__kernel_maps(&vmlinux); + /* * Step 2: * @@ -293,7 +295,7 @@ next_pair: * so use the short name, less descriptive but the same ("[kernel]" in * both cases. */ - pair = maps__find_by_name(&kallsyms.kmaps, (map->dso->kernel ? + pair = maps__find_by_name(kallsyms.kmaps, (map->dso->kernel ? map->dso->short_name : map->dso->name)); if (pair) { @@ -315,7 +317,7 @@ next_pair: mem_start = vmlinux_map->unmap_ip(vmlinux_map, map->start); mem_end = vmlinux_map->unmap_ip(vmlinux_map, map->end); - pair = maps__find(&kallsyms.kmaps, mem_start); + pair = maps__find(kallsyms.kmaps, mem_start); if (pair == NULL || pair->priv) continue; diff --git a/tools/perf/util/Build b/tools/perf/util/Build index 2a403cefcaf2..9a7209a99e16 100644 --- a/tools/perf/util/Build +++ b/tools/perf/util/Build @@ -56,6 +56,7 @@ perf-y += debug.o perf-y += fncache.o perf-y += machine.o perf-y += map.o +perf-y += maps.o perf-y += pstack.o perf-y += session.o perf-y += sample-raw.o diff --git a/tools/perf/util/PERF-VERSION-GEN b/tools/perf/util/PERF-VERSION-GEN index 59241ff342be..0ee5af529238 100755 --- a/tools/perf/util/PERF-VERSION-GEN +++ b/tools/perf/util/PERF-VERSION-GEN @@ -11,23 +11,18 @@ LF=' ' # -# First check if there is a .git to get the version from git describe -# otherwise try to get the version from the kernel Makefile +# Always try first to get the version from the kernel Makefile # CID= TAG= if test -d ../../.git -o -f ../../.git then - TAG=$(git describe --abbrev=0 --match "v[0-9].[0-9]*" 2>/dev/null ) + TAG=$(MAKEFLAGS= make -sC ../.. kernelversion) CID=$(git log -1 --abbrev=12 --pretty=format:"%h" 2>/dev/null) && CID="-g$CID" -elif test -f ../../PERF-VERSION-FILE -then +else TAG=$(cut -d' ' -f3 ../../PERF-VERSION-FILE | sed -e 's/\"//g') fi -if test -z "$TAG" -then - TAG=$(MAKEFLAGS= make -sC ../.. kernelversion) -fi + VN="$TAG$CID" if test -n "$CID" then diff --git a/tools/perf/util/annotate.c b/tools/perf/util/annotate.c index 8190a124b99d..e4c641b240df 100644 --- a/tools/perf/util/annotate.c +++ b/tools/perf/util/annotate.c @@ -33,6 +33,7 @@ #include "string2.h" #include "util/event.h" #include "arch/common.h" +#include "namespaces.h" #include #include #include @@ -1696,6 +1697,15 @@ fallback: * DSO is the same as when 'perf record' ran. */ __symbol__join_symfs(filename, filename_size, dso->long_name); + + if (access(filename, R_OK) && errno == ENOENT && dso->nsinfo) { + char *new_name = filename_with_chroot(dso->nsinfo->pid, + filename); + if (new_name) { + strlcpy(filename, new_name, filename_size); + free(new_name); + } + } } free(build_id_path); diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c index 825336304a37..9e48652662d4 100644 --- a/tools/perf/util/auxtrace.c +++ b/tools/perf/util/auxtrace.c @@ -1333,6 +1333,7 @@ void itrace_synth_opts__set_default(struct itrace_synth_opts *synth_opts, synth_opts->ptwrites = true; synth_opts->pwr_events = true; synth_opts->other_events = true; + synth_opts->intr_events = true; synth_opts->errors = true; synth_opts->flc = true; synth_opts->llc = true; @@ -1479,6 +1480,9 @@ int itrace_do_parse_synth_opts(struct itrace_synth_opts *synth_opts, case 'o': synth_opts->other_events = true; break; + case 'I': + synth_opts->intr_events = true; + break; case 'e': synth_opts->errors = true; if (get_flags(&p, &synth_opts->error_plus_flags, diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h index 19910b9011f3..dc38b6f57232 100644 --- a/tools/perf/util/auxtrace.h +++ b/tools/perf/util/auxtrace.h @@ -76,6 +76,7 @@ enum itrace_period_type { * @pwr_events: whether to synthesize power events * @other_events: whether to synthesize other events recorded due to the use of * aux_output + * @intr_events: whether to synthesize interrupt events * @errors: whether to synthesize decoder error events * @dont_decode: whether to skip decoding entirely * @log: write a decoding log @@ -120,6 +121,7 @@ struct itrace_synth_opts { bool ptwrites; bool pwr_events; bool other_events; + bool intr_events; bool errors; bool dont_decode; bool log; @@ -636,6 +638,8 @@ bool auxtrace__evsel_is_auxtrace(struct perf_session *session, " p: synthesize power events\n" \ " o: synthesize other events recorded due to the use\n" \ " of aux-output (refer to perf record)\n" \ +" I: synthesize interrupt or similar (asynchronous) events\n" \ +" (e.g. Intel PT Event Trace)\n" \ " e[flags]: synthesize error events\n" \ " each flag must be preceded by + or -\n" \ " error flags are: o (overflow)\n" \ diff --git a/tools/perf/util/bpf-event.c b/tools/perf/util/bpf-event.c index a517eaa51eb3..94624733af7e 100644 --- a/tools/perf/util/bpf-event.c +++ b/tools/perf/util/bpf-event.c @@ -33,6 +33,19 @@ struct btf * __weak btf__load_from_kernel_by_id(__u32 id) return err ? ERR_PTR(err) : btf; } +int __weak bpf_prog_load(enum bpf_prog_type prog_type, + const char *prog_name __maybe_unused, + const char *license, + const struct bpf_insn *insns, size_t insn_cnt, + const struct bpf_prog_load_opts *opts) +{ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wdeprecated-declarations" + return bpf_load_program(prog_type, insns, insn_cnt, license, + opts->kern_version, opts->log_buf, opts->log_size); +#pragma GCC diagnostic pop +} + struct bpf_program * __weak bpf_object__next_program(const struct bpf_object *obj, struct bpf_program *prev) { @@ -92,7 +105,7 @@ static int machine__process_bpf_event_load(struct machine *machine, for (i = 0; i < info_linear->info.nr_jited_ksyms; i++) { u64 *addrs = (u64 *)(uintptr_t)(info_linear->info.jited_ksyms); u64 addr = addrs[i]; - struct map *map = maps__find(&machine->kmaps, addr); + struct map *map = maps__find(machine__kernel_maps(machine), addr); if (map) { map->dso->binary_type = DSO_BINARY_TYPE__BPF_PROG_INFO; diff --git a/tools/perf/util/bpf-loader.c b/tools/perf/util/bpf-loader.c index ec6d9e7b446d..b72cef1ae959 100644 --- a/tools/perf/util/bpf-loader.c +++ b/tools/perf/util/bpf-loader.c @@ -26,6 +26,8 @@ #include "util.h" #include "llvm-utils.h" #include "c++/clang-c.h" +#include "hashmap.h" +#include "asm/bug.h" #include @@ -49,8 +51,54 @@ struct bpf_prog_priv { int *type_mapping; }; +struct bpf_perf_object { + struct list_head list; + struct bpf_object *obj; +}; + +static LIST_HEAD(bpf_objects_list); +static struct hashmap *bpf_program_hash; +static struct hashmap *bpf_map_hash; + +static struct bpf_perf_object * +bpf_perf_object__next(struct bpf_perf_object *prev) +{ + struct bpf_perf_object *next; + + if (!prev) + next = list_first_entry(&bpf_objects_list, + struct bpf_perf_object, + list); + else + next = list_next_entry(prev, list); + + /* Empty list is noticed here so don't need checking on entry. */ + if (&next->list == &bpf_objects_list) + return NULL; + + return next; +} + +#define bpf_perf_object__for_each(perf_obj, tmp) \ + for ((perf_obj) = bpf_perf_object__next(NULL), \ + (tmp) = bpf_perf_object__next(perf_obj); \ + (perf_obj) != NULL; \ + (perf_obj) = (tmp), (tmp) = bpf_perf_object__next(tmp)) + static bool libbpf_initialized; +static int bpf_perf_object__add(struct bpf_object *obj) +{ + struct bpf_perf_object *perf_obj = zalloc(sizeof(*perf_obj)); + + if (perf_obj) { + INIT_LIST_HEAD(&perf_obj->list); + perf_obj->obj = obj; + list_add_tail(&perf_obj->list, &bpf_objects_list); + } + return perf_obj ? 0 : -ENOMEM; +} + struct bpf_object * bpf__prepare_load_buffer(void *obj_buf, size_t obj_buf_sz, const char *name) { @@ -68,9 +116,21 @@ bpf__prepare_load_buffer(void *obj_buf, size_t obj_buf_sz, const char *name) return ERR_PTR(-EINVAL); } + if (bpf_perf_object__add(obj)) { + bpf_object__close(obj); + return ERR_PTR(-ENOMEM); + } + return obj; } +static void bpf_perf_object__close(struct bpf_perf_object *perf_obj) +{ + list_del(&perf_obj->list); + bpf_object__close(perf_obj->obj); + free(perf_obj); +} + struct bpf_object *bpf__prepare_load(const char *filename, bool source) { LIBBPF_OPTS(bpf_object_open_opts, opts, .object_name = filename); @@ -102,29 +162,25 @@ struct bpf_object *bpf__prepare_load(const char *filename, bool source) llvm__dump_obj(filename, obj_buf, obj_buf_sz); free(obj_buf); - } else + } else { obj = bpf_object__open(filename); + } if (IS_ERR_OR_NULL(obj)) { pr_debug("bpf: failed to load %s\n", filename); return obj; } + if (bpf_perf_object__add(obj)) { + bpf_object__close(obj); + return ERR_PTR(-BPF_LOADER_ERRNO__COMPILE); + } + return obj; } -void bpf__clear(void) -{ - struct bpf_object *obj, *tmp; - - bpf_object__for_each_safe(obj, tmp) { - bpf__unprobe(obj); - bpf_object__close(obj); - } -} - static void -clear_prog_priv(struct bpf_program *prog __maybe_unused, +clear_prog_priv(const struct bpf_program *prog __maybe_unused, void *_priv) { struct bpf_prog_priv *priv = _priv; @@ -137,6 +193,83 @@ clear_prog_priv(struct bpf_program *prog __maybe_unused, free(priv); } +static void bpf_program_hash_free(void) +{ + struct hashmap_entry *cur; + size_t bkt; + + if (IS_ERR_OR_NULL(bpf_program_hash)) + return; + + hashmap__for_each_entry(bpf_program_hash, cur, bkt) + clear_prog_priv(cur->key, cur->value); + + hashmap__free(bpf_program_hash); + bpf_program_hash = NULL; +} + +static void bpf_map_hash_free(void); + +void bpf__clear(void) +{ + struct bpf_perf_object *perf_obj, *tmp; + + bpf_perf_object__for_each(perf_obj, tmp) { + bpf__unprobe(perf_obj->obj); + bpf_perf_object__close(perf_obj); + } + + bpf_program_hash_free(); + bpf_map_hash_free(); +} + +static size_t ptr_hash(const void *__key, void *ctx __maybe_unused) +{ + return (size_t) __key; +} + +static bool ptr_equal(const void *key1, const void *key2, + void *ctx __maybe_unused) +{ + return key1 == key2; +} + +static void *program_priv(const struct bpf_program *prog) +{ + void *priv; + + if (IS_ERR_OR_NULL(bpf_program_hash)) + return NULL; + if (!hashmap__find(bpf_program_hash, prog, &priv)) + return NULL; + return priv; +} + +static int program_set_priv(struct bpf_program *prog, void *priv) +{ + void *old_priv; + + /* + * Should not happen, we warn about it in the + * caller function - config_bpf_program + */ + if (IS_ERR(bpf_program_hash)) + return PTR_ERR(bpf_program_hash); + + if (!bpf_program_hash) { + bpf_program_hash = hashmap__new(ptr_hash, ptr_equal, NULL); + if (IS_ERR(bpf_program_hash)) + return PTR_ERR(bpf_program_hash); + } + + old_priv = program_priv(prog); + if (old_priv) { + clear_prog_priv(prog, old_priv); + return hashmap__set(bpf_program_hash, prog, priv, NULL, NULL); + } + return hashmap__add(bpf_program_hash, prog, priv); +} + static int prog_config__exec(const char *value, struct perf_probe_event *pev) { @@ -378,7 +511,7 @@ config_bpf_program(struct bpf_program *prog) pr_debug("bpf: config '%s' is ok\n", config_str); set_priv: - err = bpf_program__set_priv(prog, priv, clear_prog_priv); + err = program_set_priv(prog, priv); if (err) { pr_debug("Failed to set priv for program '%s'\n", config_str); goto errout; @@ -419,7 +552,7 @@ preproc_gen_prologue(struct bpf_program *prog, int n, struct bpf_insn *orig_insns, int orig_insns_cnt, struct bpf_prog_prep_result *res) { - struct bpf_prog_priv *priv = bpf_program__priv(prog); + struct bpf_prog_priv *priv = program_priv(prog); struct probe_trace_event *tev; struct perf_probe_event *pev; struct bpf_insn *buf; @@ -570,7 +703,7 @@ static int map_prologue(struct perf_probe_event *pev, int *mapping, static int hook_load_preprocessor(struct bpf_program *prog) { - struct bpf_prog_priv *priv = bpf_program__priv(prog); + struct bpf_prog_priv *priv = program_priv(prog); struct perf_probe_event *pev; bool need_prologue = false; int err, i; @@ -646,7 +779,7 @@ int bpf__probe(struct bpf_object *obj) if (err) goto out; - priv = bpf_program__priv(prog); + priv = program_priv(prog); if (IS_ERR_OR_NULL(priv)) { if (!priv) err = -BPF_LOADER_ERRNO__INTERNAL; @@ -698,7 +831,7 @@ int bpf__unprobe(struct bpf_object *obj) struct bpf_program *prog; bpf_object__for_each_program(prog, obj) { - struct bpf_prog_priv *priv = bpf_program__priv(prog); + struct bpf_prog_priv *priv = program_priv(prog); int i; if (IS_ERR_OR_NULL(priv) || priv->is_tp) @@ -754,7 +887,7 @@ int bpf__foreach_event(struct bpf_object *obj, int err; bpf_object__for_each_program(prog, obj) { - struct bpf_prog_priv *priv = bpf_program__priv(prog); + struct bpf_prog_priv *priv = program_priv(prog); struct probe_trace_event *tev; struct perf_probe_event *pev; int i, fd; @@ -850,7 +983,7 @@ bpf_map_priv__purge(struct bpf_map_priv *priv) } static void -bpf_map_priv__clear(struct bpf_map *map __maybe_unused, +bpf_map_priv__clear(const struct bpf_map *map __maybe_unused, void *_priv) { struct bpf_map_priv *priv = _priv; @@ -859,6 +992,53 @@ bpf_map_priv__clear(struct bpf_map *map __maybe_unused, free(priv); } +static void *map_priv(const struct bpf_map *map) +{ + void *priv; + + if (IS_ERR_OR_NULL(bpf_map_hash)) + return NULL; + if (!hashmap__find(bpf_map_hash, map, &priv)) + return NULL; + return priv; +} + +static void bpf_map_hash_free(void) +{ + struct hashmap_entry *cur; + size_t bkt; + + if (IS_ERR_OR_NULL(bpf_map_hash)) + return; + + hashmap__for_each_entry(bpf_map_hash, cur, bkt) + bpf_map_priv__clear(cur->key, cur->value); + + hashmap__free(bpf_map_hash); + bpf_map_hash = NULL; +} + +static int map_set_priv(struct bpf_map *map, void *priv) +{ + void *old_priv; + + if (WARN_ON_ONCE(IS_ERR(bpf_map_hash))) + return PTR_ERR(bpf_program_hash); + + if (!bpf_map_hash) { + bpf_map_hash = hashmap__new(ptr_hash, ptr_equal, NULL); + if (IS_ERR(bpf_map_hash)) + return PTR_ERR(bpf_map_hash); + } + + old_priv = map_priv(map); + if (old_priv) { + bpf_map_priv__clear(map, old_priv); + return hashmap__set(bpf_map_hash, map, priv, NULL, NULL); + } + return hashmap__add(bpf_map_hash, map, priv); +} + static int bpf_map_op_setkey(struct bpf_map_op *op, struct parse_events_term *term) { @@ -958,7 +1138,7 @@ static int bpf_map__add_op(struct bpf_map *map, struct bpf_map_op *op) { const char *map_name = bpf_map__name(map); - struct bpf_map_priv *priv = bpf_map__priv(map); + struct bpf_map_priv *priv = map_priv(map); if (IS_ERR(priv)) { pr_debug("Failed to get private from map %s\n", map_name); @@ -973,7 +1153,7 @@ bpf_map__add_op(struct bpf_map *map, struct bpf_map_op *op) } INIT_LIST_HEAD(&priv->ops_list); - if (bpf_map__set_priv(map, priv, bpf_map_priv__clear)) { + if (map_set_priv(map, priv)) { free(priv); return -BPF_LOADER_ERRNO__INTERNAL; } @@ -1305,7 +1485,7 @@ bpf_map_config_foreach_key(struct bpf_map *map, int err, map_fd, type; struct bpf_map_op *op; const char *name = bpf_map__name(map); - struct bpf_map_priv *priv = bpf_map__priv(map); + struct bpf_map_priv *priv = map_priv(map); if (IS_ERR(priv)) { pr_debug("ERROR: failed to get private from map %s\n", name); @@ -1494,11 +1674,11 @@ apply_obj_config_object(struct bpf_object *obj) int bpf__apply_obj_config(void) { - struct bpf_object *obj, *tmp; + struct bpf_perf_object *perf_obj, *tmp; int err; - bpf_object__for_each_safe(obj, tmp) { - err = apply_obj_config_object(obj); + bpf_perf_object__for_each(perf_obj, tmp) { + err = apply_obj_config_object(perf_obj->obj); if (err) return err; } @@ -1506,27 +1686,25 @@ int bpf__apply_obj_config(void) return 0; } -#define bpf__for_each_map(pos, obj, objtmp) \ - bpf_object__for_each_safe(obj, objtmp) \ - bpf_object__for_each_map(pos, obj) +#define bpf__perf_for_each_map(map, pobj, tmp) \ + bpf_perf_object__for_each(pobj, tmp) \ + bpf_object__for_each_map(map, pobj->obj) -#define bpf__for_each_map_named(pos, obj, objtmp, name) \ - bpf__for_each_map(pos, obj, objtmp) \ - if (bpf_map__name(pos) && \ - (strcmp(name, \ - bpf_map__name(pos)) == 0)) +#define bpf__perf_for_each_map_named(map, pobj, pobjtmp, name) \ + bpf__perf_for_each_map(map, pobj, pobjtmp) \ + if (bpf_map__name(map) && (strcmp(name, bpf_map__name(map)) == 0)) struct evsel *bpf__setup_output_event(struct evlist *evlist, const char *name) { struct bpf_map_priv *tmpl_priv = NULL; - struct bpf_object *obj, *tmp; + struct bpf_perf_object *perf_obj, *tmp; struct evsel *evsel = NULL; struct bpf_map *map; int err; bool need_init = false; - bpf__for_each_map_named(map, obj, tmp, name) { - struct bpf_map_priv *priv = bpf_map__priv(map); + bpf__perf_for_each_map_named(map, perf_obj, tmp, name) { + struct bpf_map_priv *priv = map_priv(map); if (IS_ERR(priv)) return ERR_PTR(-BPF_LOADER_ERRNO__INTERNAL); @@ -1561,8 +1739,8 @@ struct evsel *bpf__setup_output_event(struct evlist *evlist, const char *name) evsel = evlist__last(evlist); } - bpf__for_each_map_named(map, obj, tmp, name) { - struct bpf_map_priv *priv = bpf_map__priv(map); + bpf__perf_for_each_map_named(map, perf_obj, tmp, name) { + struct bpf_map_priv *priv = map_priv(map); if (IS_ERR(priv)) return ERR_PTR(-BPF_LOADER_ERRNO__INTERNAL); @@ -1574,7 +1752,7 @@ struct evsel *bpf__setup_output_event(struct evlist *evlist, const char *name) if (!priv) return ERR_PTR(-ENOMEM); - err = bpf_map__set_priv(map, priv, bpf_map_priv__clear); + err = map_set_priv(map, priv); if (err) { bpf_map_priv__clear(map, priv); return ERR_PTR(err); diff --git a/tools/perf/util/bpf_ftrace.c b/tools/perf/util/bpf_ftrace.c index d756cc66eef3..4f4d3aaff37c 100644 --- a/tools/perf/util/bpf_ftrace.c +++ b/tools/perf/util/bpf_ftrace.c @@ -81,6 +81,8 @@ int perf_ftrace__latency_prepare_bpf(struct perf_ftrace *ftrace) } } + skel->bss->use_nsec = ftrace->use_nsec; + skel->links.func_begin = bpf_program__attach_kprobe(skel->progs.func_begin, false, func->name); if (IS_ERR(skel->links.func_begin)) { diff --git a/tools/perf/util/bpf_skel/func_latency.bpf.c b/tools/perf/util/bpf_skel/func_latency.bpf.c index ea94187fe443..9d01e3af7479 100644 --- a/tools/perf/util/bpf_skel/func_latency.bpf.c +++ b/tools/perf/util/bpf_skel/func_latency.bpf.c @@ -39,6 +39,7 @@ struct { int enabled = 0; int has_cpu = 0; int has_task = 0; +int use_nsec = 0; SEC("kprobe/func") int BPF_PROG(func_begin) @@ -80,6 +81,7 @@ int BPF_PROG(func_end) { __u64 tid; __u64 *start; + __u64 cmp_base = use_nsec ? 1 : 1000; if (!enabled) return 0; @@ -97,9 +99,9 @@ int BPF_PROG(func_end) if (delta < 0) return 0; - // calculate index using delta in usec + // calculate index using delta for (key = 0; key < (NUM_BUCKET - 1); key++) { - if (delta < ((1000UL) << key)) + if (delta < (cmp_base << key)) break; } diff --git a/tools/perf/util/build-id.c b/tools/perf/util/build-id.c index e32e8f2ff3bd..82f3d46bea70 100644 --- a/tools/perf/util/build-id.c +++ b/tools/perf/util/build-id.c @@ -706,7 +706,7 @@ build_id_cache__add(const char *sbuild_id, const char *name, const char *realnam if (is_kallsyms) { if (copyfile("/proc/kallsyms", filename)) goto out_free; - } else if (nsi && nsi->need_setns) { + } else if (nsi && nsinfo__need_setns(nsi)) { if (copyfile_ns(name, filename, nsi)) goto out_free; } else if (link(realname, filename) && errno != EEXIST && @@ -730,7 +730,7 @@ build_id_cache__add(const char *sbuild_id, const char *name, const char *realnam goto out_free; } if (access(filename, F_OK)) { - if (nsi && nsi->need_setns) { + if (nsi && nsinfo__need_setns(nsi)) { if (copyfile_ns(debugfile, filename, nsi)) goto out_free; @@ -762,7 +762,7 @@ build_id_cache__add(const char *sbuild_id, const char *name, const char *realnam len = readlink(linkname, path, sizeof(path) - 1); if (len <= 0) { - pr_err("Cant read link: %s\n", linkname); + pr_err("Can't read link: %s\n", linkname); goto out_free; } path[len] = '\0'; diff --git a/tools/perf/util/callchain.c b/tools/perf/util/callchain.c index 131207b91d15..5c27a4b2e7a7 100644 --- a/tools/perf/util/callchain.c +++ b/tools/perf/util/callchain.c @@ -1119,7 +1119,7 @@ int fill_callchain_info(struct addr_location *al, struct callchain_cursor_node * goto out; } - if (al->maps == &al->maps->machine->kmaps) { + if (al->maps == machine__kernel_maps(al->maps->machine)) { if (machine__is_host(al->maps->machine)) { al->cpumode = PERF_RECORD_MISC_KERNEL; al->level = 'k'; diff --git a/tools/perf/util/data.c b/tools/perf/util/data.c index 15a4547d608e..a5ace2bbc28d 100644 --- a/tools/perf/util/data.c +++ b/tools/perf/util/data.c @@ -48,12 +48,16 @@ int perf_data__create_dir(struct perf_data *data, int nr) struct perf_data_file *file = &files[i]; ret = asprintf(&file->path, "%s/data.%d", data->path, i); - if (ret < 0) + if (ret < 0) { + ret = -ENOMEM; goto out_err; + } ret = open(file->path, O_RDWR|O_CREAT|O_TRUNC, S_IRUSR|S_IWUSR); - if (ret < 0) + if (ret < 0) { + ret = -errno; goto out_err; + } file->fd = ret; } diff --git a/tools/perf/util/dso.c b/tools/perf/util/dso.c index 9cc8a1772b4b..5ac13958d1bd 100644 --- a/tools/perf/util/dso.c +++ b/tools/perf/util/dso.c @@ -508,8 +508,19 @@ static int __open_dso(struct dso *dso, struct machine *machine) root_dir, name, PATH_MAX)) goto out; - if (!is_regular_file(name)) - goto out; + if (!is_regular_file(name)) { + char *new_name; + + if (errno != ENOENT || dso->nsinfo == NULL) + goto out; + + new_name = filename_with_chroot(dso->nsinfo->pid, name); + if (!new_name) + goto out; + + free(name); + name = new_name; + } if (dso__needs_decompress(dso)) { char newpath[KMOD_DECOMP_LEN]; diff --git a/tools/perf/util/dso.h b/tools/perf/util/dso.h index 011da3924fc1..3a9fd4d389b5 100644 --- a/tools/perf/util/dso.h +++ b/tools/perf/util/dso.h @@ -167,6 +167,7 @@ struct dso { enum dso_load_errno load_errno; u8 adjust_symbols:1; u8 has_build_id:1; + u8 header_build_id:1; u8 has_srcline:1; u8 hit:1; u8 annotate_warned:1; diff --git a/tools/perf/util/dsos.c b/tools/perf/util/dsos.c index 183a81d5b2f9..b97366f77bbf 100644 --- a/tools/perf/util/dsos.c +++ b/tools/perf/util/dsos.c @@ -2,12 +2,15 @@ #include "debug.h" #include "dsos.h" #include "dso.h" +#include "util.h" #include "vdso.h" #include "namespaces.h" +#include #include #include #include #include // filename__read_build_id +#include static int __dso_id__cmp(struct dso_id *a, struct dso_id *b) { @@ -76,6 +79,16 @@ bool __dsos__read_build_ids(struct list_head *head, bool with_hits) if (filename__read_build_id(pos->long_name, &pos->bid) > 0) { have_build_id = true; pos->has_build_id = true; + } else if (errno == ENOENT && pos->nsinfo) { + char *new_name = filename_with_chroot(pos->nsinfo->pid, + pos->long_name); + + if (new_name && filename__read_build_id(new_name, + &pos->bid) > 0) { + have_build_id = true; + pos->has_build_id = true; + } + free(new_name); } nsinfo__mountns_exit(&nsc); } diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c index fe24801f8e9f..6439c888ae38 100644 --- a/tools/perf/util/event.c +++ b/tools/perf/util/event.c @@ -484,7 +484,7 @@ size_t perf_event__fprintf_text_poke(union perf_event *event, struct machine *ma if (machine) { struct addr_location al; - al.map = maps__find(&machine->kmaps, tp->addr); + al.map = maps__find(machine__kernel_maps(machine), tp->addr); if (al.map && map__load(al.map) >= 0) { al.addr = al.map->map_ip(al.map, tp->addr); al.sym = map__find_symbol(al.map, al.addr); @@ -587,13 +587,13 @@ struct map *thread__find_map(struct thread *thread, u8 cpumode, u64 addr, if (cpumode == PERF_RECORD_MISC_KERNEL && perf_host) { al->level = 'k'; - al->maps = maps = &machine->kmaps; + al->maps = maps = machine__kernel_maps(machine); load_map = true; } else if (cpumode == PERF_RECORD_MISC_USER && perf_host) { al->level = '.'; } else if (cpumode == PERF_RECORD_MISC_GUEST_KERNEL && perf_guest) { al->level = 'g'; - al->maps = maps = &machine->kmaps; + al->maps = maps = machine__kernel_maps(machine); load_map = true; } else if (cpumode == PERF_RECORD_MISC_GUEST_USER && perf_guest) { al->level = 'u'; diff --git a/tools/perf/util/event.h b/tools/perf/util/event.h index c59331eea1d9..cdd72e05fd28 100644 --- a/tools/perf/util/event.h +++ b/tools/perf/util/event.h @@ -101,9 +101,11 @@ enum { PERF_IP_FLAG_IN_TX = 1ULL << 10, PERF_IP_FLAG_VMENTRY = 1ULL << 11, PERF_IP_FLAG_VMEXIT = 1ULL << 12, + PERF_IP_FLAG_INTR_DISABLE = 1ULL << 13, + PERF_IP_FLAG_INTR_TOGGLE = 1ULL << 14, }; -#define PERF_IP_FLAG_CHARS "bcrosyiABExgh" +#define PERF_IP_FLAG_CHARS "bcrosyiABExghDt" #define PERF_BRANCH_MASK (\ PERF_IP_FLAG_BRANCH |\ @@ -182,6 +184,8 @@ enum perf_synth_id { PERF_SYNTH_INTEL_PWRX, PERF_SYNTH_INTEL_CBR, PERF_SYNTH_INTEL_PSB, + PERF_SYNTH_INTEL_EVT, + PERF_SYNTH_INTEL_IFLAG_CHG, }; /* @@ -280,6 +284,45 @@ struct perf_synth_intel_psb { u64 offset; }; +struct perf_synth_intel_evd { + union { + struct { + u8 evd_type; + u8 reserved[7]; + }; + u64 et; + }; + u64 payload; +}; + +/* Intel PT Event Trace */ +struct perf_synth_intel_evt { + u32 padding; + union { + struct { + u32 type : 5, + reserved : 2, + ip : 1, + vector : 8, + evd_cnt : 16; + }; + u32 cfe; + }; + struct perf_synth_intel_evd evd[0]; +}; + +struct perf_synth_intel_iflag_chg { + u32 padding; + union { + struct { + u32 iflag : 1, + via_branch : 1; + }; + u32 flags; + }; + u64 branch_ip; /* If via_branch */ +}; + /* * raw_data is always 4 bytes from an 8-byte boundary, so subtract 4 to get * 8-byte alignment. diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index 41a66a48cbdf..9bb79e049957 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -2145,6 +2145,22 @@ int evlist__ctlfd_process(struct evlist *evlist, enum evlist_ctl_cmd *cmd) return err; } +int evlist__ctlfd_update(struct evlist *evlist, struct pollfd *update) +{ + int ctlfd_pos = evlist->ctl_fd.pos; + struct pollfd *entries = evlist->core.pollfd.entries; + + if (!evlist__ctlfd_initialized(evlist)) + return 0; + + if (entries[ctlfd_pos].fd != update->fd || + entries[ctlfd_pos].events != update->events) + return -1; + + entries[ctlfd_pos].revents = update->revents; + return 0; +} + struct evsel *evlist__find_evsel(struct evlist *evlist, int idx) { struct evsel *evsel; diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h index 64cba56fbc74..a21daaa5fc1b 100644 --- a/tools/perf/util/evlist.h +++ b/tools/perf/util/evlist.h @@ -410,6 +410,7 @@ void evlist__close_control(int ctl_fd, int ctl_fd_ack, bool *ctl_fd_close); int evlist__initialize_ctlfd(struct evlist *evlist, int ctl_fd, int ctl_fd_ack); int evlist__finalize_ctlfd(struct evlist *evlist); bool evlist__ctlfd_initialized(struct evlist *evlist); +int evlist__ctlfd_update(struct evlist *evlist, struct pollfd *update); int evlist__ctlfd_process(struct evlist *evlist, enum evlist_ctl_cmd *cmd); int evlist__ctlfd_ack(struct evlist *evlist); diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 22d3267ce294..2a1729e7aee4 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -2847,9 +2847,23 @@ static bool find_process(const char *name) return ret ? false : true; } +static bool is_amd(const char *arch, const char *cpuid) +{ + return arch && !strcmp("x86", arch) && cpuid && strstarts(cpuid, "AuthenticAMD"); +} + +static bool is_amd_ibs(struct evsel *evsel) +{ + return evsel->core.attr.precise_ip + || (evsel->pmu_name && !strncmp(evsel->pmu_name, "ibs", 3)); +} + int evsel__open_strerror(struct evsel *evsel, struct target *target, int err, char *msg, size_t size) { + struct perf_env *env = evsel__env(evsel); + const char *arch = perf_env__arch(env); + const char *cpuid = perf_env__cpuid(env); char sbuf[STRERR_BUFSIZE]; int printed = 0, enforced = 0; @@ -2909,6 +2923,10 @@ int evsel__open_strerror(struct evsel *evsel, struct target *target, "No such device - did you specify an out-of-range profile CPU?"); break; case EOPNOTSUPP: + if (evsel->core.attr.sample_type & PERF_SAMPLE_BRANCH_STACK) + return scnprintf(msg, size, + "%s: PMU Hardware or event type doesn't support branch stack sampling.", + evsel__name(evsel)); if (evsel->core.attr.aux_output) return scnprintf(msg, size, "%s: PMU Hardware doesn't support 'aux_output' feature", @@ -2949,6 +2967,17 @@ int evsel__open_strerror(struct evsel *evsel, struct target *target, return scnprintf(msg, size, "Invalid event (%s) in per-thread mode, enable system wide with '-a'.", evsel__name(evsel)); + if (is_amd(arch, cpuid)) { + if (is_amd_ibs(evsel)) { + if (evsel->core.attr.exclude_kernel) + return scnprintf(msg, size, + "AMD IBS can't exclude kernel events. Try running at a higher privilege level."); + if (!evsel->core.system_wide) + return scnprintf(msg, size, + "AMD IBS may only be available in system-wide/per-cpu mode. Try using -a, or -C and workload affinity"); + } + } + break; case ENODATA: return scnprintf(msg, size, "Cannot collect data source with the load latency event alone. " @@ -2965,7 +2994,7 @@ int evsel__open_strerror(struct evsel *evsel, struct target *target, struct perf_env *evsel__env(struct evsel *evsel) { - if (evsel && evsel->evlist) + if (evsel && evsel->evlist && evsel->evlist->env) return evsel->evlist->env; return &perf_env; } diff --git a/tools/perf/util/ftrace.h b/tools/perf/util/ftrace.h index 887f68a185f7..a34cd15733b8 100644 --- a/tools/perf/util/ftrace.h +++ b/tools/perf/util/ftrace.h @@ -17,6 +17,7 @@ struct perf_ftrace { struct list_head nograph_funcs; unsigned long percpu_buffer_size; bool inherit; + bool use_nsec; int graph_depth; int func_stack_trace; int func_irq_info; diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c index 6da12e522edc..d546ff724dbe 100644 --- a/tools/perf/util/header.c +++ b/tools/perf/util/header.c @@ -1335,7 +1335,7 @@ static int build_mem_topology(struct memory_node *nodes, u64 size, u64 *cntp) dir = opendir(path); if (!dir) { - pr_debug2("%s: could't read %s, does this arch have topology information?\n", + pr_debug2("%s: couldn't read %s, does this arch have topology information?\n", __func__, path); return -1; } @@ -2200,6 +2200,7 @@ static int __event_process_build_id(struct perf_record_header_build_id *bev, build_id__init(&bid, bev->data, size); dso__set_build_id(dso, &bid); + dso->header_build_id = 1; if (dso_space != DSO_SPACE__USER) { struct kmod_path m = { .name = NULL, }; diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index 0a8033b09e28..1c085ab56534 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -124,6 +124,7 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) } else { symlen = unresolved_col_width + 4 + 2; hists__new_col_len(hists, HISTC_SYMBOL_FROM, symlen); + hists__new_col_len(hists, HISTC_ADDR_FROM, symlen); hists__set_unres_dso_col_len(hists, HISTC_DSO_FROM); } @@ -138,6 +139,7 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) } else { symlen = unresolved_col_width + 4 + 2; hists__new_col_len(hists, HISTC_SYMBOL_TO, symlen); + hists__new_col_len(hists, HISTC_ADDR_TO, symlen); hists__set_unres_dso_col_len(hists, HISTC_DSO_TO); } diff --git a/tools/perf/util/hist.h b/tools/perf/util/hist.h index 2a15e22fb89c..7ed4648d2fc2 100644 --- a/tools/perf/util/hist.h +++ b/tools/perf/util/hist.h @@ -77,6 +77,8 @@ enum hist_column { HISTC_GLOBAL_INS_LAT, HISTC_LOCAL_P_STAGE_CYC, HISTC_GLOBAL_P_STAGE_CYC, + HISTC_ADDR_FROM, + HISTC_ADDR_TO, HISTC_NR_COLS, /* Last entry */ }; diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c index 0e013c2d9eb4..e1d8f7504cbe 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c @@ -144,6 +144,8 @@ struct intel_pt_decoder { bool vm_tm_corr_continuous; bool nr; bool next_nr; + bool iflag; + bool next_iflag; enum intel_pt_param_flags flags; uint64_t pos; uint64_t last_ip; @@ -213,6 +215,9 @@ struct intel_pt_decoder { bool set_fup_pwre; bool set_fup_exstop; bool set_fup_bep; + bool set_fup_cfe_ip; + bool set_fup_cfe; + bool set_fup_mode_exec; bool sample_cyc; unsigned int fup_tx_flags; unsigned int tx_flags; @@ -223,6 +228,7 @@ struct intel_pt_decoder { uint64_t timestamp_insn_cnt; uint64_t sample_insn_cnt; uint64_t stuck_ip; + struct intel_pt_pkt fup_cfe_pkt; int max_loops; int no_progress; int stuck_ip_prd; @@ -231,6 +237,8 @@ struct intel_pt_decoder { const unsigned char *next_buf; size_t next_len; unsigned char temp_buf[INTEL_PT_PKT_MAX_SZ]; + int evd_cnt; + struct intel_pt_evd evd[INTEL_PT_MAX_EVDS]; }; static uint64_t intel_pt_lower_power_of_2(uint64_t x) @@ -820,6 +828,9 @@ static int intel_pt_calc_cyc_cb(struct intel_pt_pkt_info *pkt_info) case INTEL_PT_BIP: case INTEL_PT_BEP: case INTEL_PT_BEP_IP: + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: return 0; case INTEL_PT_MTC: @@ -1094,6 +1105,52 @@ static void intel_pt_sample_insn(struct intel_pt_decoder *decoder) decoder->state.type |= INTEL_PT_INSTRUCTION; } +/* + * Sample FUP instruction at the same time as reporting the FUP event, so the + * instruction sample gets the same flags as the FUP event. + */ +static void intel_pt_sample_fup_insn(struct intel_pt_decoder *decoder) +{ + struct intel_pt_insn intel_pt_insn; + uint64_t max_insn_cnt, insn_cnt = 0; + int err; + + decoder->state.insn_op = INTEL_PT_OP_OTHER; + decoder->state.insn_len = 0; + + if (!decoder->branch_enable || !decoder->pge || decoder->hop || + decoder->ip != decoder->last_ip) + return; + + if (!decoder->mtc_insn) + decoder->mtc_insn = true; + + max_insn_cnt = intel_pt_next_sample(decoder); + if (max_insn_cnt != 1) + return; + + err = decoder->walk_insn(&intel_pt_insn, &insn_cnt, &decoder->ip, + 0, max_insn_cnt, decoder->data); + /* Ignore error, it will be reported next walk anyway */ + if (err) + return; + + if (intel_pt_insn.branch != INTEL_PT_BR_NO_BRANCH) { + intel_pt_log_at("ERROR: Unexpected branch at FUP instruction", decoder->ip); + return; + } + + decoder->tot_insn_cnt += insn_cnt; + decoder->timestamp_insn_cnt += insn_cnt; + decoder->sample_insn_cnt += insn_cnt; + decoder->period_insn_cnt += insn_cnt; + + intel_pt_sample_insn(decoder); + + decoder->state.type |= INTEL_PT_INSTRUCTION; + decoder->ip += intel_pt_insn.length; +} + static int intel_pt_walk_insn(struct intel_pt_decoder *decoder, struct intel_pt_insn *intel_pt_insn, uint64_t ip) { @@ -1203,13 +1260,85 @@ out_no_progress: return err; } -static bool intel_pt_fup_event(struct intel_pt_decoder *decoder) +static void intel_pt_mode_exec_status(struct intel_pt_decoder *decoder) +{ + bool iflag = decoder->packet.count & INTEL_PT_IFLAG; + + decoder->exec_mode = decoder->packet.payload; + decoder->iflag = iflag; + decoder->next_iflag = iflag; + decoder->state.from_iflag = iflag; + decoder->state.to_iflag = iflag; +} + +static void intel_pt_mode_exec(struct intel_pt_decoder *decoder) +{ + bool iflag = decoder->packet.count & INTEL_PT_IFLAG; + + decoder->exec_mode = decoder->packet.payload; + decoder->next_iflag = iflag; +} + +static void intel_pt_sample_iflag(struct intel_pt_decoder *decoder) +{ + decoder->state.type |= INTEL_PT_IFLAG_CHG; + decoder->state.from_iflag = decoder->iflag; + decoder->state.to_iflag = decoder->next_iflag; + decoder->iflag = decoder->next_iflag; +} + +static void intel_pt_sample_iflag_chg(struct intel_pt_decoder *decoder) +{ + if (decoder->iflag != decoder->next_iflag) + intel_pt_sample_iflag(decoder); +} + +static void intel_pt_clear_fup_event(struct intel_pt_decoder *decoder) +{ + decoder->set_fup_tx_flags = false; + decoder->set_fup_ptw = false; + decoder->set_fup_mwait = false; + decoder->set_fup_pwre = false; + decoder->set_fup_exstop = false; + decoder->set_fup_bep = false; + decoder->set_fup_cfe_ip = false; + decoder->set_fup_cfe = false; + decoder->evd_cnt = 0; + decoder->set_fup_mode_exec = false; + decoder->iflag = decoder->next_iflag; +} + +static bool intel_pt_fup_event(struct intel_pt_decoder *decoder, bool no_tip) { enum intel_pt_sample_type type = decoder->state.type; + bool sample_fup_insn = false; bool ret = false; decoder->state.type &= ~INTEL_PT_BRANCH; + if (decoder->set_fup_cfe_ip || decoder->set_fup_cfe) { + bool ip = decoder->set_fup_cfe_ip; + + decoder->set_fup_cfe_ip = false; + decoder->set_fup_cfe = false; + decoder->state.type |= INTEL_PT_EVT; + if (!ip && decoder->pge) + decoder->state.type |= INTEL_PT_BRANCH; + decoder->state.cfe_type = decoder->fup_cfe_pkt.count; + decoder->state.cfe_vector = decoder->fup_cfe_pkt.payload; + decoder->state.evd_cnt = decoder->evd_cnt; + decoder->state.evd = decoder->evd; + decoder->evd_cnt = 0; + if (ip || decoder->pge) + decoder->state.flags |= INTEL_PT_FUP_IP; + ret = true; + } + if (decoder->set_fup_mode_exec) { + decoder->set_fup_mode_exec = false; + intel_pt_sample_iflag(decoder); + sample_fup_insn = no_tip; + ret = true; + } if (decoder->set_fup_tx_flags) { decoder->set_fup_tx_flags = false; decoder->tx_flags = decoder->fup_tx_flags; @@ -1266,6 +1395,8 @@ static bool intel_pt_fup_event(struct intel_pt_decoder *decoder) if (ret) { decoder->state.from_ip = decoder->ip; decoder->state.to_ip = 0; + if (sample_fup_insn) + intel_pt_sample_fup_insn(decoder); } else { decoder->state.type = type; } @@ -1298,7 +1429,7 @@ static int intel_pt_walk_fup(struct intel_pt_decoder *decoder) bool no_tip = decoder->pkt_state != INTEL_PT_STATE_FUP; decoder->pkt_state = INTEL_PT_STATE_IN_SYNC; - if (intel_pt_fup_event(decoder) && no_tip) + if (intel_pt_fup_event(decoder, no_tip) && no_tip) return 0; return -EAGAIN; } @@ -1350,6 +1481,7 @@ static int intel_pt_walk_tip(struct intel_pt_decoder *decoder) return err; intel_pt_update_nr(decoder); + intel_pt_sample_iflag_chg(decoder); if (intel_pt_insn.branch == INTEL_PT_BR_INDIRECT) { if (decoder->pkt_state == INTEL_PT_STATE_TIP_PGD) { @@ -1464,6 +1596,7 @@ static int intel_pt_walk_tnt(struct intel_pt_decoder *decoder) decoder->state.to_ip = decoder->last_ip; decoder->ip = decoder->last_ip; intel_pt_update_nr(decoder); + intel_pt_sample_iflag_chg(decoder); return 0; } @@ -1527,6 +1660,19 @@ static int intel_pt_mode_tsx(struct intel_pt_decoder *decoder, bool *no_tip) return 0; } +static int intel_pt_evd(struct intel_pt_decoder *decoder) +{ + if (decoder->evd_cnt >= INTEL_PT_MAX_EVDS) { + intel_pt_log_at("ERROR: Too many EVD packets", decoder->pos); + return -ENOSYS; + } + decoder->evd[decoder->evd_cnt++] = (struct intel_pt_evd){ + .type = decoder->packet.count, + .payload = decoder->packet.payload, + }; + return 0; +} + static uint64_t intel_pt_8b_tsc(uint64_t timestamp, uint64_t ref_timestamp) { timestamp |= (ref_timestamp & (0xffULL << 56)); @@ -1620,12 +1766,7 @@ static int intel_pt_overflow(struct intel_pt_decoder *decoder) decoder->state.from_ip = decoder->ip; decoder->ip = 0; decoder->pge = false; - decoder->set_fup_tx_flags = false; - decoder->set_fup_ptw = false; - decoder->set_fup_mwait = false; - decoder->set_fup_pwre = false; - decoder->set_fup_exstop = false; - decoder->set_fup_bep = false; + intel_pt_clear_fup_event(decoder); decoder->overflow = true; return -EOVERFLOW; } @@ -1873,6 +2014,9 @@ static int intel_pt_walk_psbend(struct intel_pt_decoder *decoder) case INTEL_PT_BIP: case INTEL_PT_BEP: case INTEL_PT_BEP_IP: + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: decoder->have_tma = false; intel_pt_log("ERROR: Unexpected packet\n"); err = -EAGAIN; @@ -1895,7 +2039,7 @@ static int intel_pt_walk_psbend(struct intel_pt_decoder *decoder) break; case INTEL_PT_MODE_EXEC: - decoder->exec_mode = decoder->packet.payload; + intel_pt_mode_exec_status(decoder); break; case INTEL_PT_PIP: @@ -1975,6 +2119,9 @@ static int intel_pt_walk_fup_tip(struct intel_pt_decoder *decoder) case INTEL_PT_BIP: case INTEL_PT_BEP: case INTEL_PT_BEP_IP: + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: intel_pt_log("ERROR: Missing TIP after FUP\n"); decoder->pkt_state = INTEL_PT_STATE_ERR3; decoder->pkt_step = 0; @@ -2026,6 +2173,7 @@ static int intel_pt_walk_fup_tip(struct intel_pt_decoder *decoder) decoder->state.to_ip = decoder->ip; } intel_pt_update_nr(decoder); + intel_pt_sample_iflag_chg(decoder); return 0; case INTEL_PT_PIP: @@ -2043,7 +2191,7 @@ static int intel_pt_walk_fup_tip(struct intel_pt_decoder *decoder) break; case INTEL_PT_MODE_EXEC: - decoder->exec_mode = decoder->packet.payload; + intel_pt_mode_exec(decoder); break; case INTEL_PT_VMCS: @@ -2134,6 +2282,9 @@ static int intel_pt_vm_psb_lookahead_cb(struct intel_pt_pkt_info *pkt_info) case INTEL_PT_TIP: case INTEL_PT_PSB: case INTEL_PT_TRACESTOP: + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: default: return 1; } @@ -2653,6 +2804,9 @@ static int intel_pt_vm_time_correlation(struct intel_pt_decoder *decoder) decoder->blk_type = 0; break; + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: case INTEL_PT_MODE_EXEC: case INTEL_PT_MODE_TSX: case INTEL_PT_MNT: @@ -2719,6 +2873,7 @@ static int intel_pt_hop_trace(struct intel_pt_decoder *decoder, bool *no_tip, in decoder->state.from_ip = decoder->ip; decoder->state.to_ip = 0; intel_pt_update_nr(decoder); + intel_pt_sample_iflag_chg(decoder); return HOP_RETURN; case INTEL_PT_FUP: @@ -2733,10 +2888,10 @@ static int intel_pt_hop_trace(struct intel_pt_decoder *decoder, bool *no_tip, in decoder->state.type = INTEL_PT_INSTRUCTION; decoder->state.from_ip = decoder->ip; decoder->state.to_ip = 0; - intel_pt_fup_event(decoder); + intel_pt_fup_event(decoder, *no_tip); return HOP_RETURN; } - intel_pt_fup_event(decoder); + intel_pt_fup_event(decoder, *no_tip); decoder->state.type |= INTEL_PT_INSTRUCTION | INTEL_PT_BRANCH; *err = intel_pt_walk_fup_tip(decoder); if (!*err && decoder->state.to_ip) @@ -2789,6 +2944,9 @@ static int intel_pt_hop_trace(struct intel_pt_decoder *decoder, bool *no_tip, in case INTEL_PT_BIP: case INTEL_PT_BEP: case INTEL_PT_BEP_IP: + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: default: return HOP_PROCESS; } @@ -2857,6 +3015,9 @@ static int intel_pt_psb_lookahead_cb(struct intel_pt_pkt_info *pkt_info) case INTEL_PT_BIP: case INTEL_PT_BEP: case INTEL_PT_BEP_IP: + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: if (data->after_psbend) { data->after_psbend -= 1; if (!data->after_psbend) @@ -2994,6 +3155,7 @@ next: decoder->pos); break; } + intel_pt_sample_iflag_chg(decoder); intel_pt_set_ip(decoder); decoder->state.from_ip = 0; decoder->state.to_ip = decoder->ip; @@ -3026,7 +3188,7 @@ next: intel_pt_set_last_ip(decoder); if (!decoder->branch_enable || !decoder->pge) { decoder->ip = decoder->last_ip; - if (intel_pt_fup_event(decoder)) + if (intel_pt_fup_event(decoder, no_tip)) return 0; no_tip = false; break; @@ -3108,8 +3270,15 @@ next: break; case INTEL_PT_MODE_EXEC: - decoder->exec_mode = decoder->packet.payload; - break; + intel_pt_mode_exec(decoder); + err = intel_pt_get_next_packet(decoder); + if (err) + return err; + if (decoder->packet.type == INTEL_PT_FUP) { + decoder->set_fup_mode_exec = true; + no_tip = true; + } + goto next; case INTEL_PT_MODE_TSX: /* MODE_TSX need not be followed by FUP */ @@ -3223,6 +3392,35 @@ next: } goto next; + case INTEL_PT_CFE: + decoder->fup_cfe_pkt = decoder->packet; + decoder->set_fup_cfe = true; + if (!decoder->pge) { + intel_pt_fup_event(decoder, true); + return 0; + } + break; + + case INTEL_PT_CFE_IP: + decoder->fup_cfe_pkt = decoder->packet; + err = intel_pt_get_next_packet(decoder); + if (err) + return err; + if (decoder->packet.type == INTEL_PT_FUP) { + decoder->set_fup_cfe_ip = true; + no_tip = true; + } else { + intel_pt_log_at("ERROR: Missing FUP after CFE", + decoder->pos); + } + goto next; + + case INTEL_PT_EVD: + err = intel_pt_evd(decoder); + if (err) + return err; + break; + default: return intel_pt_bug(decoder); } @@ -3265,6 +3463,9 @@ static int intel_pt_walk_psb(struct intel_pt_decoder *decoder) case INTEL_PT_BIP: case INTEL_PT_BEP: case INTEL_PT_BEP_IP: + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: intel_pt_log("ERROR: Unexpected packet\n"); err = -ENOENT; goto out; @@ -3307,7 +3508,7 @@ static int intel_pt_walk_psb(struct intel_pt_decoder *decoder) break; case INTEL_PT_MODE_EXEC: - decoder->exec_mode = decoder->packet.payload; + intel_pt_mode_exec_status(decoder); break; case INTEL_PT_MODE_TSX: @@ -3426,7 +3627,7 @@ static int intel_pt_walk_to_ip(struct intel_pt_decoder *decoder) break; case INTEL_PT_MODE_EXEC: - decoder->exec_mode = decoder->packet.payload; + intel_pt_mode_exec_status(decoder); break; case INTEL_PT_MODE_TSX: @@ -3476,6 +3677,9 @@ static int intel_pt_walk_to_ip(struct intel_pt_decoder *decoder) case INTEL_PT_BIP: case INTEL_PT_BEP: case INTEL_PT_BEP_IP: + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: default: break; } @@ -3486,12 +3690,7 @@ static int intel_pt_sync_ip(struct intel_pt_decoder *decoder) { int err; - decoder->set_fup_tx_flags = false; - decoder->set_fup_ptw = false; - decoder->set_fup_mwait = false; - decoder->set_fup_pwre = false; - decoder->set_fup_exstop = false; - decoder->set_fup_bep = false; + intel_pt_clear_fup_event(decoder); decoder->overflow = false; if (!decoder->branch_enable) { diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h index 8fd68f7a0963..efb2cb3ae0ca 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h +++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.h @@ -17,6 +17,7 @@ #define INTEL_PT_IN_TX (1 << 0) #define INTEL_PT_ABORT_TX (1 << 1) +#define INTEL_PT_IFLAG (1 << 2) #define INTEL_PT_ASYNC (1 << 2) #define INTEL_PT_FUP_IP (1 << 3) #define INTEL_PT_SAMPLE_IPC (1 << 4) @@ -35,6 +36,8 @@ enum intel_pt_sample_type { INTEL_PT_TRACE_END = 1 << 10, INTEL_PT_BLK_ITEMS = 1 << 11, INTEL_PT_PSB_EVT = 1 << 12, + INTEL_PT_EVT = 1 << 13, + INTEL_PT_IFLAG_CHG = 1 << 14, }; enum intel_pt_period_type { @@ -209,10 +212,24 @@ struct intel_pt_vmcs_info { bool error_printed; }; +/* + * Maximum number of event trace data in one go, assuming at most 1 per type + * and 6-bits of type in the EVD packet. + */ +#define INTEL_PT_MAX_EVDS 64 + +/* Event trace data from EVD packet */ +struct intel_pt_evd { + int type; + uint64_t payload; +}; + struct intel_pt_state { enum intel_pt_sample_type type; bool from_nr; bool to_nr; + bool from_iflag; + bool to_iflag; int err; uint64_t from_ip; uint64_t to_ip; @@ -234,6 +251,10 @@ struct intel_pt_state { int insn_len; char insn[INTEL_PT_INSN_BUF_SZ]; struct intel_pt_blk_items items; + int cfe_type; + int cfe_vector; + int evd_cnt; + struct intel_pt_evd *evd; }; struct intel_pt_insn; diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c index 4bd154848cad..18f97f43e01a 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.c @@ -64,6 +64,9 @@ static const char * const packet_name[] = { [INTEL_PT_BIP] = "BIP", [INTEL_PT_BEP] = "BEP", [INTEL_PT_BEP_IP] = "BEP", + [INTEL_PT_CFE] = "CFE", + [INTEL_PT_CFE_IP] = "CFE", + [INTEL_PT_EVD] = "EVD", }; const char *intel_pt_pkt_name(enum intel_pt_pkt_type type) @@ -197,8 +200,7 @@ static int intel_pt_get_mnt(const unsigned char *buf, size_t len, return INTEL_PT_NEED_MORE_BYTES; packet->type = INTEL_PT_MNT; memcpy_le64(&packet->payload, buf + 3, 8); - return 11 -; + return 11; } static int intel_pt_get_3byte(const unsigned char *buf, size_t len, @@ -329,6 +331,29 @@ static int intel_pt_get_bep_ip(size_t len, struct intel_pt_pkt *packet) return 2; } +static int intel_pt_get_cfe(const unsigned char *buf, size_t len, + struct intel_pt_pkt *packet) +{ + if (len < 4) + return INTEL_PT_NEED_MORE_BYTES; + packet->type = buf[2] & 0x80 ? INTEL_PT_CFE_IP : INTEL_PT_CFE; + packet->count = buf[2] & 0x1f; + packet->payload = buf[3]; + return 4; +} + +static int intel_pt_get_evd(const unsigned char *buf, size_t len, + struct intel_pt_pkt *packet) +{ + if (len < 11) + return INTEL_PT_NEED_MORE_BYTES; + packet->type = INTEL_PT_EVD; + packet->count = buf[2] & 0x3f; + packet->payload = buf[3]; + memcpy_le64(&packet->payload, buf + 3, 8); + return 11; +} + static int intel_pt_get_ext(const unsigned char *buf, size_t len, struct intel_pt_pkt *packet) { @@ -375,6 +400,10 @@ static int intel_pt_get_ext(const unsigned char *buf, size_t len, return intel_pt_get_bep(len, packet); case 0xb3: /* BEP with IP */ return intel_pt_get_bep_ip(len, packet); + case 0x13: /* CFE */ + return intel_pt_get_cfe(buf, len, packet); + case 0x53: /* EVD */ + return intel_pt_get_evd(buf, len, packet); default: return INTEL_PT_BAD_PACKET; } @@ -475,6 +504,7 @@ static int intel_pt_get_mode(const unsigned char *buf, size_t len, switch (buf[1] >> 5) { case 0: packet->type = INTEL_PT_MODE_EXEC; + packet->count = buf[1]; switch (buf[1] & 3) { case 0: packet->payload = 16; @@ -624,6 +654,9 @@ void intel_pt_upd_pkt_ctx(const struct intel_pt_pkt *packet, case INTEL_PT_MWAIT: case INTEL_PT_BEP: case INTEL_PT_BEP_IP: + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + case INTEL_PT_EVD: *ctx = INTEL_PT_NO_CTX; break; case INTEL_PT_BBP: @@ -709,7 +742,8 @@ int intel_pt_pkt_desc(const struct intel_pt_pkt *packet, char *buf, return snprintf(buf, buf_len, "%s CTC 0x%x FC 0x%x", name, (unsigned)payload, packet->count); case INTEL_PT_MODE_EXEC: - return snprintf(buf, buf_len, "%s %lld", name, payload); + return snprintf(buf, buf_len, "%s IF:%d %lld", + name, !!(packet->count & 4), payload); case INTEL_PT_MODE_TSX: return snprintf(buf, buf_len, "%s TXAbort:%u InTX:%u", name, (unsigned)(payload >> 1) & 1, @@ -751,6 +785,13 @@ int intel_pt_pkt_desc(const struct intel_pt_pkt *packet, char *buf, case INTEL_PT_BIP: return snprintf(buf, buf_len, "%s ID 0x%02x Value 0x%llx", name, packet->count, payload); + case INTEL_PT_CFE: + case INTEL_PT_CFE_IP: + return snprintf(buf, buf_len, "%s IP:%d Type 0x%02x Vector 0x%llx", + name, packet->type == INTEL_PT_CFE_IP, packet->count, payload); + case INTEL_PT_EVD: + return snprintf(buf, buf_len, "%s Type 0x%02x Payload 0x%llx", + name, packet->count, payload); default: break; } diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.h b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.h index 996090cb84f6..496ba4be875c 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.h +++ b/tools/perf/util/intel-pt-decoder/intel-pt-pkt-decoder.h @@ -56,6 +56,9 @@ enum intel_pt_pkt_type { INTEL_PT_BIP, INTEL_PT_BEP, INTEL_PT_BEP_IP, + INTEL_PT_CFE, + INTEL_PT_CFE_IP, + INTEL_PT_EVD, }; struct intel_pt_pkt { diff --git a/tools/perf/util/intel-pt.c b/tools/perf/util/intel-pt.c index e8613cbda331..ec43d364d0de 100644 --- a/tools/perf/util/intel-pt.c +++ b/tools/perf/util/intel-pt.c @@ -46,6 +46,12 @@ #define MAX_TIMESTAMP (~0ULL) +#define INTEL_PT_CFG_PASS_THRU BIT_ULL(0) +#define INTEL_PT_CFG_PWR_EVT_EN BIT_ULL(4) +#define INTEL_PT_CFG_BRANCH_EN BIT_ULL(13) +#define INTEL_PT_CFG_EVT_EN BIT_ULL(31) +#define INTEL_PT_CFG_TNT_DIS BIT_ULL(55) + struct range { u64 start; u64 end; @@ -71,6 +77,7 @@ struct intel_pt { bool mispred_all; bool use_thread_stack; bool callstack; + bool cap_event_trace; unsigned int br_stack_sz; unsigned int br_stack_sz_plus; int have_sched_switch; @@ -115,6 +122,12 @@ struct intel_pt { bool sample_pebs; struct evsel *pebs_evsel; + u64 evt_sample_type; + u64 evt_id; + + u64 iflag_chg_sample_type; + u64 iflag_chg_id; + u64 tsc_bit; u64 mtc_bit; u64 mtc_freq_bits; @@ -953,12 +966,26 @@ static bool intel_pt_branch_enable(struct intel_pt *pt) evlist__for_each_entry(pt->session->evlist, evsel) { if (intel_pt_get_config(pt, &evsel->core.attr, &config) && - (config & 1) && !(config & 0x2000)) + (config & INTEL_PT_CFG_PASS_THRU) && + !(config & INTEL_PT_CFG_BRANCH_EN)) return false; } return true; } +static bool intel_pt_disabled_tnt(struct intel_pt *pt) +{ + struct evsel *evsel; + u64 config; + + evlist__for_each_entry(pt->session->evlist, evsel) { + if (intel_pt_get_config(pt, &evsel->core.attr, &config) && + config & INTEL_PT_CFG_TNT_DIS) + return true; + } + return false; +} + static unsigned int intel_pt_mtc_period(struct intel_pt *pt) { struct evsel *evsel; @@ -1214,6 +1241,10 @@ static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt, params.first_timestamp = pt->first_timestamp; params.max_loops = pt->max_loops; + /* Cannot walk code without TNT, so force 'quick' mode */ + if (params.branch_enable && intel_pt_disabled_tnt(pt) && !params.quick) + params.quick = 1; + if (pt->filts.cnt > 0) params.pgd_ip = intel_pt_pgd_ip; @@ -1316,6 +1347,8 @@ static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt, static void intel_pt_sample_flags(struct intel_pt_queue *ptq) { + struct intel_pt *pt = ptq->pt; + ptq->insn_len = 0; if (ptq->state->flags & INTEL_PT_ABORT_TX) { ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT; @@ -1346,6 +1379,17 @@ static void intel_pt_sample_flags(struct intel_pt_queue *ptq) ptq->flags |= PERF_IP_FLAG_TRACE_BEGIN; if (ptq->state->type & INTEL_PT_TRACE_END) ptq->flags |= PERF_IP_FLAG_TRACE_END; + + if (pt->cap_event_trace) { + if (ptq->state->type & INTEL_PT_IFLAG_CHG) { + if (!ptq->state->from_iflag) + ptq->flags |= PERF_IP_FLAG_INTR_DISABLE; + if (ptq->state->from_iflag != ptq->state->to_iflag) + ptq->flags |= PERF_IP_FLAG_INTR_TOGGLE; + } else if (!ptq->state->to_iflag) { + ptq->flags |= PERF_IP_FLAG_INTR_DISABLE; + } + } } static void intel_pt_setup_time_range(struct intel_pt *pt, @@ -2160,6 +2204,78 @@ static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq) return err; } +static int intel_pt_synth_events_sample(struct intel_pt_queue *ptq) +{ + struct intel_pt *pt = ptq->pt; + union perf_event *event = ptq->event_buf; + struct perf_sample sample = { .ip = 0, }; + struct { + struct perf_synth_intel_evt cfe; + struct perf_synth_intel_evd evd[INTEL_PT_MAX_EVDS]; + } raw; + int i; + + if (intel_pt_skip_event(pt)) + return 0; + + intel_pt_prep_p_sample(pt, ptq, event, &sample); + + sample.id = ptq->pt->evt_id; + sample.stream_id = ptq->pt->evt_id; + + raw.cfe.type = ptq->state->cfe_type; + raw.cfe.reserved = 0; + raw.cfe.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); + raw.cfe.vector = ptq->state->cfe_vector; + raw.cfe.evd_cnt = ptq->state->evd_cnt; + + for (i = 0; i < ptq->state->evd_cnt; i++) { + raw.evd[i].et = 0; + raw.evd[i].evd_type = ptq->state->evd[i].type; + raw.evd[i].payload = ptq->state->evd[i].payload; + } + + sample.raw_size = perf_synth__raw_size(raw) + + ptq->state->evd_cnt * sizeof(struct perf_synth_intel_evd); + sample.raw_data = perf_synth__raw_data(&raw); + + return intel_pt_deliver_synth_event(pt, event, &sample, + pt->evt_sample_type); +} + +static int intel_pt_synth_iflag_chg_sample(struct intel_pt_queue *ptq) +{ + struct intel_pt *pt = ptq->pt; + union perf_event *event = ptq->event_buf; + struct perf_sample sample = { .ip = 0, }; + struct perf_synth_intel_iflag_chg raw; + + if (intel_pt_skip_event(pt)) + return 0; + + intel_pt_prep_p_sample(pt, ptq, event, &sample); + + sample.id = ptq->pt->iflag_chg_id; + sample.stream_id = ptq->pt->iflag_chg_id; + + raw.flags = 0; + raw.iflag = ptq->state->to_iflag; + + if (ptq->state->type & INTEL_PT_BRANCH) { + raw.via_branch = 1; + raw.branch_ip = ptq->state->to_ip; + } else { + sample.addr = 0; + } + sample.flags = ptq->flags; + + sample.raw_size = perf_synth__raw_size(raw); + sample.raw_data = perf_synth__raw_data(&raw); + + return intel_pt_deliver_synth_event(pt, event, &sample, + pt->iflag_chg_sample_type); +} + static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu, pid_t pid, pid_t tid, u64 ip, u64 timestamp) { @@ -2266,6 +2382,19 @@ static int intel_pt_sample(struct intel_pt_queue *ptq) return err; } + if (pt->synth_opts.intr_events) { + if (state->type & INTEL_PT_EVT) { + err = intel_pt_synth_events_sample(ptq); + if (err) + return err; + } + if (state->type & INTEL_PT_IFLAG_CHG) { + err = intel_pt_synth_iflag_chg_sample(ptq); + if (err) + return err; + } + } + if (pt->sample_pwr_events) { if (state->type & INTEL_PT_PSB_EVT) { err = intel_pt_synth_psb_sample(ptq); @@ -3429,7 +3558,7 @@ static int intel_pt_synth_events(struct intel_pt *pt, id += 1; } - if (pt->synth_opts.pwr_events && (evsel->core.attr.config & 0x10)) { + if (pt->synth_opts.pwr_events && (evsel->core.attr.config & INTEL_PT_CFG_PWR_EVT_EN)) { attr.config = PERF_SYNTH_INTEL_MWAIT; err = intel_pt_synth_event(session, "mwait", &attr, id); if (err) @@ -3463,6 +3592,28 @@ static int intel_pt_synth_events(struct intel_pt *pt, id += 1; } + if (pt->synth_opts.intr_events && (evsel->core.attr.config & INTEL_PT_CFG_EVT_EN)) { + attr.config = PERF_SYNTH_INTEL_EVT; + err = intel_pt_synth_event(session, "evt", &attr, id); + if (err) + return err; + pt->evt_sample_type = attr.sample_type; + pt->evt_id = id; + intel_pt_set_event_name(evlist, id, "evt"); + id += 1; + } + + if (pt->synth_opts.intr_events && pt->cap_event_trace) { + attr.config = PERF_SYNTH_INTEL_IFLAG_CHG; + err = intel_pt_synth_event(session, "iflag", &attr, id); + if (err) + return err; + pt->iflag_chg_sample_type = attr.sample_type; + pt->iflag_chg_id = id; + intel_pt_set_event_name(evlist, id, "iflag"); + id += 1; + } + return 0; } @@ -3790,7 +3941,7 @@ int intel_pt_process_auxtrace_info(union perf_event *event, } info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1; - info_end = (void *)info + auxtrace_info->header.size; + info_end = (void *)auxtrace_info + auxtrace_info->header.size; if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) { size_t len; @@ -3829,6 +3980,13 @@ int intel_pt_process_auxtrace_info(union perf_event *event, intel_pt_print_info_str("Filter string", pt->filter); } + if ((void *)info < info_end) { + pt->cap_event_trace = *info++; + if (dump_trace) + fprintf(stdout, " Cap Event Trace %d\n", + pt->cap_event_trace); + } + pt->timeless_decoding = intel_pt_timeless_decoding(pt); if (pt->timeless_decoding && !pt->tc.time_mult) pt->tc.time_mult = 1; diff --git a/tools/perf/util/jitdump.c b/tools/perf/util/jitdump.c index 917a9c707371..a23255773c60 100644 --- a/tools/perf/util/jitdump.c +++ b/tools/perf/util/jitdump.c @@ -382,15 +382,15 @@ jit_inject_event(struct jit_buf_desc *jd, union perf_event *event) static pid_t jr_entry_pid(struct jit_buf_desc *jd, union jr_entry *jr) { - if (jd->nsi && jd->nsi->in_pidns) - return jd->nsi->tgid; + if (jd->nsi && nsinfo__in_pidns(jd->nsi)) + return nsinfo__tgid(jd->nsi); return jr->load.pid; } static pid_t jr_entry_tid(struct jit_buf_desc *jd, union jr_entry *jr) { - if (jd->nsi && jd->nsi->in_pidns) - return jd->nsi->pid; + if (jd->nsi && nsinfo__in_pidns(jd->nsi)) + return nsinfo__pid(jd->nsi); return jr->load.tid; } @@ -779,7 +779,7 @@ jit_detect(char *mmap_name, pid_t pid, struct nsinfo *nsi) * pid does not match mmap pid * pid==0 in system-wide mode (synthesized) */ - if (pid && pid2 != nsi->nstgid) + if (pid && pid2 != nsinfo__nstgid(nsi)) return -1; /* * validate suffix diff --git a/tools/perf/util/machine.c b/tools/perf/util/machine.c index 394550003693..b80048546451 100644 --- a/tools/perf/util/machine.c +++ b/tools/perf/util/machine.c @@ -89,7 +89,10 @@ int machine__init(struct machine *machine, const char *root_dir, pid_t pid) int err = -ENOMEM; memset(machine, 0, sizeof(*machine)); - maps__init(&machine->kmaps, machine); + machine->kmaps = maps__new(machine); + if (machine->kmaps == NULL) + return -ENOMEM; + RB_CLEAR_NODE(&machine->rb_node); dsos__init(&machine->dsos); @@ -108,7 +111,7 @@ int machine__init(struct machine *machine, const char *root_dir, pid_t pid) machine->root_dir = strdup(root_dir); if (machine->root_dir == NULL) - return -ENOMEM; + goto out; if (machine__set_mmap_name(machine)) goto out; @@ -131,6 +134,7 @@ int machine__init(struct machine *machine, const char *root_dir, pid_t pid) out: if (err) { + zfree(&machine->kmaps); zfree(&machine->root_dir); zfree(&machine->mmap_name); } @@ -220,7 +224,7 @@ void machine__exit(struct machine *machine) return; machine__destroy_kernel_maps(machine); - maps__exit(&machine->kmaps); + maps__delete(machine->kmaps); dsos__exit(&machine->dsos); machine__exit_vdso(machine); zfree(&machine->root_dir); @@ -778,7 +782,7 @@ static int machine__process_ksymbol_register(struct machine *machine, struct perf_sample *sample __maybe_unused) { struct symbol *sym; - struct map *map = maps__find(&machine->kmaps, event->ksymbol.addr); + struct map *map = maps__find(machine__kernel_maps(machine), event->ksymbol.addr); if (!map) { struct dso *dso = dso__new(event->ksymbol.name); @@ -801,7 +805,7 @@ static int machine__process_ksymbol_register(struct machine *machine, map->start = event->ksymbol.addr; map->end = map->start + event->ksymbol.len; - maps__insert(&machine->kmaps, map); + maps__insert(machine__kernel_maps(machine), map); map__put(map); dso__set_loaded(dso); @@ -827,12 +831,12 @@ static int machine__process_ksymbol_unregister(struct machine *machine, struct symbol *sym; struct map *map; - map = maps__find(&machine->kmaps, event->ksymbol.addr); + map = maps__find(machine__kernel_maps(machine), event->ksymbol.addr); if (!map) return 0; if (map != machine->vmlinux_map) - maps__remove(&machine->kmaps, map); + maps__remove(machine__kernel_maps(machine), map); else { sym = dso__find_symbol(map->dso, map->map_ip(map, map->start)); if (sym) @@ -858,7 +862,7 @@ int machine__process_ksymbol(struct machine *machine __maybe_unused, int machine__process_text_poke(struct machine *machine, union perf_event *event, struct perf_sample *sample __maybe_unused) { - struct map *map = maps__find(&machine->kmaps, event->text_poke.addr); + struct map *map = maps__find(machine__kernel_maps(machine), event->text_poke.addr); u8 cpumode = event->header.misc & PERF_RECORD_MISC_CPUMODE_MASK; if (dump_trace) @@ -914,7 +918,7 @@ static struct map *machine__addnew_module_map(struct machine *machine, u64 start if (map == NULL) goto out; - maps__insert(&machine->kmaps, map); + maps__insert(machine__kernel_maps(machine), map); /* Put the map here because maps__insert already got it */ map__put(map); @@ -1100,7 +1104,7 @@ int machine__create_extra_kernel_map(struct machine *machine, strlcpy(kmap->name, xm->name, KMAP_NAME_LEN); - maps__insert(&machine->kmaps, map); + maps__insert(machine__kernel_maps(machine), map); pr_debug2("Added extra kernel map %s %" PRIx64 "-%" PRIx64 "\n", kmap->name, map->start, map->end); @@ -1145,7 +1149,7 @@ static u64 find_entry_trampoline(struct dso *dso) int machine__map_x86_64_entry_trampolines(struct machine *machine, struct dso *kernel) { - struct maps *kmaps = &machine->kmaps; + struct maps *kmaps = machine__kernel_maps(machine); int nr_cpus_avail, cpu; bool found = false; struct map *map; @@ -1215,7 +1219,7 @@ __machine__create_kernel_maps(struct machine *machine, struct dso *kernel) return -1; machine->vmlinux_map->map_ip = machine->vmlinux_map->unmap_ip = identity__map_ip; - maps__insert(&machine->kmaps, machine->vmlinux_map); + maps__insert(machine__kernel_maps(machine), machine->vmlinux_map); return 0; } @@ -1228,7 +1232,7 @@ void machine__destroy_kernel_maps(struct machine *machine) return; kmap = map__kmap(map); - maps__remove(&machine->kmaps, map); + maps__remove(machine__kernel_maps(machine), map); if (kmap && kmap->ref_reloc_sym) { zfree((char **)&kmap->ref_reloc_sym->name); zfree(&kmap->ref_reloc_sym); @@ -1323,7 +1327,7 @@ int machine__load_kallsyms(struct machine *machine, const char *filename) * kernel, with modules between them, fixup the end of all * sections. */ - maps__fixup_end(&machine->kmaps); + maps__fixup_end(machine__kernel_maps(machine)); } return ret; @@ -1471,7 +1475,7 @@ static int machine__set_modules_path(struct machine *machine) machine->root_dir, version); free(version); - return maps__set_modules_path_dir(&machine->kmaps, modules_path, 0); + return maps__set_modules_path_dir(machine__kernel_maps(machine), modules_path, 0); } int __weak arch__fix_module_text_start(u64 *start __maybe_unused, u64 *size __maybe_unused, @@ -1544,11 +1548,11 @@ static void machine__update_kernel_mmap(struct machine *machine, struct map *map = machine__kernel_map(machine); map__get(map); - maps__remove(&machine->kmaps, map); + maps__remove(machine__kernel_maps(machine), map); machine__set_kernel_mmap(machine, start, end); - maps__insert(&machine->kmaps, map); + maps__insert(machine__kernel_maps(machine), map); map__put(map); } diff --git a/tools/perf/util/machine.h b/tools/perf/util/machine.h index c5a45dc8df4c..0023165422aa 100644 --- a/tools/perf/util/machine.h +++ b/tools/perf/util/machine.h @@ -51,7 +51,7 @@ struct machine { struct vdso_info *vdso_info; struct perf_env *env; struct dsos dsos; - struct maps kmaps; + struct maps *kmaps; struct map *vmlinux_map; u64 kernel_start; pid_t *current_tid; @@ -83,7 +83,7 @@ struct map *machine__kernel_map(struct machine *machine) static inline struct maps *machine__kernel_maps(struct machine *machine) { - return &machine->kmaps; + return machine->kmaps; } int machine__get_kernel_start(struct machine *machine); @@ -223,7 +223,7 @@ static inline struct symbol *machine__find_kernel_symbol(struct machine *machine, u64 addr, struct map **mapp) { - return maps__find_symbol(&machine->kmaps, addr, mapp); + return maps__find_symbol(machine->kmaps, addr, mapp); } static inline @@ -231,7 +231,7 @@ struct symbol *machine__find_kernel_symbol_by_name(struct machine *machine, const char *name, struct map **mapp) { - return maps__find_symbol_by_name(&machine->kmaps, name, mapp); + return maps__find_symbol_by_name(machine->kmaps, name, mapp); } int arch__fix_module_text_start(u64 *start, u64 *size, const char *name); diff --git a/tools/perf/util/map.c b/tools/perf/util/map.c index 8af693d9678c..e0aa4a254583 100644 --- a/tools/perf/util/map.c +++ b/tools/perf/util/map.c @@ -1,31 +1,20 @@ // SPDX-License-Identifier: GPL-2.0 -#include "symbol.h" -#include -#include #include #include +#include #include #include -#include -#include -#include /* To get things like MAP_HUGETLB even on older libc headers */ -#include "dso.h" -#include "map.h" -#include "map_symbol.h" -#include "thread.h" -#include "vdso.h" -#include "build-id.h" -#include "debug.h" -#include "machine.h" #include #include -#include "srcline.h" +#include /* To get things like MAP_HUGETLB even on older libc headers */ +#include "debug.h" +#include "dso.h" +#include "map.h" #include "namespaces.h" -#include "unwind.h" -#include "srccode.h" -#include "ui/ui.h" - -static void __maps__insert(struct maps *maps, struct map *map); +#include "srcline.h" +#include "symbol.h" +#include "thread.h" +#include "vdso.h" static inline int is_android_lib(const char *filename) { @@ -138,7 +127,7 @@ struct map *map__new(struct machine *machine, u64 start, u64 len, if (map != NULL) { char newfilename[PATH_MAX]; - struct dso *dso; + struct dso *dso, *header_bid_dso; int anon, no_dso, vdso, android; android = is_android_lib(filename); @@ -151,7 +140,7 @@ struct map *map__new(struct machine *machine, u64 start, u64 len, if ((anon || no_dso) && nsi && (prot & PROT_EXEC)) { snprintf(newfilename, sizeof(newfilename), - "/tmp/perf-%d.map", nsi->pid); + "/tmp/perf-%d.map", nsinfo__pid(nsi)); filename = newfilename; } @@ -168,7 +157,7 @@ struct map *map__new(struct machine *machine, u64 start, u64 len, nnsi = nsinfo__copy(nsi); if (nnsi) { nsinfo__put(nsi); - nnsi->need_setns = false; + nsinfo__clear_need_setns(nnsi); nsi = nnsi; } pgoff = 0; @@ -194,9 +183,23 @@ struct map *map__new(struct machine *machine, u64 start, u64 len, } dso->nsinfo = nsi; - if (build_id__is_defined(bid)) + if (build_id__is_defined(bid)) { dso__set_build_id(dso, bid); - + } else { + /* + * If the mmap event had no build ID, search for an existing dso from the + * build ID header by name. Otherwise only the dso loaded at the time of + * reading the header will have the build ID set and all future mmaps will + * have it missing. + */ + down_read(&machine->dsos.lock); + header_bid_dso = __dsos__find(&machine->dsos, filename, false); + up_read(&machine->dsos.lock); + if (header_bid_dso && header_bid_dso->header_build_id) { + dso__set_build_id(dso, &header_bid_dso->bid); + dso->header_build_id = 1; + } + } dso__put(dso); } return map; @@ -524,403 +527,13 @@ u64 map__objdump_2mem(struct map *map, u64 ip) return ip + map->reloc; } -void maps__init(struct maps *maps, struct machine *machine) -{ - maps->entries = RB_ROOT; - init_rwsem(&maps->lock); - maps->machine = machine; - maps->last_search_by_name = NULL; - maps->nr_maps = 0; - maps->maps_by_name = NULL; - refcount_set(&maps->refcnt, 1); -} - -static void __maps__free_maps_by_name(struct maps *maps) -{ - /* - * Free everything to try to do it from the rbtree in the next search - */ - zfree(&maps->maps_by_name); - maps->nr_maps_allocated = 0; -} - -void maps__insert(struct maps *maps, struct map *map) -{ - down_write(&maps->lock); - __maps__insert(maps, map); - ++maps->nr_maps; - - if (map->dso && map->dso->kernel) { - struct kmap *kmap = map__kmap(map); - - if (kmap) - kmap->kmaps = maps; - else - pr_err("Internal error: kernel dso with non kernel map\n"); - } - - - /* - * If we already performed some search by name, then we need to add the just - * inserted map and resort. - */ - if (maps->maps_by_name) { - if (maps->nr_maps > maps->nr_maps_allocated) { - int nr_allocate = maps->nr_maps * 2; - struct map **maps_by_name = realloc(maps->maps_by_name, nr_allocate * sizeof(map)); - - if (maps_by_name == NULL) { - __maps__free_maps_by_name(maps); - up_write(&maps->lock); - return; - } - - maps->maps_by_name = maps_by_name; - maps->nr_maps_allocated = nr_allocate; - } - maps->maps_by_name[maps->nr_maps - 1] = map; - __maps__sort_by_name(maps); - } - up_write(&maps->lock); -} - -static void __maps__remove(struct maps *maps, struct map *map) -{ - rb_erase_init(&map->rb_node, &maps->entries); - map__put(map); -} - -void maps__remove(struct maps *maps, struct map *map) -{ - down_write(&maps->lock); - if (maps->last_search_by_name == map) - maps->last_search_by_name = NULL; - - __maps__remove(maps, map); - --maps->nr_maps; - if (maps->maps_by_name) - __maps__free_maps_by_name(maps); - up_write(&maps->lock); -} - -static void __maps__purge(struct maps *maps) -{ - struct map *pos, *next; - - maps__for_each_entry_safe(maps, pos, next) { - rb_erase_init(&pos->rb_node, &maps->entries); - map__put(pos); - } -} - -void maps__exit(struct maps *maps) -{ - down_write(&maps->lock); - __maps__purge(maps); - up_write(&maps->lock); -} - -bool maps__empty(struct maps *maps) -{ - return !maps__first(maps); -} - -struct maps *maps__new(struct machine *machine) -{ - struct maps *maps = zalloc(sizeof(*maps)); - - if (maps != NULL) - maps__init(maps, machine); - - return maps; -} - -void maps__delete(struct maps *maps) -{ - maps__exit(maps); - unwind__finish_access(maps); - free(maps); -} - -void maps__put(struct maps *maps) -{ - if (maps && refcount_dec_and_test(&maps->refcnt)) - maps__delete(maps); -} - -struct symbol *maps__find_symbol(struct maps *maps, u64 addr, struct map **mapp) -{ - struct map *map = maps__find(maps, addr); - - /* Ensure map is loaded before using map->map_ip */ - if (map != NULL && map__load(map) >= 0) { - if (mapp != NULL) - *mapp = map; - return map__find_symbol(map, map->map_ip(map, addr)); - } - - return NULL; -} - -static bool map__contains_symbol(struct map *map, struct symbol *sym) +bool map__contains_symbol(const struct map *map, const struct symbol *sym) { u64 ip = map->unmap_ip(map, sym->start); return ip >= map->start && ip < map->end; } -struct symbol *maps__find_symbol_by_name(struct maps *maps, const char *name, struct map **mapp) -{ - struct symbol *sym; - struct map *pos; - - down_read(&maps->lock); - - maps__for_each_entry(maps, pos) { - sym = map__find_symbol_by_name(pos, name); - - if (sym == NULL) - continue; - if (!map__contains_symbol(pos, sym)) { - sym = NULL; - continue; - } - if (mapp != NULL) - *mapp = pos; - goto out; - } - - sym = NULL; -out: - up_read(&maps->lock); - return sym; -} - -int maps__find_ams(struct maps *maps, struct addr_map_symbol *ams) -{ - if (ams->addr < ams->ms.map->start || ams->addr >= ams->ms.map->end) { - if (maps == NULL) - return -1; - ams->ms.map = maps__find(maps, ams->addr); - if (ams->ms.map == NULL) - return -1; - } - - ams->al_addr = ams->ms.map->map_ip(ams->ms.map, ams->addr); - ams->ms.sym = map__find_symbol(ams->ms.map, ams->al_addr); - - return ams->ms.sym ? 0 : -1; -} - -size_t maps__fprintf(struct maps *maps, FILE *fp) -{ - size_t printed = 0; - struct map *pos; - - down_read(&maps->lock); - - maps__for_each_entry(maps, pos) { - printed += fprintf(fp, "Map:"); - printed += map__fprintf(pos, fp); - if (verbose > 2) { - printed += dso__fprintf(pos->dso, fp); - printed += fprintf(fp, "--\n"); - } - } - - up_read(&maps->lock); - - return printed; -} - -int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) -{ - struct rb_root *root; - struct rb_node *next, *first; - int err = 0; - - down_write(&maps->lock); - - root = &maps->entries; - - /* - * Find first map where end > map->start. - * Same as find_vma() in kernel. - */ - next = root->rb_node; - first = NULL; - while (next) { - struct map *pos = rb_entry(next, struct map, rb_node); - - if (pos->end > map->start) { - first = next; - if (pos->start <= map->start) - break; - next = next->rb_left; - } else - next = next->rb_right; - } - - next = first; - while (next) { - struct map *pos = rb_entry(next, struct map, rb_node); - next = rb_next(&pos->rb_node); - - /* - * Stop if current map starts after map->end. - * Maps are ordered by start: next will not overlap for sure. - */ - if (pos->start >= map->end) - break; - - if (verbose >= 2) { - - if (use_browser) { - pr_debug("overlapping maps in %s (disable tui for more info)\n", - map->dso->name); - } else { - fputs("overlapping maps:\n", fp); - map__fprintf(map, fp); - map__fprintf(pos, fp); - } - } - - rb_erase_init(&pos->rb_node, root); - /* - * Now check if we need to create new maps for areas not - * overlapped by the new map: - */ - if (map->start > pos->start) { - struct map *before = map__clone(pos); - - if (before == NULL) { - err = -ENOMEM; - goto put_map; - } - - before->end = map->start; - __maps__insert(maps, before); - if (verbose >= 2 && !use_browser) - map__fprintf(before, fp); - map__put(before); - } - - if (map->end < pos->end) { - struct map *after = map__clone(pos); - - if (after == NULL) { - err = -ENOMEM; - goto put_map; - } - - after->start = map->end; - after->pgoff += map->end - pos->start; - assert(pos->map_ip(pos, map->end) == after->map_ip(after, map->end)); - __maps__insert(maps, after); - if (verbose >= 2 && !use_browser) - map__fprintf(after, fp); - map__put(after); - } -put_map: - map__put(pos); - - if (err) - goto out; - } - - err = 0; -out: - up_write(&maps->lock); - return err; -} - -/* - * XXX This should not really _copy_ te maps, but refcount them. - */ -int maps__clone(struct thread *thread, struct maps *parent) -{ - struct maps *maps = thread->maps; - int err; - struct map *map; - - down_read(&parent->lock); - - maps__for_each_entry(parent, map) { - struct map *new = map__clone(map); - - if (new == NULL) { - err = -ENOMEM; - goto out_unlock; - } - - err = unwind__prepare_access(maps, new, NULL); - if (err) - goto out_unlock; - - maps__insert(maps, new); - map__put(new); - } - - err = 0; -out_unlock: - up_read(&parent->lock); - return err; -} - -static void __maps__insert(struct maps *maps, struct map *map) -{ - struct rb_node **p = &maps->entries.rb_node; - struct rb_node *parent = NULL; - const u64 ip = map->start; - struct map *m; - - while (*p != NULL) { - parent = *p; - m = rb_entry(parent, struct map, rb_node); - if (ip < m->start) - p = &(*p)->rb_left; - else - p = &(*p)->rb_right; - } - - rb_link_node(&map->rb_node, parent, p); - rb_insert_color(&map->rb_node, &maps->entries); - map__get(map); -} - -struct map *maps__find(struct maps *maps, u64 ip) -{ - struct rb_node *p; - struct map *m; - - down_read(&maps->lock); - - p = maps->entries.rb_node; - while (p != NULL) { - m = rb_entry(p, struct map, rb_node); - if (ip < m->start) - p = p->rb_left; - else if (ip >= m->end) - p = p->rb_right; - else - goto out; - } - - m = NULL; -out: - up_read(&maps->lock); - return m; -} - -struct map *maps__first(struct maps *maps) -{ - struct rb_node *first = rb_first(&maps->entries); - - if (first) - return rb_entry(first, struct map, rb_node); - return NULL; -} - static struct map *__map__next(struct map *map) { struct rb_node *next = rb_next(&map->rb_node); @@ -961,3 +574,18 @@ struct maps *map__kmaps(struct map *map) } return kmap->kmaps; } + +u64 map__map_ip(const struct map *map, u64 ip) +{ + return ip - map->start + map->pgoff; +} + +u64 map__unmap_ip(const struct map *map, u64 ip) +{ + return ip + map->start - map->pgoff; +} + +u64 identity__map_ip(const struct map *map __maybe_unused, u64 ip) +{ + return ip; +} diff --git a/tools/perf/util/map.h b/tools/perf/util/map.h index d32f5b28c1fb..3dcfe06db6b3 100644 --- a/tools/perf/util/map.h +++ b/tools/perf/util/map.h @@ -29,9 +29,9 @@ struct map { u64 reloc; /* ip -> dso rip */ - u64 (*map_ip)(struct map *, u64); + u64 (*map_ip)(const struct map *, u64); /* dso rip -> ip */ - u64 (*unmap_ip)(struct map *, u64); + u64 (*unmap_ip)(const struct map *, u64); struct dso *dso; refcount_t refcnt; @@ -44,20 +44,12 @@ struct kmap *__map__kmap(struct map *map); struct kmap *map__kmap(struct map *map); struct maps *map__kmaps(struct map *map); -static inline u64 map__map_ip(struct map *map, u64 ip) -{ - return ip - map->start + map->pgoff; -} - -static inline u64 map__unmap_ip(struct map *map, u64 ip) -{ - return ip + map->start - map->pgoff; -} - -static inline u64 identity__map_ip(struct map *map __maybe_unused, u64 ip) -{ - return ip; -} +/* ip -> dso rip */ +u64 map__map_ip(const struct map *map, u64 ip); +/* dso rip -> ip */ +u64 map__unmap_ip(const struct map *map, u64 ip); +/* Returns ip */ +u64 identity__map_ip(const struct map *map __maybe_unused, u64 ip); static inline size_t map__size(const struct map *map) { @@ -160,6 +152,8 @@ static inline bool __map__is_kmodule(const struct map *map) bool map__has_symbols(const struct map *map); +bool map__contains_symbol(const struct map *map, const struct symbol *sym); + #define ENTRY_TRAMPOLINE_NAME "__entry_SYSCALL_64_trampoline" static inline bool is_entry_trampoline(const char *name) diff --git a/tools/perf/util/maps.c b/tools/perf/util/maps.c new file mode 100644 index 000000000000..37bd5b40000d --- /dev/null +++ b/tools/perf/util/maps.c @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include "debug.h" +#include "dso.h" +#include "map.h" +#include "maps.h" +#include "thread.h" +#include "ui/ui.h" +#include "unwind.h" + +static void __maps__insert(struct maps *maps, struct map *map); + +static void maps__init(struct maps *maps, struct machine *machine) +{ + maps->entries = RB_ROOT; + init_rwsem(&maps->lock); + maps->machine = machine; + maps->last_search_by_name = NULL; + maps->nr_maps = 0; + maps->maps_by_name = NULL; + refcount_set(&maps->refcnt, 1); +} + +static void __maps__free_maps_by_name(struct maps *maps) +{ + /* + * Free everything to try to do it from the rbtree in the next search + */ + zfree(&maps->maps_by_name); + maps->nr_maps_allocated = 0; +} + +void maps__insert(struct maps *maps, struct map *map) +{ + down_write(&maps->lock); + __maps__insert(maps, map); + ++maps->nr_maps; + + if (map->dso && map->dso->kernel) { + struct kmap *kmap = map__kmap(map); + + if (kmap) + kmap->kmaps = maps; + else + pr_err("Internal error: kernel dso with non kernel map\n"); + } + + + /* + * If we already performed some search by name, then we need to add the just + * inserted map and resort. + */ + if (maps->maps_by_name) { + if (maps->nr_maps > maps->nr_maps_allocated) { + int nr_allocate = maps->nr_maps * 2; + struct map **maps_by_name = realloc(maps->maps_by_name, nr_allocate * sizeof(map)); + + if (maps_by_name == NULL) { + __maps__free_maps_by_name(maps); + up_write(&maps->lock); + return; + } + + maps->maps_by_name = maps_by_name; + maps->nr_maps_allocated = nr_allocate; + } + maps->maps_by_name[maps->nr_maps - 1] = map; + __maps__sort_by_name(maps); + } + up_write(&maps->lock); +} + +static void __maps__remove(struct maps *maps, struct map *map) +{ + rb_erase_init(&map->rb_node, &maps->entries); + map__put(map); +} + +void maps__remove(struct maps *maps, struct map *map) +{ + down_write(&maps->lock); + if (maps->last_search_by_name == map) + maps->last_search_by_name = NULL; + + __maps__remove(maps, map); + --maps->nr_maps; + if (maps->maps_by_name) + __maps__free_maps_by_name(maps); + up_write(&maps->lock); +} + +static void __maps__purge(struct maps *maps) +{ + struct map *pos, *next; + + maps__for_each_entry_safe(maps, pos, next) { + rb_erase_init(&pos->rb_node, &maps->entries); + map__put(pos); + } +} + +static void maps__exit(struct maps *maps) +{ + down_write(&maps->lock); + __maps__purge(maps); + up_write(&maps->lock); +} + +bool maps__empty(struct maps *maps) +{ + return !maps__first(maps); +} + +struct maps *maps__new(struct machine *machine) +{ + struct maps *maps = zalloc(sizeof(*maps)); + + if (maps != NULL) + maps__init(maps, machine); + + return maps; +} + +void maps__delete(struct maps *maps) +{ + maps__exit(maps); + unwind__finish_access(maps); + free(maps); +} + +void maps__put(struct maps *maps) +{ + if (maps && refcount_dec_and_test(&maps->refcnt)) + maps__delete(maps); +} + +struct symbol *maps__find_symbol(struct maps *maps, u64 addr, struct map **mapp) +{ + struct map *map = maps__find(maps, addr); + + /* Ensure map is loaded before using map->map_ip */ + if (map != NULL && map__load(map) >= 0) { + if (mapp != NULL) + *mapp = map; + return map__find_symbol(map, map->map_ip(map, addr)); + } + + return NULL; +} + +struct symbol *maps__find_symbol_by_name(struct maps *maps, const char *name, struct map **mapp) +{ + struct symbol *sym; + struct map *pos; + + down_read(&maps->lock); + + maps__for_each_entry(maps, pos) { + sym = map__find_symbol_by_name(pos, name); + + if (sym == NULL) + continue; + if (!map__contains_symbol(pos, sym)) { + sym = NULL; + continue; + } + if (mapp != NULL) + *mapp = pos; + goto out; + } + + sym = NULL; +out: + up_read(&maps->lock); + return sym; +} + +int maps__find_ams(struct maps *maps, struct addr_map_symbol *ams) +{ + if (ams->addr < ams->ms.map->start || ams->addr >= ams->ms.map->end) { + if (maps == NULL) + return -1; + ams->ms.map = maps__find(maps, ams->addr); + if (ams->ms.map == NULL) + return -1; + } + + ams->al_addr = ams->ms.map->map_ip(ams->ms.map, ams->addr); + ams->ms.sym = map__find_symbol(ams->ms.map, ams->al_addr); + + return ams->ms.sym ? 0 : -1; +} + +size_t maps__fprintf(struct maps *maps, FILE *fp) +{ + size_t printed = 0; + struct map *pos; + + down_read(&maps->lock); + + maps__for_each_entry(maps, pos) { + printed += fprintf(fp, "Map:"); + printed += map__fprintf(pos, fp); + if (verbose > 2) { + printed += dso__fprintf(pos->dso, fp); + printed += fprintf(fp, "--\n"); + } + } + + up_read(&maps->lock); + + return printed; +} + +int maps__fixup_overlappings(struct maps *maps, struct map *map, FILE *fp) +{ + struct rb_root *root; + struct rb_node *next, *first; + int err = 0; + + down_write(&maps->lock); + + root = &maps->entries; + + /* + * Find first map where end > map->start. + * Same as find_vma() in kernel. + */ + next = root->rb_node; + first = NULL; + while (next) { + struct map *pos = rb_entry(next, struct map, rb_node); + + if (pos->end > map->start) { + first = next; + if (pos->start <= map->start) + break; + next = next->rb_left; + } else + next = next->rb_right; + } + + next = first; + while (next) { + struct map *pos = rb_entry(next, struct map, rb_node); + next = rb_next(&pos->rb_node); + + /* + * Stop if current map starts after map->end. + * Maps are ordered by start: next will not overlap for sure. + */ + if (pos->start >= map->end) + break; + + if (verbose >= 2) { + + if (use_browser) { + pr_debug("overlapping maps in %s (disable tui for more info)\n", + map->dso->name); + } else { + fputs("overlapping maps:\n", fp); + map__fprintf(map, fp); + map__fprintf(pos, fp); + } + } + + rb_erase_init(&pos->rb_node, root); + /* + * Now check if we need to create new maps for areas not + * overlapped by the new map: + */ + if (map->start > pos->start) { + struct map *before = map__clone(pos); + + if (before == NULL) { + err = -ENOMEM; + goto put_map; + } + + before->end = map->start; + __maps__insert(maps, before); + if (verbose >= 2 && !use_browser) + map__fprintf(before, fp); + map__put(before); + } + + if (map->end < pos->end) { + struct map *after = map__clone(pos); + + if (after == NULL) { + err = -ENOMEM; + goto put_map; + } + + after->start = map->end; + after->pgoff += map->end - pos->start; + assert(pos->map_ip(pos, map->end) == after->map_ip(after, map->end)); + __maps__insert(maps, after); + if (verbose >= 2 && !use_browser) + map__fprintf(after, fp); + map__put(after); + } +put_map: + map__put(pos); + + if (err) + goto out; + } + + err = 0; +out: + up_write(&maps->lock); + return err; +} + +/* + * XXX This should not really _copy_ te maps, but refcount them. + */ +int maps__clone(struct thread *thread, struct maps *parent) +{ + struct maps *maps = thread->maps; + int err; + struct map *map; + + down_read(&parent->lock); + + maps__for_each_entry(parent, map) { + struct map *new = map__clone(map); + + if (new == NULL) { + err = -ENOMEM; + goto out_unlock; + } + + err = unwind__prepare_access(maps, new, NULL); + if (err) + goto out_unlock; + + maps__insert(maps, new); + map__put(new); + } + + err = 0; +out_unlock: + up_read(&parent->lock); + return err; +} + +static void __maps__insert(struct maps *maps, struct map *map) +{ + struct rb_node **p = &maps->entries.rb_node; + struct rb_node *parent = NULL; + const u64 ip = map->start; + struct map *m; + + while (*p != NULL) { + parent = *p; + m = rb_entry(parent, struct map, rb_node); + if (ip < m->start) + p = &(*p)->rb_left; + else + p = &(*p)->rb_right; + } + + rb_link_node(&map->rb_node, parent, p); + rb_insert_color(&map->rb_node, &maps->entries); + map__get(map); +} + +struct map *maps__find(struct maps *maps, u64 ip) +{ + struct rb_node *p; + struct map *m; + + down_read(&maps->lock); + + p = maps->entries.rb_node; + while (p != NULL) { + m = rb_entry(p, struct map, rb_node); + if (ip < m->start) + p = p->rb_left; + else if (ip >= m->end) + p = p->rb_right; + else + goto out; + } + + m = NULL; +out: + up_read(&maps->lock); + return m; +} + +struct map *maps__first(struct maps *maps) +{ + struct rb_node *first = rb_first(&maps->entries); + + if (first) + return rb_entry(first, struct map, rb_node); + return NULL; +} diff --git a/tools/perf/util/maps.h b/tools/perf/util/maps.h index 3dd000ddf925..7e729ff42749 100644 --- a/tools/perf/util/maps.h +++ b/tools/perf/util/maps.h @@ -60,8 +60,6 @@ static inline struct maps *maps__get(struct maps *maps) } void maps__put(struct maps *maps); -void maps__init(struct maps *maps, struct machine *machine); -void maps__exit(struct maps *maps); int maps__clone(struct thread *thread, struct maps *parent); size_t maps__fprintf(struct maps *maps, FILE *fp); diff --git a/tools/perf/util/mmap.c b/tools/perf/util/mmap.c index 0e8ff8d1e206..50502b4a7ca4 100644 --- a/tools/perf/util/mmap.c +++ b/tools/perf/util/mmap.c @@ -230,6 +230,10 @@ void mmap__munmap(struct mmap *map) { bitmap_free(map->affinity_mask.bits); +#ifndef PYTHON_PERF + zstd_fini(&map->zstd_data); +#endif + perf_mmap__aio_munmap(map); if (map->data != NULL) { munmap(map->data, mmap__mmap_len(map)); @@ -292,6 +296,12 @@ int mmap__mmap(struct mmap *map, struct mmap_params *mp, int fd, struct perf_cpu map->core.flush = mp->flush; map->comp_level = mp->comp_level; +#ifndef PYTHON_PERF + if (zstd_init(&map->zstd_data, map->comp_level)) { + pr_debug2("failed to init mmap compressor, error %d\n", errno); + return -1; + } +#endif if (map->comp_level && !perf_mmap__aio_enabled(map)) { map->data = mmap(NULL, mmap__mmap_len(map), PROT_READ|PROT_WRITE, diff --git a/tools/perf/util/mmap.h b/tools/perf/util/mmap.h index 83f6bd4d4082..cd8b0777473b 100644 --- a/tools/perf/util/mmap.h +++ b/tools/perf/util/mmap.h @@ -15,6 +15,7 @@ #endif #include "auxtrace.h" #include "event.h" +#include "util/compress.h" struct aiocb; @@ -45,6 +46,8 @@ struct mmap { struct mmap_cpu_mask affinity_mask; void *data; int comp_level; + struct perf_data_file *file; + struct zstd_data zstd_data; }; struct mmap_params { diff --git a/tools/perf/util/namespaces.c b/tools/perf/util/namespaces.c index 48aa3217300b..dd536220cdb9 100644 --- a/tools/perf/util/namespaces.c +++ b/tools/perf/util/namespaces.c @@ -76,7 +76,7 @@ static int nsinfo__get_nspid(struct nsinfo *nsi, const char *path) if (strstr(statln, "Tgid:") != NULL) { nsi->tgid = (pid_t)strtol(strrchr(statln, '\t'), NULL, 10); - nsi->nstgid = nsi->tgid; + nsi->nstgid = nsinfo__tgid(nsi); } if (strstr(statln, "NStgid:") != NULL) { @@ -108,7 +108,7 @@ int nsinfo__init(struct nsinfo *nsi) if (snprintf(oldns, PATH_MAX, "/proc/self/ns/mnt") >= PATH_MAX) return rv; - if (asprintf(&newns, "/proc/%d/ns/mnt", nsi->pid) == -1) + if (asprintf(&newns, "/proc/%d/ns/mnt", nsinfo__pid(nsi)) == -1) return rv; if (stat(oldns, &old_stat) < 0) @@ -129,7 +129,7 @@ int nsinfo__init(struct nsinfo *nsi) /* If we're dealing with a process that is in a different PID namespace, * attempt to work out the innermost tgid for the process. */ - if (snprintf(spath, PATH_MAX, "/proc/%d/status", nsi->pid) >= PATH_MAX) + if (snprintf(spath, PATH_MAX, "/proc/%d/status", nsinfo__pid(nsi)) >= PATH_MAX) goto out; rv = nsinfo__get_nspid(nsi, spath); @@ -166,7 +166,7 @@ struct nsinfo *nsinfo__new(pid_t pid) return nsi; } -struct nsinfo *nsinfo__copy(struct nsinfo *nsi) +struct nsinfo *nsinfo__copy(const struct nsinfo *nsi) { struct nsinfo *nnsi; @@ -175,11 +175,11 @@ struct nsinfo *nsinfo__copy(struct nsinfo *nsi) nnsi = calloc(1, sizeof(*nnsi)); if (nnsi != NULL) { - nnsi->pid = nsi->pid; - nnsi->tgid = nsi->tgid; - nnsi->nstgid = nsi->nstgid; - nnsi->need_setns = nsi->need_setns; - nnsi->in_pidns = nsi->in_pidns; + nnsi->pid = nsinfo__pid(nsi); + nnsi->tgid = nsinfo__tgid(nsi); + nnsi->nstgid = nsinfo__nstgid(nsi); + nnsi->need_setns = nsinfo__need_setns(nsi); + nnsi->in_pidns = nsinfo__in_pidns(nsi); if (nsi->mntns_path) { nnsi->mntns_path = strdup(nsi->mntns_path); if (!nnsi->mntns_path) { @@ -193,7 +193,7 @@ struct nsinfo *nsinfo__copy(struct nsinfo *nsi) return nnsi; } -void nsinfo__delete(struct nsinfo *nsi) +static void nsinfo__delete(struct nsinfo *nsi) { zfree(&nsi->mntns_path); free(nsi); @@ -212,6 +212,36 @@ void nsinfo__put(struct nsinfo *nsi) nsinfo__delete(nsi); } +bool nsinfo__need_setns(const struct nsinfo *nsi) +{ + return nsi->need_setns; +} + +void nsinfo__clear_need_setns(struct nsinfo *nsi) +{ + nsi->need_setns = false; +} + +pid_t nsinfo__tgid(const struct nsinfo *nsi) +{ + return nsi->tgid; +} + +pid_t nsinfo__nstgid(const struct nsinfo *nsi) +{ + return nsi->nstgid; +} + +pid_t nsinfo__pid(const struct nsinfo *nsi) +{ + return nsi->pid; +} + +pid_t nsinfo__in_pidns(const struct nsinfo *nsi) +{ + return nsi->in_pidns; +} + void nsinfo__mountns_enter(struct nsinfo *nsi, struct nscookie *nc) { diff --git a/tools/perf/util/namespaces.h b/tools/perf/util/namespaces.h index 9ceea9643507..567829262c42 100644 --- a/tools/perf/util/namespaces.h +++ b/tools/perf/util/namespaces.h @@ -47,12 +47,18 @@ struct nscookie { int nsinfo__init(struct nsinfo *nsi); struct nsinfo *nsinfo__new(pid_t pid); -struct nsinfo *nsinfo__copy(struct nsinfo *nsi); -void nsinfo__delete(struct nsinfo *nsi); +struct nsinfo *nsinfo__copy(const struct nsinfo *nsi); struct nsinfo *nsinfo__get(struct nsinfo *nsi); void nsinfo__put(struct nsinfo *nsi); +bool nsinfo__need_setns(const struct nsinfo *nsi); +void nsinfo__clear_need_setns(struct nsinfo *nsi); +pid_t nsinfo__tgid(const struct nsinfo *nsi); +pid_t nsinfo__nstgid(const struct nsinfo *nsi); +pid_t nsinfo__pid(const struct nsinfo *nsi); +pid_t nsinfo__in_pidns(const struct nsinfo *nsi); + void nsinfo__mountns_enter(struct nsinfo *nsi, struct nscookie *nc); void nsinfo__mountns_exit(struct nscookie *nc); diff --git a/tools/perf/util/ordered-events.c b/tools/perf/util/ordered-events.c index 48c8f609441b..b887dfeea673 100644 --- a/tools/perf/util/ordered-events.c +++ b/tools/perf/util/ordered-events.c @@ -192,7 +192,7 @@ void ordered_events__delete(struct ordered_events *oe, struct ordered_event *eve } int ordered_events__queue(struct ordered_events *oe, union perf_event *event, - u64 timestamp, u64 file_offset) + u64 timestamp, u64 file_offset, const char *file_path) { struct ordered_event *oevent; @@ -217,6 +217,7 @@ int ordered_events__queue(struct ordered_events *oe, union perf_event *event, return -ENOMEM; oevent->file_offset = file_offset; + oevent->file_path = file_path; return 0; } diff --git a/tools/perf/util/ordered-events.h b/tools/perf/util/ordered-events.h index 75345946c4b9..0b05c3c0aeaa 100644 --- a/tools/perf/util/ordered-events.h +++ b/tools/perf/util/ordered-events.h @@ -9,6 +9,7 @@ struct perf_sample; struct ordered_event { u64 timestamp; u64 file_offset; + const char *file_path; union perf_event *event; struct list_head list; }; @@ -53,7 +54,7 @@ struct ordered_events { }; int ordered_events__queue(struct ordered_events *oe, union perf_event *event, - u64 timestamp, u64 file_offset); + u64 timestamp, u64 file_offset, const char *file_path); void ordered_events__delete(struct ordered_events *oe, struct ordered_event *event); int ordered_events__flush(struct ordered_events *oe, enum oe_flush how); int ordered_events__flush_time(struct ordered_events *oe, u64 timestamp); diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index 8dfbba15aeb8..9a1c7e63e663 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1998,7 +1998,8 @@ int perf_pmu__cpus_match(struct perf_pmu *pmu, struct perf_cpu_map *cpus, { struct perf_cpu_map *pmu_cpus = pmu->cpus; struct perf_cpu_map *matched_cpus, *unmatched_cpus; - int matched_nr = 0, unmatched_nr = 0; + struct perf_cpu cpu; + int i, matched_nr = 0, unmatched_nr = 0; matched_cpus = perf_cpu_map__default_new(); if (!matched_cpus) @@ -2010,14 +2011,11 @@ int perf_pmu__cpus_match(struct perf_pmu *pmu, struct perf_cpu_map *cpus, return -1; } - for (int i = 0; i < cpus->nr; i++) { - int cpu; - - cpu = perf_cpu_map__idx(pmu_cpus, cpus->map[i]); - if (cpu == -1) - unmatched_cpus->map[unmatched_nr++] = cpus->map[i]; + perf_cpu_map__for_each_cpu(cpu, i, cpus) { + if (!perf_cpu_map__has(pmu_cpus, cpu)) + unmatched_cpus->map[unmatched_nr++] = cpu; else - matched_cpus->map[matched_nr++] = cpus->map[i]; + matched_cpus->map[matched_nr++] = cpu; } unmatched_cpus->nr = unmatched_nr; diff --git a/tools/perf/util/probe-event.c b/tools/perf/util/probe-event.c index a834918a0a0d..062b5cbe67af 100644 --- a/tools/perf/util/probe-event.c +++ b/tools/perf/util/probe-event.c @@ -332,7 +332,7 @@ static int kernel_get_module_dso(const char *module, struct dso **pdso) char module_name[128]; snprintf(module_name, sizeof(module_name), "[%s]", module); - map = maps__find_by_name(&host_machine->kmaps, module_name); + map = maps__find_by_name(machine__kernel_maps(host_machine), module_name); if (map) { dso = map->dso; goto found; diff --git a/tools/perf/util/python.c b/tools/perf/util/python.c index 52d8995cfd73..5be5fa2391de 100644 --- a/tools/perf/util/python.c +++ b/tools/perf/util/python.c @@ -58,10 +58,21 @@ int parse_callchain_record(const char *arg __maybe_unused, } /* - * Add this one here not to drag util/env.c + * Add these not to drag util/env.c */ struct perf_env perf_env; +const char *perf_env__cpuid(struct perf_env *env __maybe_unused) +{ + return NULL; +} + +// This one is a bit easier, wouldn't drag too much, but leave it as a stub we need it here +const char *perf_env__arch(struct perf_env *env __maybe_unused) +{ + return NULL; +} + /* * Add this one here not to drag util/stat-shadow.c */ diff --git a/tools/perf/util/record.h b/tools/perf/util/record.h index ef6c2715fdd9..be9a957501f4 100644 --- a/tools/perf/util/record.h +++ b/tools/perf/util/record.h @@ -78,6 +78,8 @@ struct record_opts { int ctl_fd_ack; bool ctl_fd_close; int synth; + int threads_spec; + const char *threads_user_spec; }; extern const char * const *record_usage; diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index e752e1f4a5f0..413f2d19c13f 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -1216,7 +1216,7 @@ static void python_export_sample_table(struct db_export *dbe, struct tables *tables = container_of(dbe, struct tables, dbe); PyObject *t; - t = tuple_new(24); + t = tuple_new(25); tuple_set_d64(t, 0, es->db_id); tuple_set_d64(t, 1, es->evsel->db_id); @@ -1242,6 +1242,7 @@ static void python_export_sample_table(struct db_export *dbe, tuple_set_d64(t, 21, es->call_path_id); tuple_set_d64(t, 22, es->sample->insn_cnt); tuple_set_d64(t, 23, es->sample->cyc_cnt); + tuple_set_s32(t, 24, es->sample->flags); call_object(tables->sample_handler, t, "sample_table"); diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index 498b05708db5..3b8dfe603e50 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -39,7 +39,8 @@ #ifdef HAVE_ZSTD_SUPPORT static int perf_session__process_compressed_event(struct perf_session *session, - union perf_event *event, u64 file_offset) + union perf_event *event, u64 file_offset, + const char *file_path) { void *src; size_t decomp_size, src_size; @@ -61,6 +62,7 @@ static int perf_session__process_compressed_event(struct perf_session *session, } decomp->file_pos = file_offset; + decomp->file_path = file_path; decomp->mmap_len = mmap_len; decomp->head = 0; @@ -100,7 +102,8 @@ static int perf_session__process_compressed_event(struct perf_session *session, static int perf_session__deliver_event(struct perf_session *session, union perf_event *event, struct perf_tool *tool, - u64 file_offset); + u64 file_offset, + const char *file_path); static int perf_session__open(struct perf_session *session, int repipe_fd) { @@ -182,7 +185,8 @@ static int ordered_events__deliver_event(struct ordered_events *oe, ordered_events); return perf_session__deliver_event(session, event->event, - session->tool, event->file_offset); + session->tool, event->file_offset, + event->file_path); } struct perf_session *__perf_session__new(struct perf_data *data, @@ -471,7 +475,8 @@ static int process_event_time_conv_stub(struct perf_session *perf_session __mayb static int perf_session__process_compressed_event_stub(struct perf_session *session __maybe_unused, union perf_event *event __maybe_unused, - u64 file_offset __maybe_unused) + u64 file_offset __maybe_unused, + const char *file_path __maybe_unused) { dump_printf(": unhandled!\n"); return 0; @@ -1072,9 +1077,9 @@ static int process_finished_round(struct perf_tool *tool __maybe_unused, } int perf_session__queue_event(struct perf_session *s, union perf_event *event, - u64 timestamp, u64 file_offset) + u64 timestamp, u64 file_offset, const char *file_path) { - return ordered_events__queue(&s->ordered_events, event, timestamp, file_offset); + return ordered_events__queue(&s->ordered_events, event, timestamp, file_offset, file_path); } static void callchain__lbr_callstack_printf(struct perf_sample *sample) @@ -1154,14 +1159,15 @@ static void branch_stack__printf(struct perf_sample *sample, bool callstack) struct branch_entry *e = &entries[i]; if (!callstack) { - printf("..... %2"PRIu64": %016" PRIx64 " -> %016" PRIx64 " %hu cycles %s%s%s%s %x\n", + printf("..... %2"PRIu64": %016" PRIx64 " -> %016" PRIx64 " %hu cycles %s%s%s%s %x %s\n", i, e->from, e->to, (unsigned short)e->flags.cycles, e->flags.mispred ? "M" : " ", e->flags.predicted ? "P" : " ", e->flags.abort ? "A" : " ", e->flags.in_tx ? "T" : " ", - (unsigned)e->flags.reserved); + (unsigned)e->flags.reserved, + e->flags.type ? branch_type_name(e->flags.type) : ""); } else { printf("..... %2"PRIu64": %016" PRIx64 "\n", i, i > 0 ? e->from : e->to); @@ -1277,13 +1283,14 @@ static void sample_read__printf(struct perf_sample *sample, u64 read_format) } static void dump_event(struct evlist *evlist, union perf_event *event, - u64 file_offset, struct perf_sample *sample) + u64 file_offset, struct perf_sample *sample, + const char *file_path) { if (!dump_trace) return; - printf("\n%#" PRIx64 " [%#x]: event: %d\n", - file_offset, event->header.size, event->header.type); + printf("\n%#" PRIx64 "@%s [%#x]: event: %d\n", + file_offset, file_path, event->header.size, event->header.type); trace_event(event); if (event->header.type == PERF_RECORD_SAMPLE && evlist->trace_event_sample_raw) @@ -1486,12 +1493,13 @@ static int machines__deliver_event(struct machines *machines, struct evlist *evlist, union perf_event *event, struct perf_sample *sample, - struct perf_tool *tool, u64 file_offset) + struct perf_tool *tool, u64 file_offset, + const char *file_path) { struct evsel *evsel; struct machine *machine; - dump_event(evlist, event, file_offset, sample); + dump_event(evlist, event, file_offset, sample, file_path); evsel = evlist__id2evsel(evlist, sample->id); @@ -1573,7 +1581,8 @@ static int machines__deliver_event(struct machines *machines, static int perf_session__deliver_event(struct perf_session *session, union perf_event *event, struct perf_tool *tool, - u64 file_offset) + u64 file_offset, + const char *file_path) { struct perf_sample sample; int ret = evlist__parse_sample(session->evlist, event, &sample); @@ -1590,7 +1599,7 @@ static int perf_session__deliver_event(struct perf_session *session, return 0; ret = machines__deliver_event(&session->machines, session->evlist, - event, &sample, tool, file_offset); + event, &sample, tool, file_offset, file_path); if (dump_trace && sample.aux_sample.size) auxtrace__dump_auxtrace_sample(session, &sample); @@ -1600,7 +1609,8 @@ static int perf_session__deliver_event(struct perf_session *session, static s64 perf_session__process_user_event(struct perf_session *session, union perf_event *event, - u64 file_offset) + u64 file_offset, + const char *file_path) { struct ordered_events *oe = &session->ordered_events; struct perf_tool *tool = session->tool; @@ -1610,7 +1620,7 @@ static s64 perf_session__process_user_event(struct perf_session *session, if (event->header.type != PERF_RECORD_COMPRESSED || tool->compressed == perf_session__process_compressed_event_stub) - dump_event(session->evlist, event, file_offset, &sample); + dump_event(session->evlist, event, file_offset, &sample, file_path); /* These events are processed right away */ switch (event->header.type) { @@ -1669,9 +1679,9 @@ static s64 perf_session__process_user_event(struct perf_session *session, case PERF_RECORD_HEADER_FEATURE: return tool->feature(session, event); case PERF_RECORD_COMPRESSED: - err = tool->compressed(session, event, file_offset); + err = tool->compressed(session, event, file_offset, file_path); if (err) - dump_event(session->evlist, event, file_offset, &sample); + dump_event(session->evlist, event, file_offset, &sample, file_path); return err; default: return -EINVAL; @@ -1688,9 +1698,9 @@ int perf_session__deliver_synth_event(struct perf_session *session, events_stats__inc(&evlist->stats, event->header.type); if (event->header.type >= PERF_RECORD_USER_TYPE_START) - return perf_session__process_user_event(session, event, 0); + return perf_session__process_user_event(session, event, 0, NULL); - return machines__deliver_event(&session->machines, evlist, event, sample, tool, 0); + return machines__deliver_event(&session->machines, evlist, event, sample, tool, 0, NULL); } static void event_swap(union perf_event *event, bool sample_id_all) @@ -1787,7 +1797,8 @@ int perf_session__peek_events(struct perf_session *session, u64 offset, } static s64 perf_session__process_event(struct perf_session *session, - union perf_event *event, u64 file_offset) + union perf_event *event, u64 file_offset, + const char *file_path) { struct evlist *evlist = session->evlist; struct perf_tool *tool = session->tool; @@ -1802,7 +1813,7 @@ static s64 perf_session__process_event(struct perf_session *session, events_stats__inc(&evlist->stats, event->header.type); if (event->header.type >= PERF_RECORD_USER_TYPE_START) - return perf_session__process_user_event(session, event, file_offset); + return perf_session__process_user_event(session, event, file_offset, file_path); if (tool->ordered_events) { u64 timestamp = -1ULL; @@ -1811,12 +1822,12 @@ static s64 perf_session__process_event(struct perf_session *session, if (ret && ret != -1) return ret; - ret = perf_session__queue_event(session, event, timestamp, file_offset); + ret = perf_session__queue_event(session, event, timestamp, file_offset, file_path); if (ret != -ETIME) return ret; } - return perf_session__deliver_event(session, event, tool, file_offset); + return perf_session__deliver_event(session, event, tool, file_offset, file_path); } void perf_event_header__bswap(struct perf_event_header *hdr) @@ -2043,7 +2054,7 @@ more: } } - if ((skip = perf_session__process_event(session, event, head)) < 0) { + if ((skip = perf_session__process_event(session, event, head, "pipe")) < 0) { pr_err("%#" PRIx64 " [%#x]: failed to process type: %d\n", head, event->header.size, event->header.type); err = -EINVAL; @@ -2140,7 +2151,8 @@ static int __perf_session__process_decomp_events(struct perf_session *session) size = event->header.size; if (size < sizeof(struct perf_event_header) || - (skip = perf_session__process_event(session, event, decomp->file_pos)) < 0) { + (skip = perf_session__process_event(session, event, decomp->file_pos, + decomp->file_path)) < 0) { pr_err("%#" PRIx64 " [%#x]: failed to process type: %d\n", decomp->file_pos + decomp->head, event->header.size, event->header.type); return -EINVAL; @@ -2171,10 +2183,12 @@ struct reader; typedef s64 (*reader_cb_t)(struct perf_session *session, union perf_event *event, - u64 file_offset); + u64 file_offset, + const char *file_path); struct reader { int fd; + const char *path; u64 data_size; u64 data_offset; reader_cb_t process; @@ -2186,6 +2200,8 @@ struct reader { u64 file_pos; u64 file_offset; u64 head; + u64 size; + bool done; struct zstd_data zstd_data; struct decomp_data decomp_data; }; @@ -2292,7 +2308,7 @@ reader__read_event(struct reader *rd, struct perf_session *session, skip = -EINVAL; if (size < sizeof(struct perf_event_header) || - (skip = rd->process(session, event, rd->file_pos)) < 0) { + (skip = rd->process(session, event, rd->file_pos, rd->path)) < 0) { pr_err("%#" PRIx64 " [%#x]: failed to process type: %d [%s]\n", rd->file_offset + rd->head, event->header.size, event->header.type, strerror(-skip)); @@ -2303,6 +2319,7 @@ reader__read_event(struct reader *rd, struct perf_session *session, if (skip) size += skip; + rd->size += size; rd->head += size; rd->file_pos += size; @@ -2359,15 +2376,17 @@ out: static s64 process_simple(struct perf_session *session, union perf_event *event, - u64 file_offset) + u64 file_offset, + const char *file_path) { - return perf_session__process_event(session, event, file_offset); + return perf_session__process_event(session, event, file_offset, file_path); } static int __perf_session__process_events(struct perf_session *session) { struct reader rd = { .fd = perf_data__fd(session->data), + .path = session->data->file.path, .data_size = session->header.data_size, .data_offset = session->header.data_offset, .process = process_simple, @@ -2411,6 +2430,135 @@ out_err: return err; } +/* + * Processing 2 MB of data from each reader in sequence, + * because that's the way the ordered events sorting works + * most efficiently. + */ +#define READER_MAX_SIZE (2 * 1024 * 1024) + +/* + * This function reads, merge and process directory data. + * It assumens the version 1 of directory data, where each + * data file holds per-cpu data, already sorted by kernel. + */ +static int __perf_session__process_dir_events(struct perf_session *session) +{ + struct perf_data *data = session->data; + struct perf_tool *tool = session->tool; + int i, ret, readers, nr_readers; + struct ui_progress prog; + u64 total_size = perf_data__size(session->data); + struct reader *rd; + + perf_tool__fill_defaults(tool); + + ui_progress__init_size(&prog, total_size, "Sorting events..."); + + nr_readers = 1; + for (i = 0; i < data->dir.nr; i++) { + if (data->dir.files[i].size) + nr_readers++; + } + + rd = zalloc(nr_readers * sizeof(struct reader)); + if (!rd) + return -ENOMEM; + + rd[0] = (struct reader) { + .fd = perf_data__fd(session->data), + .path = session->data->file.path, + .data_size = session->header.data_size, + .data_offset = session->header.data_offset, + .process = process_simple, + .in_place_update = session->data->in_place_update, + }; + ret = reader__init(&rd[0], NULL); + if (ret) + goto out_err; + ret = reader__mmap(&rd[0], session); + if (ret) + goto out_err; + readers = 1; + + for (i = 0; i < data->dir.nr; i++) { + if (!data->dir.files[i].size) + continue; + rd[readers] = (struct reader) { + .fd = data->dir.files[i].fd, + .path = data->dir.files[i].path, + .data_size = data->dir.files[i].size, + .data_offset = 0, + .process = process_simple, + .in_place_update = session->data->in_place_update, + }; + ret = reader__init(&rd[readers], NULL); + if (ret) + goto out_err; + ret = reader__mmap(&rd[readers], session); + if (ret) + goto out_err; + readers++; + } + + i = 0; + while (readers) { + if (session_done()) + break; + + if (rd[i].done) { + i = (i + 1) % nr_readers; + continue; + } + if (reader__eof(&rd[i])) { + rd[i].done = true; + readers--; + continue; + } + + session->active_decomp = &rd[i].decomp_data; + ret = reader__read_event(&rd[i], session, &prog); + if (ret < 0) { + goto out_err; + } else if (ret == READER_NODATA) { + ret = reader__mmap(&rd[i], session); + if (ret) + goto out_err; + } + + if (rd[i].size >= READER_MAX_SIZE) { + rd[i].size = 0; + i = (i + 1) % nr_readers; + } + } + + ret = ordered_events__flush(&session->ordered_events, OE_FLUSH__FINAL); + if (ret) + goto out_err; + + ret = perf_session__flush_thread_stacks(session); +out_err: + ui_progress__finish(); + + if (!tool->no_warn) + perf_session__warn_about_errors(session); + + /* + * We may switching perf.data output, make ordered_events + * reusable. + */ + ordered_events__reinit(&session->ordered_events); + + session->one_mmap = false; + + session->active_decomp = &session->decomp_data; + for (i = 0; i < nr_readers; i++) + reader__release_decomp(&rd[i]); + zfree(&rd); + + return ret; +} + int perf_session__process_events(struct perf_session *session) { if (perf_session__register_idle_thread(session) < 0) @@ -2419,6 +2567,9 @@ int perf_session__process_events(struct perf_session *session) if (perf_data__is_pipe(session->data)) return __perf_session__process_pipe_events(session); + if (perf_data__is_dir(session->data)) + return __perf_session__process_dir_events(session); + return __perf_session__process_events(session); } diff --git a/tools/perf/util/session.h b/tools/perf/util/session.h index 46c854292ad6..34500a3da735 100644 --- a/tools/perf/util/session.h +++ b/tools/perf/util/session.h @@ -52,6 +52,7 @@ struct perf_session { struct decomp { struct decomp *next; u64 file_pos; + const char *file_path; size_t mmap_len; u64 head; size_t size; @@ -87,7 +88,7 @@ int perf_session__peek_events(struct perf_session *session, u64 offset, int perf_session__process_events(struct perf_session *session); int perf_session__queue_event(struct perf_session *s, union perf_event *event, - u64 timestamp, u64 file_offset); + u64 timestamp, u64 file_offset, const char *file_path); void perf_tool__fill_defaults(struct perf_tool *tool); diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 2da081ef532b..6d5588e80935 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -990,6 +990,128 @@ struct sort_entry sort_sym_to = { .se_width_idx = HISTC_SYMBOL_TO, }; +static int _hist_entry__addr_snprintf(struct map_symbol *ms, + u64 ip, char level, char *bf, size_t size, + unsigned int width) +{ + struct symbol *sym = ms->sym; + struct map *map = ms->map; + size_t ret = 0, offs; + + ret += repsep_snprintf(bf + ret, size - ret, "[%c] ", level); + if (sym && map) { + if (sym->type == STT_OBJECT) { + ret += repsep_snprintf(bf + ret, size - ret, "%s", sym->name); + ret += repsep_snprintf(bf + ret, size - ret, "+0x%llx", + ip - map->unmap_ip(map, sym->start)); + } else { + ret += repsep_snprintf(bf + ret, size - ret, "%.*s", + width - ret, + sym->name); + offs = ip - sym->start; + if (offs) + ret += repsep_snprintf(bf + ret, size - ret, "+0x%llx", offs); + } + } else { + size_t len = BITS_PER_LONG / 4; + ret += repsep_snprintf(bf + ret, size - ret, "%-#.*llx", + len, ip); + } + + return ret; +} + +static int hist_entry__addr_from_snprintf(struct hist_entry *he, char *bf, + size_t size, unsigned int width) +{ + if (he->branch_info) { + struct addr_map_symbol *from = &he->branch_info->from; + + return _hist_entry__addr_snprintf(&from->ms, from->al_addr, + he->level, bf, size, width); + } + + return repsep_snprintf(bf, size, "%-*.*s", width, width, "N/A"); +} + +static int hist_entry__addr_to_snprintf(struct hist_entry *he, char *bf, + size_t size, unsigned int width) +{ + if (he->branch_info) { + struct addr_map_symbol *to = &he->branch_info->to; + + return _hist_entry__addr_snprintf(&to->ms, to->al_addr, + he->level, bf, size, width); + } + + return repsep_snprintf(bf, size, "%-*.*s", width, width, "N/A"); +} + +static int64_t +sort__addr_from_cmp(struct hist_entry *left, struct hist_entry *right) +{ + struct addr_map_symbol *from_l; + struct addr_map_symbol *from_r; + int64_t ret; + + if (!left->branch_info || !right->branch_info) + return cmp_null(left->branch_info, right->branch_info); + + from_l = &left->branch_info->from; + from_r = &right->branch_info->from; + + /* + * comparing symbol address alone is not enough since it's a + * relative address within a dso. + */ + ret = _sort__dso_cmp(from_l->ms.map, from_r->ms.map); + if (ret != 0) + return ret; + + return _sort__addr_cmp(from_l->addr, from_r->addr); +} + +static int64_t +sort__addr_to_cmp(struct hist_entry *left, struct hist_entry *right) +{ + struct addr_map_symbol *to_l; + struct addr_map_symbol *to_r; + int64_t ret; + + if (!left->branch_info || !right->branch_info) + return cmp_null(left->branch_info, right->branch_info); + + to_l = &left->branch_info->to; + to_r = &right->branch_info->to; + + /* + * comparing symbol address alone is not enough since it's a + * relative address within a dso. + */ + ret = _sort__dso_cmp(to_l->ms.map, to_r->ms.map); + if (ret != 0) + return ret; + + return _sort__addr_cmp(to_l->addr, to_r->addr); +} + +struct sort_entry sort_addr_from = { + .se_header = "Source Address", + .se_cmp = sort__addr_from_cmp, + .se_snprintf = hist_entry__addr_from_snprintf, + .se_filter = hist_entry__sym_from_filter, /* shared with sym_from */ + .se_width_idx = HISTC_ADDR_FROM, +}; + +struct sort_entry sort_addr_to = { + .se_header = "Target Address", + .se_cmp = sort__addr_to_cmp, + .se_snprintf = hist_entry__addr_to_snprintf, + .se_filter = hist_entry__sym_to_filter, /* shared with sym_to */ + .se_width_idx = HISTC_ADDR_TO, +}; + + static int64_t sort__mispredict_cmp(struct hist_entry *left, struct hist_entry *right) { @@ -1893,6 +2015,8 @@ static struct sort_dimension bstack_sort_dimensions[] = { DIM(SORT_SRCLINE_FROM, "srcline_from", sort_srcline_from), DIM(SORT_SRCLINE_TO, "srcline_to", sort_srcline_to), DIM(SORT_SYM_IPC, "ipc_lbr", sort_sym_ipc), + DIM(SORT_ADDR_FROM, "addr_from", sort_addr_from), + DIM(SORT_ADDR_TO, "addr_to", sort_addr_to), }; #undef DIM @@ -3126,6 +3250,10 @@ static bool get_elide(int idx, FILE *output) return __get_elide(symbol_conf.dso_from_list, "dso_from", output); case HISTC_DSO_TO: return __get_elide(symbol_conf.dso_to_list, "dso_to", output); + case HISTC_ADDR_FROM: + return __get_elide(symbol_conf.sym_from_list, "addr_from", output); + case HISTC_ADDR_TO: + return __get_elide(symbol_conf.sym_to_list, "addr_to", output); default: break; } diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h index f994261888e1..2ddc00d1c464 100644 --- a/tools/perf/util/sort.h +++ b/tools/perf/util/sort.h @@ -251,6 +251,8 @@ enum sort_type { SORT_SRCLINE_FROM, SORT_SRCLINE_TO, SORT_SYM_IPC, + SORT_ADDR_FROM, + SORT_ADDR_TO, /* memory mode specific sort keys */ __SORT_MEMORY_MODE, diff --git a/tools/perf/util/symbol.c b/tools/perf/util/symbol.c index dfde9eada224..dea0fc495185 100644 --- a/tools/perf/util/symbol.c +++ b/tools/perf/util/symbol.c @@ -1735,8 +1735,8 @@ static int dso__find_perf_map(char *filebuf, size_t bufsz, nsi = *nsip; - if (nsi->need_setns) { - snprintf(filebuf, bufsz, "/tmp/perf-%d.map", nsi->nstgid); + if (nsinfo__need_setns(nsi)) { + snprintf(filebuf, bufsz, "/tmp/perf-%d.map", nsinfo__nstgid(nsi)); nsinfo__mountns_enter(nsi, &nsc); rc = access(filebuf, R_OK); nsinfo__mountns_exit(&nsc); @@ -1748,8 +1748,8 @@ static int dso__find_perf_map(char *filebuf, size_t bufsz, if (nnsi) { nsinfo__put(nsi); - nnsi->need_setns = false; - snprintf(filebuf, bufsz, "/tmp/perf-%d.map", nnsi->tgid); + nsinfo__clear_need_setns(nnsi); + snprintf(filebuf, bufsz, "/tmp/perf-%d.map", nsinfo__tgid(nnsi)); *nsip = nnsi; rc = 0; } @@ -1864,6 +1864,16 @@ int dso__load(struct dso *dso, struct map *map) nsinfo__mountns_exit(&nsc); is_reg = is_regular_file(name); + if (!is_reg && errno == ENOENT && dso->nsinfo) { + char *new_name = filename_with_chroot(dso->nsinfo->pid, + name); + if (new_name) { + is_reg = is_regular_file(new_name); + strlcpy(name, new_name, PATH_MAX); + free(new_name); + } + } + #ifdef HAVE_LIBBFD_SUPPORT if (is_reg) bfdrc = dso__load_bfd_symbols(dso, name); diff --git a/tools/perf/util/tool.h b/tools/perf/util/tool.h index ef873f2cc38f..f2352dba1875 100644 --- a/tools/perf/util/tool.h +++ b/tools/perf/util/tool.h @@ -28,7 +28,8 @@ typedef int (*event_attr_op)(struct perf_tool *tool, typedef int (*event_op2)(struct perf_session *session, union perf_event *event); typedef s64 (*event_op3)(struct perf_session *session, union perf_event *event); -typedef int (*event_op4)(struct perf_session *session, union perf_event *event, u64 data); +typedef int (*event_op4)(struct perf_session *session, union perf_event *event, u64 data, + const char *str); typedef int (*event_oe)(struct perf_tool *tool, union perf_event *event, struct ordered_events *oe); diff --git a/tools/perf/util/top.h b/tools/perf/util/top.h index ff8391208ecd..1c2c0a838430 100644 --- a/tools/perf/util/top.h +++ b/tools/perf/util/top.h @@ -33,7 +33,10 @@ struct perf_top { int print_entries, count_filter, delay_secs; int max_stack; bool hide_kernel_symbols, hide_user_symbols, zero; - bool use_tui, use_stdio; +#ifdef HAVE_SLANG_SUPPORT + bool use_tui; +#endif + bool use_stdio; bool vmlinux_warned; bool dump_symtab; bool stitch_lbr; diff --git a/tools/perf/util/trace-event-parse.c b/tools/perf/util/trace-event-parse.c index 9634f0ae57be..c9c83a40647c 100644 --- a/tools/perf/util/trace-event-parse.c +++ b/tools/perf/util/trace-event-parse.c @@ -206,7 +206,7 @@ unsigned long long eval_flag(const char *flag) if (isdigit(flag[0])) return strtoull(flag, NULL, 0); - for (i = 0; i < (int)(sizeof(flags)/sizeof(flags[0])); i++) + for (i = 0; i < (int)(ARRAY_SIZE(flags)); i++) if (strcmp(flags[i].name, flag) == 0) return flags[i].value; diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c index fb4f6616b5fa..f8571a66d063 100644 --- a/tools/perf/util/util.c +++ b/tools/perf/util/util.c @@ -431,3 +431,34 @@ void perf_debuginfod_setup(struct perf_debuginfod *di) pr_debug("DEBUGINFOD_URLS=%s\n", getenv("DEBUGINFOD_URLS")); } + +/* + * Return a new filename prepended with task's root directory if it's in + * a chroot. Callers should free the returned string. + */ +char *filename_with_chroot(int pid, const char *filename) +{ + char buf[PATH_MAX]; + char proc_root[32]; + char *new_name = NULL; + int ret; + + scnprintf(proc_root, sizeof(proc_root), "/proc/%d/root", pid); + ret = readlink(proc_root, buf, sizeof(buf) - 1); + if (ret <= 0) + return NULL; + + /* readlink(2) does not append a null byte to buf */ + buf[ret] = '\0'; + + if (!strcmp(buf, "/")) + return NULL; + + if (strstr(buf, "(deleted)")) + return NULL; + + if (asprintf(&new_name, "%s/%s", buf, filename) < 0) + return NULL; + + return new_name; +} diff --git a/tools/perf/util/util.h b/tools/perf/util/util.h index 7b625cbd2dd8..0f78f1e7782d 100644 --- a/tools/perf/util/util.h +++ b/tools/perf/util/util.h @@ -77,4 +77,6 @@ struct perf_debuginfod { bool set; }; void perf_debuginfod_setup(struct perf_debuginfod *di); + +char *filename_with_chroot(int pid, const char *filename); #endif /* GIT_COMPAT_UTIL_H */ diff --git a/tools/testing/memblock/.gitignore b/tools/testing/memblock/.gitignore new file mode 100644 index 000000000000..654338e0be52 --- /dev/null +++ b/tools/testing/memblock/.gitignore @@ -0,0 +1,4 @@ +main +memblock.c +linux/memblock.h +asm/cmpxchg.h diff --git a/tools/testing/memblock/Makefile b/tools/testing/memblock/Makefile new file mode 100644 index 000000000000..a698e24b35e7 --- /dev/null +++ b/tools/testing/memblock/Makefile @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0 + +# Memblock simulator requires AddressSanitizer (libasan) and liburcu development +# packages installed +CFLAGS += -I. -I../../include -Wall -O2 -fsanitize=address \ + -fsanitize=undefined -D CONFIG_PHYS_ADDR_T_64BIT +LDFLAGS += -fsanitize=address -fsanitize=undefined +TARGETS = main +TEST_OFILES = tests/alloc_nid_api.o tests/alloc_helpers_api.o tests/alloc_api.o \ + tests/basic_api.o tests/common.o +DEP_OFILES = memblock.o lib/slab.o mmzone.o slab.o +OFILES = main.o $(DEP_OFILES) $(TEST_OFILES) +EXTR_SRC = ../../../mm/memblock.c + +ifeq ($(BUILD), 32) + CFLAGS += -m32 + LDFLAGS += -m32 +endif + +# Process user parameters +include scripts/Makefile.include + +main: $(OFILES) + +$(OFILES): include + +include: ../../../include/linux/memblock.h ../../include/linux/*.h \ + ../../include/asm/*.h + + @mkdir -p linux + test -L linux/memblock.h || ln -s ../../../../include/linux/memblock.h linux/memblock.h + test -L asm/cmpxchg.h || ln -s ../../../arch/x86/include/asm/cmpxchg.h asm/cmpxchg.h + +memblock.c: $(EXTR_SRC) + test -L memblock.c || ln -s $(EXTR_SRC) memblock.c + +clean: + $(RM) $(TARGETS) $(OFILES) linux/memblock.h memblock.c asm/cmpxchg.h + +help: + @echo 'Memblock simulator' + @echo '' + @echo 'Available targets:' + @echo ' main - Build the memblock simulator' + @echo ' clean - Remove generated files and symlinks in the directory' + @echo '' + @echo 'Configuration:' + @echo ' make NUMA=1 - simulate enabled NUMA' + @echo ' make MOVABLE_NODE=1 - override `movable_node_is_enabled`' + @echo ' definition to simulate movable NUMA nodes' + @echo ' make 32BIT_PHYS_ADDR_T=1 - Use 32 bit physical addresses' + +vpath %.c ../../lib + +.PHONY: clean include help diff --git a/tools/testing/memblock/README b/tools/testing/memblock/README new file mode 100644 index 000000000000..ca6afcff013a --- /dev/null +++ b/tools/testing/memblock/README @@ -0,0 +1,107 @@ +================== +Memblock simulator +================== + +Introduction +============ + +Memblock is a boot time memory allocator[1] that manages memory regions before +the actual memory management is initialized. Its APIs allow to register physical +memory regions, mark them as available or reserved, allocate a block of memory +within the requested range and/or in specific NUMA node, and many more. + +Because it is used so early in the booting process, testing and debugging it is +difficult. This test suite, usually referred as memblock simulator, is +an attempt at testing the memblock mechanism. It runs one monolithic test that +consist of a series of checks that exercise both the basic operations and +allocation functionalities of memblock. The main data structure of the boot time +memory allocator is initialized at the build time, so the checks here reuse its +instance throughout the duration of the test. To ensure that tests don't affect +each other, region arrays are reset in between. + +As this project uses the actual memblock code and has to run in user space, +some of the kernel definitions were stubbed by the initial commit that +introduced memblock simulator (commit 16802e55dea9 ("memblock tests: Add +skeleton of the memblock simulator")) and a few preparation commits just +before it. Most of them don't match the kernel implementation, so one should +consult them first before making any significant changes to the project. + +Usage +===== + +To run the tests, build the main target and run it: + +$ make && ./main + +A successful run produces no output. It is also possible to override different +configuration parameters. For example, to simulate enabled NUMA, use: + +$ make NUMA=1 + +For the full list of options, see `make help`. + +Project structure +================= + +The project has one target, main, which calls a group of checks for basic and +allocation functions. Tests for each group are defined in dedicated files, as it +can be seen here: + +memblock +|-- asm ------------------, +|-- lib |-- implement function and struct stubs +|-- linux ------------------' +|-- scripts +| |-- Makefile.include -- handles `make` parameters +|-- tests +| |-- alloc_api.(c|h) -- memblock_alloc tests +| |-- alloc_helpers_api.(c|h) -- memblock_alloc_from tests +| |-- alloc_nid_api.(c|h) -- memblock_alloc_try_nid tests +| |-- basic_api.(c|h) -- memblock_add/memblock_reserve/... tests +| |-- common.(c|h) -- helper functions for resetting memblock; +|-- main.c --------------. dummy physical memory definition +|-- Makefile `- test runner +|-- README +|-- TODO +|-- .gitignore + +Simulating physical memory +========================== + +Some allocation functions clear the memory in the process, so it is required for +memblock to track valid memory ranges. To achieve this, the test suite registers +with memblock memory stored by test_memory struct. It is a small wrapper that +points to a block of memory allocated via malloc. For each group of allocation +tests, dummy physical memory is allocated, added to memblock, and then released +at the end of the test run. The structure of a test runner checking allocation +functions is as follows: + +int memblock_alloc_foo_checks(void) +{ + reset_memblock_attributes(); /* data structure reset */ + dummy_physical_memory_init(); /* allocate and register memory */ + + (...allocation checks...) + + dummy_physical_memory_cleanup(); /* free the memory */ +} + +There's no need to explicitly free the dummy memory from memblock via +memblock_free() call. The entry will be erased by reset_memblock_regions(), +called at the beginning of each test. + +Known issues +============ + +1. Requesting a specific NUMA node via memblock_alloc_node() does not work as + intended. Once the fix is in place, tests for this function can be added. + +2. Tests for memblock_alloc_low() can't be easily implemented. The function uses + ARCH_LOW_ADDRESS_LIMIT marco, which can't be changed to point at the low + memory of the memory_block. + +References +========== + +1. Boot time memory management documentation page: + https://www.kernel.org/doc/html/latest/core-api/boot-time-mm.html diff --git a/tools/testing/memblock/TODO b/tools/testing/memblock/TODO new file mode 100644 index 000000000000..c25b2fdec45e --- /dev/null +++ b/tools/testing/memblock/TODO @@ -0,0 +1,28 @@ +TODO +===== + +1. Add verbose output (e.g., what is being tested and how many tests cases are + passing) + +2. Add flags to Makefile: + + verbosity level + + enable memblock_dbg() messages (i.e. pass "-D CONFIG_DEBUG_MEMORY_INIT" + flag) + +3. Add tests trying to memblock_add() or memblock_reserve() 129th region. + This will trigger memblock_double_array(), make sure it succeeds. + *Important:* These tests require valid memory ranges, use dummy physical + memory block from common.c to implement them. It is also very + likely that the current MEM_SIZE won't be enough for these + test cases. Use realloc to adjust the size accordingly. + +4. Add test cases using this functions (implement them for both directions): + + memblock_alloc_raw() + + memblock_alloc_exact_nid_raw() + + memblock_alloc_try_nid_raw() + +5. Add tests for memblock_alloc_node() to check if the correct NUMA node is set + for the new region + +6. Update comments in tests/basic_api.c to match the style used in + tests/alloc_*.c diff --git a/tools/testing/memblock/asm/dma.h b/tools/testing/memblock/asm/dma.h new file mode 100644 index 000000000000..13ff8e5d22ef --- /dev/null +++ b/tools/testing/memblock/asm/dma.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _TOOLS_DMA_H +#define _TOOLS_DMA_H + +#endif diff --git a/tools/testing/memblock/internal.h b/tools/testing/memblock/internal.h new file mode 100644 index 000000000000..94b52a8718b5 --- /dev/null +++ b/tools/testing/memblock/internal.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _MM_INTERNAL_H +#define _MM_INTERNAL_H + +struct page {}; + +void memblock_free_pages(struct page *page, unsigned long pfn, + unsigned int order) +{ +} + +#endif diff --git a/tools/testing/memblock/lib/slab.c b/tools/testing/memblock/lib/slab.c new file mode 100644 index 000000000000..6be6020328fb --- /dev/null +++ b/tools/testing/memblock/lib/slab.c @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +enum slab_state slab_state; + +bool slab_is_available(void) +{ + return slab_state >= UP; +} diff --git a/tools/testing/memblock/linux/init.h b/tools/testing/memblock/linux/init.h new file mode 100644 index 000000000000..828e0ee0bc6c --- /dev/null +++ b/tools/testing/memblock/linux/init.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_INIT_H +#define _LINUX_INIT_H + +#include +#include +#include + +#define __section(section) __attribute__((__section__(section))) + +#define __initconst +#define __meminit +#define __meminitdata +#define __refdata +#define __initdata + +struct obs_kernel_param { + const char *str; + int (*setup_func)(char *st); + int early; +}; + +#define __setup_param(str, unique_id, fn, early) \ + static const char __setup_str_##unique_id[] __initconst \ + __aligned(1) = str; \ + static struct obs_kernel_param __setup_##unique_id \ + __used __section(".init.setup") \ + __aligned(__alignof__(struct obs_kernel_param)) = \ + { __setup_str_##unique_id, fn, early } + +#define early_param(str, fn) \ + __setup_param(str, fn, fn, 1) + +#endif diff --git a/tools/testing/memblock/linux/kernel.h b/tools/testing/memblock/linux/kernel.h new file mode 100644 index 000000000000..d2f148bd8902 --- /dev/null +++ b/tools/testing/memblock/linux/kernel.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _MEMBLOCK_LINUX_KERNEL_H +#define _MEMBLOCK_LINUX_KERNEL_H + +#include <../../include/linux/kernel.h> +#include +#include +#include +#include +#include + +#endif diff --git a/tools/testing/memblock/linux/kmemleak.h b/tools/testing/memblock/linux/kmemleak.h new file mode 100644 index 000000000000..462f8c5e8aa0 --- /dev/null +++ b/tools/testing/memblock/linux/kmemleak.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _KMEMLEAK_H +#define _KMEMLEAK_H + +static inline void kmemleak_free_part_phys(phys_addr_t phys, size_t size) +{ +} + +static inline void kmemleak_alloc_phys(phys_addr_t phys, size_t size, + int min_count, gfp_t gfp) +{ +} + +static inline void dump_stack(void) +{ +} + +#endif diff --git a/tools/testing/memblock/linux/memory_hotplug.h b/tools/testing/memblock/linux/memory_hotplug.h new file mode 100644 index 000000000000..47988765a219 --- /dev/null +++ b/tools/testing/memblock/linux/memory_hotplug.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_MEMORY_HOTPLUG_H +#define _LINUX_MEMORY_HOTPLUG_H + +#include +#include +#include +#include + +static inline bool movable_node_is_enabled(void) +{ +#ifdef MOVABLE_NODE + return true; +#else + return false; +#endif +} + +#endif diff --git a/tools/testing/memblock/linux/mmzone.h b/tools/testing/memblock/linux/mmzone.h new file mode 100644 index 000000000000..7c2eb5c9bb54 --- /dev/null +++ b/tools/testing/memblock/linux/mmzone.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _TOOLS_MMZONE_H +#define _TOOLS_MMZONE_H + +#include + +struct pglist_data *first_online_pgdat(void); +struct pglist_data *next_online_pgdat(struct pglist_data *pgdat); + +#define for_each_online_pgdat(pgdat) \ + for (pgdat = first_online_pgdat(); \ + pgdat; \ + pgdat = next_online_pgdat(pgdat)) + +enum zone_type { + __MAX_NR_ZONES +}; + +#define MAX_NR_ZONES __MAX_NR_ZONES +#define MAX_ORDER 11 +#define MAX_ORDER_NR_PAGES (1 << (MAX_ORDER - 1)) + +#define pageblock_order (MAX_ORDER - 1) +#define pageblock_nr_pages BIT(pageblock_order) + +struct zone { + atomic_long_t managed_pages; +}; + +typedef struct pglist_data { + struct zone node_zones[MAX_NR_ZONES]; + +} pg_data_t; + +#endif diff --git a/tools/testing/memblock/linux/printk.h b/tools/testing/memblock/linux/printk.h new file mode 100644 index 000000000000..61af424d8c6c --- /dev/null +++ b/tools/testing/memblock/linux/printk.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _PRINTK_H +#define _PRINTK_H + +#include +#include + +/* + * memblock_dbg is called with u64 arguments that don't match the "%llu" + * specifier in printf. This results in warnings that cannot be fixed without + * modifying memblock.c, which we wish to avoid. As these messaged are not used + * in testing anyway, the mismatch can be ignored. + */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wformat" +#define printk printf +#pragma GCC diagnostic push + +#define pr_info printk +#define pr_debug printk +#define pr_cont printk +#define pr_err printk +#define pr_warn printk + +#endif diff --git a/tools/testing/memblock/main.c b/tools/testing/memblock/main.c new file mode 100644 index 000000000000..fb183c9e76d1 --- /dev/null +++ b/tools/testing/memblock/main.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include "tests/basic_api.h" +#include "tests/alloc_api.h" +#include "tests/alloc_helpers_api.h" +#include "tests/alloc_nid_api.h" + +int main(int argc, char **argv) +{ + memblock_basic_checks(); + memblock_alloc_checks(); + memblock_alloc_helpers_checks(); + memblock_alloc_nid_checks(); + + return 0; +} diff --git a/tools/testing/memblock/mmzone.c b/tools/testing/memblock/mmzone.c new file mode 100644 index 000000000000..7b0909e8b759 --- /dev/null +++ b/tools/testing/memblock/mmzone.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include + +struct pglist_data *first_online_pgdat(void) +{ + return NULL; +} + +struct pglist_data *next_online_pgdat(struct pglist_data *pgdat) +{ + return NULL; +} + +void reserve_bootmem_region(phys_addr_t start, phys_addr_t end) +{ +} + +void atomic_long_set(atomic_long_t *v, long i) +{ +} diff --git a/tools/testing/memblock/scripts/Makefile.include b/tools/testing/memblock/scripts/Makefile.include new file mode 100644 index 000000000000..641569ccb7b0 --- /dev/null +++ b/tools/testing/memblock/scripts/Makefile.include @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 +# Definitions for user-provided arguments + +# Simulate CONFIG_NUMA=y +ifeq ($(NUMA), 1) + CFLAGS += -D CONFIG_NUMA +endif + +# Simulate movable NUMA memory regions +ifeq ($(MOVABLE_NODE), 1) + CFLAGS += -D MOVABLE_NODE +endif + +# Use 32 bit physical addresses. +# Remember to install 32-bit version of dependencies. +ifeq ($(32BIT_PHYS_ADDR_T), 1) + CFLAGS += -m32 -U CONFIG_PHYS_ADDR_T_64BIT + LDFLAGS += -m32 +endif diff --git a/tools/testing/memblock/tests/alloc_api.c b/tools/testing/memblock/tests/alloc_api.c new file mode 100644 index 000000000000..d1aa7e15c18d --- /dev/null +++ b/tools/testing/memblock/tests/alloc_api.c @@ -0,0 +1,750 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include "alloc_api.h" + +/* + * A simple test that tries to allocate a small memory region. + * Expect to allocate an aligned region near the end of the available memory. + */ +static int alloc_top_down_simple_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + phys_addr_t size = SZ_2; + phys_addr_t expected_start; + + setup_memblock(); + + expected_start = memblock_end_of_DRAM() - SMP_CACHE_BYTES; + + allocated_ptr = memblock_alloc(size, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == size); + assert(rgn->base == expected_start); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate memory next to a reserved region that starts at + * the misaligned address. Expect to create two separate entries, with the new + * entry aligned to the provided alignment: + * + * + + * | +--------+ +--------| + * | | rgn2 | | rgn1 | + * +------------+--------+---------+--------+ + * ^ + * | + * Aligned address boundary + * + * The allocation direction is top-down and region arrays are sorted from lower + * to higher addresses, so the new region will be the first entry in + * memory.reserved array. The previously reserved region does not get modified. + * Region counter and total size get updated. + */ +static int alloc_top_down_disjoint_check(void) +{ + /* After allocation, this will point to the "old" region */ + struct memblock_region *rgn1 = &memblock.reserved.regions[1]; + struct memblock_region *rgn2 = &memblock.reserved.regions[0]; + struct region r1; + void *allocated_ptr = NULL; + + phys_addr_t r2_size = SZ_16; + /* Use custom alignment */ + phys_addr_t alignment = SMP_CACHE_BYTES * 2; + phys_addr_t total_size; + phys_addr_t expected_start; + + setup_memblock(); + + r1.base = memblock_end_of_DRAM() - SZ_2; + r1.size = SZ_2; + + total_size = r1.size + r2_size; + expected_start = memblock_end_of_DRAM() - alignment; + + memblock_reserve(r1.base, r1.size); + + allocated_ptr = memblock_alloc(r2_size, alignment); + + assert(allocated_ptr); + assert(rgn1->size == r1.size); + assert(rgn1->base == r1.base); + + assert(rgn2->size == r2_size); + assert(rgn2->base == expected_start); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory when there is enough space at the end + * of the previously reserved block (i.e. first fit): + * + * | +--------+--------------| + * | | r1 | r2 | + * +--------------+--------+--------------+ + * + * Expect a merge of both regions. Only the region size gets updated. + */ +static int alloc_top_down_before_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + /* + * The first region ends at the aligned address to test region merging + */ + phys_addr_t r1_size = SMP_CACHE_BYTES; + phys_addr_t r2_size = SZ_512; + phys_addr_t total_size = r1_size + r2_size; + + setup_memblock(); + + memblock_reserve(memblock_end_of_DRAM() - total_size, r1_size); + + allocated_ptr = memblock_alloc(r2_size, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == total_size); + assert(rgn->base == memblock_end_of_DRAM() - total_size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory when there is not enough space at the + * end of the previously reserved block (i.e. second fit): + * + * | +-----------+------+ | + * | | r2 | r1 | | + * +------------+-----------+------+-----+ + * + * Expect a merge of both regions. Both the base address and size of the region + * get updated. + */ +static int alloc_top_down_after_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + struct region r1; + void *allocated_ptr = NULL; + + phys_addr_t r2_size = SZ_512; + phys_addr_t total_size; + + setup_memblock(); + + /* + * The first region starts at the aligned address to test region merging + */ + r1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES; + r1.size = SZ_8; + + total_size = r1.size + r2_size; + + memblock_reserve(r1.base, r1.size); + + allocated_ptr = memblock_alloc(r2_size, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == total_size); + assert(rgn->base == r1.base - r2_size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory when there are two reserved regions with + * a gap too small to fit the new region: + * + * | +--------+----------+ +------| + * | | r3 | r2 | | r1 | + * +-------+--------+----------+---+------+ + * + * Expect to allocate a region before the one that starts at the lower address, + * and merge them into one. The region counter and total size fields get + * updated. + */ +static int alloc_top_down_second_fit_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + struct region r1, r2; + void *allocated_ptr = NULL; + + phys_addr_t r3_size = SZ_1K; + phys_addr_t total_size; + + setup_memblock(); + + r1.base = memblock_end_of_DRAM() - SZ_512; + r1.size = SZ_512; + + r2.base = r1.base - SZ_512; + r2.size = SZ_256; + + total_size = r1.size + r2.size + r3_size; + + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + allocated_ptr = memblock_alloc(r3_size, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == r2.size + r3_size); + assert(rgn->base == r2.base - r3_size); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory when there are two reserved regions with + * a gap big enough to accommodate the new region: + * + * | +--------+--------+--------+ | + * | | r2 | r3 | r1 | | + * +-----+--------+--------+--------+-----+ + * + * Expect to merge all of them, creating one big entry in memblock.reserved + * array. The region counter and total size fields get updated. + */ +static int alloc_in_between_generic_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + struct region r1, r2; + void *allocated_ptr = NULL; + + phys_addr_t gap_size = SMP_CACHE_BYTES; + phys_addr_t r3_size = SZ_64; + /* + * Calculate regions size so there's just enough space for the new entry + */ + phys_addr_t rgn_size = (MEM_SIZE - (2 * gap_size + r3_size)) / 2; + phys_addr_t total_size; + + setup_memblock(); + + r1.size = rgn_size; + r1.base = memblock_end_of_DRAM() - (gap_size + rgn_size); + + r2.size = rgn_size; + r2.base = memblock_start_of_DRAM() + gap_size; + + total_size = r1.size + r2.size + r3_size; + + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + allocated_ptr = memblock_alloc(r3_size, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == total_size); + assert(rgn->base == r1.base - r2.size - r3_size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory when the memory is filled with reserved + * regions with memory gaps too small to fit the new region: + * + * +-------+ + * | new | + * +--+----+ + * | +-----+ +-----+ +-----+ | + * | | res | | res | | res | | + * +----+-----+----+-----+----+-----+----+ + * + * Expect no allocation to happen. + */ +static int alloc_small_gaps_generic_check(void) +{ + void *allocated_ptr = NULL; + + phys_addr_t region_size = SZ_1K; + phys_addr_t gap_size = SZ_256; + phys_addr_t region_end; + + setup_memblock(); + + region_end = memblock_start_of_DRAM(); + + while (region_end < memblock_end_of_DRAM()) { + memblock_reserve(region_end + gap_size, region_size); + region_end += gap_size + region_size; + } + + allocated_ptr = memblock_alloc(region_size, SMP_CACHE_BYTES); + + assert(!allocated_ptr); + + return 0; +} + +/* + * A test that tries to allocate memory when all memory is reserved. + * Expect no allocation to happen. + */ +static int alloc_all_reserved_generic_check(void) +{ + void *allocated_ptr = NULL; + + setup_memblock(); + + /* Simulate full memory */ + memblock_reserve(memblock_start_of_DRAM(), MEM_SIZE); + + allocated_ptr = memblock_alloc(SZ_256, SMP_CACHE_BYTES); + + assert(!allocated_ptr); + + return 0; +} + +/* + * A test that tries to allocate memory when the memory is almost full, + * with not enough space left for the new region: + * + * +-------+ + * | new | + * +-------+ + * |-----------------------------+ | + * | reserved | | + * +-----------------------------+---+ + * + * Expect no allocation to happen. + */ +static int alloc_no_space_generic_check(void) +{ + void *allocated_ptr = NULL; + + setup_memblock(); + + phys_addr_t available_size = SZ_256; + phys_addr_t reserved_size = MEM_SIZE - available_size; + + /* Simulate almost-full memory */ + memblock_reserve(memblock_start_of_DRAM(), reserved_size); + + allocated_ptr = memblock_alloc(SZ_1K, SMP_CACHE_BYTES); + + assert(!allocated_ptr); + + return 0; +} + +/* + * A test that tries to allocate memory when the memory is almost full, + * but there is just enough space left: + * + * |---------------------------+---------| + * | reserved | new | + * +---------------------------+---------+ + * + * Expect to allocate memory and merge all the regions. The total size field + * gets updated. + */ +static int alloc_limited_space_generic_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + phys_addr_t available_size = SZ_256; + phys_addr_t reserved_size = MEM_SIZE - available_size; + + setup_memblock(); + + /* Simulate almost-full memory */ + memblock_reserve(memblock_start_of_DRAM(), reserved_size); + + allocated_ptr = memblock_alloc(available_size, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == MEM_SIZE); + assert(rgn->base == memblock_start_of_DRAM()); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == MEM_SIZE); + + return 0; +} + +/* + * A test that tries to allocate memory when there is no available memory + * registered (i.e. memblock.memory has only a dummy entry). + * Expect no allocation to happen. + */ +static int alloc_no_memory_generic_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + reset_memblock_regions(); + + allocated_ptr = memblock_alloc(SZ_1K, SMP_CACHE_BYTES); + + assert(!allocated_ptr); + assert(rgn->size == 0); + assert(rgn->base == 0); + assert(memblock.reserved.total_size == 0); + + return 0; +} + +/* + * A simple test that tries to allocate a small memory region. + * Expect to allocate an aligned region at the beginning of the available + * memory. + */ +static int alloc_bottom_up_simple_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + setup_memblock(); + + allocated_ptr = memblock_alloc(SZ_2, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == SZ_2); + assert(rgn->base == memblock_start_of_DRAM()); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == SZ_2); + + return 0; +} + +/* + * A test that tries to allocate memory next to a reserved region that starts at + * the misaligned address. Expect to create two separate entries, with the new + * entry aligned to the provided alignment: + * + * + + * | +----------+ +----------+ | + * | | rgn1 | | rgn2 | | + * +----+----------+---+----------+-----+ + * ^ + * | + * Aligned address boundary + * + * The allocation direction is bottom-up, so the new region will be the second + * entry in memory.reserved array. The previously reserved region does not get + * modified. Region counter and total size get updated. + */ +static int alloc_bottom_up_disjoint_check(void) +{ + struct memblock_region *rgn1 = &memblock.reserved.regions[0]; + struct memblock_region *rgn2 = &memblock.reserved.regions[1]; + struct region r1; + void *allocated_ptr = NULL; + + phys_addr_t r2_size = SZ_16; + /* Use custom alignment */ + phys_addr_t alignment = SMP_CACHE_BYTES * 2; + phys_addr_t total_size; + phys_addr_t expected_start; + + setup_memblock(); + + r1.base = memblock_start_of_DRAM() + SZ_2; + r1.size = SZ_2; + + total_size = r1.size + r2_size; + expected_start = memblock_start_of_DRAM() + alignment; + + memblock_reserve(r1.base, r1.size); + + allocated_ptr = memblock_alloc(r2_size, alignment); + + assert(allocated_ptr); + + assert(rgn1->size == r1.size); + assert(rgn1->base == r1.base); + + assert(rgn2->size == r2_size); + assert(rgn2->base == expected_start); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory when there is enough space at + * the beginning of the previously reserved block (i.e. first fit): + * + * |------------------+--------+ | + * | r1 | r2 | | + * +------------------+--------+---------+ + * + * Expect a merge of both regions. Only the region size gets updated. + */ +static int alloc_bottom_up_before_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + phys_addr_t r1_size = SZ_512; + phys_addr_t r2_size = SZ_128; + phys_addr_t total_size = r1_size + r2_size; + + setup_memblock(); + + memblock_reserve(memblock_start_of_DRAM() + r1_size, r2_size); + + allocated_ptr = memblock_alloc(r1_size, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == total_size); + assert(rgn->base == memblock_start_of_DRAM()); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory when there is not enough space at + * the beginning of the previously reserved block (i.e. second fit): + * + * | +--------+--------------+ | + * | | r1 | r2 | | + * +----+--------+--------------+---------+ + * + * Expect a merge of both regions. Only the region size gets updated. + */ +static int alloc_bottom_up_after_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + struct region r1; + void *allocated_ptr = NULL; + + phys_addr_t r2_size = SZ_512; + phys_addr_t total_size; + + setup_memblock(); + + /* + * The first region starts at the aligned address to test region merging + */ + r1.base = memblock_start_of_DRAM() + SMP_CACHE_BYTES; + r1.size = SZ_64; + + total_size = r1.size + r2_size; + + memblock_reserve(r1.base, r1.size); + + allocated_ptr = memblock_alloc(r2_size, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == total_size); + assert(rgn->base == r1.base); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory when there are two reserved regions, the + * first one starting at the beginning of the available memory, with a gap too + * small to fit the new region: + * + * |------------+ +--------+--------+ | + * | r1 | | r2 | r3 | | + * +------------+-----+--------+--------+--+ + * + * Expect to allocate after the second region, which starts at the higher + * address, and merge them into one. The region counter and total size fields + * get updated. + */ +static int alloc_bottom_up_second_fit_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[1]; + struct region r1, r2; + void *allocated_ptr = NULL; + + phys_addr_t r3_size = SZ_1K; + phys_addr_t total_size; + + setup_memblock(); + + r1.base = memblock_start_of_DRAM(); + r1.size = SZ_512; + + r2.base = r1.base + r1.size + SZ_512; + r2.size = SZ_256; + + total_size = r1.size + r2.size + r3_size; + + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + allocated_ptr = memblock_alloc(r3_size, SMP_CACHE_BYTES); + + assert(allocated_ptr); + assert(rgn->size == r2.size + r3_size); + assert(rgn->base == r2.base); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* Test case wrappers */ +static int alloc_simple_check(void) +{ + memblock_set_bottom_up(false); + alloc_top_down_simple_check(); + memblock_set_bottom_up(true); + alloc_bottom_up_simple_check(); + + return 0; +} + +static int alloc_disjoint_check(void) +{ + memblock_set_bottom_up(false); + alloc_top_down_disjoint_check(); + memblock_set_bottom_up(true); + alloc_bottom_up_disjoint_check(); + + return 0; +} + +static int alloc_before_check(void) +{ + memblock_set_bottom_up(false); + alloc_top_down_before_check(); + memblock_set_bottom_up(true); + alloc_bottom_up_before_check(); + + return 0; +} + +static int alloc_after_check(void) +{ + memblock_set_bottom_up(false); + alloc_top_down_after_check(); + memblock_set_bottom_up(true); + alloc_bottom_up_after_check(); + + return 0; +} + +static int alloc_in_between_check(void) +{ + memblock_set_bottom_up(false); + alloc_in_between_generic_check(); + memblock_set_bottom_up(true); + alloc_in_between_generic_check(); + + return 0; +} + +static int alloc_second_fit_check(void) +{ + memblock_set_bottom_up(false); + alloc_top_down_second_fit_check(); + memblock_set_bottom_up(true); + alloc_bottom_up_second_fit_check(); + + return 0; +} + +static int alloc_small_gaps_check(void) +{ + memblock_set_bottom_up(false); + alloc_small_gaps_generic_check(); + memblock_set_bottom_up(true); + alloc_small_gaps_generic_check(); + + return 0; +} + +static int alloc_all_reserved_check(void) +{ + memblock_set_bottom_up(false); + alloc_all_reserved_generic_check(); + memblock_set_bottom_up(true); + alloc_all_reserved_generic_check(); + + return 0; +} + +static int alloc_no_space_check(void) +{ + memblock_set_bottom_up(false); + alloc_no_space_generic_check(); + memblock_set_bottom_up(true); + alloc_no_space_generic_check(); + + return 0; +} + +static int alloc_limited_space_check(void) +{ + memblock_set_bottom_up(false); + alloc_limited_space_generic_check(); + memblock_set_bottom_up(true); + alloc_limited_space_generic_check(); + + return 0; +} + +static int alloc_no_memory_check(void) +{ + memblock_set_bottom_up(false); + alloc_no_memory_generic_check(); + memblock_set_bottom_up(true); + alloc_no_memory_generic_check(); + + return 0; +} + +int memblock_alloc_checks(void) +{ + reset_memblock_attributes(); + dummy_physical_memory_init(); + + alloc_simple_check(); + alloc_disjoint_check(); + alloc_before_check(); + alloc_after_check(); + alloc_second_fit_check(); + alloc_small_gaps_check(); + alloc_in_between_check(); + alloc_all_reserved_check(); + alloc_no_space_check(); + alloc_limited_space_check(); + alloc_no_memory_check(); + + dummy_physical_memory_cleanup(); + + return 0; +} diff --git a/tools/testing/memblock/tests/alloc_api.h b/tools/testing/memblock/tests/alloc_api.h new file mode 100644 index 000000000000..585b085baf21 --- /dev/null +++ b/tools/testing/memblock/tests/alloc_api.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _MEMBLOCK_ALLOCS_H +#define _MEMBLOCK_ALLOCS_H + +#include "common.h" + +int memblock_alloc_checks(void); + +#endif diff --git a/tools/testing/memblock/tests/alloc_helpers_api.c b/tools/testing/memblock/tests/alloc_helpers_api.c new file mode 100644 index 000000000000..963a966db461 --- /dev/null +++ b/tools/testing/memblock/tests/alloc_helpers_api.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include "alloc_helpers_api.h" + +/* + * A simple test that tries to allocate a memory region above a specified, + * aligned address: + * + * + + * | +-----------+ | + * | | rgn | | + * +----------+-----------+---------+ + * ^ + * | + * Aligned min_addr + * + * Expect to allocate a cleared region at the minimal memory address. + */ +static int alloc_from_simple_generic_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_16; + phys_addr_t min_addr; + + setup_memblock(); + + min_addr = memblock_end_of_DRAM() - SMP_CACHE_BYTES; + + allocated_ptr = memblock_alloc_from(size, SMP_CACHE_BYTES, min_addr); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == min_addr); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate a memory region above a certain address. + * The minimal address here is not aligned: + * + * + + + * | + +---------+ | + * | | | rgn | | + * +------+------+---------+------------+ + * ^ ^------. + * | | + * min_addr Aligned address + * boundary + * + * Expect to allocate a cleared region at the closest aligned memory address. + */ +static int alloc_from_misaligned_generic_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_32; + phys_addr_t min_addr; + + setup_memblock(); + + /* A misaligned address */ + min_addr = memblock_end_of_DRAM() - (SMP_CACHE_BYTES * 2 - 1); + + allocated_ptr = memblock_alloc_from(size, SMP_CACHE_BYTES, min_addr); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == memblock_end_of_DRAM() - SMP_CACHE_BYTES); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate a memory region above an address that is too + * close to the end of the memory: + * + * + + + * | +--------+---+ | + * | | rgn + | | + * +-----------+--------+---+------+ + * ^ ^ + * | | + * | min_addr + * | + * Aligned address + * boundary + * + * Expect to prioritize granting memory over satisfying the minimal address + * requirement. + */ +static int alloc_from_top_down_high_addr_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + phys_addr_t size = SZ_32; + phys_addr_t min_addr; + + setup_memblock(); + + /* The address is too close to the end of the memory */ + min_addr = memblock_end_of_DRAM() - SZ_16; + + allocated_ptr = memblock_alloc_from(size, SMP_CACHE_BYTES, min_addr); + + assert(allocated_ptr); + assert(rgn->size == size); + assert(rgn->base == memblock_end_of_DRAM() - SMP_CACHE_BYTES); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate a memory region when there is no space + * available above the minimal address above a certain address: + * + * + + * | +---------+-------------| + * | | rgn | | + * +--------+---------+-------------+ + * ^ + * | + * min_addr + * + * Expect to prioritize granting memory over satisfying the minimal address + * requirement and to allocate next to the previously reserved region. The + * regions get merged into one. + */ +static int alloc_from_top_down_no_space_above_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + phys_addr_t r1_size = SZ_64; + phys_addr_t r2_size = SZ_2; + phys_addr_t total_size = r1_size + r2_size; + phys_addr_t min_addr; + + setup_memblock(); + + min_addr = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2; + + /* No space above this address */ + memblock_reserve(min_addr, r2_size); + + allocated_ptr = memblock_alloc_from(r1_size, SMP_CACHE_BYTES, min_addr); + + assert(allocated_ptr); + assert(rgn->base == min_addr - r1_size); + assert(rgn->size == total_size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate a memory region with a minimal address below + * the start address of the available memory. As the allocation is top-down, + * first reserve a region that will force allocation near the start. + * Expect successful allocation and merge of both regions. + */ +static int alloc_from_top_down_min_addr_cap_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + phys_addr_t r1_size = SZ_64; + phys_addr_t min_addr; + phys_addr_t start_addr; + + setup_memblock(); + + start_addr = (phys_addr_t)memblock_start_of_DRAM(); + min_addr = start_addr - SMP_CACHE_BYTES * 3; + + memblock_reserve(start_addr + r1_size, MEM_SIZE - r1_size); + + allocated_ptr = memblock_alloc_from(r1_size, SMP_CACHE_BYTES, min_addr); + + assert(allocated_ptr); + assert(rgn->base == start_addr); + assert(rgn->size == MEM_SIZE); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == MEM_SIZE); + + return 0; +} + +/* + * A test that tries to allocate a memory region above an address that is too + * close to the end of the memory: + * + * + + * |-----------+ + | + * | rgn | | | + * +-----------+--------------+-----+ + * ^ ^ + * | | + * Aligned address min_addr + * boundary + * + * Expect to prioritize granting memory over satisfying the minimal address + * requirement. Allocation happens at beginning of the available memory. + */ +static int alloc_from_bottom_up_high_addr_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + phys_addr_t size = SZ_32; + phys_addr_t min_addr; + + setup_memblock(); + + /* The address is too close to the end of the memory */ + min_addr = memblock_end_of_DRAM() - SZ_8; + + allocated_ptr = memblock_alloc_from(size, SMP_CACHE_BYTES, min_addr); + + assert(allocated_ptr); + assert(rgn->size == size); + assert(rgn->base == memblock_start_of_DRAM()); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate a memory region when there is no space + * available above the minimal address above a certain address: + * + * + + * |-----------+ +-------------------| + * | rgn | | | + * +-----------+----+-------------------+ + * ^ + * | + * min_addr + * + * Expect to prioritize granting memory over satisfying the minimal address + * requirement and to allocate at the beginning of the available memory. + */ +static int alloc_from_bottom_up_no_space_above_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + phys_addr_t r1_size = SZ_64; + phys_addr_t min_addr; + phys_addr_t r2_size; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() + SZ_128; + r2_size = memblock_end_of_DRAM() - min_addr; + + /* No space above this address */ + memblock_reserve(min_addr - SMP_CACHE_BYTES, r2_size); + + allocated_ptr = memblock_alloc_from(r1_size, SMP_CACHE_BYTES, min_addr); + + assert(allocated_ptr); + assert(rgn->base == memblock_start_of_DRAM()); + assert(rgn->size == r1_size); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == r1_size + r2_size); + + return 0; +} + +/* + * A test that tries to allocate a memory region with a minimal address below + * the start address of the available memory. Expect to allocate a region + * at the beginning of the available memory. + */ +static int alloc_from_bottom_up_min_addr_cap_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + + phys_addr_t r1_size = SZ_64; + phys_addr_t min_addr; + phys_addr_t start_addr; + + setup_memblock(); + + start_addr = (phys_addr_t)memblock_start_of_DRAM(); + min_addr = start_addr - SMP_CACHE_BYTES * 3; + + allocated_ptr = memblock_alloc_from(r1_size, SMP_CACHE_BYTES, min_addr); + + assert(allocated_ptr); + assert(rgn->base == start_addr); + assert(rgn->size == r1_size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == r1_size); + + return 0; +} + +/* Test case wrappers */ +static int alloc_from_simple_check(void) +{ + memblock_set_bottom_up(false); + alloc_from_simple_generic_check(); + memblock_set_bottom_up(true); + alloc_from_simple_generic_check(); + + return 0; +} + +static int alloc_from_misaligned_check(void) +{ + memblock_set_bottom_up(false); + alloc_from_misaligned_generic_check(); + memblock_set_bottom_up(true); + alloc_from_misaligned_generic_check(); + + return 0; +} + +static int alloc_from_high_addr_check(void) +{ + memblock_set_bottom_up(false); + alloc_from_top_down_high_addr_check(); + memblock_set_bottom_up(true); + alloc_from_bottom_up_high_addr_check(); + + return 0; +} + +static int alloc_from_no_space_above_check(void) +{ + memblock_set_bottom_up(false); + alloc_from_top_down_no_space_above_check(); + memblock_set_bottom_up(true); + alloc_from_bottom_up_no_space_above_check(); + + return 0; +} + +static int alloc_from_min_addr_cap_check(void) +{ + memblock_set_bottom_up(false); + alloc_from_top_down_min_addr_cap_check(); + memblock_set_bottom_up(true); + alloc_from_bottom_up_min_addr_cap_check(); + + return 0; +} + +int memblock_alloc_helpers_checks(void) +{ + reset_memblock_attributes(); + dummy_physical_memory_init(); + + alloc_from_simple_check(); + alloc_from_misaligned_check(); + alloc_from_high_addr_check(); + alloc_from_no_space_above_check(); + alloc_from_min_addr_cap_check(); + + dummy_physical_memory_cleanup(); + + return 0; +} diff --git a/tools/testing/memblock/tests/alloc_helpers_api.h b/tools/testing/memblock/tests/alloc_helpers_api.h new file mode 100644 index 000000000000..c9e4827b1623 --- /dev/null +++ b/tools/testing/memblock/tests/alloc_helpers_api.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _MEMBLOCK_ALLOC_HELPERS_H +#define _MEMBLOCK_ALLOC_HELPERS_H + +#include "common.h" + +int memblock_alloc_helpers_checks(void); + +#endif diff --git a/tools/testing/memblock/tests/alloc_nid_api.c b/tools/testing/memblock/tests/alloc_nid_api.c new file mode 100644 index 000000000000..6390206e50e1 --- /dev/null +++ b/tools/testing/memblock/tests/alloc_nid_api.c @@ -0,0 +1,1174 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include "alloc_nid_api.h" + +/* + * A simple test that tries to allocate a memory region within min_addr and + * max_addr range: + * + * + + + * | + +-----------+ | + * | | | rgn | | + * +----+-------+-----------+------+ + * ^ ^ + * | | + * min_addr max_addr + * + * Expect to allocate a cleared region that ends at max_addr. + */ +static int alloc_try_nid_top_down_simple_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_128; + phys_addr_t min_addr; + phys_addr_t max_addr; + phys_addr_t rgn_end; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() + SMP_CACHE_BYTES * 2; + max_addr = min_addr + SZ_512; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + rgn_end = rgn->base + rgn->size; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == max_addr - size); + assert(rgn_end == max_addr); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A simple test that tries to allocate a memory region within min_addr and + * max_addr range, where the end address is misaligned: + * + * + + + + * | + +---------+ + | + * | | | rgn | | | + * +------+-------+---------+--+----+ + * ^ ^ ^ + * | | | + * min_add | max_addr + * | + * Aligned address + * boundary + * + * Expect to allocate a cleared, aligned region that ends before max_addr. + */ +static int alloc_try_nid_top_down_end_misaligned_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_128; + phys_addr_t misalign = SZ_2; + phys_addr_t min_addr; + phys_addr_t max_addr; + phys_addr_t rgn_end; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() + SMP_CACHE_BYTES * 2; + max_addr = min_addr + SZ_512 + misalign; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + rgn_end = rgn->base + rgn->size; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == max_addr - size - misalign); + assert(rgn_end < max_addr); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A simple test that tries to allocate a memory region, which spans over the + * min_addr and max_addr range: + * + * + + + * | +---------------+ | + * | | rgn | | + * +------+---------------+-------+ + * ^ ^ + * | | + * min_addr max_addr + * + * Expect to allocate a cleared region that starts at min_addr and ends at + * max_addr, given that min_addr is aligned. + */ +static int alloc_try_nid_exact_address_generic_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_1K; + phys_addr_t min_addr; + phys_addr_t max_addr; + phys_addr_t rgn_end; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() + SMP_CACHE_BYTES; + max_addr = min_addr + size; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + rgn_end = rgn->base + rgn->size; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == min_addr); + assert(rgn_end == max_addr); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate a memory region, which can't fit into + * min_addr and max_addr range: + * + * + + + + * | +----------+-----+ | + * | | rgn + | | + * +--------+----------+-----+----+ + * ^ ^ ^ + * | | | + * Aligned | max_addr + * address | + * boundary min_add + * + * Expect to drop the lower limit and allocate a cleared memory region which + * ends at max_addr (if the address is aligned). + */ +static int alloc_try_nid_top_down_narrow_range_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_256; + phys_addr_t min_addr; + phys_addr_t max_addr; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() + SZ_512; + max_addr = min_addr + SMP_CACHE_BYTES; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == max_addr - size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate a memory region, which can't fit into + * min_addr and max_addr range, with the latter being too close to the beginning + * of the available memory: + * + * +-------------+ + * | new | + * +-------------+ + * + + + * | + | + * | | | + * +-------+--------------+ + * ^ ^ + * | | + * | max_addr + * | + * min_addr + * + * Expect no allocation to happen. + */ +static int alloc_try_nid_low_max_generic_check(void) +{ + void *allocated_ptr = NULL; + + phys_addr_t size = SZ_1K; + phys_addr_t min_addr; + phys_addr_t max_addr; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM(); + max_addr = min_addr + SMP_CACHE_BYTES; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + + assert(!allocated_ptr); + + return 0; +} + +/* + * A test that tries to allocate a memory region within min_addr min_addr range, + * with min_addr being so close that it's next to an allocated region: + * + * + + + * | +--------+---------------| + * | | r1 | rgn | + * +-------+--------+---------------+ + * ^ ^ + * | | + * min_addr max_addr + * + * Expect a merge of both regions. Only the region size gets updated. + */ +static int alloc_try_nid_min_reserved_generic_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t r1_size = SZ_128; + phys_addr_t r2_size = SZ_64; + phys_addr_t total_size = r1_size + r2_size; + phys_addr_t min_addr; + phys_addr_t max_addr; + phys_addr_t reserved_base; + + setup_memblock(); + + max_addr = memblock_end_of_DRAM(); + min_addr = max_addr - r2_size; + reserved_base = min_addr - r1_size; + + memblock_reserve(reserved_base, r1_size); + + allocated_ptr = memblock_alloc_try_nid(r2_size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == total_size); + assert(rgn->base == reserved_base); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate a memory region within min_addr and max_addr, + * with max_addr being so close that it's next to an allocated region: + * + * + + + * | +-------------+--------| + * | | rgn | r1 | + * +----------+-------------+--------+ + * ^ ^ + * | | + * min_addr max_addr + * + * Expect a merge of regions. Only the region size gets updated. + */ +static int alloc_try_nid_max_reserved_generic_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t r1_size = SZ_64; + phys_addr_t r2_size = SZ_128; + phys_addr_t total_size = r1_size + r2_size; + phys_addr_t min_addr; + phys_addr_t max_addr; + + setup_memblock(); + + max_addr = memblock_end_of_DRAM() - r1_size; + min_addr = max_addr - r2_size; + + memblock_reserve(max_addr, r1_size); + + allocated_ptr = memblock_alloc_try_nid(r2_size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == total_size); + assert(rgn->base == min_addr); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory within min_addr and max_add range, when + * there are two reserved regions at the borders, with a gap big enough to fit + * a new region: + * + * + + + * | +--------+ +-------+------+ | + * | | r2 | | rgn | r1 | | + * +----+--------+---+-------+------+--+ + * ^ ^ + * | | + * min_addr max_addr + * + * Expect to merge the new region with r1. The second region does not get + * updated. The total size field gets updated. + */ + +static int alloc_try_nid_top_down_reserved_with_space_check(void) +{ + struct memblock_region *rgn1 = &memblock.reserved.regions[1]; + struct memblock_region *rgn2 = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + struct region r1, r2; + + phys_addr_t r3_size = SZ_64; + phys_addr_t gap_size = SMP_CACHE_BYTES; + phys_addr_t total_size; + phys_addr_t max_addr; + phys_addr_t min_addr; + + setup_memblock(); + + r1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2; + r1.size = SMP_CACHE_BYTES; + + r2.size = SZ_128; + r2.base = r1.base - (r3_size + gap_size + r2.size); + + total_size = r1.size + r2.size + r3_size; + min_addr = r2.base + r2.size; + max_addr = r1.base; + + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + allocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn1->size == r1.size + r3_size); + assert(rgn1->base == max_addr - r3_size); + + assert(rgn2->size == r2.size); + assert(rgn2->base == r2.base); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory within min_addr and max_add range, when + * there are two reserved regions at the borders, with a gap of a size equal to + * the size of the new region: + * + * + + + * | +--------+--------+--------+ | + * | | r2 | r3 | r1 | | + * +-----+--------+--------+--------+-----+ + * ^ ^ + * | | + * min_addr max_addr + * + * Expect to merge all of the regions into one. The region counter and total + * size fields get updated. + */ +static int alloc_try_nid_reserved_full_merge_generic_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + struct region r1, r2; + + phys_addr_t r3_size = SZ_64; + phys_addr_t total_size; + phys_addr_t max_addr; + phys_addr_t min_addr; + + setup_memblock(); + + r1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2; + r1.size = SMP_CACHE_BYTES; + + r2.size = SZ_128; + r2.base = r1.base - (r3_size + r2.size); + + total_size = r1.size + r2.size + r3_size; + min_addr = r2.base + r2.size; + max_addr = r1.base; + + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + allocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == total_size); + assert(rgn->base == r2.base); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory within min_addr and max_add range, when + * there are two reserved regions at the borders, with a gap that can't fit + * a new region: + * + * + + + * | +----------+------+ +------+ | + * | | r3 | r2 | | r1 | | + * +--+----------+------+----+------+---+ + * ^ ^ + * | | + * | max_addr + * | + * min_addr + * + * Expect to merge the new region with r2. The second region does not get + * updated. The total size counter gets updated. + */ +static int alloc_try_nid_top_down_reserved_no_space_check(void) +{ + struct memblock_region *rgn1 = &memblock.reserved.regions[1]; + struct memblock_region *rgn2 = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + struct region r1, r2; + + phys_addr_t r3_size = SZ_256; + phys_addr_t gap_size = SMP_CACHE_BYTES; + phys_addr_t total_size; + phys_addr_t max_addr; + phys_addr_t min_addr; + + setup_memblock(); + + r1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2; + r1.size = SMP_CACHE_BYTES; + + r2.size = SZ_128; + r2.base = r1.base - (r2.size + gap_size); + + total_size = r1.size + r2.size + r3_size; + min_addr = r2.base + r2.size; + max_addr = r1.base; + + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + allocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn1->size == r1.size); + assert(rgn1->base == r1.base); + + assert(rgn2->size == r2.size + r3_size); + assert(rgn2->base == r2.base - r3_size); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory within min_addr and max_add range, but + * it's too narrow and everything else is reserved: + * + * +-----------+ + * | new | + * +-----------+ + * + + + * |--------------+ +----------| + * | r2 | | r1 | + * +--------------+------+----------+ + * ^ ^ + * | | + * | max_addr + * | + * min_addr + * + * Expect no allocation to happen. + */ + +static int alloc_try_nid_reserved_all_generic_check(void) +{ + void *allocated_ptr = NULL; + struct region r1, r2; + + phys_addr_t r3_size = SZ_256; + phys_addr_t gap_size = SMP_CACHE_BYTES; + phys_addr_t max_addr; + phys_addr_t min_addr; + + setup_memblock(); + + r1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES; + r1.size = SMP_CACHE_BYTES; + + r2.size = MEM_SIZE - (r1.size + gap_size); + r2.base = memblock_start_of_DRAM(); + + min_addr = r2.base + r2.size; + max_addr = r1.base; + + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + allocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + + assert(!allocated_ptr); + + return 0; +} + +/* + * A test that tries to allocate a memory region, where max_addr is + * bigger than the end address of the available memory. Expect to allocate + * a cleared region that ends before the end of the memory. + */ +static int alloc_try_nid_top_down_cap_max_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_256; + phys_addr_t min_addr; + phys_addr_t max_addr; + + setup_memblock(); + + min_addr = memblock_end_of_DRAM() - SZ_1K; + max_addr = memblock_end_of_DRAM() + SZ_256; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == memblock_end_of_DRAM() - size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate a memory region, where min_addr is + * smaller than the start address of the available memory. Expect to allocate + * a cleared region that ends before the end of the memory. + */ +static int alloc_try_nid_top_down_cap_min_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_1K; + phys_addr_t min_addr; + phys_addr_t max_addr; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() - SZ_256; + max_addr = memblock_end_of_DRAM(); + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == memblock_end_of_DRAM() - size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A simple test that tries to allocate a memory region within min_addr and + * max_addr range: + * + * + + + * | +-----------+ | | + * | | rgn | | | + * +----+-----------+-----------+------+ + * ^ ^ + * | | + * min_addr max_addr + * + * Expect to allocate a cleared region that ends before max_addr. + */ +static int alloc_try_nid_bottom_up_simple_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_128; + phys_addr_t min_addr; + phys_addr_t max_addr; + phys_addr_t rgn_end; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() + SMP_CACHE_BYTES * 2; + max_addr = min_addr + SZ_512; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, + NUMA_NO_NODE); + b = (char *)allocated_ptr; + rgn_end = rgn->base + rgn->size; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == min_addr); + assert(rgn_end < max_addr); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A simple test that tries to allocate a memory region within min_addr and + * max_addr range, where the start address is misaligned: + * + * + + + * | + +-----------+ + | + * | | | rgn | | | + * +-----+---+-----------+-----+-----+ + * ^ ^----. ^ + * | | | + * min_add | max_addr + * | + * Aligned address + * boundary + * + * Expect to allocate a cleared, aligned region that ends before max_addr. + */ +static int alloc_try_nid_bottom_up_start_misaligned_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_128; + phys_addr_t misalign = SZ_2; + phys_addr_t min_addr; + phys_addr_t max_addr; + phys_addr_t rgn_end; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() + misalign; + max_addr = min_addr + SZ_512; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, + NUMA_NO_NODE); + b = (char *)allocated_ptr; + rgn_end = rgn->base + rgn->size; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == min_addr + (SMP_CACHE_BYTES - misalign)); + assert(rgn_end < max_addr); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate a memory region, which can't fit into min_addr + * and max_addr range: + * + * + + + * |---------+ + + | + * | rgn | | | | + * +---------+---------+----+------+ + * ^ ^ + * | | + * | max_addr + * | + * min_add + * + * Expect to drop the lower limit and allocate a cleared memory region which + * starts at the beginning of the available memory. + */ +static int alloc_try_nid_bottom_up_narrow_range_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_256; + phys_addr_t min_addr; + phys_addr_t max_addr; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() + SZ_512; + max_addr = min_addr + SMP_CACHE_BYTES; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, + NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == memblock_start_of_DRAM()); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate memory within min_addr and max_add range, when + * there are two reserved regions at the borders, with a gap big enough to fit + * a new region: + * + * + + + * | +--------+-------+ +------+ | + * | | r2 | rgn | | r1 | | + * +----+--------+-------+---+------+--+ + * ^ ^ + * | | + * min_addr max_addr + * + * Expect to merge the new region with r2. The second region does not get + * updated. The total size field gets updated. + */ + +static int alloc_try_nid_bottom_up_reserved_with_space_check(void) +{ + struct memblock_region *rgn1 = &memblock.reserved.regions[1]; + struct memblock_region *rgn2 = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + struct region r1, r2; + + phys_addr_t r3_size = SZ_64; + phys_addr_t gap_size = SMP_CACHE_BYTES; + phys_addr_t total_size; + phys_addr_t max_addr; + phys_addr_t min_addr; + + setup_memblock(); + + r1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2; + r1.size = SMP_CACHE_BYTES; + + r2.size = SZ_128; + r2.base = r1.base - (r3_size + gap_size + r2.size); + + total_size = r1.size + r2.size + r3_size; + min_addr = r2.base + r2.size; + max_addr = r1.base; + + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + allocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES, + min_addr, max_addr, + NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn1->size == r1.size); + assert(rgn1->base == max_addr); + + assert(rgn2->size == r2.size + r3_size); + assert(rgn2->base == r2.base); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate memory within min_addr and max_add range, when + * there are two reserved regions at the borders, with a gap of a size equal to + * the size of the new region: + * + * + + + * |----------+ +------+ +----+ | + * | r3 | | r2 | | r1 | | + * +----------+----+------+---+----+--+ + * ^ ^ + * | | + * | max_addr + * | + * min_addr + * + * Expect to drop the lower limit and allocate memory at the beginning of the + * available memory. The region counter and total size fields get updated. + * Other regions are not modified. + */ + +static int alloc_try_nid_bottom_up_reserved_no_space_check(void) +{ + struct memblock_region *rgn1 = &memblock.reserved.regions[2]; + struct memblock_region *rgn2 = &memblock.reserved.regions[1]; + struct memblock_region *rgn3 = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + struct region r1, r2; + + phys_addr_t r3_size = SZ_256; + phys_addr_t gap_size = SMP_CACHE_BYTES; + phys_addr_t total_size; + phys_addr_t max_addr; + phys_addr_t min_addr; + + setup_memblock(); + + r1.base = memblock_end_of_DRAM() - SMP_CACHE_BYTES * 2; + r1.size = SMP_CACHE_BYTES; + + r2.size = SZ_128; + r2.base = r1.base - (r2.size + gap_size); + + total_size = r1.size + r2.size + r3_size; + min_addr = r2.base + r2.size; + max_addr = r1.base; + + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + allocated_ptr = memblock_alloc_try_nid(r3_size, SMP_CACHE_BYTES, + min_addr, max_addr, + NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn3->size == r3_size); + assert(rgn3->base == memblock_start_of_DRAM()); + + assert(rgn2->size == r2.size); + assert(rgn2->base == r2.base); + + assert(rgn1->size == r1.size); + assert(rgn1->base == r1.base); + + assert(memblock.reserved.cnt == 3); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to allocate a memory region, where max_addr is + * bigger than the end address of the available memory. Expect to allocate + * a cleared region that starts at the min_addr + */ +static int alloc_try_nid_bottom_up_cap_max_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_256; + phys_addr_t min_addr; + phys_addr_t max_addr; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM() + SZ_1K; + max_addr = memblock_end_of_DRAM() + SZ_256; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, + NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == min_addr); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* + * A test that tries to allocate a memory region, where min_addr is + * smaller than the start address of the available memory. Expect to allocate + * a cleared region at the beginning of the available memory. + */ +static int alloc_try_nid_bottom_up_cap_min_check(void) +{ + struct memblock_region *rgn = &memblock.reserved.regions[0]; + void *allocated_ptr = NULL; + char *b; + + phys_addr_t size = SZ_1K; + phys_addr_t min_addr; + phys_addr_t max_addr; + + setup_memblock(); + + min_addr = memblock_start_of_DRAM(); + max_addr = memblock_end_of_DRAM() - SZ_256; + + allocated_ptr = memblock_alloc_try_nid(size, SMP_CACHE_BYTES, + min_addr, max_addr, + NUMA_NO_NODE); + b = (char *)allocated_ptr; + + assert(allocated_ptr); + assert(*b == 0); + + assert(rgn->size == size); + assert(rgn->base == memblock_start_of_DRAM()); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == size); + + return 0; +} + +/* Test case wrappers */ +static int alloc_try_nid_simple_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_top_down_simple_check(); + memblock_set_bottom_up(true); + alloc_try_nid_bottom_up_simple_check(); + + return 0; +} + +static int alloc_try_nid_misaligned_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_top_down_end_misaligned_check(); + memblock_set_bottom_up(true); + alloc_try_nid_bottom_up_start_misaligned_check(); + + return 0; +} + +static int alloc_try_nid_narrow_range_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_top_down_narrow_range_check(); + memblock_set_bottom_up(true); + alloc_try_nid_bottom_up_narrow_range_check(); + + return 0; +} + +static int alloc_try_nid_reserved_with_space_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_top_down_reserved_with_space_check(); + memblock_set_bottom_up(true); + alloc_try_nid_bottom_up_reserved_with_space_check(); + + return 0; +} + +static int alloc_try_nid_reserved_no_space_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_top_down_reserved_no_space_check(); + memblock_set_bottom_up(true); + alloc_try_nid_bottom_up_reserved_no_space_check(); + + return 0; +} + +static int alloc_try_nid_cap_max_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_top_down_cap_max_check(); + memblock_set_bottom_up(true); + alloc_try_nid_bottom_up_cap_max_check(); + + return 0; +} + +static int alloc_try_nid_cap_min_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_top_down_cap_min_check(); + memblock_set_bottom_up(true); + alloc_try_nid_bottom_up_cap_min_check(); + + return 0; +} + +static int alloc_try_nid_min_reserved_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_min_reserved_generic_check(); + memblock_set_bottom_up(true); + alloc_try_nid_min_reserved_generic_check(); + + return 0; +} + +static int alloc_try_nid_max_reserved_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_max_reserved_generic_check(); + memblock_set_bottom_up(true); + alloc_try_nid_max_reserved_generic_check(); + + return 0; +} + +static int alloc_try_nid_exact_address_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_exact_address_generic_check(); + memblock_set_bottom_up(true); + alloc_try_nid_exact_address_generic_check(); + + return 0; +} + +static int alloc_try_nid_reserved_full_merge_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_reserved_full_merge_generic_check(); + memblock_set_bottom_up(true); + alloc_try_nid_reserved_full_merge_generic_check(); + + return 0; +} + +static int alloc_try_nid_reserved_all_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_reserved_all_generic_check(); + memblock_set_bottom_up(true); + alloc_try_nid_reserved_all_generic_check(); + + return 0; +} + +static int alloc_try_nid_low_max_check(void) +{ + memblock_set_bottom_up(false); + alloc_try_nid_low_max_generic_check(); + memblock_set_bottom_up(true); + alloc_try_nid_low_max_generic_check(); + + return 0; +} + +int memblock_alloc_nid_checks(void) +{ + reset_memblock_attributes(); + dummy_physical_memory_init(); + + alloc_try_nid_simple_check(); + alloc_try_nid_misaligned_check(); + alloc_try_nid_narrow_range_check(); + alloc_try_nid_reserved_with_space_check(); + alloc_try_nid_reserved_no_space_check(); + alloc_try_nid_cap_max_check(); + alloc_try_nid_cap_min_check(); + + alloc_try_nid_min_reserved_check(); + alloc_try_nid_max_reserved_check(); + alloc_try_nid_exact_address_check(); + alloc_try_nid_reserved_full_merge_check(); + alloc_try_nid_reserved_all_check(); + alloc_try_nid_low_max_check(); + + dummy_physical_memory_cleanup(); + + return 0; +} diff --git a/tools/testing/memblock/tests/alloc_nid_api.h b/tools/testing/memblock/tests/alloc_nid_api.h new file mode 100644 index 000000000000..b35cf3c3f489 --- /dev/null +++ b/tools/testing/memblock/tests/alloc_nid_api.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _MEMBLOCK_ALLOC_NID_H +#define _MEMBLOCK_ALLOC_NID_H + +#include "common.h" + +int memblock_alloc_nid_checks(void); + +#endif diff --git a/tools/testing/memblock/tests/basic_api.c b/tools/testing/memblock/tests/basic_api.c new file mode 100644 index 000000000000..fbc1ce160303 --- /dev/null +++ b/tools/testing/memblock/tests/basic_api.c @@ -0,0 +1,903 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include +#include +#include "basic_api.h" + +#define EXPECTED_MEMBLOCK_REGIONS 128 + +static int memblock_initialization_check(void) +{ + assert(memblock.memory.regions); + assert(memblock.memory.cnt == 1); + assert(memblock.memory.max == EXPECTED_MEMBLOCK_REGIONS); + assert(strcmp(memblock.memory.name, "memory") == 0); + + assert(memblock.reserved.regions); + assert(memblock.reserved.cnt == 1); + assert(memblock.memory.max == EXPECTED_MEMBLOCK_REGIONS); + assert(strcmp(memblock.reserved.name, "reserved") == 0); + + assert(!memblock.bottom_up); + assert(memblock.current_limit == MEMBLOCK_ALLOC_ANYWHERE); + + return 0; +} + +/* + * A simple test that adds a memory block of a specified base address + * and size to the collection of available memory regions (memblock.memory). + * It checks if a new entry was created and if region counter and total memory + * were correctly updated. + */ +static int memblock_add_simple_check(void) +{ + struct memblock_region *rgn; + + rgn = &memblock.memory.regions[0]; + + struct region r = { + .base = SZ_1G, + .size = SZ_4M + }; + + reset_memblock_regions(); + memblock_add(r.base, r.size); + + assert(rgn->base == r.base); + assert(rgn->size == r.size); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == r.size); + + return 0; +} + +/* + * A simple test that adds a memory block of a specified base address, size + * NUMA node and memory flags to the collection of available memory regions. + * It checks if the new entry, region counter and total memory size have + * expected values. + */ +static int memblock_add_node_simple_check(void) +{ + struct memblock_region *rgn; + + rgn = &memblock.memory.regions[0]; + + struct region r = { + .base = SZ_1M, + .size = SZ_16M + }; + + reset_memblock_regions(); + memblock_add_node(r.base, r.size, 1, MEMBLOCK_HOTPLUG); + + assert(rgn->base == r.base); + assert(rgn->size == r.size); +#ifdef CONFIG_NUMA + assert(rgn->nid == 1); +#endif + assert(rgn->flags == MEMBLOCK_HOTPLUG); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == r.size); + + return 0; +} + +/* + * A test that tries to add two memory blocks that don't overlap with one + * another. It checks if two correctly initialized entries were added to the + * collection of available memory regions (memblock.memory) and if this + * change was reflected in memblock.memory's total size and region counter. + */ +static int memblock_add_disjoint_check(void) +{ + struct memblock_region *rgn1, *rgn2; + + rgn1 = &memblock.memory.regions[0]; + rgn2 = &memblock.memory.regions[1]; + + struct region r1 = { + .base = SZ_1G, + .size = SZ_8K + }; + struct region r2 = { + .base = SZ_1G + SZ_16K, + .size = SZ_8K + }; + + reset_memblock_regions(); + memblock_add(r1.base, r1.size); + memblock_add(r2.base, r2.size); + + assert(rgn1->base == r1.base); + assert(rgn1->size == r1.size); + + assert(rgn2->base == r2.base); + assert(rgn2->size == r2.size); + + assert(memblock.memory.cnt == 2); + assert(memblock.memory.total_size == r1.size + r2.size); + + return 0; +} + +/* + * A test that tries to add two memory blocks, where the second one overlaps + * with the beginning of the first entry (that is r1.base < r2.base + r2.size). + * After this, it checks if two entries are merged into one region that starts + * at r2.base and has size of two regions minus their intersection. It also + * verifies the reported total size of the available memory and region counter. + */ +static int memblock_add_overlap_top_check(void) +{ + struct memblock_region *rgn; + phys_addr_t total_size; + + rgn = &memblock.memory.regions[0]; + + struct region r1 = { + .base = SZ_512M, + .size = SZ_1G + }; + struct region r2 = { + .base = SZ_256M, + .size = SZ_512M + }; + + total_size = (r1.base - r2.base) + r1.size; + + reset_memblock_regions(); + memblock_add(r1.base, r1.size); + memblock_add(r2.base, r2.size); + + assert(rgn->base == r2.base); + assert(rgn->size == total_size); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == total_size); + + return 0; +} + +/* + * A test that tries to add two memory blocks, where the second one overlaps + * with the end of the first entry (that is r2.base < r1.base + r1.size). + * After this, it checks if two entries are merged into one region that starts + * at r1.base and has size of two regions minus their intersection. It verifies + * that memblock can still see only one entry and has a correct total size of + * the available memory. + */ +static int memblock_add_overlap_bottom_check(void) +{ + struct memblock_region *rgn; + phys_addr_t total_size; + + rgn = &memblock.memory.regions[0]; + + struct region r1 = { + .base = SZ_128M, + .size = SZ_512M + }; + struct region r2 = { + .base = SZ_256M, + .size = SZ_1G + }; + + total_size = (r2.base - r1.base) + r2.size; + + reset_memblock_regions(); + memblock_add(r1.base, r1.size); + memblock_add(r2.base, r2.size); + + assert(rgn->base == r1.base); + assert(rgn->size == total_size); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == total_size); + + return 0; +} + +/* + * A test that tries to add two memory blocks, where the second one is + * within the range of the first entry (that is r1.base < r2.base && + * r2.base + r2.size < r1.base + r1.size). It checks if two entries are merged + * into one region that stays the same. The counter and total size of available + * memory are expected to not be updated. + */ +static int memblock_add_within_check(void) +{ + struct memblock_region *rgn; + + rgn = &memblock.memory.regions[0]; + + struct region r1 = { + .base = SZ_8M, + .size = SZ_32M + }; + struct region r2 = { + .base = SZ_16M, + .size = SZ_1M + }; + + reset_memblock_regions(); + memblock_add(r1.base, r1.size); + memblock_add(r2.base, r2.size); + + assert(rgn->base == r1.base); + assert(rgn->size == r1.size); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == r1.size); + + return 0; +} + +/* + * A simple test that tries to add the same memory block twice. The counter + * and total size of available memory are expected to not be updated. + */ +static int memblock_add_twice_check(void) +{ + struct region r = { + .base = SZ_16K, + .size = SZ_2M + }; + + reset_memblock_regions(); + + memblock_add(r.base, r.size); + memblock_add(r.base, r.size); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == r.size); + + return 0; +} + +static int memblock_add_checks(void) +{ + memblock_add_simple_check(); + memblock_add_node_simple_check(); + memblock_add_disjoint_check(); + memblock_add_overlap_top_check(); + memblock_add_overlap_bottom_check(); + memblock_add_within_check(); + memblock_add_twice_check(); + + return 0; +} + + /* + * A simple test that marks a memory block of a specified base address + * and size as reserved and to the collection of reserved memory regions + * (memblock.reserved). It checks if a new entry was created and if region + * counter and total memory size were correctly updated. + */ +static int memblock_reserve_simple_check(void) +{ + struct memblock_region *rgn; + + rgn = &memblock.reserved.regions[0]; + + struct region r = { + .base = SZ_2G, + .size = SZ_128M + }; + + reset_memblock_regions(); + memblock_reserve(r.base, r.size); + + assert(rgn->base == r.base); + assert(rgn->size == r.size); + + return 0; +} + +/* + * A test that tries to mark two memory blocks that don't overlap as reserved + * and checks if two entries were correctly added to the collection of reserved + * memory regions (memblock.reserved) and if this change was reflected in + * memblock.reserved's total size and region counter. + */ +static int memblock_reserve_disjoint_check(void) +{ + struct memblock_region *rgn1, *rgn2; + + rgn1 = &memblock.reserved.regions[0]; + rgn2 = &memblock.reserved.regions[1]; + + struct region r1 = { + .base = SZ_256M, + .size = SZ_16M + }; + struct region r2 = { + .base = SZ_512M, + .size = SZ_512M + }; + + reset_memblock_regions(); + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + assert(rgn1->base == r1.base); + assert(rgn1->size == r1.size); + + assert(rgn2->base == r2.base); + assert(rgn2->size == r2.size); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == r1.size + r2.size); + + return 0; +} + +/* + * A test that tries to mark two memory blocks as reserved, where the + * second one overlaps with the beginning of the first (that is + * r1.base < r2.base + r2.size). + * It checks if two entries are merged into one region that starts at r2.base + * and has size of two regions minus their intersection. The test also verifies + * that memblock can still see only one entry and has a correct total size of + * the reserved memory. + */ +static int memblock_reserve_overlap_top_check(void) +{ + struct memblock_region *rgn; + phys_addr_t total_size; + + rgn = &memblock.reserved.regions[0]; + + struct region r1 = { + .base = SZ_1G, + .size = SZ_1G + }; + struct region r2 = { + .base = SZ_128M, + .size = SZ_1G + }; + + total_size = (r1.base - r2.base) + r1.size; + + reset_memblock_regions(); + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + assert(rgn->base == r2.base); + assert(rgn->size == total_size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to mark two memory blocks as reserved, where the + * second one overlaps with the end of the first entry (that is + * r2.base < r1.base + r1.size). + * It checks if two entries are merged into one region that starts at r1.base + * and has size of two regions minus their intersection. It verifies that + * memblock can still see only one entry and has a correct total size of the + * reserved memory. + */ +static int memblock_reserve_overlap_bottom_check(void) +{ + struct memblock_region *rgn; + phys_addr_t total_size; + + rgn = &memblock.reserved.regions[0]; + + struct region r1 = { + .base = SZ_2K, + .size = SZ_128K + }; + struct region r2 = { + .base = SZ_128K, + .size = SZ_128K + }; + + total_size = (r2.base - r1.base) + r2.size; + + reset_memblock_regions(); + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + assert(rgn->base == r1.base); + assert(rgn->size == total_size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to mark two memory blocks as reserved, where the second + * one is within the range of the first entry (that is + * (r1.base < r2.base) && (r2.base + r2.size < r1.base + r1.size)). + * It checks if two entries are merged into one region that stays the + * same. The counter and total size of available memory are expected to not be + * updated. + */ +static int memblock_reserve_within_check(void) +{ + struct memblock_region *rgn; + + rgn = &memblock.reserved.regions[0]; + + struct region r1 = { + .base = SZ_1M, + .size = SZ_8M + }; + struct region r2 = { + .base = SZ_2M, + .size = SZ_64K + }; + + reset_memblock_regions(); + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + + assert(rgn->base == r1.base); + assert(rgn->size == r1.size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == r1.size); + + return 0; +} + +/* + * A simple test that tries to reserve the same memory block twice. + * The region counter and total size of reserved memory are expected to not + * be updated. + */ +static int memblock_reserve_twice_check(void) +{ + struct region r = { + .base = SZ_16K, + .size = SZ_2M + }; + + reset_memblock_regions(); + + memblock_reserve(r.base, r.size); + memblock_reserve(r.base, r.size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == r.size); + + return 0; +} + +static int memblock_reserve_checks(void) +{ + memblock_reserve_simple_check(); + memblock_reserve_disjoint_check(); + memblock_reserve_overlap_top_check(); + memblock_reserve_overlap_bottom_check(); + memblock_reserve_within_check(); + memblock_reserve_twice_check(); + + return 0; +} + + /* + * A simple test that tries to remove the first entry of the array of + * available memory regions. By "removing" a region we mean overwriting it + * with the next region in memblock.memory. To check this is the case, the + * test adds two memory blocks and verifies that the value of the latter + * was used to erase r1 region. It also checks if the region counter and + * total size were updated to expected values. + */ +static int memblock_remove_simple_check(void) +{ + struct memblock_region *rgn; + + rgn = &memblock.memory.regions[0]; + + struct region r1 = { + .base = SZ_2K, + .size = SZ_4K + }; + struct region r2 = { + .base = SZ_128K, + .size = SZ_4M + }; + + reset_memblock_regions(); + memblock_add(r1.base, r1.size); + memblock_add(r2.base, r2.size); + memblock_remove(r1.base, r1.size); + + assert(rgn->base == r2.base); + assert(rgn->size == r2.size); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == r2.size); + + return 0; +} + + /* + * A test that tries to remove a region that was not registered as available + * memory (i.e. has no corresponding entry in memblock.memory). It verifies + * that array, regions counter and total size were not modified. + */ +static int memblock_remove_absent_check(void) +{ + struct memblock_region *rgn; + + rgn = &memblock.memory.regions[0]; + + struct region r1 = { + .base = SZ_512K, + .size = SZ_4M + }; + struct region r2 = { + .base = SZ_64M, + .size = SZ_1G + }; + + reset_memblock_regions(); + memblock_add(r1.base, r1.size); + memblock_remove(r2.base, r2.size); + + assert(rgn->base == r1.base); + assert(rgn->size == r1.size); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == r1.size); + + return 0; +} + +/* + * A test that tries to remove a region which overlaps with the beginning of + * the already existing entry r1 (that is r1.base < r2.base + r2.size). It + * checks if only the intersection of both regions is removed from the available + * memory pool. The test also checks if the regions counter and total size are + * updated to expected values. + */ +static int memblock_remove_overlap_top_check(void) +{ + struct memblock_region *rgn; + phys_addr_t r1_end, r2_end, total_size; + + rgn = &memblock.memory.regions[0]; + + struct region r1 = { + .base = SZ_32M, + .size = SZ_32M + }; + struct region r2 = { + .base = SZ_16M, + .size = SZ_32M + }; + + r1_end = r1.base + r1.size; + r2_end = r2.base + r2.size; + total_size = r1_end - r2_end; + + reset_memblock_regions(); + memblock_add(r1.base, r1.size); + memblock_remove(r2.base, r2.size); + + assert(rgn->base == r1.base + r2.base); + assert(rgn->size == total_size); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == total_size); + + return 0; +} + +/* + * A test that tries to remove a region which overlaps with the end of the + * first entry (that is r2.base < r1.base + r1.size). It checks if only the + * intersection of both regions is removed from the available memory pool. + * The test also checks if the regions counter and total size are updated to + * expected values. + */ +static int memblock_remove_overlap_bottom_check(void) +{ + struct memblock_region *rgn; + phys_addr_t total_size; + + rgn = &memblock.memory.regions[0]; + + struct region r1 = { + .base = SZ_2M, + .size = SZ_64M + }; + struct region r2 = { + .base = SZ_32M, + .size = SZ_256M + }; + + total_size = r2.base - r1.base; + + reset_memblock_regions(); + memblock_add(r1.base, r1.size); + memblock_remove(r2.base, r2.size); + + assert(rgn->base == r1.base); + assert(rgn->size == total_size); + + assert(memblock.memory.cnt == 1); + assert(memblock.memory.total_size == total_size); + return 0; +} + +/* + * A test that tries to remove a region which is within the range of the + * already existing entry (that is + * (r1.base < r2.base) && (r2.base + r2.size < r1.base + r1.size)). + * It checks if the region is split into two - one that ends at r2.base and + * second that starts at r2.base + size, with appropriate sizes. The test + * also checks if the region counter and total size were updated to + * expected values. + */ +static int memblock_remove_within_check(void) +{ + struct memblock_region *rgn1, *rgn2; + phys_addr_t r1_size, r2_size, total_size; + + rgn1 = &memblock.memory.regions[0]; + rgn2 = &memblock.memory.regions[1]; + + struct region r1 = { + .base = SZ_1M, + .size = SZ_32M + }; + struct region r2 = { + .base = SZ_16M, + .size = SZ_1M + }; + + r1_size = r2.base - r1.base; + r2_size = (r1.base + r1.size) - (r2.base + r2.size); + total_size = r1_size + r2_size; + + reset_memblock_regions(); + memblock_add(r1.base, r1.size); + memblock_remove(r2.base, r2.size); + + assert(rgn1->base == r1.base); + assert(rgn1->size == r1_size); + + assert(rgn2->base == r2.base + r2.size); + assert(rgn2->size == r2_size); + + assert(memblock.memory.cnt == 2); + assert(memblock.memory.total_size == total_size); + + return 0; +} + +static int memblock_remove_checks(void) +{ + memblock_remove_simple_check(); + memblock_remove_absent_check(); + memblock_remove_overlap_top_check(); + memblock_remove_overlap_bottom_check(); + memblock_remove_within_check(); + + return 0; +} + +/* + * A simple test that tries to free a memory block that was marked earlier + * as reserved. By "freeing" a region we mean overwriting it with the next + * entry in memblock.reserved. To check this is the case, the test reserves + * two memory regions and verifies that the value of the latter was used to + * erase r1 region. + * The test also checks if the region counter and total size were updated. + */ +static int memblock_free_simple_check(void) +{ + struct memblock_region *rgn; + + rgn = &memblock.reserved.regions[0]; + + struct region r1 = { + .base = SZ_4M, + .size = SZ_1M + }; + struct region r2 = { + .base = SZ_8M, + .size = SZ_1M + }; + + reset_memblock_regions(); + memblock_reserve(r1.base, r1.size); + memblock_reserve(r2.base, r2.size); + memblock_free((void *)r1.base, r1.size); + + assert(rgn->base == r2.base); + assert(rgn->size == r2.size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == r2.size); + + return 0; +} + + /* + * A test that tries to free a region that was not marked as reserved + * (i.e. has no corresponding entry in memblock.reserved). It verifies + * that array, regions counter and total size were not modified. + */ +static int memblock_free_absent_check(void) +{ + struct memblock_region *rgn; + + rgn = &memblock.reserved.regions[0]; + + struct region r1 = { + .base = SZ_2M, + .size = SZ_8K + }; + struct region r2 = { + .base = SZ_16M, + .size = SZ_128M + }; + + reset_memblock_regions(); + memblock_reserve(r1.base, r1.size); + memblock_free((void *)r2.base, r2.size); + + assert(rgn->base == r1.base); + assert(rgn->size == r1.size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == r1.size); + + return 0; +} + +/* + * A test that tries to free a region which overlaps with the beginning of + * the already existing entry r1 (that is r1.base < r2.base + r2.size). It + * checks if only the intersection of both regions is freed. The test also + * checks if the regions counter and total size are updated to expected + * values. + */ +static int memblock_free_overlap_top_check(void) +{ + struct memblock_region *rgn; + phys_addr_t total_size; + + rgn = &memblock.reserved.regions[0]; + + struct region r1 = { + .base = SZ_8M, + .size = SZ_32M + }; + struct region r2 = { + .base = SZ_1M, + .size = SZ_8M + }; + + total_size = (r1.size + r1.base) - (r2.base + r2.size); + + reset_memblock_regions(); + memblock_reserve(r1.base, r1.size); + memblock_free((void *)r2.base, r2.size); + + assert(rgn->base == r2.base + r2.size); + assert(rgn->size == total_size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to free a region which overlaps with the end of the + * first entry (that is r2.base < r1.base + r1.size). It checks if only the + * intersection of both regions is freed. The test also checks if the + * regions counter and total size are updated to expected values. + */ +static int memblock_free_overlap_bottom_check(void) +{ + struct memblock_region *rgn; + phys_addr_t total_size; + + rgn = &memblock.reserved.regions[0]; + + struct region r1 = { + .base = SZ_8M, + .size = SZ_32M + }; + struct region r2 = { + .base = SZ_32M, + .size = SZ_32M + }; + + total_size = r2.base - r1.base; + + reset_memblock_regions(); + memblock_reserve(r1.base, r1.size); + memblock_free((void *)r2.base, r2.size); + + assert(rgn->base == r1.base); + assert(rgn->size == total_size); + + assert(memblock.reserved.cnt == 1); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +/* + * A test that tries to free a region which is within the range of the + * already existing entry (that is + * (r1.base < r2.base) && (r2.base + r2.size < r1.base + r1.size)). + * It checks if the region is split into two - one that ends at r2.base and + * second that starts at r2.base + size, with appropriate sizes. It is + * expected that the region counter and total size fields were updated t + * reflect that change. + */ +static int memblock_free_within_check(void) +{ + struct memblock_region *rgn1, *rgn2; + phys_addr_t r1_size, r2_size, total_size; + + rgn1 = &memblock.reserved.regions[0]; + rgn2 = &memblock.reserved.regions[1]; + + struct region r1 = { + .base = SZ_1M, + .size = SZ_8M + }; + struct region r2 = { + .base = SZ_4M, + .size = SZ_1M + }; + + r1_size = r2.base - r1.base; + r2_size = (r1.base + r1.size) - (r2.base + r2.size); + total_size = r1_size + r2_size; + + reset_memblock_regions(); + memblock_reserve(r1.base, r1.size); + memblock_free((void *)r2.base, r2.size); + + assert(rgn1->base == r1.base); + assert(rgn1->size == r1_size); + + assert(rgn2->base == r2.base + r2.size); + assert(rgn2->size == r2_size); + + assert(memblock.reserved.cnt == 2); + assert(memblock.reserved.total_size == total_size); + + return 0; +} + +static int memblock_free_checks(void) +{ + memblock_free_simple_check(); + memblock_free_absent_check(); + memblock_free_overlap_top_check(); + memblock_free_overlap_bottom_check(); + memblock_free_within_check(); + + return 0; +} + +int memblock_basic_checks(void) +{ + memblock_initialization_check(); + memblock_add_checks(); + memblock_reserve_checks(); + memblock_remove_checks(); + memblock_free_checks(); + + return 0; +} diff --git a/tools/testing/memblock/tests/basic_api.h b/tools/testing/memblock/tests/basic_api.h new file mode 100644 index 000000000000..1873faa54754 --- /dev/null +++ b/tools/testing/memblock/tests/basic_api.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _MEMBLOCK_BASIC_H +#define _MEMBLOCK_BASIC_H + +#include "common.h" + +int memblock_basic_checks(void); + +#endif diff --git a/tools/testing/memblock/tests/common.c b/tools/testing/memblock/tests/common.c new file mode 100644 index 000000000000..62d3191f7c9a --- /dev/null +++ b/tools/testing/memblock/tests/common.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#include "tests/common.h" +#include + +#define INIT_MEMBLOCK_REGIONS 128 +#define INIT_MEMBLOCK_RESERVED_REGIONS INIT_MEMBLOCK_REGIONS + +static struct test_memory memory_block; + +void reset_memblock_regions(void) +{ + memset(memblock.memory.regions, 0, + memblock.memory.cnt * sizeof(struct memblock_region)); + memblock.memory.cnt = 1; + memblock.memory.max = INIT_MEMBLOCK_REGIONS; + memblock.memory.total_size = 0; + + memset(memblock.reserved.regions, 0, + memblock.reserved.cnt * sizeof(struct memblock_region)); + memblock.reserved.cnt = 1; + memblock.reserved.max = INIT_MEMBLOCK_RESERVED_REGIONS; + memblock.reserved.total_size = 0; +} + +void reset_memblock_attributes(void) +{ + memblock.memory.name = "memory"; + memblock.reserved.name = "reserved"; + memblock.bottom_up = false; + memblock.current_limit = MEMBLOCK_ALLOC_ANYWHERE; +} + +void setup_memblock(void) +{ + reset_memblock_regions(); + memblock_add((phys_addr_t)memory_block.base, MEM_SIZE); +} + +void dummy_physical_memory_init(void) +{ + memory_block.base = malloc(MEM_SIZE); + assert(memory_block.base); +} + +void dummy_physical_memory_cleanup(void) +{ + free(memory_block.base); +} diff --git a/tools/testing/memblock/tests/common.h b/tools/testing/memblock/tests/common.h new file mode 100644 index 000000000000..619054d03219 --- /dev/null +++ b/tools/testing/memblock/tests/common.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef _MEMBLOCK_TEST_H +#define _MEMBLOCK_TEST_H + +#include +#include +#include +#include +#include + +#define MEM_SIZE SZ_16K + +/* + * Available memory registered with memblock needs to be valid for allocs + * test to run. This is a convenience wrapper for memory allocated in + * dummy_physical_memory_init() that is later registered with memblock + * in setup_memblock(). + */ +struct test_memory { + void *base; +}; + +struct region { + phys_addr_t base; + phys_addr_t size; +}; + +void reset_memblock_regions(void); +void reset_memblock_attributes(void); +void setup_memblock(void); +void dummy_physical_memory_init(void); +void dummy_physical_memory_cleanup(void); + +#endif diff --git a/tools/testing/radix-tree/Makefile b/tools/testing/radix-tree/Makefile index aa6abfe0749c..c4ea4fbb0bfc 100644 --- a/tools/testing/radix-tree/Makefile +++ b/tools/testing/radix-tree/Makefile @@ -5,7 +5,8 @@ CFLAGS += -I. -I../../include -g -Og -Wall -D_LGPL_SOURCE -fsanitize=address \ LDFLAGS += -fsanitize=address -fsanitize=undefined LDLIBS+= -lpthread -lurcu TARGETS = main idr-test multiorder xarray -CORE_OFILES := xarray.o radix-tree.o idr.o linux.o test.o find_bit.o bitmap.o +CORE_OFILES := xarray.o radix-tree.o idr.o linux.o test.o find_bit.o bitmap.o \ + slab.o OFILES = main.o $(CORE_OFILES) regression1.o regression2.o regression3.o \ regression4.o tag_check.o multiorder.o idr-test.o iteration_check.o \ iteration_check_2.o benchmark.o diff --git a/tools/testing/radix-tree/linux.c b/tools/testing/radix-tree/linux.c index 2d9c59df60de..81539f543954 100644 --- a/tools/testing/radix-tree/linux.c +++ b/tools/testing/radix-tree/linux.c @@ -14,7 +14,6 @@ int nr_allocated; int preempt_count; -int kmalloc_verbose; int test_verbose; struct kmem_cache { @@ -78,32 +77,6 @@ void kmem_cache_free(struct kmem_cache *cachep, void *objp) pthread_mutex_unlock(&cachep->lock); } -void *kmalloc(size_t size, gfp_t gfp) -{ - void *ret; - - if (!(gfp & __GFP_DIRECT_RECLAIM)) - return NULL; - - ret = malloc(size); - uatomic_inc(&nr_allocated); - if (kmalloc_verbose) - printf("Allocating %p from malloc\n", ret); - if (gfp & __GFP_ZERO) - memset(ret, 0, size); - return ret; -} - -void kfree(void *p) -{ - if (!p) - return; - uatomic_dec(&nr_allocated); - if (kmalloc_verbose) - printf("Freeing %p to malloc\n", p); - free(p); -} - struct kmem_cache * kmem_cache_create(const char *name, unsigned int size, unsigned int align, unsigned int flags, void (*ctor)(void *)) diff --git a/tools/testing/radix-tree/linux/gfp.h b/tools/testing/radix-tree/linux/gfp.h deleted file mode 100644 index 32159c08a52e..000000000000 --- a/tools/testing/radix-tree/linux/gfp.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _GFP_H -#define _GFP_H - -#include - -#define __GFP_BITS_SHIFT 26 -#define __GFP_BITS_MASK ((gfp_t)((1 << __GFP_BITS_SHIFT) - 1)) - -#define __GFP_HIGH 0x20u -#define __GFP_IO 0x40u -#define __GFP_FS 0x80u -#define __GFP_NOWARN 0x200u -#define __GFP_ZERO 0x8000u -#define __GFP_ATOMIC 0x80000u -#define __GFP_ACCOUNT 0x100000u -#define __GFP_DIRECT_RECLAIM 0x400000u -#define __GFP_KSWAPD_RECLAIM 0x2000000u - -#define __GFP_RECLAIM (__GFP_DIRECT_RECLAIM|__GFP_KSWAPD_RECLAIM) - -#define GFP_ZONEMASK 0x0fu -#define GFP_ATOMIC (__GFP_HIGH|__GFP_ATOMIC|__GFP_KSWAPD_RECLAIM) -#define GFP_KERNEL (__GFP_RECLAIM | __GFP_IO | __GFP_FS) -#define GFP_NOWAIT (__GFP_KSWAPD_RECLAIM) - - -static inline bool gfpflags_allow_blocking(const gfp_t gfp_flags) -{ - return !!(gfp_flags & __GFP_DIRECT_RECLAIM); -} - -#endif