Merge "usb: phy: Add CC line polarity inversion support for QMP PHY"
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commit
f3040bed7d
1 changed files with 13 additions and 1 deletions
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@ -53,6 +53,8 @@ enum core_ldo_levels {
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#define SW_PORTSELECT BIT(0)
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/* port select mux: 1 - sw control. 0 - HW control*/
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#define SW_PORTSELECT_MX BIT(1)
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/* port select polarity: 1 - invert polarity of portselect from gpio */
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#define PORTSELECT_POLARITY BIT(2)
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/* USB3_DP_PHY_USB3_DP_COM_SWI_CTRL bits */
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@ -150,6 +152,7 @@ struct msm_ssphy_qmp {
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int reg_offset_cnt;
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u32 *qmp_phy_init_seq;
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int init_seq_len;
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bool invert_ps_polarity;
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enum qmp_phy_type phy_type;
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};
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@ -455,6 +458,14 @@ static void usb_qmp_update_portselect_phymode(struct msm_ssphy_qmp *phy)
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switch (phy->phy_type) {
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case USB3_AND_DP:
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/*
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* if port select inversion is enabled, enable it only for the input to the PHY.
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* The lane selection based on PHY flags will not get affected.
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*/
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if (val < 0 && phy->invert_ps_polarity)
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writel_relaxed(PORTSELECT_POLARITY,
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phy->base + phy->phy_reg[USB3_DP_COM_TYPEC_CTRL]);
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writel_relaxed(0x01,
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phy->base + phy->phy_reg[USB3_DP_COM_SW_RESET]);
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writel_relaxed(0x00,
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@ -1219,7 +1230,8 @@ static int msm_ssphy_qmp_probe(struct platform_device *pdev)
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&phy->vdd_max_uA) || !phy->vdd_max_uA)
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phy->vdd_max_uA = USB_SSPHY_HPM_LOAD;
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platform_set_drvdata(pdev, phy);
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phy->invert_ps_polarity = of_property_read_bool(dev->of_node,
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"qcom,invert-ps-polarity");
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phy->phy.dev = dev;
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phy->phy.init = msm_ssphy_qmp_init;
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