drm/amd/amdgpu: limit one queue per gang
commit 5ee33d905f89c18d4b33da6e5eefdae6060502df upstream. Limit one queue per gang in mes self test, due to mes schq fw change. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 3 additions and 6 deletions
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@ -1328,12 +1328,9 @@ int amdgpu_mes_self_test(struct amdgpu_device *adev)
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struct amdgpu_mes_ctx_data ctx_data = {0};
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struct amdgpu_mes_ctx_data ctx_data = {0};
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struct amdgpu_ring *added_rings[AMDGPU_MES_CTX_MAX_RINGS] = { NULL };
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struct amdgpu_ring *added_rings[AMDGPU_MES_CTX_MAX_RINGS] = { NULL };
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int gang_ids[3] = {0};
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int gang_ids[3] = {0};
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int queue_types[][2] = { { AMDGPU_RING_TYPE_GFX,
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int queue_types[][2] = { { AMDGPU_RING_TYPE_GFX, 1 },
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AMDGPU_MES_CTX_MAX_GFX_RINGS},
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{ AMDGPU_RING_TYPE_COMPUTE, 1 },
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{ AMDGPU_RING_TYPE_COMPUTE,
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{ AMDGPU_RING_TYPE_SDMA, 1} };
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AMDGPU_MES_CTX_MAX_COMPUTE_RINGS},
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{ AMDGPU_RING_TYPE_SDMA,
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AMDGPU_MES_CTX_MAX_SDMA_RINGS } };
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int i, r, pasid, k = 0;
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int i, r, pasid, k = 0;
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pasid = amdgpu_pasid_alloc(16);
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pasid = amdgpu_pasid_alloc(16);
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